diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
| commit | b63631536d974f31cf99ee280271dc0f7b4c746f (patch) | |
| tree | ff83820d8dd75de8238e4b7ddaf3b91e4cf8374f /tests/long/fs/10.linux-boot/ref/arm | |
| parent | 646c4a23ca44aab5468c896034288151c89be782 (diff) | |
| download | gem5-b63631536d974f31cf99ee280271dc0f7b4c746f.tar.xz | |
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.
The main reason for bundling them up is to minimise the changeset
size.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
6 files changed, 8379 insertions, 8781 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 03035c465..4688e11b5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,131 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534332 # Number of seconds simulated -sim_ticks 2534332336000 # Number of ticks simulated -final_tick 2534332336000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.524310 # Number of seconds simulated +sim_ticks 2524309551500 # Number of ticks simulated +final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47356 # Simulator instruction rate (inst/s) -host_op_rate 60934 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1990051953 # Simulator tick rate (ticks/s) -host_mem_usage 400524 # Number of bytes of host memory used -host_seconds 1273.50 # Real time elapsed on the host -sim_insts 60307773 # Number of instructions simulated -sim_ops 77599321 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119572608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory +host_inst_rate 67450 # Simulator instruction rate (inst/s) +host_op_rate 86789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2823365435 # Simulator tick rate (ticks/s) +host_mem_usage 397608 # Number of bytes of host memory used +host_seconds 894.08 # Real time elapsed on the host +sim_insts 60305560 # Number of instructions simulated +sim_ops 77596391 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095056 # Number of bytes read from this memory -system.physmem.bytes_read::total 129468752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory +system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14946576 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12471 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142144 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15101237 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47181108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1111 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51085941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493575 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683661 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47181108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53769602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15101237 # Total number of read requests seen -system.physmem.writeReqs 813162 # Total number of write requests seen -system.physmem.cpureqs 218445 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966479168 # Total number of bytes read from memory -system.physmem.bytesWritten 52042368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129468752 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6801288 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 279 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4676 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 944611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 944270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 944423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944612 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943694 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943515 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944002 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 942812 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943693 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51011 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51200 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50757 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51124 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 966197440 # Total number of bytes read from memory +system.physmem.bytesWritten 52040704 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32457 # Number of times wr buffer was full causing retry -system.physmem.totGap 2534332242000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 2524308440000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14946576 # Categorize read packet sizes +system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154625 # Categorize read packet sizes +system.physmem.readPktSize::6 154591 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59144 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1052232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 984006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 974713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3682136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2757823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2756219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2725955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 12526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59118 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -139,316 +140,294 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32470 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 42332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 24053.235566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1833.734815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32311.504914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 8211 19.40% 19.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3440 8.13% 27.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2237 5.28% 32.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1775 4.19% 37.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1231 2.91% 39.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1031 2.44% 42.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 888 2.10% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 774 1.83% 46.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 547 1.29% 47.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 559 1.32% 48.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 426 1.01% 49.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 432 1.02% 50.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 287 0.68% 51.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 279 0.66% 52.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 159 0.38% 52.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 249 0.59% 53.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 131 0.31% 53.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 141 0.33% 53.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 101 0.24% 54.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 136 0.32% 54.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 82 0.19% 54.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 379 0.90% 55.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 1813 4.28% 59.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 447 1.06% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 86 0.20% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 158 0.37% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 41 0.10% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 104 0.25% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 37 0.09% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 64 0.15% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 25 0.06% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 71 0.17% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 17 0.04% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 45 0.11% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 11 0.03% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 40 0.09% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 10 0.02% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 26 0.06% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 12 0.03% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 19 0.04% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 3 0.01% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 16 0.04% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 8 0.02% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 18 0.04% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 12 0.03% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 13 0.03% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 25 0.06% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 6 0.01% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 6 0.01% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 9 0.02% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 13 0.03% 62.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 6 0.01% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 6 0.01% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 2 0.00% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 9 0.02% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 8 0.02% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 5 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 1 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 6 0.01% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 43 0.10% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 2 0.00% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 3 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 7 0.02% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 8 0.02% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 8 0.02% 63.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 6 0.01% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 7 0.02% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 4 0.01% 63.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 2 0.00% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 2 0.00% 63.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 10 0.02% 63.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 3 0.01% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 2 0.00% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5727 1 0.00% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 1 0.00% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5855 3 0.01% 63.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 5 0.01% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5983 1 0.00% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 1 0.00% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 7 0.02% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 1 0.00% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 4 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 3 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 2 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 20 0.05% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 3 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 3 0.01% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7007 1 0.00% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 4 0.01% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7135 1 0.00% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 4 0.01% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 4 0.01% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7519 1 0.00% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 3 0.01% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 1 0.00% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 7 0.02% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7775 1 0.00% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 2 0.00% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 3 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 3 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 11 0.03% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8479 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 1 0.00% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 18 0.04% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10527 2 0.00% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 2 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 1 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11807 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 3 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12511 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12831 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13087 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 2 0.00% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 5 0.01% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14495 1 0.00% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15839 1 0.00% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16991 1 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 4 0.01% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 5 0.01% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18399 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18719 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18816-18847 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18975 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19167 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 3 0.01% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19615 1 0.00% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20511 2 0.00% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21023 1 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21279 2 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21919 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22367 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 2 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24031 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24095 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24640-24671 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24799 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24863 1 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25311 1 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 2 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25887 2 0.00% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26271 1 0.00% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 3 0.01% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26911 1 0.00% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 3 0.01% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27743 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27935 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28191 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28639 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 2 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29599 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29727 3 0.01% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30303 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30495 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 3 0.01% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31007 2 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31967 1 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32031 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32159 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32543 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33055 2 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 1 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 6 0.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33631 2 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33695 1 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 44 0.10% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34591 2 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35231 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35871 2 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37535 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37919 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37983 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38943 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40287 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40735 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40991 3 0.01% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44575 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46111 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47647 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50207 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51231 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52255 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52992-53023 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53056-53087 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53760-53791 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54528-54559 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57344-57375 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57856-57887 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58399 2 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62495 1 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62528-62559 1 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65119 8 0.02% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65247 18 0.04% 65.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65375 12 0.03% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65503 12 0.03% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14415 34.05% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130816-130847 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 330 0.78% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::159168-159199 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160704-160735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192512-192543 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196416-196447 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 42332 # Bytes accessed per row activation -system.physmem.totQLat 352162436750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 443380465500 # Sum of mem lat for all requests -system.physmem.totBusLat 75504790000 # Total cycles spent in databus access -system.physmem.totBankLat 15713238750 # Total cycles spent in bank access -system.physmem.avgQLat 23320.54 # Average queueing delay per request -system.physmem.avgBankLat 1040.55 # Average bank access latency per request +system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation +system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests +system.physmem.totBusLat 75453215000 # Total cycles spent in databus access +system.physmem.totBankLat 15307050000 # Total cycles spent in bank access +system.physmem.avgQLat 19314.15 # Average queueing delay per request +system.physmem.avgBankLat 1014.34 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29361.08 # Average memory access latency -system.physmem.avgRdBW 381.35 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25328.49 # Average memory access latency +system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 10.77 # Average write queue length over time -system.physmem.readRowHits 15074158 # Number of row buffer hits during reads -system.physmem.writeRowHits 797610 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.09 # Row buffer hit rate for writes -system.physmem.avgGap 159247.75 # Average gap between requests +system.physmem.busUtil 3.15 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 14.41 # Average write queue length over time +system.physmem.readRowHits 15065383 # Number of row buffer hits during reads +system.physmem.writeRowHits 94229 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes +system.physmem.avgGap 158662.04 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -461,60 +440,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54715776 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16153842 # Transaction distribution -system.membus.trans_dist::ReadResp 16153842 # Transaction distribution -system.membus.trans_dist::WriteReq 763336 # Transaction distribution -system.membus.trans_dist::WriteResp 763336 # Transaction distribution -system.membus.trans_dist::Writeback 59144 # Transaction distribution +system.membus.throughput 54917647 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149440 # Transaction distribution +system.membus.trans_dist::ReadResp 16149440 # Transaction distribution +system.membus.trans_dist::WriteReq 763332 # Transaction distribution +system.membus.trans_dist::WriteResp 763332 # Transaction distribution +system.membus.trans_dist::Writeback 59118 # Transaction distribution system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4676 # Transaction distribution -system.membus.trans_dist::ReadExReq 131438 # Transaction distribution -system.membus.trans_dist::ReadExResp 131438 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution +system.membus.trans_dist::ReadExReq 131433 # Transaction distribution +system.membus.trans_dist::ReadExResp 131433 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29893152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29893152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 31779006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34165728 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095353 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119572608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119572608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 136270040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138667961 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138667961 # Total data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138629141 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475262000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17374745000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3634500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4718589198 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33742309741 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -522,15 +491,15 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48124265 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16129900 # Transaction distribution -system.iobus.trans_dist::ReadResp 16129887 # Transaction distribution -system.iobus.trans_dist::WriteReq 8158 # Transaction distribution -system.iobus.trans_dist::WriteResp 8158 # Transaction distribution +system.iobus.throughput 48301509 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution +system.iobus.trans_dist::WriteReq 8157 # Transaction distribution +system.iobus.trans_dist::WriteResp 8157 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -550,38 +519,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32276103 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -601,42 +546,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390313 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121962881 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121962881 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121927961 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -676,26 +597,26 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14946584000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374790000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40962341509 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14663186 # Number of BP lookups -system.cpu.branchPred.condPredicted 11751443 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703165 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9748962 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7940354 # Number of BTB hits +system.cpu.branchPred.lookups 14390442 # Number of BP lookups +system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.448199 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1396465 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72132 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987443 # DTB read hits -system.cpu.checker.dtb.read_misses 7307 # DTB read misses -system.cpu.checker.dtb.write_hits 11227745 # DTB write hits +system.cpu.checker.dtb.read_hits 14986742 # DTB read hits +system.cpu.checker.dtb.read_misses 7308 # DTB read misses +system.cpu.checker.dtb.write_hits 11227334 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -706,13 +627,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994750 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229934 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994050 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229523 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215188 # DTB hits -system.cpu.checker.dtb.misses 9496 # DTB misses -system.cpu.checker.dtb.accesses 26224684 # DTB accesses -system.cpu.checker.itb.inst_hits 61481774 # ITB inst hits +system.cpu.checker.dtb.hits 26214076 # DTB hits +system.cpu.checker.dtb.misses 9497 # DTB misses +system.cpu.checker.dtb.accesses 26223573 # DTB accesses +system.cpu.checker.itb.inst_hits 61479547 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -729,36 +650,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61486245 # ITB inst accesses -system.cpu.checker.itb.hits 61481774 # DTB hits +system.cpu.checker.itb.inst_accesses 61484018 # ITB inst accesses +system.cpu.checker.itb.hits 61479547 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61486245 # DTB accesses -system.cpu.checker.numCycles 77885129 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61484018 # DTB accesses +system.cpu.checker.numCycles 77882185 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51389107 # DTB read hits -system.cpu.dtb.read_misses 64168 # DTB read misses -system.cpu.dtb.write_hits 11699261 # DTB write hits -system.cpu.dtb.write_misses 15977 # DTB write misses +system.cpu.dtb.read_hits 51188083 # DTB read hits +system.cpu.dtb.read_misses 64353 # DTB read misses +system.cpu.dtb.write_hits 11697459 # DTB write hits +system.cpu.dtb.write_misses 15788 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6541 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2439 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6547 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51453275 # DTB read accesses -system.cpu.dtb.write_accesses 11715238 # DTB write accesses +system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51252436 # DTB read accesses +system.cpu.dtb.write_accesses 11713247 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63088368 # DTB hits -system.cpu.dtb.misses 80145 # DTB misses -system.cpu.dtb.accesses 63168513 # DTB accesses -system.cpu.itb.inst_hits 12244686 # ITB inst hits -system.cpu.itb.inst_misses 11272 # ITB inst misses +system.cpu.dtb.hits 62885542 # DTB hits +system.cpu.dtb.misses 80141 # DTB misses +system.cpu.dtb.accesses 62965683 # DTB accesses +system.cpu.itb.inst_hits 11520428 # ITB inst hits +system.cpu.itb.inst_misses 11439 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -767,114 +688,114 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4958 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4968 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2937 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12255958 # ITB inst accesses -system.cpu.itb.hits 12244686 # DTB hits -system.cpu.itb.misses 11272 # DTB misses -system.cpu.itb.accesses 12255958 # DTB accesses -system.cpu.numCycles 475312551 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11531867 # ITB inst accesses +system.cpu.itb.hits 11520428 # DTB hits +system.cpu.itb.misses 11439 # DTB misses +system.cpu.itb.accesses 11531867 # DTB accesses +system.cpu.numCycles 473080437 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30486466 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96013812 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14663186 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9336819 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21137847 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5287329 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121734 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94652697 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86418 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2672948 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 439 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12241258 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 862361 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5349 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152790281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.777398 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.141854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131667661 86.18% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302340 0.85% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711403 1.12% 88.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2491779 1.63% 89.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2204039 1.44% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109873 0.73% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2734812 1.79% 93.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 742969 0.49% 94.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8825405 5.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152790281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030850 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.202001 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32434469 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96765795 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19163623 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 968040 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3458354 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1955309 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172027 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112442167 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568180 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3458354 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34339332 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38106819 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52671042 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18167139 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6047595 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106212332 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004586 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4065982 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 631 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110697957 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485950395 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485859311 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91084 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390094 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32307862 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830633 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736877 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12210661 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20268413 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13492534 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1964739 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2435625 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97824738 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983401 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124295624 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165509 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21636439 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56320984 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501000 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152790281 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.528895 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108515921 71.02% 71.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13589329 8.89% 79.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7066338 4.62% 84.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5978859 3.91% 88.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12565558 8.22% 96.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2772936 1.81% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1725765 1.13% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 449060 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126515 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152790281 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62738 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available @@ -902,416 +823,416 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365929 94.58% 95.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 416628 4.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58652585 47.19% 47.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93247 0.08% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52864927 42.53% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319034 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124295624 # Type of FU issued -system.cpu.iq.rate 0.261503 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8845299 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071163 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 410448757 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121460975 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86059539 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23386 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12542 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10302 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132764827 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12430 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 625909 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued +system.cpu.iq.rate 0.259812 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4613851 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6375 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30092 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1760453 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107892 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 916935 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3458354 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29328857 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436741 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100030676 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203650 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20268413 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13492534 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410837 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 115234 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3326 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30092 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349264 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268145 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 617409 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121630045 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52076046 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2665579 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222537 # number of nop insts executed -system.cpu.iew.exec_refs 64287237 # number of memory reference insts executed -system.cpu.iew.exec_branches 11556571 # Number of branches executed -system.cpu.iew.exec_stores 12211191 # Number of stores executed -system.cpu.iew.exec_rate 0.255895 # Inst execution rate -system.cpu.iew.wb_sent 120479293 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86069841 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47268516 # num instructions producing a value -system.cpu.iew.wb_consumers 88195904 # num instructions consuming a value +system.cpu.iew.exec_nop 221034 # number of nop insts executed +system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed +system.cpu.iew.exec_branches 11474602 # Number of branches executed +system.cpu.iew.exec_stores 12209197 # Number of stores executed +system.cpu.iew.exec_rate 0.255417 # Inst execution rate +system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47030253 # num instructions producing a value +system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.181081 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535949 # average fanout of values written-back +system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21374007 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482401 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 533608 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149331927 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520650 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.508241 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121887208 81.62% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13290460 8.90% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3923979 2.63% 93.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2130804 1.43% 94.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1950357 1.31% 95.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968781 0.65% 96.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1543061 1.03% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 783043 0.52% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2854234 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149331927 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458154 # Number of instructions committed -system.cpu.commit.committedOps 77749702 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60455941 # Number of instructions committed +system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386643 # Number of memory references committed -system.cpu.commit.loads 15654562 # Number of loads committed -system.cpu.commit.membars 403601 # Number of memory barriers committed -system.cpu.commit.branches 9961356 # Number of branches committed +system.cpu.commit.refs 27385481 # Number of memory references committed +system.cpu.commit.loads 15653838 # Number of loads committed +system.cpu.commit.membars 403568 # Number of memory barriers committed +system.cpu.commit.branches 9961054 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854920 # Number of committed integer instructions. -system.cpu.commit.function_calls 991265 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2854234 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852229 # Number of committed integer instructions. +system.cpu.commit.function_calls 991205 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243752783 # The number of ROB reads -system.cpu.rob.rob_writes 201807644 # The number of ROB writes -system.cpu.timesIdled 1781061 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322522270 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593269077 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307773 # Number of Instructions Simulated -system.cpu.committedOps 77599321 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307773 # Number of Instructions Simulated -system.cpu.cpi 7.881448 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.881448 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126880 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126880 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550637147 # number of integer regfile reads -system.cpu.int_regfile_writes 88566596 # number of integer regfile writes -system.cpu.fp_regfile_reads 8370 # number of floating regfile reads -system.cpu.fp_regfile_writes 2906 # number of floating regfile writes -system.cpu.misc_regfile_reads 30124157 # number of misc regfile reads -system.cpu.misc_regfile_writes 831896 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58663468 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657447 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657446 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2983 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 245999 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 245999 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1961368 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5795761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126683 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7914273 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62726656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85494329 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 41328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 209684 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148471997 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148471997 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 200728 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128200875 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 239241509 # The number of ROB reads +system.cpu.rob.rob_writes 195965670 # The number of ROB writes +system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305560 # Number of Instructions Simulated +system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated +system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547265504 # number of integer regfile reads +system.cpu.int_regfile_writes 87536110 # number of integer regfile writes +system.cpu.fp_regfile_reads 8349 # number of floating regfile reads +system.cpu.fp_regfile_writes 2916 # number of floating regfile writes +system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads +system.cpu.misc_regfile_writes 831835 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474731013 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2562590429 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20135737 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74394752 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980590 # number of replacements -system.cpu.icache.tags.tagsinuse 511.580932 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11180201 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981102 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.395554 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6861342250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.580932 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11180201 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11180201 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11180201 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11180201 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11180201 # number of overall hits -system.cpu.icache.overall_hits::total 11180201 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060929 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060929 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060929 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060929 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060929 # number of overall misses -system.cpu.icache.overall_misses::total 1060929 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14286603183 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14286603183 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14286603183 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14286603183 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14286603183 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14286603183 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12241130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12241130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12241130 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12241130 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12241130 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12241130 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086669 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086669 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086669 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086669 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086669 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086669 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13466.125615 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13466.125615 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13466.125615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13466.125615 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8464 # number of cycles access was blocked +system.cpu.icache.tags.replacements 979660 # number of replacements +system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits +system.cpu.icache.overall_hits::total 10456897 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses +system.cpu.icache.overall_misses::total 1059959 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 385 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.984416 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79785 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79785 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79785 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79785 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79785 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79785 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981144 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981144 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981144 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981144 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981144 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981144 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11597968227 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11597968227 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11597968227 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11597968227 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11597968227 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11597968227 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9563750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9563750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9563750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 9563750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080151 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.080151 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.080151 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11820.862409 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11820.862409 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64396 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51354.796312 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1885755 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129794 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.528830 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2499257274500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36876.248148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 31.469348 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000368 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8188.920307 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6258.158141 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.562687 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000480 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 64363 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.183198 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.182382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563463 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000589 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124953 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095492 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783612 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52377 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10330 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 386975 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1417303 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607541 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607541 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 14 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112810 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112810 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52377 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10330 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 499785 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1530113 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52377 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10330 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 499785 # number of overall hits -system.cpu.l2cache.overall_hits::total 1530113 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 44 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124713 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095141 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.783907 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52355 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10525 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 966696 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387308 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1416884 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607864 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607864 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112905 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112905 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52355 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10525 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966696 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500213 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529789 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52355 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10525 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 966696 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500213 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529789 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12364 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10739 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23149 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2922 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2922 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133189 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133189 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 44 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23117 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2916 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2916 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133190 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133190 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12364 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143928 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156338 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 44 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143913 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156307 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12364 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143928 # number of overall misses -system.cpu.l2cache.overall_misses::total 156338 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4379500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143913 # number of overall misses +system.cpu.l2cache.overall_misses::total 156307 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4640000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 918927250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 809103750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1732540750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 487979 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 487979 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9125635499 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9125635499 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4379500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 910966750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 788627999 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1704364999 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395483 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 395483 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9130512743 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9130512743 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4640000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 918927250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9934739249 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10858176249 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4379500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 910966750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9919140742 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10834877742 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4640000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 918927250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9934739249 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10858176249 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52421 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10332 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397714 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440452 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607541 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607541 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 245999 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 245999 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52421 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10332 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979985 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643713 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686451 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52421 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10332 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979985 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643713 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686451 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000839 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000194 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012617 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.027002 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016071 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985165 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985165 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.176471 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.176471 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541421 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541421 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000839 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000194 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012617 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223590 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092702 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000839 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000194 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012617 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223590 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092702 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 99534.090909 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 910966750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9919140742 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10834877742 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52406 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10527 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 979037 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 398031 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1440001 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607864 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607864 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246095 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246095 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52406 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10527 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 979037 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 644126 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1686096 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52406 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10527 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979037 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 644126 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1686096 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000973 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012605 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026940 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016053 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986802 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986802 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.181818 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541214 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541214 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000973 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012605 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223424 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092703 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000973 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012605 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223424 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092703 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 90980.392157 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65125 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74322.812197 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75342.559829 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74843.006177 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 167.001711 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 167.001711 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68516.435284 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68516.435284 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 99534.090909 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73816.283121 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73545.462930 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73727.776052 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 135.625171 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 135.625171 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68552.539553 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68552.539553 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74322.812197 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69025.757664 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69453.211945 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 99534.090909 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69317.930368 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74322.812197 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69025.757664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69453.211945 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69317.930368 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1320,109 +1241,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59144 # number of writebacks -system.cpu.l2cache.writebacks::total 59144 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59118 # number of writebacks +system.cpu.l2cache.writebacks::total 59118 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 69 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 69 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 44 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12352 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10670 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23068 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2922 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2922 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133189 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133189 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 44 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12329 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10658 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23040 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2916 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133190 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133190 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12352 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156257 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 44 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12329 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143848 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156230 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12352 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156257 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3822500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12329 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143848 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156230 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3990500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 761684000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 670036500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1435648750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29223421 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29223421 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7438270001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7438270001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3822500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 754066500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 649417249 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1407579999 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29164415 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29164415 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7443119257 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7443119257 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3990500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 761684000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8108306501 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8873918751 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3822500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 754066500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8092536506 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8850699256 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3990500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 761684000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8108306501 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8873918751 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 7076250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166924302000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166931378250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26354291876 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26354291876 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 7076250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193278593876 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193285670126 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012604 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016014 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985165 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985165 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541421 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541421 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012604 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223483 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092654 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012604 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223483 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092654 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 86875 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 754066500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8092536506 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8850699256 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6234999 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166923461500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166929696499 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17446167056 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17446167056 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6234999 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184369628556 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184375863555 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026777 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986802 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986802 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541214 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541214 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092658 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092658 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61664.831606 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62796.298032 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62235.510231 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.170773 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.170773 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61162.016384 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60932.374648 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61092.881901 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.514060 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.514060 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55847.479904 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55847.479904 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 86875 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61664.831606 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56362.872681 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56790.535790 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 86875 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61664.831606 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56362.872681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56790.535790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1432,161 +1353,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643201 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.992056 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21499493 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643713 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.399190 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 48741250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.992056 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13746666 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13746666 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259188 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259188 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242891 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242891 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247601 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247601 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21005854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21005854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21005854 # number of overall hits -system.cpu.dcache.overall_hits::total 21005854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 736262 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 736262 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963161 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963161 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13548 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13548 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699423 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699423 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699423 # number of overall misses -system.cpu.dcache.overall_misses::total 3699423 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10077942358 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10077942358 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134690017209 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134690017209 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184520250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184520250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 258503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 258503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144767959567 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144767959567 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144767959567 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144767959567 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14482928 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14482928 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256439 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256439 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247618 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247618 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24705277 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24705277 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24705277 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24705277 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050837 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050837 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289871 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289871 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052831 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052831 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149742 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149742 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149742 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149742 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13687.983840 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13687.983840 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45454.842720 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45454.842720 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13619.740921 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13619.740921 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15206.058824 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15206.058824 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39132.578126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39132.578126 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32140 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 25391 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2640 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 284 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.174242 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.404930 # average number of cycles each access was blocked +system.cpu.dcache.tags.replacements 643614 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits +system.cpu.dcache.overall_hits::total 21018772 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses +system.cpu.dcache.overall_misses::total 3700946 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607541 # number of writebacks -system.cpu.dcache.writebacks::total 607541 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350669 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350669 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714279 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714279 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064948 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064948 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064948 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064948 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385593 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385593 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248882 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248882 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12204 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12204 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634475 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634475 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634475 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634475 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967192840 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967192840 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10605079278 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10605079278 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144959500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144959500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 224497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 224497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15572272118 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15572272118 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15572272118 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15572272118 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182317512000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182317512000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35728890492 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35728890492 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218046402492 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 218046402492 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024347 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024347 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.958023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.958023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42610.872936 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42610.872936 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11878.031793 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11878.031793 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13205.705882 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13205.705882 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks +system.cpu.dcache.writebacks::total 607864 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1594,12 +1515,12 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1608,16 +1529,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1486035968259 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 5451e0c81..0edabf3c5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,150 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.114023 # Number of seconds simulated -sim_ticks 1114022852000 # Number of ticks simulated -final_tick 1114022852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.104038 # Number of seconds simulated +sim_ticks 1104038330000 # Number of ticks simulated +final_tick 1104038330000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79652 # Simulator instruction rate (inst/s) -host_op_rate 102538 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1440387686 # Simulator tick rate (ticks/s) -host_mem_usage 404604 # Number of bytes of host memory used -host_seconds 773.42 # Real time elapsed on the host -sim_insts 61604368 # Number of instructions simulated -sim_ops 79304455 # Number of ops (including micro ops) simulated +host_inst_rate 80920 # Simulator instruction rate (inst/s) +host_op_rate 104171 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1450259542 # Simulator tick rate (ticks/s) +host_mem_usage 402880 # Number of bytes of host memory used +host_seconds 761.27 # Real time elapsed on the host +sim_insts 61602211 # Number of instructions simulated +sim_ops 79302243 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4367220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 410368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory -system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4263872 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory +system.physmem.bytes_read::total 59194084 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 410368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 816192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7291216 # Number of bytes written to this memory +system.physmem.bytes_written::total 7294544 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66623 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257998 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66675 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823459 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43768208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 367504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3920225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 364632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4710438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53132845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 367504 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 364632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 732136 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3827455 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15260 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2702228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6544943 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3827455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43768208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 367504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3935485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 364632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7412667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59677788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257953 # Total number of read requests seen -system.physmem.writeReqs 823459 # Total number of write requests seen -system.physmem.cpureqs 242171 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400508992 # Total number of bytes read from memory -system.physmem.bytesWritten 52701376 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7291216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12548 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391049 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 391102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391825 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 391535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 391243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391065 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 391482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 390299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 390904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 391045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391022 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49928 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51967 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51963 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 52290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51872 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51692 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51908 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51308 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51011 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51134 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51585 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51529 # Track writes on a per bank basis +system.physmem.num_writes::total 823511 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44164032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 371697 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3955272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4755646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53615968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 371697 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367581 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3865083 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2726666 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6607147 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3865083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44164032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 371697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3970670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7482313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60223116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257998 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 823511 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 6257998 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 823511 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 400511872 # Total number of bytes read from memory +system.physmem.bytesWritten 52704704 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59194084 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7294544 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 4191 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 12574 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391051 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 391031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 390511 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391821 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 391470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 391242 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 390250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 391418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 389084 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 390982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 391146 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 389937 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7210 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7320 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7294 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7815 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7419 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7389 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7204 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7511 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7529 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6626 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7294 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7205 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32580 # Number of times wr buffer was full causing retry -system.physmem.totGap 1114021721000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1104037196000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163000 # Categorize read packet sizes +system.physmem.readPktSize::6 163045 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66623 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 508306 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 436400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 409055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1494610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1111724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1109849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1096192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 11963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 16960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 11777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8816 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 12128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5024 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66675 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 510579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 438231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 410611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1497375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1129368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1114937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1085131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 10318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 12945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 12334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,366 +161,312 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32597 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38811 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11677.106800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 598.829081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 25969.144286 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 10478 27.00% 27.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 4256 10.97% 37.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2718 7.00% 44.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 2024 5.22% 50.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1422 3.66% 53.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1213 3.13% 56.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 997 2.57% 59.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 905 2.33% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 654 1.69% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 573 1.48% 65.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 456 1.17% 66.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 470 1.21% 67.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 308 0.79% 68.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 261 0.67% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 192 0.49% 69.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 284 0.73% 70.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 136 0.35% 70.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 144 0.37% 70.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 111 0.29% 71.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 147 0.38% 71.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 83 0.21% 71.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 412 1.06% 72.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 1956 5.04% 77.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 510 1.31% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 94 0.24% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 178 0.46% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 53 0.14% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 122 0.31% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 38 0.10% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 83 0.21% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 40 0.10% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 68 0.18% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 23 0.06% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 47 0.12% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 17 0.04% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 43 0.11% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 13 0.03% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 28 0.07% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 13 0.03% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 25 0.06% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 10 0.03% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 18 0.05% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 7 0.02% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 19 0.05% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 4 0.01% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 20 0.05% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.02% 81.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 20 0.05% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 6 0.02% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 9 0.02% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 7 0.02% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 18 0.05% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 3 0.01% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 11 0.03% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 6 0.02% 81.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 12 0.03% 81.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 6 0.02% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 2 0.01% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 6 0.02% 81.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 7 0.02% 81.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 5 0.01% 81.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 10 0.03% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 2 0.01% 81.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 40 0.10% 82.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 1 0.00% 82.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 7 0.02% 82.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 2 0.01% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 5 0.01% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 3 0.01% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 4 0.01% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 3 0.01% 82.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 9 0.02% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 1 0.00% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 2 0.01% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 2 0.01% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 2 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 2 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 5 0.01% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5087 1 0.00% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 7 0.02% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 4 0.01% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 2 0.01% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 2 0.01% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.01% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 2 0.01% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 2 0.01% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5599 3 0.01% 82.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 3 0.01% 82.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5727 2 0.01% 82.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 1 0.00% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5855 1 0.00% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 2 0.01% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5983 2 0.01% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 3 0.01% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 2 0.01% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 5 0.01% 82.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 3 0.01% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 4 0.01% 82.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6367 2 0.01% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 4 0.01% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 1 0.00% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 1 0.00% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 1 0.00% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 2 0.01% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 2 0.01% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 14 0.04% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 3 0.01% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 3 0.01% 82.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7007 2 0.01% 82.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 2 0.01% 82.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 3 0.01% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7263 1 0.00% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 1 0.00% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 6 0.02% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7519 1 0.00% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 4 0.01% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 6 0.02% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7775 2 0.01% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 2 0.01% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 2 0.01% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 7 0.02% 82.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 82.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 7 0.02% 82.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 316 0.81% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8287 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 2 0.01% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 5 0.01% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9375 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9503 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9695 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10015 2 0.01% 83.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 15 0.04% 83.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10399 1 0.00% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10527 1 0.00% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10783 1 0.00% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11039 3 0.01% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 3 0.01% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11807 2 0.01% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12063 1 0.00% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 5 0.01% 83.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 1 0.00% 83.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12831 2 0.01% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12895 1 0.00% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13087 1 0.00% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 2 0.01% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13535 1 0.00% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13599 1 0.00% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 4 0.01% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15135 3 0.01% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 1 0.00% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15455 1 0.00% 83.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15775 1 0.00% 83.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16671 3 0.01% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17183 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 1 0.00% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17375 1 0.00% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 2 0.01% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17695 2 0.01% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17759 1 0.00% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-18015 1 0.00% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18207 3 0.01% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18591 1 0.00% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18719 2 0.01% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18975 2 0.01% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19231 1 0.00% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 4 0.01% 83.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19615 1 0.00% 83.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19999 3 0.01% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20127 1 0.00% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20255 1 0.00% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20511 12 0.03% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20767 1 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21279 1 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 2 0.01% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21791 1 0.00% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21952-21983 2 0.01% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22047 1 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 4 0.01% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22687 1 0.00% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22815 3 0.01% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23327 1 0.00% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 1 0.00% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24031 1 0.00% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24095 2 0.01% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24223 1 0.00% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 1 0.00% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 2 0.01% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24735 2 0.01% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25375 1 0.00% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25408-25439 1 0.00% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 2 0.01% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25887 1 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26079 1 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26143 4 0.01% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26335 1 0.00% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27167 3 0.01% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27423 2 0.01% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27487 1 0.00% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 2 0.01% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27935 1 0.00% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 2 0.01% 83.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30495 1 0.00% 83.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30559 1 0.00% 83.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 3 0.01% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30943 1 0.00% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31007 2 0.01% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31071 1 0.00% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 2 0.01% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31808-31839 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32192-32223 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32415 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32543 2 0.01% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32799 2 0.01% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 1 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33375 1 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 5 0.01% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33631 2 0.01% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33695 3 0.01% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33759 2 0.01% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 43 0.11% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34496-34527 1 0.00% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34847 2 0.01% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35167 1 0.00% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35871 1 0.00% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36127 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36288-36319 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36383 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37824-37855 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37919 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38175 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39263 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39455 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39519 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40287 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40832-40863 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40991 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41503 2 0.01% 84.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41664-41695 1 0.00% 84.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42271 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43039 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44127 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45599 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46111 2 0.01% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46367 2 0.01% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46879 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-47007 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48671 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48927 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49183 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49472-49503 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51231 2 0.01% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51776-51807 1 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52255 2 0.01% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54528-54559 2 0.01% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54784-54815 1 0.00% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56064-56095 1 0.00% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56351 1 0.00% 84.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57280-57311 1 0.00% 84.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57600-57631 2 0.01% 84.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57792-57823 1 0.00% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57856-57887 1 0.00% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58624-58655 1 0.00% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59840-59871 1 0.00% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59968-59999 1 0.00% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60447 1 0.00% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61471 4 0.01% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62208-62239 1 0.00% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62400-62431 1 0.00% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62495 1 0.00% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63519 2 0.01% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63744-63775 1 0.00% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64543 1 0.00% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65183 6 0.02% 84.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 6 0.02% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65439 1 0.00% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 5797 14.94% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129920-129951 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130880-130911 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 326 0.84% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132127 2 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::133632-133663 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::165568-165599 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::169728-169759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::175552-175583 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::189440-189471 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 6 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38811 # Bytes accessed per row activation -system.physmem.totQLat 182252409750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 221627859750 # Sum of mem lat for all requests -system.physmem.totBusLat 31289130000 # Total cycles spent in databus access -system.physmem.totBankLat 8086320000 # Total cycles spent in bank access -system.physmem.avgQLat 29123.92 # Average queueing delay per request -system.physmem.avgBankLat 1292.19 # Average bank access latency per request +system.physmem.wrQLenPdf::0 5005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 35262 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11560.822642 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 608.575977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 24356.197009 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-79 8749 24.81% 24.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-143 4356 12.35% 37.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-207 2652 7.52% 44.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-271 2010 5.70% 50.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-335 1437 4.08% 54.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-399 1214 3.44% 57.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-463 927 2.63% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-527 1120 3.18% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-591 659 1.87% 65.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-655 617 1.75% 67.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-719 450 1.28% 68.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-783 454 1.29% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-847 302 0.86% 70.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-911 302 0.86% 71.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-975 179 0.51% 72.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1039 219 0.62% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1103 133 0.38% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1167 156 0.44% 73.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1231 97 0.28% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1295 134 0.38% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1359 73 0.21% 74.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1423 395 1.12% 75.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1487 262 0.74% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1551 538 1.53% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1615 109 0.31% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1679 178 0.50% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1743 51 0.14% 78.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1807 128 0.36% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1871 49 0.14% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1935 68 0.19% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1999 39 0.11% 79.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2063 74 0.21% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2127 17 0.05% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2191 56 0.16% 79.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2255 22 0.06% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2319 30 0.09% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2383 13 0.04% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2447 29 0.08% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2511 10 0.03% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2575 19 0.05% 80.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2639 9 0.03% 80.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2703 17 0.05% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2767 7 0.02% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2831 14 0.04% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2895 6 0.02% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2959 10 0.03% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3023 4 0.01% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3087 17 0.05% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3151 3 0.01% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3215 15 0.04% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3279 4 0.01% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3343 7 0.02% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3407 9 0.03% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3471 11 0.03% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3535 3 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3599 7 0.02% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3663 3 0.01% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3727 11 0.03% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3791 3 0.01% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3855 4 0.01% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3919 5 0.01% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3983 13 0.04% 80.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4047 3 0.01% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4111 28 0.08% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4175 4 0.01% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4239 7 0.02% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4303 4 0.01% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4367 3 0.01% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4431 1 0.00% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4495 6 0.02% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4559 4 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4623 2 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4687 1 0.00% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4751 1 0.00% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4815 6 0.02% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4879 4 0.01% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4943 5 0.01% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5007 3 0.01% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5135 4 0.01% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5199 4 0.01% 81.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5263 2 0.01% 81.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5327 1 0.00% 81.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5391 5 0.01% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5455 1 0.00% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5519 1 0.00% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5583 4 0.01% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5647 3 0.01% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5711 1 0.00% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5775 4 0.01% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5839 1 0.00% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5903 2 0.01% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6031 2 0.01% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6095 1 0.00% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6159 2 0.01% 81.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6223 3 0.01% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6287 2 0.01% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6351 3 0.01% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6415 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6479 3 0.01% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6543 1 0.00% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6671 2 0.01% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6735 2 0.01% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6799 16 0.05% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6863 3 0.01% 81.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6927 5 0.01% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6991 3 0.01% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7055 1 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7183 8 0.02% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7247 1 0.00% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7311 1 0.00% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7439 3 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7567 5 0.01% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7631 2 0.01% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7695 3 0.01% 81.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7759 2 0.01% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7823 1 0.00% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7887 4 0.01% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7951 6 0.02% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8015 1 0.00% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8079 7 0.02% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8143 5 0.01% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8207 318 0.90% 82.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8399 1 0.00% 82.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8463 41 0.12% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8527 122 0.35% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8591 8 0.02% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8719 1 0.00% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8783 3 0.01% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9231 3 0.01% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9487 1 0.00% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9743 2 0.01% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9999 1 0.00% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10255 2 0.01% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10767 2 0.01% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11023 1 0.00% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11279 2 0.01% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11535 2 0.01% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12047 2 0.01% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12303 1 0.00% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12751 1 0.00% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13071 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13583 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13839 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14351 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14607 1 0.00% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15375 2 0.01% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15631 1 0.00% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16399 2 0.01% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16527 1 0.00% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17423 3 0.01% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17679 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17935 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18447 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18895 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19151 1 0.00% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19215 1 0.00% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19727 1 0.00% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19904-19919 1 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20239 1 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20495 2 0.01% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20928-20943 1 0.00% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21007 2 0.01% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21327 1 0.00% 83.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21519 2 0.01% 83.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22031 1 0.00% 83.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22543 3 0.01% 83.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23567 1 0.00% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23823 1 0.00% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24143 1 0.00% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24591 4 0.01% 83.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24847 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25024-25039 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25103 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25359 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26319 1 0.00% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26383 1 0.00% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26639 1 0.00% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26703 1 0.00% 83.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27215 1 0.00% 83.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27407 1 0.00% 83.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27663 2 0.01% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27983 1 0.00% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28111 1 0.00% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28687 3 0.01% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29455 1 0.00% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29711 1 0.00% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29967 3 0.01% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30415 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30479 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30735 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31247 2 0.01% 83.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31759 3 0.01% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32015 1 0.00% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32271 1 0.00% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32527 1 0.00% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32655 1 0.00% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32783 2 0.01% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32911 1 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33039 1 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33295 1 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33551 9 0.03% 83.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33615 9 0.03% 83.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33679 3 0.01% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33743 3 0.01% 83.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33807 23 0.07% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36879 1 0.00% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37583 1 0.00% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37903 2 0.01% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39247 1 0.00% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39695 1 0.00% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42767 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43535 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44239 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44559 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45583 1 0.00% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46400-46415 1 0.00% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46863 1 0.00% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47119 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47247 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47311 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47439 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47887 1 0.00% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48143 2 0.01% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48335 2 0.01% 83.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49039 1 0.00% 83.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49615 1 0.00% 83.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49935 1 0.00% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52864-52879 1 0.00% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53504-53519 1 0.00% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54287 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54464-54479 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54784-54799 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58383 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60160-60175 1 0.00% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60672-60687 1 0.00% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60928-60943 1 0.00% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64527 1 0.00% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65039 10 0.03% 83.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65423 6 0.02% 83.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65551 5666 16.07% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::68672-68687 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::69120-69135 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::72128-72143 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73088-73103 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73935 20 0.06% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-73999 91 0.26% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74048-74063 61 0.17% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74112-74127 4 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 35262 # Bytes accessed per row activation +system.physmem.totQLat 121597245250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 160506894000 # Sum of mem lat for all requests +system.physmem.totBusLat 31269035000 # Total cycles spent in databus access +system.physmem.totBankLat 7640613750 # Total cycles spent in bank access +system.physmem.avgQLat 19443.72 # Average queueing delay per request +system.physmem.avgBankLat 1221.75 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35416.11 # Average memory access latency -system.physmem.avgRdBW 359.52 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.31 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.13 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.54 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25665.47 # Average memory access latency +system.physmem.avgRdBW 362.77 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.74 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.62 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.18 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 11.52 # Average write queue length over time -system.physmem.readRowHits 6237911 # Number of row buffer hits during reads -system.physmem.writeRowHits 804550 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes -system.physmem.avgGap 157316.33 # Average gap between requests +system.physmem.busUtil 3.21 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 12.74 # Average write queue length over time +system.physmem.readRowHits 6235456 # Number of row buffer hits during reads +system.physmem.writeRowHits 98940 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 12.01 # Row buffer hit rate for writes +system.physmem.avgGap 155904.23 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -525,307 +476,309 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 57 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 345 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 402 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 57 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 345 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 402 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 57 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 345 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 402 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 61845817 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306747 # Transaction distribution -system.membus.trans_dist::ReadResp 7306747 # Transaction distribution -system.membus.trans_dist::WriteReq 767893 # Transaction distribution -system.membus.trans_dist::WriteResp 767893 # Transaction distribution -system.membus.trans_dist::Writeback 66623 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33809 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17757 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12548 # Transaction distribution -system.membus.trans_dist::ReadExReq 138043 # Transaction distribution -system.membus.trans_dist::ReadExResp 137663 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382510 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 62410733 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306749 # Transaction distribution +system.membus.trans_dist::ReadResp 7306749 # Transaction distribution +system.membus.trans_dist::WriteReq 767894 # Transaction distribution +system.membus.trans_dist::WriteResp 767894 # Transaction distribution +system.membus.trans_dist::Writeback 66675 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33869 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17715 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12574 # Transaction distribution +system.membus.trans_dist::ReadExReq 138085 # Transaction distribution +system.membus.trans_dist::ReadExResp 137703 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382522 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1970999 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11642 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 850 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971187 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366211 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 14160695 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 11650 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.local_cpu_timer.pio 850 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555723 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389777 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16555907 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389789 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17723636 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23300 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23284 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1700 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20138869 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729844 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20145057 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2389777 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 66482420 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 23300 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1700 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68897653 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68897653 # Total data (bytes) +system.membus.tot_pkt_size::total 68903841 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68903841 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475761000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475612500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 8620588249 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) -system.membus.reqLayer3.occupancy 9828000 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9865000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 750000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 756000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4823074562 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8618805999 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4854602214 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13762899732 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13760099489 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 72713 # number of replacements -system.l2c.tags.tagsinuse 53848.744123 # Cycle average of tags in use -system.l2c.tags.total_refs 1839089 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137893 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.337073 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39490.919089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.921030 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000842 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4011.444595 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2831.104153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.348710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3706.565293 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3793.440412 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.602584 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000090 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061210 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043199 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056558 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057883 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821667 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22072 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4261 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386985 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166655 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 31010 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5009 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 589730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198052 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403774 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581377 # number of Writeback hits -system.l2c.Writeback_hits::total 581377 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1341 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 735 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2076 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 150 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 360 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48293 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58659 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106952 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22072 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4261 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386985 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214948 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 31010 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5009 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 589730 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256711 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510726 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22072 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4261 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386985 # number of overall hits -system.l2c.overall_hits::cpu0.data 214948 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 31010 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5009 # number of overall hits -system.l2c.overall_hits::cpu1.inst 589730 # number of overall hits -system.l2c.overall_hits::cpu1.data 256711 # number of overall hits -system.l2c.overall_hits::total 1510726 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6279 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6380 # number of ReadReq misses +system.l2c.tags.replacements 72758 # number of replacements +system.l2c.tags.tagsinuse 53808.125296 # Cycle average of tags in use +system.l2c.tags.total_refs 1836602 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 137939 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.314596 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 39514.415699 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.446892 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257540 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4002.916228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2827.365052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.413975 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.918976 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3679.171285 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3769.219649 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.602942 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000068 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061080 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043142 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056140 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.057514 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.821047 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21860 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4237 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386435 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166509 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30879 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4932 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 588366 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198248 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1401466 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581263 # number of Writeback hits +system.l2c.Writeback_hits::total 581263 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1335 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 743 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2078 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 202 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 141 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 343 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48314 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58639 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106953 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 21860 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4237 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 386435 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214823 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30879 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4932 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 588366 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256887 # number of demand (read+write) hits +system.l2c.demand_hits::total 1508419 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 21860 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4237 # number of overall hits +system.l2c.overall_hits::cpu0.inst 386435 # number of overall hits +system.l2c.overall_hits::cpu0.data 214823 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30879 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4932 # number of overall hits +system.l2c.overall_hits::cpu1.inst 588366 # number of overall hits +system.l2c.overall_hits::cpu1.data 256887 # number of overall hits +system.l2c.overall_hits::total 1508419 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6295 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6381 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6315 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6308 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 6244 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25250 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5158 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3783 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8941 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 636 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 418 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1054 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63263 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76953 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140216 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6279 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69643 # number of demand (read+write) misses +system.l2c.ReadReq_misses::total 25258 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5140 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3782 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8922 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 633 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 424 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63292 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 77006 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140298 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6295 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69673 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6315 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83197 # number of demand (read+write) misses -system.l2c.demand_misses::total 165466 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6279 # number of overall misses -system.l2c.overall_misses::cpu0.data 69643 # number of overall misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6308 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83250 # number of demand (read+write) misses +system.l2c.demand_misses::total 165556 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6295 # number of overall misses +system.l2c.overall_misses::cpu0.data 69673 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6315 # number of overall misses -system.l2c.overall_misses::cpu1.data 83197 # number of overall misses -system.l2c.overall_misses::total 165466 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1558000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 130250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 460466000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 469540999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1630500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 488082250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 485700250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1907108249 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 9003592 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12282479 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21286071 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 512478 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3025371 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3537849 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4258752123 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5521303068 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9780055191 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1558000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 130250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 460466000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4728293122 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1630500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 488082250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6007003318 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11687163440 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1558000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 130250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 460466000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4728293122 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1630500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 488082250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6007003318 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11687163440 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 22088 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4263 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 393264 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 173035 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 31024 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5009 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 596045 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 204296 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1429024 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 581377 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 581377 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6499 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4518 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11017 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 846 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 568 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1414 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135612 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247168 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 22088 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4263 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 393264 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 284591 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 31024 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5009 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 596045 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 339908 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1676192 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 22088 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4263 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 393264 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 284591 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 31024 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5009 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 596045 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 339908 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1676192 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000724 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000469 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015966 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036871 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010595 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030563 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017669 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.793661 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.837317 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.811564 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.751773 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.735915 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.745403 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.567096 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.567450 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.567290 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000724 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000469 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015966 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244713 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010595 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.244763 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098715 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000724 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000469 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015966 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244713 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000451 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010595 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.244763 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098715 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 97375 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 65125 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73334.288900 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73595.767868 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 116464.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77289.350752 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 77786.715247 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 75529.039564 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1745.558744 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3246.756278 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2380.725981 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 805.783019 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7237.729665 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3356.592979 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67318.213221 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71749.029512 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69749.922912 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 97375 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 73334.288900 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 67893.300432 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 116464.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 77289.350752 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 72202.162554 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 70631.812215 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 97375 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 73334.288900 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 67893.300432 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 116464.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 77289.350752 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 72202.162554 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 70631.812215 # average overall miss latency +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6308 # number of overall misses +system.l2c.overall_misses::cpu1.data 83250 # number of overall misses +system.l2c.overall_misses::total 165556 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 956500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 219500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 459403500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 469850249 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1252250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 486933250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 475323500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1894027999 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8999593 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12092485 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 21092078 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 513478 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 3097867 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3611345 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4257399342 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5547277314 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9804676656 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 956500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 219500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 459403500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4727249591 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1252250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 89250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 486933250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6022600814 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11698704655 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 956500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 219500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 459403500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4727249591 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1252250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 89250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 486933250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6022600814 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11698704655 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 21872 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4240 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 392730 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 172890 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30893 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 4933 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 594674 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 204492 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1426724 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 581263 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 581263 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6475 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4525 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 11000 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 835 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 565 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1400 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111606 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135645 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247251 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 21872 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4240 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 392730 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 284496 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30893 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 4933 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 594674 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 340137 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1673975 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 21872 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4240 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 392730 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 284496 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30893 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 4933 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 594674 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 340137 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1673975 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000549 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000708 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016029 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036908 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000453 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000203 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010607 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030534 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017703 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.793822 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835801 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.811091 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.758084 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.750442 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.755000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.567102 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.567702 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.567431 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000549 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000708 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016029 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.244900 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000453 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000203 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010607 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.244754 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098900 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000549 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000708 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016029 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.244900 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000453 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000203 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010607 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.244754 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098900 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79708.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 73166.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72979.110405 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 73632.698480 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89446.428571 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77192.969245 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 76124.839846 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 74987.251524 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1750.893580 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3197.378371 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2364.052679 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 811.181675 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7306.290094 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3416.598865 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67265.994786 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72036.949251 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 69884.650216 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79708.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 73166.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 72979.110405 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 67849.089188 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89446.428571 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 77192.969245 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 72343.553321 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 70663.127008 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79708.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 73166.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 72979.110405 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 67849.089188 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89446.428571 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 77192.969245 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 72343.553321 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 70663.127008 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -834,168 +787,180 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66623 # number of writebacks -system.l2c.writebacks::total 66623 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 26 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 26 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 26 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 16 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6276 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6343 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 66675 # number of writebacks +system.l2c.writebacks::total 66675 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 27 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 27 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 27 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 77 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 12 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6291 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6342 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6307 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6218 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25176 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5158 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3783 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8941 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 636 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 418 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1054 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63263 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76953 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140216 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 16 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6276 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69606 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6301 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6217 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25181 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5140 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3782 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8922 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 633 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 424 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1057 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63292 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 77006 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140298 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 12 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6291 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69634 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6307 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83171 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165392 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 16 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6276 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69606 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6301 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 83223 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165479 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 12 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6291 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69634 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6307 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83171 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165392 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1354500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 105750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 380765750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 387112499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1453000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 407670750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 405239750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1583701999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51696595 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 37937764 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 89634359 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6384131 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4197915 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10582046 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3459046363 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4543162420 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8002208783 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1354500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 105750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 380765750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3846158862 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1453000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 407670750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4948402170 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9585910782 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1354500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 105750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 380765750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3846158862 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1453000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 407670750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4948402170 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9585910782 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 7151250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399747242 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6301 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 83223 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165479 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 805500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 182000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 379474750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 387080999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1074250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 406686000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 393745000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1569124749 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51534074 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 37985753 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 89519827 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6330633 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4257919 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10588552 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3457418648 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4568436180 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8025854828 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 805500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 182000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 379474750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3844499647 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1074250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 406686000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4962181180 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9594979577 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 805500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 182000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 379474750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3844499647 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1074250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 406686000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4962181180 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9594979577 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6406999 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399719988 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2451249 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154593597491 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167002947232 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1054895750 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25482276685 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 26537172435 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7151250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13454642992 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154593049986 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167001628222 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1006386499 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16503554515 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17509941014 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6406999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13406106487 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2451249 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180075874176 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 193540119667 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000724 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000469 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036657 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010581 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030436 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017618 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.793661 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.837317 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.811564 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.751773 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735915 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.745403 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567096 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567450 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.567290 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000724 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000469 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244583 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010581 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244687 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098671 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000724 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000469 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244583 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010581 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244687 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098671 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61029.875296 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65172.040849 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62905.227161 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.604692 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.486386 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.093278 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.941824 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.858852 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.891841 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54677.242037 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59038.145621 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 57070.582409 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55256.139729 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57958.733083 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55256.139729 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57958.733083 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171096604501 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184511569236 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036682 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030402 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017650 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.793822 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835801 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.811091 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.758084 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750442 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567102 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567702 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567431 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244763 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244675 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098854 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244763 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244675 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098854 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61034.531536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63333.601415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62313.837775 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10026.084436 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10043.826811 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.605358 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.261792 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10017.551561 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54626.471718 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59325.717217 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57205.767923 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1016,64 +981,64 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 135543504 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2708876 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2708875 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767893 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767893 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581377 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33332 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18117 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51449 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258856 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258856 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 787342 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073883 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13468 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 55968 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1192763 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4801194 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 14594 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 72477 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 8011689 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25176640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34854805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 17052 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 88352 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 38149824 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 47763808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 20036 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 124096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 146194613 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146194613 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4803948 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4894718895 # Layer occupancy (ticks) +system.toL2Bus.throughput 136659470 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2706207 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2706206 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 581263 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33352 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18058 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51410 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258939 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258939 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 786305 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13268 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55413 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1190023 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801593 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14394 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72130 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8006701 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25142464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34843867 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38062080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47776006 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 19732 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 123572 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146072169 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146072169 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4805124 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4892877936 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1774755611 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1772488367 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1516721983 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1516304011 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9224710 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9043467 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34035182 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 33687702 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2687171756 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2681029210 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3246383092 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 3243394678 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9605952 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 9483701 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41732428 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41522672 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45913386 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution -system.iobus.trans_dist::WriteReq 7946 # Transaction distribution -system.iobus.trans_dist::WriteResp 7946 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes) +system.iobus.throughput 46328621 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278159 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278159 # Transaction distribution +system.iobus.trans_dist::WriteReq 7950 # Transaction distribution +system.iobus.trans_dist::WriteResp 7950 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) @@ -1093,38 +1058,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382510 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572206 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 14572218 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16052 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) @@ -1144,42 +1085,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389777 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389789 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148561 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148561 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 51148573 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148573 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4018000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4019000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 369000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 368000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1220,43 +1137,43 @@ system.iobus.reqLayer22.utilization 0.0 # La system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374564000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374572000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16693526268 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16699589511 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6007013 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4581243 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296095 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3784394 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2916091 # Number of BTB hits +system.cpu0.branchPred.lookups 6002321 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4576737 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295742 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3785758 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2914394 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.055692 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673819 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28621 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.983104 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673290 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28745 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8911671 # DTB read hits -system.cpu0.dtb.read_misses 28579 # DTB read misses -system.cpu0.dtb.write_hits 5140325 # DTB write hits -system.cpu0.dtb.write_misses 5457 # DTB write misses +system.cpu0.dtb.read_hits 8907919 # DTB read hits +system.cpu0.dtb.read_misses 28331 # DTB read misses +system.cpu0.dtb.write_hits 5140728 # DTB write hits +system.cpu0.dtb.write_misses 5464 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 935 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1828 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 958 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 555 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8940250 # DTB read accesses -system.cpu0.dtb.write_accesses 5145782 # DTB write accesses +system.cpu0.dtb.perms_faults 551 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8936250 # DTB read accesses +system.cpu0.dtb.write_accesses 5146192 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14051996 # DTB hits -system.cpu0.dtb.misses 34036 # DTB misses -system.cpu0.dtb.accesses 14086032 # DTB accesses -system.cpu0.itb.inst_hits 4224524 # ITB inst hits -system.cpu0.itb.inst_misses 5106 # ITB inst misses +system.cpu0.dtb.hits 14048647 # DTB hits +system.cpu0.dtb.misses 33795 # DTB misses +system.cpu0.dtb.accesses 14082442 # DTB accesses +system.cpu0.itb.inst_hits 4222709 # ITB inst hits +system.cpu0.itb.inst_misses 5005 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1265,534 +1182,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1346 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1348 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1478 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1494 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4229630 # ITB inst accesses -system.cpu0.itb.hits 4224524 # DTB hits -system.cpu0.itb.misses 5106 # DTB misses -system.cpu0.itb.accesses 4229630 # DTB accesses -system.cpu0.numCycles 69191123 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4227714 # ITB inst accesses +system.cpu0.itb.hits 4222709 # DTB hits +system.cpu0.itb.misses 5005 # DTB misses +system.cpu0.itb.accesses 4227714 # DTB accesses +system.cpu0.numCycles 69175889 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11726999 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32040106 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6007013 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3589910 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7522223 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1454890 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60839 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19594371 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47034 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1322790 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4222942 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157135 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2060 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41323427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.001891 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.382270 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11717201 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32026454 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6002321 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3587684 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7519324 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1452827 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60860 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19607589 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5035 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47006 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1325879 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 324 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4221110 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157905 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2000 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41325646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.001484 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.381957 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33808589 81.81% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565594 1.37% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 817189 1.98% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676917 1.64% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 774557 1.87% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 561158 1.36% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 668023 1.62% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352527 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098873 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33813760 81.82% 81.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565868 1.37% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 817164 1.98% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676151 1.64% 86.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 772838 1.87% 88.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 560246 1.36% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 669817 1.62% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351583 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3098219 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41323427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086818 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.463067 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12228313 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20776644 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6830919 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 507068 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 980483 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935966 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64632 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40044073 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213118 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 980483 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12794933 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5974902 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12785484 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6719608 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2068017 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38935181 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1840 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 426390 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1152446 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 100 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39283995 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175854037 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175819876 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34161 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30939461 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8344533 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411347 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370357 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5351975 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7655764 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5689444 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124222 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1281984 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36848399 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895286 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37254672 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81509 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6299557 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13203578 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256355 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41323427 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.901539 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514633 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41325646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086769 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.462971 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12221128 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20791110 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6824454 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 510238 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 978716 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935346 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64732 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40027040 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212951 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 978716 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12790081 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5972534 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12789547 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6714080 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2080688 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38920228 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 436221 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1152507 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 84 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39264921 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175790758 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175756522 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34236 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30938700 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8326220 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411215 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370279 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5370420 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7651291 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5689186 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1120456 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1254854 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36835170 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895288 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37251130 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81272 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6287660 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13163035 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256365 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41325646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.901405 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.514906 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26248165 63.52% 63.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5684023 13.75% 77.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3115322 7.54% 84.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2467752 5.97% 90.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2139591 5.18% 95.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 926164 2.24% 98.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 502996 1.22% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 185723 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53691 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26248472 63.52% 63.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5690851 13.77% 77.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3114453 7.54% 84.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2470786 5.98% 90.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2128163 5.15% 95.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 926108 2.24% 98.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 506651 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 185379 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54783 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41323427 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41325646 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27493 2.57% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.04% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842638 78.71% 81.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 200034 18.68% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27685 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.04% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 842164 78.64% 81.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 200566 18.73% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22336809 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46914 0.13% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22335497 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46969 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9369783 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5448235 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9366005 25.14% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5449722 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37254672 # Type of FU issued -system.cpu0.iq.rate 0.538431 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070617 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028738 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117010237 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44051144 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34347967 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8478 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38268613 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4462 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307627 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37251130 # Type of FU issued +system.cpu0.iq.rate 0.538499 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070867 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028747 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117005145 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44025943 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34344840 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8484 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3874 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38265319 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4464 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307168 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1377452 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2519 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13094 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537577 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1372814 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2493 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13018 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 537400 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192819 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5737 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192818 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5781 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 980483 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4321779 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 103852 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37861161 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83824 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7655764 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5689444 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571291 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39684 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 13815 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13094 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150380 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118124 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 268504 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36875907 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9227090 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 378765 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 978716 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4319425 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 103424 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37848942 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83231 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7651291 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5689186 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571145 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39872 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 13404 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13018 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150227 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117595 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267822 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36871306 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9223534 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 379824 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117476 # number of nop insts executed -system.cpu0.iew.exec_refs 14627584 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4856181 # Number of branches executed -system.cpu0.iew.exec_stores 5400494 # Number of stores executed -system.cpu0.iew.exec_rate 0.532957 # Inst execution rate -system.cpu0.iew.wb_sent 36680744 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34351839 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18317228 # num instructions producing a value -system.cpu0.iew.wb_consumers 35218038 # num instructions consuming a value +system.cpu0.iew.exec_nop 118484 # number of nop insts executed +system.cpu0.iew.exec_refs 14624342 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4855002 # Number of branches executed +system.cpu0.iew.exec_stores 5400808 # Number of stores executed +system.cpu0.iew.exec_rate 0.533008 # Inst execution rate +system.cpu0.iew.wb_sent 36677174 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34348714 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18316479 # num instructions producing a value +system.cpu0.iew.wb_consumers 35213732 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.496478 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520109 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.496542 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520152 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6105741 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638931 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232529 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40342944 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775737 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.743782 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6093987 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638923 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232030 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40346930 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775643 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740681 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28719843 71.19% 71.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5706970 14.15% 85.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1863125 4.62% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 981446 2.43% 92.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 776304 1.92% 94.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 515472 1.28% 95.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 394004 0.98% 96.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 214891 0.53% 97.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1170889 2.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28704762 71.14% 71.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5702920 14.13% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1886389 4.68% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 981050 2.43% 92.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 790069 1.96% 94.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 509429 1.26% 95.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395100 0.98% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 219754 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1157457 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40342944 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23687602 # Number of instructions committed -system.cpu0.commit.committedOps 31295507 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40346930 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23686340 # Number of instructions committed +system.cpu0.commit.committedOps 31294803 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11430179 # Number of memory references committed -system.cpu0.commit.loads 6278312 # Number of loads committed -system.cpu0.commit.membars 229695 # Number of memory barriers committed -system.cpu0.commit.branches 4246577 # Number of branches committed +system.cpu0.commit.refs 11430263 # Number of memory references committed +system.cpu0.commit.loads 6278477 # Number of loads committed +system.cpu0.commit.membars 229716 # Number of memory barriers committed +system.cpu0.commit.branches 4246456 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27650890 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489495 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1170889 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27650320 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489514 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1157457 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75722045 # The number of ROB reads -system.cpu0.rob.rob_writes 75784919 # The number of ROB writes -system.cpu0.timesIdled 368023 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27867696 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2158812857 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23606860 # Number of Instructions Simulated -system.cpu0.committedOps 31214765 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23606860 # Number of Instructions Simulated -system.cpu0.cpi 2.930975 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.930975 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.341183 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.341183 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171887932 # number of integer regfile reads -system.cpu0.int_regfile_writes 34101589 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads -system.cpu0.fp_regfile_writes 874 # number of floating regfile writes -system.cpu0.misc_regfile_reads 12983242 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451267 # number of misc regfile writes -system.cpu0.icache.tags.replacements 393301 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.011114 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3798020 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 393813 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.644222 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6979217250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.011114 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998069 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998069 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3798020 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3798020 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3798020 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3798020 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3798020 # number of overall hits -system.cpu0.icache.overall_hits::total 3798020 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 424793 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 424793 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 424793 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 424793 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 424793 # number of overall misses -system.cpu0.icache.overall_misses::total 424793 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5908836480 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5908836480 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5908836480 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5908836480 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5908836480 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5908836480 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4222813 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4222813 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4222813 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4222813 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4222813 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4222813 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100595 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100595 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100595 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100595 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100595 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100595 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13909.919608 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.919608 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.919608 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13909.919608 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.919608 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13909.919608 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3571 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75726854 # The number of ROB reads +system.cpu0.rob.rob_writes 75758265 # The number of ROB writes +system.cpu0.timesIdled 367474 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27850243 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138859041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23605598 # Number of Instructions Simulated +system.cpu0.committedOps 31214061 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23605598 # Number of Instructions Simulated +system.cpu0.cpi 2.930487 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.930487 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.341240 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.341240 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171860544 # number of integer regfile reads +system.cpu0.int_regfile_writes 34096305 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads +system.cpu0.fp_regfile_writes 892 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13010065 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451140 # number of misc regfile writes +system.cpu0.icache.tags.replacements 392795 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.002835 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3796668 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 393307 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.653192 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6982777250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.002835 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998052 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3796668 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3796668 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3796668 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3796668 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3796668 # number of overall hits +system.cpu0.icache.overall_hits::total 3796668 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 424314 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 424314 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 424314 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 424314 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 424314 # number of overall misses +system.cpu0.icache.overall_misses::total 424314 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5901888496 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5901888496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5901888496 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5901888496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5901888496 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5901888496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4220982 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4220982 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4220982 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4220982 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4220982 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4220982 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100525 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100525 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100525 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100525 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100525 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100525 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13909.247623 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.247623 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13909.247623 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13909.247623 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3930 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 194 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.620879 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.257732 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30958 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30958 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30958 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30958 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30958 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30958 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393835 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393835 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393835 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393835 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393835 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393835 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4811729884 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4811729884 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4811729884 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4811729884 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4811729884 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4811729884 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9686500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9686500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9686500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 9686500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093264 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093264 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093264 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.628916 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.628916 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.628916 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30982 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30982 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30982 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30982 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30982 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30982 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393332 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393332 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393332 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393332 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393332 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393332 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4803860873 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4803860873 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4803860873 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4803860873 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4803860873 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4803860873 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8948750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8948750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8948750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8948750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093185 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093185 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093185 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093185 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093185 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093185 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12213.247010 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12213.247010 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12213.247010 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 276277 # number of replacements -system.cpu0.dcache.tags.tagsinuse 458.508643 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9265297 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 276789 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.474224 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 49564250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 458.508643 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.895525 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.895525 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5784459 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5784459 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3159328 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3159328 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139329 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139329 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137110 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137110 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8943787 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8943787 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8943787 # number of overall hits -system.cpu0.dcache.overall_hits::total 8943787 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392022 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392022 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1584787 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1584787 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8757 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8757 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7526 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7526 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1976809 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1976809 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1976809 # number of overall misses -system.cpu0.dcache.overall_misses::total 1976809 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5532398989 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5532398989 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77338129003 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77338129003 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88246985 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88246985 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46297127 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46297127 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 82870527992 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 82870527992 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 82870527992 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 82870527992 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176481 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6176481 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744115 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4744115 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148086 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 148086 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144636 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144636 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10920596 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10920596 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10920596 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10920596 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063470 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063470 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334053 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.334053 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059135 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059135 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052034 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052034 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181017 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.181017 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181017 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181017 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14112.470701 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14112.470701 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48800.330267 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 48800.330267 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10077.307868 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10077.307868 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6151.624635 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6151.624635 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41921.363163 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41921.363163 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41921.363163 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41921.363163 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9474 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 7234 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 614 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 133 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.429967 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 54.390977 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 276222 # number of replacements +system.cpu0.dcache.tags.tagsinuse 460.530312 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9262144 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 276734 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.469483 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 42960250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 460.530312 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.899473 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.899473 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5781621 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5781621 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3159389 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3159389 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139147 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139147 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137077 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137077 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8941010 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8941010 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8941010 # number of overall hits +system.cpu0.dcache.overall_hits::total 8941010 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 391790 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 391790 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1584826 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1584826 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8742 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8742 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7480 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7480 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1976616 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1976616 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1976616 # number of overall misses +system.cpu0.dcache.overall_misses::total 1976616 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5523901183 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5523901183 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77315448541 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77315448541 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88125732 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88125732 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45924629 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45924629 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 82839349724 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 82839349724 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 82839349724 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 82839349724 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6173411 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6173411 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744215 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744215 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147889 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147889 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144557 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144557 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10917626 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10917626 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10917626 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10917626 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063464 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063464 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334054 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.334054 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059112 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059112 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051744 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051744 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14099.137760 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14099.137760 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48784.818359 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 48784.818359 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10080.728895 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10080.728895 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6139.656283 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6139.656283 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41909.682874 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41909.682874 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 11704 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 6407 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 613 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.092985 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 48.908397 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256588 # number of writebacks -system.cpu0.dcache.writebacks::total 256588 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203202 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203202 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454368 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454368 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 460 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 460 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657570 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657570 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657570 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657570 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188820 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188820 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130419 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130419 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8297 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8297 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7522 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7522 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319239 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319239 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319239 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319239 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2408343372 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2408343372 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110867707 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110867707 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66642015 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66642015 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31254873 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31254873 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7519211079 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7519211079 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7519211079 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7519211079 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504631783 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504631783 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180253969 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180253969 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14684885752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14684885752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030571 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030571 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027491 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027491 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056028 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056028 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052006 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052006 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029233 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029233 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.704862 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.704862 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39188.060842 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39188.060842 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8032.061589 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8032.061589 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4155.128024 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4155.128024 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks +system.cpu0.dcache.writebacks::total 256512 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203095 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203095 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454344 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1454344 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 453 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 453 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657439 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657439 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188695 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188695 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130482 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130482 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8289 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8289 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7480 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7480 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319177 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319177 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319177 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319177 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2406687867 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2406687867 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110325446 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110325446 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66640768 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66640768 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30961371 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30961371 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7517013313 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7517013313 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7517013313 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7517013313 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504611525 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504611525 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131834379 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131834379 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636445904 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636445904 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030566 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030566 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027503 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027503 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051744 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051744 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029235 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029235 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.380704 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.380704 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39164.984028 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39164.984028 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.663168 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.663168 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4139.220722 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4139.220722 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1800,38 +1713,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9066954 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7451944 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 406719 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6049384 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5236824 # Number of BTB hits +system.cpu1.branchPred.lookups 8782132 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7168426 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 407819 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5819499 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4955017 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.567889 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772531 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42321 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.145079 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 773793 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42171 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42909677 # DTB read hits -system.cpu1.dtb.read_misses 36560 # DTB read misses -system.cpu1.dtb.write_hits 6823585 # DTB write hits -system.cpu1.dtb.write_misses 10691 # DTB write misses +system.cpu1.dtb.read_hits 42691295 # DTB read hits +system.cpu1.dtb.read_misses 36496 # DTB read misses +system.cpu1.dtb.write_hits 6824033 # DTB write hits +system.cpu1.dtb.write_misses 10597 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2608 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2020 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2612 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42946237 # DTB read accesses -system.cpu1.dtb.write_accesses 6834276 # DTB write accesses +system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42727791 # DTB read accesses +system.cpu1.dtb.write_accesses 6834630 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49733262 # DTB hits -system.cpu1.dtb.misses 47251 # DTB misses -system.cpu1.dtb.accesses 49780513 # DTB accesses -system.cpu1.itb.inst_hits 8323198 # ITB inst hits -system.cpu1.itb.inst_misses 5400 # ITB inst misses +system.cpu1.dtb.hits 49515328 # DTB hits +system.cpu1.dtb.misses 47093 # DTB misses +system.cpu1.dtb.accesses 49562421 # DTB accesses +system.cpu1.itb.inst_hits 7577708 # ITB inst hits +system.cpu1.itb.inst_misses 5297 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1844,109 +1757,109 @@ system.cpu1.itb.flush_entries 1529 # Nu system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1545 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8328598 # ITB inst accesses -system.cpu1.itb.hits 8323198 # DTB hits -system.cpu1.itb.misses 5400 # DTB misses -system.cpu1.itb.accesses 8328598 # DTB accesses -system.cpu1.numCycles 410695591 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7583005 # ITB inst accesses +system.cpu1.itb.hits 7577708 # DTB hits +system.cpu1.itb.misses 5297 # DTB misses +system.cpu1.itb.accesses 7583005 # DTB accesses +system.cpu1.numCycles 408491180 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19628666 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66104666 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9066954 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6009355 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14131573 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3952223 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 62853 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77248707 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42228 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1436171 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 176 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8321388 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 704092 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2736 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 115246116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.694374 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.038205 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18854224 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 60287918 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8782132 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5728810 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13124144 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3307681 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 62009 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77240238 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4754 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42673 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1437796 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7575877 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 546214 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2648 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 113028448 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.652235 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.978835 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 101121884 87.74% 87.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796637 0.69% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937162 0.81% 89.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1885853 1.64% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1499695 1.30% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 570142 0.49% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2110638 1.83% 94.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410756 0.36% 94.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5913349 5.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99911588 88.40% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796149 0.70% 89.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 938672 0.83% 89.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1688468 1.49% 91.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1396344 1.24% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570472 0.50% 93.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1929580 1.71% 94.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410359 0.36% 95.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5386816 4.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 115246116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022077 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.160958 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21155925 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78195753 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12775663 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 524358 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2594417 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105836 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98153 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75067660 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 326745 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2594417 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22501379 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33242741 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40762154 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11860446 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4284979 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69913296 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18816 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 670004 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3042907 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 379 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73978163 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321899381 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321840484 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58897 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49060581 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24917582 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444517 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387690 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7870912 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13163327 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8127092 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1028302 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1543452 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63442447 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157372 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89134089 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93553 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16181139 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45168283 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 276533 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 115246116 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.773424 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.513958 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 113028448 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021499 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.147587 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20182430 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78186513 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11968696 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 524734 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2166075 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1104186 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 97997 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69821372 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 325725 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2166075 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21372370 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33233612 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40763249 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11209012 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4284130 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 65907040 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18855 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 668466 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3042854 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1130 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 69218982 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 302521919 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 302462653 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49058929 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20160053 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444772 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387840 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7873214 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12591353 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7935523 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1036537 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1457992 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60681374 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157953 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 87712578 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93570 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13421216 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 35924412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277156 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 113028448 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.776022 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519284 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84850695 73.63% 73.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8420843 7.31% 80.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4255514 3.69% 84.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3817238 3.31% 87.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10566074 9.17% 97.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1932638 1.68% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1074262 0.93% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 253370 0.22% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 75482 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83202776 73.61% 73.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8275815 7.32% 80.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4119768 3.64% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3698740 3.27% 87.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10372542 9.18% 97.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1968067 1.74% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1039899 0.92% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 275618 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 75223 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 115246116 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 113028448 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32069 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32070 0.41% 0.41% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available @@ -1975,395 +1888,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7550960 95.79% 96.21% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 298953 3.79% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7550021 95.87% 96.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 292311 3.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37650996 42.24% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59191 0.07% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43937068 49.29% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7171235 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36603154 41.73% 42.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59244 0.07% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43563118 49.67% 91.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7171472 8.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89134089 # Type of FU issued -system.cpu1.iq.rate 0.217032 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7882978 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088440 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 301522554 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80789150 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53744584 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15343 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8026 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96694852 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8153 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 340284 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 87712578 # Type of FU issued +system.cpu1.iq.rate 0.214723 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7875398 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089786 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 296453915 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 75268930 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53141218 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15550 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8086 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6819 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95265602 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8312 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 341261 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3407112 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2835568 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3737 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 16742 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1286559 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17004 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1095143 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31912923 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 915604 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31913350 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 674872 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2594417 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25467221 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 361914 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64703269 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112618 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13163327 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8127092 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869000 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64609 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6290 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 16742 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 200151 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154994 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 355145 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86813167 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43279828 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2320922 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2166075 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25455774 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 362563 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 61943028 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112233 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12591353 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7935523 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869270 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64753 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6199 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17004 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201423 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154723 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 356146 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85989556 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43061283 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1723022 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103450 # number of nop insts executed -system.cpu1.iew.exec_refs 50389574 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6997831 # Number of branches executed -system.cpu1.iew.exec_stores 7109746 # Number of stores executed -system.cpu1.iew.exec_rate 0.211381 # Inst execution rate -system.cpu1.iew.wb_sent 85834090 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53751385 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29958578 # num instructions producing a value -system.cpu1.iew.wb_consumers 53322000 # num instructions consuming a value +system.cpu1.iew.exec_nop 103701 # number of nop insts executed +system.cpu1.iew.exec_refs 50171461 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6912906 # Number of branches executed +system.cpu1.iew.exec_stores 7110178 # Number of stores executed +system.cpu1.iew.exec_rate 0.210505 # Inst execution rate +system.cpu1.iew.wb_sent 85230378 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53148037 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29710424 # num instructions producing a value +system.cpu1.iew.wb_consumers 52969976 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.130879 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.561843 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.130108 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560892 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16054832 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880839 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 310229 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112651699 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.427506 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.393608 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13294883 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880797 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 311444 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 110862373 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.434393 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.404754 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95929787 85.16% 85.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8195439 7.28% 92.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2121242 1.88% 94.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1255081 1.11% 95.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1260461 1.12% 96.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 575308 0.51% 97.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 943355 0.84% 97.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 590559 0.52% 98.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1780467 1.58% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94147475 84.92% 84.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8220753 7.42% 92.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2089215 1.88% 94.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1249683 1.13% 95.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1247924 1.13% 96.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 575753 0.52% 96.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 991767 0.89% 97.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 529898 0.48% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1809905 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112651699 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38067147 # Number of instructions committed -system.cpu1.commit.committedOps 48159329 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 110862373 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38066252 # Number of instructions committed +system.cpu1.commit.committedOps 48157821 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16596748 # Number of memory references committed -system.cpu1.commit.loads 9756215 # Number of loads committed -system.cpu1.commit.membars 190139 # Number of memory barriers committed -system.cpu1.commit.branches 5967970 # Number of branches committed +system.cpu1.commit.refs 16596165 # Number of memory references committed +system.cpu1.commit.loads 9755785 # Number of loads committed +system.cpu1.commit.membars 190126 # Number of memory barriers committed +system.cpu1.commit.branches 5967905 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42694003 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534679 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1780467 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42692526 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534650 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1809905 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 174041277 # The number of ROB reads -system.cpu1.rob.rob_writes 131120872 # The number of ROB writes -system.cpu1.timesIdled 1414866 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295449475 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1816711228 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37997508 # Number of Instructions Simulated -system.cpu1.committedOps 48089690 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37997508 # Number of Instructions Simulated -system.cpu1.cpi 10.808488 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.808488 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092520 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092520 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 388394171 # number of integer regfile reads -system.cpu1.int_regfile_writes 56329363 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5049 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2330 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18495746 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405487 # number of misc regfile writes -system.cpu1.icache.tags.replacements 596092 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.837460 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7679654 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 596604 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 12.872280 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74828235500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.837460 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.939136 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.939136 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7679654 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7679654 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7679654 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7679654 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7679654 # number of overall hits -system.cpu1.icache.overall_hits::total 7679654 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641686 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641686 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641686 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641686 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641686 # number of overall misses -system.cpu1.icache.overall_misses::total 641686 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8725652874 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8725652874 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8725652874 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8725652874 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8725652874 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8725652874 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8321340 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8321340 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8321340 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8321340 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8321340 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8321340 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.077113 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.077113 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.077113 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.077113 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.077113 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.077113 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13598.010357 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13598.010357 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13598.010357 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13598.010357 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13598.010357 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13598.010357 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3474 # number of cycles access was blocked +system.cpu1.rob.rob_reads 169461098 # The number of ROB reads +system.cpu1.rob.rob_writes 125154390 # The number of ROB writes +system.cpu1.timesIdled 1414583 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295462732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1798949280 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37996613 # Number of Instructions Simulated +system.cpu1.committedOps 48088182 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37996613 # Number of Instructions Simulated +system.cpu1.cpi 10.750726 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.750726 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093017 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093017 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 384900722 # number of integer regfile reads +system.cpu1.int_regfile_writes 55276259 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5045 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18451458 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405460 # number of misc regfile writes +system.cpu1.icache.tags.replacements 594712 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.460982 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6935744 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 595224 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.652326 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74833132000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.460982 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938400 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938400 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 6935744 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6935744 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6935744 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6935744 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6935744 # number of overall hits +system.cpu1.icache.overall_hits::total 6935744 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 640085 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 640085 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 640085 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 640085 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 640085 # number of overall misses +system.cpu1.icache.overall_misses::total 640085 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8700934064 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8700934064 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8700934064 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8700934064 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8700934064 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8700934064 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7575829 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7575829 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7575829 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7575829 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7575829 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7575829 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084490 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084490 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084490 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084490 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084490 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084490 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13593.404101 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13593.404101 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13593.404101 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13593.404101 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2623 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 210 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 183 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.542857 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.333333 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 45060 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 45060 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 45060 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 45060 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 45060 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 45060 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596626 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 596626 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 596626 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 596626 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 596626 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 596626 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7121155232 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7121155232 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7121155232 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7121155232 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7121155232 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7121155232 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3411250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3411250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3411250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3411250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071698 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071698 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071698 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11935.710532 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11935.710532 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11935.710532 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44828 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44828 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44828 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44828 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44828 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44828 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 595257 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 595257 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 595257 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 595257 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 595257 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 595257 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7103878279 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7103878279 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7103878279 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7103878279 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7103878279 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7103878279 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3410750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3410750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3410750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3410750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078573 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.078573 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.078573 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11934.136481 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11934.136481 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11934.136481 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11934.136481 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 360464 # number of replacements -system.cpu1.dcache.tags.tagsinuse 473.569939 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12678323 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 360816 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.137918 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70878166000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.569939 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924941 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.924941 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8311494 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8311494 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4138859 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4138859 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97571 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97571 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94878 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94878 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12450353 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12450353 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12450353 # number of overall hits -system.cpu1.dcache.overall_hits::total 12450353 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 398176 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 398176 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1558152 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1558152 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13940 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13940 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10599 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10599 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1956328 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1956328 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1956328 # number of overall misses -system.cpu1.dcache.overall_misses::total 1956328 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6132182064 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6132182064 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75676889684 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 75676889684 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129078996 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129078996 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53253915 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53253915 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 81809071748 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 81809071748 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 81809071748 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 81809071748 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8709670 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8709670 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5697011 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5697011 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111511 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111511 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105477 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105477 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14406681 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14406681 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14406681 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14406681 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045717 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045717 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273503 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273503 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125010 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125010 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100486 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100486 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135793 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135793 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135793 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135793 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15400.682271 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15400.682271 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48568.361549 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 48568.361549 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9259.612339 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9259.612339 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5024.428248 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5024.428248 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 41817.666438 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 41817.666438 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 41817.666438 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 41817.666438 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29976 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 17316 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3303 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 173 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.075386 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 100.092486 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 360690 # number of replacements +system.cpu1.dcache.tags.tagsinuse 473.926621 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 12678192 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 361043 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.115463 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70882645000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.926621 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925638 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.925638 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8311339 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8311339 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4138952 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4138952 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97545 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97545 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94900 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94900 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12450291 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12450291 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12450291 # number of overall hits +system.cpu1.dcache.overall_hits::total 12450291 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 397118 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 397118 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1557827 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1557827 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13956 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13956 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10582 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10582 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1954945 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1954945 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1954945 # number of overall misses +system.cpu1.dcache.overall_misses::total 1954945 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6022716747 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6022716747 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 76093468282 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 76093468282 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129448993 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129448993 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53146420 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53146420 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 82116185029 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 82116185029 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 82116185029 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 82116185029 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8708457 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8708457 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696779 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5696779 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111501 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111501 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105482 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105482 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14405236 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14405236 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14405236 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14405236 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045601 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045601 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273458 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273458 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125165 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125165 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100320 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100320 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15166.063354 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15166.063354 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48845.904123 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 48845.904123 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9275.508240 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9275.508240 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5022.341712 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5022.341712 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 42004.345406 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 42004.345406 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29557 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18184 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3279 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.014029 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 108.238095 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324789 # number of writebacks -system.cpu1.dcache.writebacks::total 324789 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170095 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 170095 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396532 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1396532 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1437 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1437 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566627 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1566627 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566627 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1566627 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228081 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228081 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161620 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161620 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12503 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12503 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10598 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10598 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389701 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389701 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389701 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389701 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2839406051 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2839406051 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6490016907 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6490016907 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88435503 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88435503 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32057085 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32057085 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9329422958 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9329422958 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9329422958 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9329422958 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168915044006 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168915044006 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34787133815 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34787133815 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 203702177821 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 203702177821 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026187 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112123 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112123 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100477 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100477 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12449.112600 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12449.112600 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40156.025906 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40156.025906 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7073.142686 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7073.142686 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.824023 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.824023 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23939.951291 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23939.951291 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23939.951291 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23939.951291 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324751 # number of writebacks +system.cpu1.dcache.writebacks::total 324751 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168850 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 168850 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396175 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1396175 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565025 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1565025 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565025 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1565025 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228268 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228268 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161652 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161652 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12509 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12509 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10578 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10578 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389920 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389920 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389920 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389920 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2830993566 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2830993566 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6516328872 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6516328872 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88639506 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88639506 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31988580 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31988580 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9347322438 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9347322438 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9347322438 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9347322438 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168914513007 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168914513007 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25825904490 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25825904490 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194740417497 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194740417497 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026212 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026212 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028376 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028376 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112187 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112187 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100283 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100283 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027068 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027068 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12402.060587 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12402.060587 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40310.845965 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40310.845965 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7086.058518 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7086.058518 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.066931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.066931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2371,12 +2284,12 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2385,18 +2298,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 644226028268 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 644226028268 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 644226028268 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 644226028268 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 582931892511 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 582931892511 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 582931892511 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 582931892511 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41731 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 49ef0687e..6a97d3f47 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,131 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534332 # Number of seconds simulated -sim_ticks 2534332336000 # Number of ticks simulated -final_tick 2534332336000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.524310 # Number of seconds simulated +sim_ticks 2524309551500 # Number of ticks simulated +final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60160 # Simulator instruction rate (inst/s) -host_op_rate 77409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2528112838 # Simulator tick rate (ticks/s) -host_mem_usage 401532 # Number of bytes of host memory used -host_seconds 1002.46 # Real time elapsed on the host -sim_insts 60307773 # Number of instructions simulated -sim_ops 77599321 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119572608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory +host_inst_rate 81082 # Simulator instruction rate (inst/s) +host_op_rate 104330 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3394002800 # Simulator tick rate (ticks/s) +host_mem_usage 397632 # Number of bytes of host memory used +host_seconds 743.76 # Real time elapsed on the host +sim_insts 60305560 # Number of instructions simulated +sim_ops 77596391 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095056 # Number of bytes read from this memory -system.physmem.bytes_read::total 129468752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory +system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14946576 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12471 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142144 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15101237 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47181108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1111 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51085941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493575 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683661 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47181108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53769602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15101237 # Total number of read requests seen -system.physmem.writeReqs 813162 # Total number of write requests seen -system.physmem.cpureqs 218445 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966479168 # Total number of bytes read from memory -system.physmem.bytesWritten 52042368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129468752 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6801288 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 279 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4676 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 944611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 944270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 944423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944612 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943694 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943515 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944002 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943653 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 942812 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943693 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51011 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51200 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50757 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51124 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 966197440 # Total number of bytes read from memory +system.physmem.bytesWritten 52040704 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32457 # Number of times wr buffer was full causing retry -system.physmem.totGap 2534332242000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 2524308440000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14946576 # Categorize read packet sizes +system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154625 # Categorize read packet sizes +system.physmem.readPktSize::6 154591 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59144 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1052232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 984006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 974713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3682136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2757823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2756219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2725955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 12526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59118 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -139,316 +140,294 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32470 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 42332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 24053.235566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1833.734815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32311.504914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 8211 19.40% 19.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3440 8.13% 27.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2237 5.28% 32.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1775 4.19% 37.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1231 2.91% 39.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1031 2.44% 42.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 888 2.10% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 774 1.83% 46.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 547 1.29% 47.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 559 1.32% 48.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 426 1.01% 49.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 432 1.02% 50.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 287 0.68% 51.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 279 0.66% 52.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 159 0.38% 52.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 249 0.59% 53.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 131 0.31% 53.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 141 0.33% 53.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 101 0.24% 54.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 136 0.32% 54.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 82 0.19% 54.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 379 0.90% 55.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 1813 4.28% 59.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 447 1.06% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 86 0.20% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 158 0.37% 61.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 41 0.10% 61.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 104 0.25% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 37 0.09% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 64 0.15% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 25 0.06% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 71 0.17% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 17 0.04% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 45 0.11% 62.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 11 0.03% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 40 0.09% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 10 0.02% 62.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 26 0.06% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 12 0.03% 62.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 19 0.04% 62.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 3 0.01% 62.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 16 0.04% 62.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 8 0.02% 62.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 18 0.04% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 12 0.03% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 13 0.03% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 25 0.06% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 6 0.01% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 6 0.01% 62.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 9 0.02% 62.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 13 0.03% 62.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 6 0.01% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 6 0.01% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 2 0.00% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 9 0.02% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 8 0.02% 63.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 5 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 1 0.00% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 6 0.01% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 43 0.10% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 2 0.00% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 3 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 7 0.02% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 8 0.02% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 8 0.02% 63.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 6 0.01% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 7 0.02% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 4 0.01% 63.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 2 0.00% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 2 0.00% 63.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 10 0.02% 63.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 3 0.01% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 2 0.00% 63.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 1 0.00% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5727 1 0.00% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 1 0.00% 63.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5855 3 0.01% 63.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 5 0.01% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5983 1 0.00% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 1 0.00% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 7 0.02% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 1 0.00% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 4 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 3 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 2 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 20 0.05% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 3 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 3 0.01% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7007 1 0.00% 63.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 4 0.01% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7135 1 0.00% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 4 0.01% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 4 0.01% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7519 1 0.00% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 3 0.01% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 1 0.00% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 7 0.02% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7775 1 0.00% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 2 0.00% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 3 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 3 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 11 0.03% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8479 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 1 0.00% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 18 0.04% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10527 2 0.00% 64.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 2 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 1 0.00% 64.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11807 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 3 0.01% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12511 1 0.00% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12831 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13087 1 0.00% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 2 0.00% 64.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 5 0.01% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14495 1 0.00% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15839 1 0.00% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16991 1 0.00% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 4 0.01% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 5 0.01% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18399 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18719 1 0.00% 64.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18816-18847 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18975 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19136-19167 1 0.00% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 3 0.01% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19615 1 0.00% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20511 2 0.00% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21023 1 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21279 2 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21919 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22367 1 0.00% 64.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 2 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24031 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24095 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24640-24671 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24799 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24863 1 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25280-25311 1 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 2 0.00% 64.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25887 2 0.00% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26271 1 0.00% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 3 0.01% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26911 1 0.00% 64.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 3 0.01% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27712-27743 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27935 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28191 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28608-28639 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 2 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29568-29599 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29727 3 0.01% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30303 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30495 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 3 0.01% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31007 2 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31936-31967 1 0.00% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32031 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32159 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32543 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33055 2 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 1 0.00% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 6 0.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33631 2 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33695 1 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 44 0.10% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34591 2 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35200-35231 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35871 2 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37504-37535 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37919 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37952-37983 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38943 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40287 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40735 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40991 3 0.01% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44575 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46111 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47647 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50207 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51231 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52255 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52992-53023 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53056-53087 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53760-53791 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54528-54559 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57344-57375 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57856-57887 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58399 2 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62495 1 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62528-62559 1 0.00% 64.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65119 8 0.02% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65247 18 0.04% 65.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65375 12 0.03% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65503 12 0.03% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14415 34.05% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130816-130847 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 330 0.78% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::159168-159199 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160704-160735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192512-192543 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196416-196447 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 42332 # Bytes accessed per row activation -system.physmem.totQLat 352162436750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 443380465500 # Sum of mem lat for all requests -system.physmem.totBusLat 75504790000 # Total cycles spent in databus access -system.physmem.totBankLat 15713238750 # Total cycles spent in bank access -system.physmem.avgQLat 23320.54 # Average queueing delay per request -system.physmem.avgBankLat 1040.55 # Average bank access latency per request +system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation +system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests +system.physmem.totBusLat 75453215000 # Total cycles spent in databus access +system.physmem.totBankLat 15307050000 # Total cycles spent in bank access +system.physmem.avgQLat 19314.15 # Average queueing delay per request +system.physmem.avgBankLat 1014.34 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29361.08 # Average memory access latency -system.physmem.avgRdBW 381.35 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25328.49 # Average memory access latency +system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 10.77 # Average write queue length over time -system.physmem.readRowHits 15074158 # Number of row buffer hits during reads -system.physmem.writeRowHits 797610 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.09 # Row buffer hit rate for writes -system.physmem.avgGap 159247.75 # Average gap between requests +system.physmem.busUtil 3.15 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 14.41 # Average write queue length over time +system.physmem.readRowHits 15065383 # Number of row buffer hits during reads +system.physmem.writeRowHits 94229 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes +system.physmem.avgGap 158662.04 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -461,60 +440,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54715776 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16153842 # Transaction distribution -system.membus.trans_dist::ReadResp 16153842 # Transaction distribution -system.membus.trans_dist::WriteReq 763336 # Transaction distribution -system.membus.trans_dist::WriteResp 763336 # Transaction distribution -system.membus.trans_dist::Writeback 59144 # Transaction distribution +system.membus.throughput 54917647 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149440 # Transaction distribution +system.membus.trans_dist::ReadResp 16149440 # Transaction distribution +system.membus.trans_dist::WriteReq 763332 # Transaction distribution +system.membus.trans_dist::WriteResp 763332 # Transaction distribution +system.membus.trans_dist::Writeback 59118 # Transaction distribution system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4676 # Transaction distribution -system.membus.trans_dist::ReadExReq 131438 # Transaction distribution -system.membus.trans_dist::ReadExResp 131438 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution +system.membus.trans_dist::ReadExReq 131433 # Transaction distribution +system.membus.trans_dist::ReadExResp 131433 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29893152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29893152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 31779006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34165728 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095353 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119572608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119572608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 136270040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138667961 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138667961 # Total data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138629141 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475262000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17374745000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3634500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4718589198 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33742309741 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -522,15 +491,15 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48124265 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16129900 # Transaction distribution -system.iobus.trans_dist::ReadResp 16129887 # Transaction distribution -system.iobus.trans_dist::WriteReq 8158 # Transaction distribution -system.iobus.trans_dist::WriteResp 8158 # Transaction distribution +system.iobus.throughput 48301509 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution +system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution +system.iobus.trans_dist::WriteReq 8157 # Transaction distribution +system.iobus.trans_dist::WriteResp 8157 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -550,38 +519,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32276103 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -601,42 +546,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390313 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121962881 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121962881 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121927961 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -676,44 +597,44 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14946584000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374790000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40962341509 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14663186 # Number of BP lookups -system.cpu.branchPred.condPredicted 11751443 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703165 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9748962 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7940354 # Number of BTB hits +system.cpu.branchPred.lookups 14390442 # Number of BP lookups +system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.448199 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1396465 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72132 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51389107 # DTB read hits -system.cpu.dtb.read_misses 64168 # DTB read misses -system.cpu.dtb.write_hits 11699261 # DTB write hits -system.cpu.dtb.write_misses 15977 # DTB write misses +system.cpu.dtb.read_hits 51188083 # DTB read hits +system.cpu.dtb.read_misses 64353 # DTB read misses +system.cpu.dtb.write_hits 11697459 # DTB write hits +system.cpu.dtb.write_misses 15788 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3558 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2439 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51453275 # DTB read accesses -system.cpu.dtb.write_accesses 11715238 # DTB write accesses +system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51252436 # DTB read accesses +system.cpu.dtb.write_accesses 11713247 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63088368 # DTB hits -system.cpu.dtb.misses 80145 # DTB misses -system.cpu.dtb.accesses 63168513 # DTB accesses -system.cpu.itb.inst_hits 12244686 # ITB inst hits -system.cpu.itb.inst_misses 11272 # ITB inst misses +system.cpu.dtb.hits 62885542 # DTB hits +system.cpu.dtb.misses 80141 # DTB misses +system.cpu.dtb.accesses 62965683 # DTB accesses +system.cpu.itb.inst_hits 11520428 # ITB inst hits +system.cpu.itb.inst_misses 11439 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -722,114 +643,114 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2481 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2486 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2937 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12255958 # ITB inst accesses -system.cpu.itb.hits 12244686 # DTB hits -system.cpu.itb.misses 11272 # DTB misses -system.cpu.itb.accesses 12255958 # DTB accesses -system.cpu.numCycles 475312551 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11531867 # ITB inst accesses +system.cpu.itb.hits 11520428 # DTB hits +system.cpu.itb.misses 11439 # DTB misses +system.cpu.itb.accesses 11531867 # DTB accesses +system.cpu.numCycles 473080437 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30486466 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96013812 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14663186 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9336819 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21137847 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5287329 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121734 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94652697 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 3821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86418 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2672948 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 439 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12241258 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 862361 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5349 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152790281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.777398 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.141854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131667661 86.18% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302340 0.85% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711403 1.12% 88.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2491779 1.63% 89.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2204039 1.44% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109873 0.73% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2734812 1.79% 93.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 742969 0.49% 94.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8825405 5.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152790281 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030850 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.202001 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32434469 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96765795 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19163623 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 968040 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3458354 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1955309 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172027 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112442167 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568180 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3458354 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34339332 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38106819 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52671042 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18167139 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6047595 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106212332 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004586 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4065982 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 631 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110697957 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485950395 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485859311 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91084 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390094 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32307862 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830633 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736877 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12210661 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20268413 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13492534 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1964739 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2435625 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97824738 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983401 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124295624 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165509 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21636439 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56320984 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501000 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152790281 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.528895 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108515921 71.02% 71.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13589329 8.89% 79.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7066338 4.62% 84.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5978859 3.91% 88.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12565558 8.22% 96.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2772936 1.81% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1725765 1.13% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 449060 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126515 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152790281 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62738 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available @@ -857,416 +778,416 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365929 94.58% 95.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 416628 4.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58652585 47.19% 47.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93247 0.08% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52864927 42.53% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319034 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124295624 # Type of FU issued -system.cpu.iq.rate 0.261503 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8845299 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071163 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 410448757 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121460975 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86059539 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23386 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12542 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10302 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132764827 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12430 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 625909 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued +system.cpu.iq.rate 0.259812 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4613851 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6375 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30092 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1760453 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107892 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 916935 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3458354 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29328857 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436741 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100030676 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203650 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20268413 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13492534 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410837 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 115234 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3326 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30092 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349264 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268145 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 617409 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121630045 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52076046 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2665579 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222537 # number of nop insts executed -system.cpu.iew.exec_refs 64287237 # number of memory reference insts executed -system.cpu.iew.exec_branches 11556571 # Number of branches executed -system.cpu.iew.exec_stores 12211191 # Number of stores executed -system.cpu.iew.exec_rate 0.255895 # Inst execution rate -system.cpu.iew.wb_sent 120479293 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86069841 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47268516 # num instructions producing a value -system.cpu.iew.wb_consumers 88195904 # num instructions consuming a value +system.cpu.iew.exec_nop 221034 # number of nop insts executed +system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed +system.cpu.iew.exec_branches 11474602 # Number of branches executed +system.cpu.iew.exec_stores 12209197 # Number of stores executed +system.cpu.iew.exec_rate 0.255417 # Inst execution rate +system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47030253 # num instructions producing a value +system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.181081 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535949 # average fanout of values written-back +system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21374007 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482401 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 533608 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149331927 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520650 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.508241 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121887208 81.62% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13290460 8.90% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3923979 2.63% 93.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2130804 1.43% 94.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1950357 1.31% 95.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968781 0.65% 96.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1543061 1.03% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 783043 0.52% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2854234 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149331927 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458154 # Number of instructions committed -system.cpu.commit.committedOps 77749702 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60455941 # Number of instructions committed +system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386643 # Number of memory references committed -system.cpu.commit.loads 15654562 # Number of loads committed -system.cpu.commit.membars 403601 # Number of memory barriers committed -system.cpu.commit.branches 9961356 # Number of branches committed +system.cpu.commit.refs 27385481 # Number of memory references committed +system.cpu.commit.loads 15653838 # Number of loads committed +system.cpu.commit.membars 403568 # Number of memory barriers committed +system.cpu.commit.branches 9961054 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854920 # Number of committed integer instructions. -system.cpu.commit.function_calls 991265 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2854234 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852229 # Number of committed integer instructions. +system.cpu.commit.function_calls 991205 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243752783 # The number of ROB reads -system.cpu.rob.rob_writes 201807644 # The number of ROB writes -system.cpu.timesIdled 1781061 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322522270 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593269077 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307773 # Number of Instructions Simulated -system.cpu.committedOps 77599321 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307773 # Number of Instructions Simulated -system.cpu.cpi 7.881448 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.881448 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126880 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126880 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550637144 # number of integer regfile reads -system.cpu.int_regfile_writes 88566595 # number of integer regfile writes -system.cpu.fp_regfile_reads 8370 # number of floating regfile reads -system.cpu.fp_regfile_writes 2906 # number of floating regfile writes -system.cpu.misc_regfile_reads 30124157 # number of misc regfile reads -system.cpu.misc_regfile_writes 831896 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58663468 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657447 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657446 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2983 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 245999 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 245999 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1961368 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5795761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126683 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7914273 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62726656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85494329 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 41328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 209684 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148471997 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148471997 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 200728 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128200875 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 239241509 # The number of ROB reads +system.cpu.rob.rob_writes 195965670 # The number of ROB writes +system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305560 # Number of Instructions Simulated +system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated +system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547265501 # number of integer regfile reads +system.cpu.int_regfile_writes 87536109 # number of integer regfile writes +system.cpu.fp_regfile_reads 8349 # number of floating regfile reads +system.cpu.fp_regfile_writes 2916 # number of floating regfile writes +system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads +system.cpu.misc_regfile_writes 831835 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474731013 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2562590429 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20135737 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74394752 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980590 # number of replacements -system.cpu.icache.tags.tagsinuse 511.580932 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11180201 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981102 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.395554 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6861342250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.580932 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11180201 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11180201 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11180201 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11180201 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11180201 # number of overall hits -system.cpu.icache.overall_hits::total 11180201 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060929 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060929 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060929 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060929 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060929 # number of overall misses -system.cpu.icache.overall_misses::total 1060929 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14286603183 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14286603183 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14286603183 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14286603183 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14286603183 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14286603183 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12241130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12241130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12241130 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12241130 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12241130 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12241130 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086669 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086669 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086669 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086669 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086669 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086669 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13466.125615 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13466.125615 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13466.125615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13466.125615 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8464 # number of cycles access was blocked +system.cpu.icache.tags.replacements 979660 # number of replacements +system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits +system.cpu.icache.overall_hits::total 10456897 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses +system.cpu.icache.overall_misses::total 1059959 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 385 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.984416 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79785 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79785 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79785 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79785 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79785 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79785 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981144 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981144 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981144 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981144 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981144 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981144 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11597968227 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11597968227 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11597968227 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11597968227 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11597968227 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11597968227 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9563750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9563750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9563750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 9563750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080151 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.080151 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.080151 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.080151 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11820.862409 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11820.862409 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11820.862409 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11820.862409 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64396 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51354.796312 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1885755 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129794 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.528830 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2499257274500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36876.248148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 31.469348 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000368 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8188.920307 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6258.158141 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.562687 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000480 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 64363 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.183198 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.182382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563463 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000589 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124953 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095492 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783612 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52377 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10330 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 386975 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1417303 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607541 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607541 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 14 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112810 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112810 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52377 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10330 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 967621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 499785 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1530113 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52377 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10330 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 967621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 499785 # number of overall hits -system.cpu.l2cache.overall_hits::total 1530113 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 44 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124713 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095141 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.783907 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52355 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10525 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 966696 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387308 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1416884 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607864 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607864 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112905 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112905 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52355 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10525 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966696 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500213 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529789 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52355 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10525 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 966696 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500213 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529789 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12364 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10739 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23149 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2922 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2922 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133189 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133189 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 44 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23117 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2916 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2916 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133190 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133190 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12364 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143928 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156338 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 44 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143913 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156307 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12364 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143928 # number of overall misses -system.cpu.l2cache.overall_misses::total 156338 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4379500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143913 # number of overall misses +system.cpu.l2cache.overall_misses::total 156307 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4640000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 918927250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 809103750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1732540750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 487979 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 487979 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9125635499 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9125635499 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4379500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 910966750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 788627999 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1704364999 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395483 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 395483 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9130512743 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9130512743 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4640000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 918927250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9934739249 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10858176249 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4379500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 910966750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9919140742 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10834877742 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4640000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 918927250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9934739249 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10858176249 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52421 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10332 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979985 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397714 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440452 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607541 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607541 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 245999 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 245999 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52421 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10332 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979985 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 643713 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686451 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52421 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10332 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979985 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 643713 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686451 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000839 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000194 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012617 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.027002 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016071 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985165 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985165 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.176471 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.176471 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541421 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541421 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000839 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000194 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012617 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223590 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092702 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000839 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000194 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012617 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223590 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092702 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 99534.090909 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 910966750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9919140742 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10834877742 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52406 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10527 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 979037 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 398031 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1440001 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607864 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607864 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246095 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246095 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52406 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10527 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 979037 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 644126 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1686096 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52406 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10527 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979037 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 644126 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1686096 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000973 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012605 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026940 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016053 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986802 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986802 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.181818 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541214 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541214 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000973 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012605 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223424 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092703 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000973 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012605 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223424 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092703 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 90980.392157 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65125 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74322.812197 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75342.559829 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74843.006177 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 167.001711 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 167.001711 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68516.435284 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68516.435284 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 99534.090909 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73816.283121 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73545.462930 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73727.776052 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 135.625171 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 135.625171 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68552.539553 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68552.539553 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74322.812197 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69025.757664 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69453.211945 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 99534.090909 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69317.930368 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74322.812197 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69025.757664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69453.211945 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69317.930368 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1275,109 +1196,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59144 # number of writebacks -system.cpu.l2cache.writebacks::total 59144 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59118 # number of writebacks +system.cpu.l2cache.writebacks::total 59118 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 69 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 69 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 44 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12352 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10670 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23068 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2922 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2922 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133189 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133189 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 44 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12329 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10658 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23040 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2916 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133190 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133190 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12352 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156257 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 44 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12329 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143848 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156230 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12352 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156257 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3822500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12329 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143848 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156230 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3990500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 761684000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 670036500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1435648750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29223421 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29223421 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7438270001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7438270001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3822500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 754066500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 649417249 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1407579999 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29164415 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29164415 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7443119257 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7443119257 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3990500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 761684000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8108306501 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8873918751 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3822500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 754066500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8092536506 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8850699256 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3990500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 761684000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8108306501 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8873918751 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 7076250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166924302000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166931378250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26354291876 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26354291876 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 7076250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193278593876 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193285670126 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012604 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016014 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985165 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985165 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541421 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541421 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012604 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223483 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092654 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012604 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223483 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092654 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 86875 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 754066500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8092536506 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8850699256 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6234999 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166923461500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166929696499 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17446167056 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17446167056 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6234999 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184369628556 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184375863555 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026777 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016000 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986802 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986802 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541214 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541214 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092658 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092658 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61664.831606 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62796.298032 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62235.510231 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.170773 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.170773 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61162.016384 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60932.374648 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61092.881901 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.514060 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.514060 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55847.479904 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55847.479904 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 86875 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61664.831606 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56362.872681 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56790.535790 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 86875 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61664.831606 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56362.872681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56790.535790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1387,161 +1308,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643201 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.992056 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21499493 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643713 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.399190 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 48741250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.992056 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13746666 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13746666 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259188 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259188 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242891 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242891 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247601 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247601 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21005854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21005854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21005854 # number of overall hits -system.cpu.dcache.overall_hits::total 21005854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 736262 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 736262 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963161 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963161 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13548 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13548 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3699423 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3699423 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3699423 # number of overall misses -system.cpu.dcache.overall_misses::total 3699423 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10077942358 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10077942358 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134690017209 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134690017209 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184520250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 184520250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 258503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 258503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144767959567 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144767959567 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144767959567 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144767959567 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14482928 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14482928 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256439 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256439 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247618 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247618 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24705277 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24705277 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24705277 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24705277 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050837 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050837 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289871 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289871 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052831 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052831 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149742 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149742 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149742 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149742 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13687.983840 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13687.983840 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45454.842720 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45454.842720 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13619.740921 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13619.740921 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15206.058824 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15206.058824 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39132.578126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39132.578126 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32140 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 25391 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2640 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 284 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.174242 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.404930 # average number of cycles each access was blocked +system.cpu.dcache.tags.replacements 643614 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits +system.cpu.dcache.overall_hits::total 21018772 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses +system.cpu.dcache.overall_misses::total 3700946 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607541 # number of writebacks -system.cpu.dcache.writebacks::total 607541 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350669 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350669 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714279 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714279 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064948 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064948 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064948 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064948 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385593 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385593 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248882 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248882 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12204 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12204 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634475 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634475 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634475 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634475 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967192840 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967192840 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10605079278 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10605079278 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144959500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144959500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 224497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 224497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15572272118 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15572272118 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15572272118 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15572272118 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182317512000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182317512000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35728890492 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35728890492 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218046402492 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 218046402492 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024347 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024347 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.958023 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.958023 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42610.872936 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42610.872936 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11878.031793 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11878.031793 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13205.705882 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13205.705882 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks +system.cpu.dcache.writebacks::total 607864 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1549,12 +1470,12 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1563,16 +1484,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1486035968259 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 2906c8c25..9d62fc018 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,163 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403594 # Number of seconds simulated -sim_ticks 2403594294500 # Number of ticks simulated -final_tick 2403594294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403596 # Number of seconds simulated +sim_ticks 2403595690000 # Number of ticks simulated +final_tick 2403595690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127977 # Simulator instruction rate (inst/s) -host_op_rate 164357 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5098961801 # Simulator tick rate (ticks/s) -host_mem_usage 401544 # Number of bytes of host memory used -host_seconds 471.39 # Real time elapsed on the host -sim_insts 60327163 # Number of instructions simulated -sim_ops 77476179 # Number of ops (including micro ops) simulated +host_inst_rate 160402 # Simulator instruction rate (inst/s) +host_op_rate 206018 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6390741250 # Simulator tick rate (ticks/s) +host_mem_usage 398660 # Number of bytes of host memory used +host_seconds 376.11 # Real time elapsed on the host +sim_insts 60328186 # Number of instructions simulated +sim_ops 77484426 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 511136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7143248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7050896 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 688768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 171584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1244640 # Number of bytes read from this memory -system.physmem.bytes_read::total 124657616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 511136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 171584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 761248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3742592 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1523692 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 157804 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1334320 # Number of bytes written to this memory -system.physmem.bytes_written::total 6758408 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 677568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 187392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1347680 # Number of bytes read from this memory +system.physmem.bytes_read::total 124659728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 187392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743680 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298324 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759496 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14189 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 111647 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110204 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10762 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2681 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 19455 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512355 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58478 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380923 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39451 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 333580 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812432 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47769739 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10587 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2928 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21065 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512388 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58495 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324581 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389548 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812449 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47769711 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 212655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2971903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 212814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2933478 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 286558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 71386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 517824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 212655 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 71386 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316712 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557081 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 633922 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 65653 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 555135 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2811792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47769739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 281898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 560693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 212814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77963 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557533 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812243 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47769711 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 212655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3605825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 212814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3473637 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 352211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 71386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1072960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54674794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13478004 # Total number of read requests seen -system.physmem.writeReqs 390132 # Total number of write requests seen -system.physmem.cpureqs 53582 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 862592256 # Total number of bytes read from memory -system.physmem.bytesWritten 24968448 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 109734944 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2586588 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2357 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 837777 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 837385 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 837533 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 838713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 839756 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 839804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 839650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 840522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 841715 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 844141 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 844930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 846498 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 848135 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 848079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 846803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 846563 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 25455 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 25327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 25409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 26300 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 26088 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 25421 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 23356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 23184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 23261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 21260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 21580 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24628 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 23500 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25208 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 26973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 348173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1208969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54676094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13479442 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 446461 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 13479442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 446461 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 862684288 # Total number of bytes read from memory +system.physmem.bytesWritten 28573504 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 109828768 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2811124 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 837727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 837365 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 837535 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 838843 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 839834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 839919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 839832 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 840753 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 841921 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 844340 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 845026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 846543 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 848256 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 848014 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 846904 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 846630 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2743 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2603 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2565 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 3057 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 3449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 3230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2572 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2333 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 2233 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 2377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 3826 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 3451 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2698 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2556 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14413 # Number of times wr buffer was full causing retry -system.physmem.totGap 2402559124000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 2402560453500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 8 # Categorize read packet sizes -system.physmem.readPktSize::3 13443872 # Categorize read packet sizes +system.physmem.readPktSize::3 13443840 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 34124 # Categorize read packet sizes +system.physmem.readPktSize::6 35594 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 373031 # Categorize write packet sizes +system.physmem.writePktSize::2 429373 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17101 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 870514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 846629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 868006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3320451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2492641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2492474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2466384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 13526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 25989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 38321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17088 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 871692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 848345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 868847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3321058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2492431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2492072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2465727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 13341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 25821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 38140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 25648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -173,191 +178,188 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 16973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 16965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 16963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 16956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 16951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 16946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 16929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 16918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 16918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14424 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 40328.985823 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 6672.817905 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32794.691650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 2992 13.60% 13.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 1338 6.08% 19.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 840 3.82% 23.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 568 2.58% 26.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 356 1.62% 27.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 350 1.59% 29.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 274 1.25% 30.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 258 1.17% 31.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 159 0.72% 32.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 152 0.69% 33.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 129 0.59% 33.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 166 0.75% 34.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 85 0.39% 34.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 79 0.36% 35.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 56 0.25% 35.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 66 0.30% 35.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 41 0.19% 35.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 34 0.15% 36.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 24 0.11% 36.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 38 0.17% 36.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 28 0.13% 36.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 94 0.43% 36.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 111 0.50% 37.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 95 0.43% 37.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 19 0.09% 37.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 37 0.17% 38.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 24 0.11% 38.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 40 0.18% 38.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 12 0.05% 38.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 17 0.08% 38.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 8 0.04% 38.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 19 0.09% 38.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 12 0.05% 38.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 11 0.05% 38.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 5 0.02% 38.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 5 0.02% 38.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 3 0.01% 38.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 10 0.05% 38.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 2 0.01% 38.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 1 0.00% 38.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 1 0.00% 38.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 5 0.02% 38.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 5 0.02% 38.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 5 0.02% 38.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 3 0.01% 38.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 1 0.00% 38.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 1 0.00% 38.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 7 0.03% 39.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 2 0.01% 39.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 3 0.01% 39.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 4 0.02% 39.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 7 0.03% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 2 0.01% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 2 0.01% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 3 0.01% 39.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 2 0.01% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 1 0.00% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 2 0.01% 39.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 3 0.01% 39.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 3 0.01% 39.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 7 0.03% 39.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 3 0.01% 39.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 1 0.00% 39.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 1 0.00% 39.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 2 0.01% 39.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 3 0.01% 39.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 1 0.00% 39.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 1 0.00% 39.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 1 0.00% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.01% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 1 0.00% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 2 0.01% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 8 0.04% 39.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 1 0.00% 39.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 1 0.00% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 1 0.00% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 4 0.02% 39.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 2 0.01% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 2 0.01% 39.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 1 0.00% 39.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 2 0.01% 39.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 1 0.00% 39.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 1 0.00% 39.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 2 0.01% 39.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 1 0.00% 39.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 3 0.01% 39.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8479 1 0.00% 39.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8607 1 0.00% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 1 0.00% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 3 0.01% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 1 0.00% 39.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13983 1 0.00% 39.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 1 0.00% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19231 1 0.00% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 1 0.00% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19999 1 0.00% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21791 1 0.00% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 2 0.01% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23327 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28191 1 0.00% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 1 0.00% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32031 2 0.01% 39.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33055 2 0.01% 39.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 2 0.01% 39.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 2 0.01% 39.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 1 0.00% 39.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34847 1 0.00% 39.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35871 1 0.00% 39.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36895 1 0.00% 39.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37919 1 0.00% 39.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38943 1 0.00% 39.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40991 1 0.00% 39.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 1 0.00% 39.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42783 1 0.00% 39.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46111 1 0.00% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49439 1 0.00% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50944-50975 1 0.00% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 39.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54303 1 0.00% 39.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54464-54495 1 0.00% 39.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56576-56607 1 0.00% 39.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58240-58271 1 0.00% 39.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58624-58655 1 0.00% 39.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59423 1 0.00% 39.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 13106 59.55% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 181 0.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22008 # Bytes accessed per row activation -system.physmem.totQLat 259991264250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 339839911750 # Sum of mem lat for all requests -system.physmem.totBusLat 67390020000 # Total cycles spent in databus access -system.physmem.totBankLat 12458627500 # Total cycles spent in bank access -system.physmem.avgQLat 19290.04 # Average queueing delay per request -system.physmem.avgBankLat 924.37 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 22080 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 39201.023188 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 6463.207550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31878.388388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-79 3036 13.75% 13.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-143 1347 6.10% 19.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-207 793 3.59% 23.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-271 589 2.67% 26.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-335 391 1.77% 27.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-399 355 1.61% 29.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-463 279 1.26% 30.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-527 235 1.06% 31.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-591 172 0.78% 32.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-655 146 0.66% 33.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-719 130 0.59% 33.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-783 164 0.74% 34.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-847 77 0.35% 34.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-911 80 0.36% 35.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-975 63 0.29% 35.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1039 74 0.34% 35.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1103 30 0.14% 36.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1167 39 0.18% 36.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1231 22 0.10% 36.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1295 39 0.18% 36.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1359 28 0.13% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1423 83 0.38% 37.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1487 95 0.43% 37.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1551 108 0.49% 37.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1615 17 0.08% 38.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1679 45 0.20% 38.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1743 23 0.10% 38.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1807 32 0.14% 38.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1871 10 0.05% 38.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1935 20 0.09% 38.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1999 6 0.03% 38.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2063 23 0.10% 38.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2127 8 0.04% 38.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2191 15 0.07% 38.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2255 1 0.00% 38.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2319 6 0.03% 38.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2383 4 0.02% 38.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2447 10 0.05% 38.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2511 3 0.01% 38.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2575 2 0.01% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2639 1 0.00% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2703 3 0.01% 38.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2767 5 0.02% 38.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2831 8 0.04% 39.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2895 3 0.01% 39.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2959 3 0.01% 39.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3023 1 0.00% 39.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3087 6 0.03% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3151 2 0.01% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3215 2 0.01% 39.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3279 5 0.02% 39.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3343 6 0.03% 39.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3407 2 0.01% 39.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3471 3 0.01% 39.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3535 1 0.00% 39.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3599 2 0.01% 39.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3663 2 0.01% 39.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3727 2 0.01% 39.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3791 3 0.01% 39.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3855 1 0.00% 39.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4047 3 0.01% 39.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4111 7 0.03% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4367 3 0.01% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4431 1 0.00% 39.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4687 2 0.01% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4815 2 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4943 1 0.00% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5007 2 0.01% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5135 1 0.00% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5391 2 0.01% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5455 1 0.00% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6287 1 0.00% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6479 1 0.00% 39.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6543 3 0.01% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6799 15 0.07% 39.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6863 2 0.01% 39.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6991 1 0.00% 39.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7055 3 0.01% 39.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7183 3 0.01% 39.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7375 2 0.01% 39.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7439 1 0.00% 39.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7695 1 0.00% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7759 1 0.00% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7951 2 0.01% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8079 1 0.00% 39.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8207 3 0.01% 39.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8463 45 0.20% 39.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8527 150 0.68% 40.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8591 12 0.05% 40.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8975 1 0.00% 40.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9231 1 0.00% 40.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9487 1 0.00% 40.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12047 2 0.01% 40.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14863 1 0.00% 40.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16335 1 0.00% 40.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17423 1 0.00% 40.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17679 1 0.00% 40.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20239 1 0.00% 40.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22799 1 0.00% 40.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24591 1 0.00% 40.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25871 1 0.00% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27663 1 0.00% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29455 1 0.00% 40.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30735 2 0.01% 40.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31247 1 0.00% 40.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33039 1 0.00% 40.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33295 3 0.01% 40.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33807 1 0.00% 40.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34319 1 0.00% 40.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34831 1 0.00% 40.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35855 1 0.00% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37903 1 0.00% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38927 1 0.00% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40207 1 0.00% 40.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40975 1 0.00% 40.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41999 1 0.00% 40.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42767 1 0.00% 40.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47887 1 0.00% 40.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52239 1 0.00% 40.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53263 1 0.00% 40.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53504-53519 1 0.00% 40.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56064-56079 1 0.00% 40.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59407 1 0.00% 40.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65551 13109 59.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22080 # Bytes accessed per row activation +system.physmem.totQLat 259652718750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 339530350000 # Sum of mem lat for all requests +system.physmem.totBusLat 67397210000 # Total cycles spent in databus access +system.physmem.totBankLat 12480421250 # Total cycles spent in bank access +system.physmem.avgQLat 19262.87 # Average queueing delay per request +system.physmem.avgBankLat 925.89 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25214.41 # Average memory access latency -system.physmem.avgRdBW 358.88 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 45.65 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.08 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25188.75 # Average memory access latency +system.physmem.avgRdBW 358.91 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 11.89 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 45.69 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.17 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.88 # Data bus utilization in percentage +system.physmem.busUtil 2.90 # Data bus utilization in percentage system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 0.40 # Average write queue length over time -system.physmem.readRowHits 13460829 # Number of row buffer hits during reads -system.physmem.writeRowHits 385299 # Number of row buffer hits during writes +system.physmem.avgWrQLen 0.39 # Average write queue length over time +system.physmem.readRowHits 13462207 # Number of row buffer hits during reads +system.physmem.writeRowHits 40077 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.76 # Row buffer hit rate for writes -system.physmem.avgGap 173243.12 # Average gap between requests +system.physmem.writeRowHitRate 8.98 # Row buffer hit rate for writes +system.physmem.avgGap 172524.57 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -370,315 +372,323 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55672102 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13817032 # Transaction distribution -system.membus.trans_dist::ReadResp 13817032 # Transaction distribution -system.membus.trans_dist::WriteReq 375870 # Transaction distribution -system.membus.trans_dist::WriteResp 375870 # Transaction distribution -system.membus.trans_dist::Writeback 17101 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2357 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2357 # Transaction distribution -system.membus.trans_dist::ReadExReq 26474 # Transaction distribution -system.membus.trans_dist::ReadExResp 26474 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736448 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 836141 # Packet count per connected master and slave (bytes) +system.membus.throughput 55673401 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13817014 # Transaction distribution +system.membus.trans_dist::ReadResp 13817014 # Transaction distribution +system.membus.trans_dist::WriteReq 432240 # Transaction distribution +system.membus.trans_dist::WriteResp 432240 # Transaction distribution +system.membus.trans_dist::Writeback 17088 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2349 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2349 # Transaction distribution +system.membus.trans_dist::ReadExReq 28007 # Transaction distribution +system.membus.trans_dist::ReadExResp 28007 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736658 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1572823 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887744 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26887744 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 736448 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 27723885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28460567 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 4770556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1688628 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26887680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28576308 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740538 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5511420 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550976 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107550976 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 112321532 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113062396 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133813146 # Total data (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5089172 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5830178 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107550720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113380898 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133816346 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 415491000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 415555000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 14469192250 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) -system.membus.reqLayer3.occupancy 218000 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1494318294 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 219000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 14607219000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 1602404901 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30346616000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30345557250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 63199 # number of replacements -system.l2c.tags.tagsinuse 50350.442050 # Cycle average of tags in use -system.l2c.tags.total_refs 1748255 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128595 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.595046 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375554811500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36868.064409 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5218.650868 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3758.862884 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 721.252750 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 766.461515 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 4.929404 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1435.478788 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1575.747972 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562562 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079630 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.057356 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011005 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011695 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000075 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.021904 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768287 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8900 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3220 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 462102 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166367 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2587 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1159 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 134524 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 65754 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18045 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4210 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 282039 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 141097 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290004 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597664 # number of Writeback hits -system.l2c.Writeback_hits::total 597664 # number of Writeback hits +system.l2c.tags.replacements 63232 # number of replacements +system.l2c.tags.tagsinuse 50385.545216 # Cycle average of tags in use +system.l2c.tags.total_refs 1748703 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128626 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.595253 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375561795000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36863.517049 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5225.910742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3838.689123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 514.601539 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 693.553663 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.833611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974677 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1665.560742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1574.910611 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562493 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079741 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.007852 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000104 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768822 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8792 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3229 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 468268 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 177348 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2569 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1162 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 128925 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64565 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18612 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4274 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 281840 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 131110 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1290694 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597529 # number of Writeback hits +system.l2c.Writeback_hits::total 597529 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 11 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60793 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19412 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33407 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113612 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8900 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3220 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 462102 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 227160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2587 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1159 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 134524 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 85166 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18045 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4210 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 282039 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 174504 # number of demand (read+write) hits -system.l2c.demand_hits::total 1403616 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8900 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3220 # number of overall hits -system.l2c.overall_hits::cpu0.inst 462102 # number of overall hits -system.l2c.overall_hits::cpu0.data 227160 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2587 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1159 # number of overall hits -system.l2c.overall_hits::cpu1.inst 134524 # number of overall hits -system.l2c.overall_hits::cpu1.data 85166 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18045 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4210 # number of overall hits -system.l2c.overall_hits::cpu2.inst 282039 # number of overall hits -system.l2c.overall_hits::cpu2.data 174504 # number of overall hits -system.l2c.overall_hits::total 1403616 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 61796 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 18660 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33186 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113642 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8792 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3229 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 468268 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 239144 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2569 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1162 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 128925 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 83225 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 18612 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4274 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 281840 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 164296 # number of demand (read+write) hits +system.l2c.demand_hits::total 1404336 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8792 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3229 # number of overall hits +system.l2c.overall_hits::cpu0.inst 468268 # number of overall hits +system.l2c.overall_hits::cpu0.data 239144 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2569 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1162 # number of overall hits +system.l2c.overall_hits::cpu1.inst 128925 # number of overall hits +system.l2c.overall_hits::cpu1.data 83225 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18612 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4274 # number of overall hits +system.l2c.overall_hits::cpu2.inst 281840 # number of overall hits +system.l2c.overall_hits::cpu2.data 164296 # number of overall hits +system.l2c.overall_hits::total 1404336 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7573 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6382 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7579 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6466 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1227 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1212 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 6 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2682 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2534 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21620 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1013 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1126 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2929 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2523 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21648 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1417 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 474 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 1011 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2902 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 106027 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9825 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 17521 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133373 # number of ReadExReq misses +system.l2c.UpgradeReq_misses::cpu2.data 1014 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 104500 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9736 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 19132 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133368 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7573 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 112409 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7579 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 110966 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1227 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 11037 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 6 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2682 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 20055 # number of demand (read+write) misses -system.l2c.demand_misses::total 154993 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1013 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10862 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2929 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 21655 # number of demand (read+write) misses +system.l2c.demand_misses::total 155016 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7573 # number of overall misses -system.l2c.overall_misses::cpu0.data 112409 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7579 # number of overall misses +system.l2c.overall_misses::cpu0.data 110966 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1227 # number of overall misses -system.l2c.overall_misses::cpu1.data 11037 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 6 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2682 # number of overall misses -system.l2c.overall_misses::cpu2.data 20055 # number of overall misses -system.l2c.overall_misses::total 154993 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1013 # number of overall misses +system.l2c.overall_misses::cpu1.data 10862 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2929 # number of overall misses +system.l2c.overall_misses::cpu2.data 21655 # number of overall misses +system.l2c.overall_misses::total 155016 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 88750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 89183000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 89694250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 534000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 214633000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 192644000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 586777000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 75420750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 83519750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 595250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 88750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 229132750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 191859499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 580705499 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 93996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 93496 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 187492 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 627602225 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1227849653 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1855451878 # number of ReadExReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 163493 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 257489 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 623287225 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1332698664 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1955985889 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 88750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 89183000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 717296475 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 534000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 214633000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1420493653 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2442228878 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 75420750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 706806975 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 595250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 88750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 229132750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1524558163 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2536691388 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 88750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 89183000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 717296475 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 534000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 214633000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1420493653 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2442228878 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8901 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3222 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 469675 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 172749 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2588 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1159 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 135751 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 66966 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 18051 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 4210 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 284721 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 143631 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1311624 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597664 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597664 # number of Writeback accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 75420750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 706806975 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 595250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 88750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 229132750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1524558163 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2536691388 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8793 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3231 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 475847 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 183814 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2570 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1162 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 129938 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 65691 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 18619 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4275 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 284769 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 133633 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1312342 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597529 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597529 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1431 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 478 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1026 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2935 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 1025 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2934 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu2.data 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166820 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 29237 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 50928 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246985 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8901 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3222 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 469675 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 339569 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2588 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1159 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 135751 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 96203 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 18051 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 4210 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 284721 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 194559 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1558609 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8901 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3222 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 469675 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 339569 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2588 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1159 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 135751 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 96203 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 18051 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 4210 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 284721 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 194559 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1558609 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000621 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016124 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036944 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000386 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009039 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.018099 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000332 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.009420 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.017642 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016483 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 166296 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28396 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 52318 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247010 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8793 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3231 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 475847 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 350110 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2570 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1162 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 129938 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 94087 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 18619 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4275 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 284769 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 185951 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1559352 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8793 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3231 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 475847 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 350110 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2570 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1162 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 129938 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 94087 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 18619 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4275 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 284769 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 185951 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1559352 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000619 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015927 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.035177 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007796 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017141 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000376 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000234 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.010286 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.018880 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016496 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990217 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991632 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.985380 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.988756 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.635577 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.336047 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.344035 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.540004 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000621 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016124 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.331034 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000386 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009039 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.114726 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000332 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.009420 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.103079 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.099443 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000621 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016124 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.331034 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000386 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009039 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.114726 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000332 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.009420 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.103079 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.099443 # miss rate for overall accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.989268 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.990116 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.628398 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.342865 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.365687 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539930 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000619 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015927 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.316946 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007796 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.115446 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000376 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000234 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.010286 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.116455 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.099411 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000114 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000619 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015927 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.316946 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007796 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.115446 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000376 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000234 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.010286 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.116455 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.099411 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72683.781581 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 74005.156766 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 89000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 80027.218494 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 76023.677979 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 27140.471785 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74452.862784 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 74173.845471 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85035.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78229.003073 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 76044.193024 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 26824.902947 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 198.303797 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 92.478734 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 64.607857 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63878.089059 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 70078.742823 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 13911.750339 # average ReadExReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 161.235700 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 88.636489 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64018.819330 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 69658.094501 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 14666.080986 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72683.781581 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 64990.167165 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 89000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 80027.218494 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 70829.900424 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 15757.026950 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 74452.862784 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 65071.531486 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85035.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 78229.003073 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 70402.131748 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 16364.061697 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72683.781581 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 64990.167165 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 89000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 80027.218494 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 70829.900424 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 15757.026950 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 74452.862784 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 65071.531486 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85035.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 78229.003073 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 70402.131748 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 16364.061697 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -687,134 +697,146 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58478 # number of writebacks -system.l2c.writebacks::total 58478 # number of writebacks +system.l2c.writebacks::writebacks 58495 # number of writebacks +system.l2c.writebacks::total 58495 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.data 12 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1227 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1212 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 6 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2681 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2523 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7650 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1013 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1126 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2928 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2511 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7587 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 474 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 1011 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1485 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9825 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 17521 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 27346 # number of ReadExReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 1014 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1488 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9736 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 19132 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 28868 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1227 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 11037 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 6 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2681 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 20044 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 34996 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1013 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10862 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2928 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 21643 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 36455 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1227 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 11037 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 6 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2681 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 20044 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 34996 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1013 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10862 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2928 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 21643 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 36455 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 73683000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 74301250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 457500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 180621750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 160030500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 489170250 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4740974 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10111011 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14851985 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 504138275 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1005417847 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1509556122 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 62622750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 69218750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 506250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 76250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 191992000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 159345749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 483837999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4740474 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10141014 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14881488 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 500926275 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1090069836 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1590996111 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 73683000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 578439525 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 457500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 180621750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1165448347 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1998726372 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 62622750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 570145025 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 506250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 76250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 191992000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1249415585 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2074834110 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 73683000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 578439525 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 457500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 180621750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1165448347 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1998726372 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25110922000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26464964500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 51575886500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 934919099 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9811837250 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 10746756349 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26045841099 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36276801750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 62322642849 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000386 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009039 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018099 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000332 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009416 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017566 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.005832 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 62622750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 570145025 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 506250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 76250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 191992000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1249415585 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2074834110 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25122070000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26464740500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51586810500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 939177000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8518259500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 9457436500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26061247000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34983000000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 61044247000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007796 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017141 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000376 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000234 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010282 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018790 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005781 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991632 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985380 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.505963 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.336047 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.344035 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.110719 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000386 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009039 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.114726 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000332 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009416 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.103023 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.022453 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000386 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009039 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.114726 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000332 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009416 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.103023 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.022453 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.989268 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.507157 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.342865 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365687 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.116870 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007796 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.115446 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000376 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000234 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010282 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116391 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023378 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007796 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115446 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000376 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000234 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010282 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116391 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023378 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60051.344743 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61304.661716 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 67371.036927 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63428.656361 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63943.823529 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.054852 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61819.101678 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61473.134991 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63459.079650 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63771.978252 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.336700 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51311.783715 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 57383.588094 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 55202.081548 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51450.932108 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 56976.261551 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 55112.793093 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60051.344743 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52409.126121 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 67371.036927 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 58144.499451 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57112.994971 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61819.101678 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52489.875253 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 57728.391859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 56914.939240 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60051.344743 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52409.126121 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 67371.036927 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 58144.499451 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57112.994971 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61819.101678 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52489.875253 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 72321.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65571.038251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 57728.391859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 56914.939240 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -831,52 +853,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58801079 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1037457 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1037456 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 375870 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 375870 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 275194 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution +system.toL2Bus.throughput 58805533 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1021031 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1021030 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432240 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432240 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 264941 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1503 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1507 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80165 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80165 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 841603 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2342492 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15419 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50807 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 3250321 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26910144 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38454204 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21476 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 82556 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 65468380 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141234858 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 99080 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2173969472 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1506 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80714 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80714 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830128 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423683 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15492 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51832 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3321135 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26541184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37337186 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21748 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 63984874 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141242678 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 102048 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2176255494 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1896208409 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1870489205 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1871332229 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1849664390 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10065963 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10070717 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30326428 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30771737 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48764132 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13809327 # Transaction distribution -system.iobus.trans_dist::ReadResp 13809327 # Transaction distribution -system.iobus.trans_dist::WriteReq 2769 # Transaction distribution -system.iobus.trans_dist::WriteResp 2769 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48764104 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13809372 # Transaction distribution +system.iobus.trans_dist::ReadResp 13809372 # Transaction distribution +system.iobus.trans_dist::WriteReq 2797 # Transaction distribution +system.iobus.trans_dist::WriteResp 2797 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11494 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 22 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721570 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -892,42 +914,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 736448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26887744 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27624192 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 736658 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887680 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26887680 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27624338 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6052 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 44 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -943,42 +941,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 740396 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550976 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108291372 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 740538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550720 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550720 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108291258 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 117209190 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7942000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 8031000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1545000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1513000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 131000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -986,7 +960,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 361211000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 361287000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -1018,35 +992,35 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13443872000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13443840000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 733679000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 733861000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36855511000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36856295750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8066197 # DTB read hits -system.cpu0.dtb.read_misses 6232 # DTB read misses -system.cpu0.dtb.write_hits 6664992 # DTB write hits -system.cpu0.dtb.write_misses 2050 # DTB write misses +system.cpu0.dtb.read_hits 8004008 # DTB read hits +system.cpu0.dtb.read_misses 6222 # DTB read misses +system.cpu0.dtb.write_hits 6595133 # DTB write hits +system.cpu0.dtb.write_misses 2001 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5697 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5693 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 113 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 118 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8072429 # DTB read accesses -system.cpu0.dtb.write_accesses 6667042 # DTB write accesses +system.cpu0.dtb.read_accesses 8010230 # DTB read accesses +system.cpu0.dtb.write_accesses 6597134 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14731189 # DTB hits -system.cpu0.dtb.misses 8282 # DTB misses -system.cpu0.dtb.accesses 14739471 # DTB accesses -system.cpu0.itb.inst_hits 32886560 # ITB inst hits -system.cpu0.itb.inst_misses 3493 # ITB inst misses +system.cpu0.dtb.hits 14599141 # DTB hits +system.cpu0.dtb.misses 8223 # DTB misses +system.cpu0.dtb.accesses 14607364 # DTB accesses +system.cpu0.itb.inst_hits 32379967 # ITB inst hits +system.cpu0.itb.inst_misses 3492 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1055,407 +1029,407 @@ system.cpu0.itb.flush_tlb 279 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2599 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2598 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32890053 # ITB inst accesses -system.cpu0.itb.hits 32886560 # DTB hits -system.cpu0.itb.misses 3493 # DTB misses -system.cpu0.itb.accesses 32890053 # DTB accesses -system.cpu0.numCycles 114224752 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32383459 # ITB inst accesses +system.cpu0.itb.hits 32379967 # DTB hits +system.cpu0.itb.misses 3492 # DTB misses +system.cpu0.itb.accesses 32383459 # DTB accesses +system.cpu0.numCycles 113662532 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32403519 # Number of instructions committed -system.cpu0.committedOps 42610516 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37756553 # Number of integer alu accesses +system.cpu0.committedInsts 31896171 # Number of instructions committed +system.cpu0.committedOps 42061376 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37196625 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5021 # Number of float alu accesses -system.cpu0.num_func_calls 1186218 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4240514 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37756553 # number of integer instructions +system.cpu0.num_func_calls 1200231 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4252287 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37196625 # number of integer instructions system.cpu0.num_fp_insts 5021 # number of float instructions -system.cpu0.num_int_register_reads 192274568 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39869839 # number of times the integer registers were written +system.cpu0.num_int_register_reads 189594254 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39319391 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3591 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1432 # number of times the floating registers were written -system.cpu0.num_mem_refs 15395098 # number of memory refs -system.cpu0.num_load_insts 8432454 # Number of load instructions -system.cpu0.num_store_insts 6962644 # Number of store instructions -system.cpu0.num_idle_cycles 13455441823.416426 # Number of idle cycles -system.cpu0.num_busy_cycles -13341217071.416426 # Number of busy cycles -system.cpu0.not_idle_fraction -116.797952 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.797952 # Percentage of idle cycles +system.cpu0.num_mem_refs 15267333 # number of memory refs +system.cpu0.num_load_insts 8373046 # Number of load instructions +system.cpu0.num_store_insts 6894287 # Number of store instructions +system.cpu0.num_idle_cycles 110849279.389256 # Number of idle cycles +system.cpu0.num_busy_cycles 2813252.610744 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024751 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975249 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891011 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.603846 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 44299550 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891523 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 49.689744 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8175687500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 482.268023 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 22.017936 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 7.317887 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.941930 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.043004 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.014293 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32418840 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8204019 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3676691 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44299550 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32418840 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8204019 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3676691 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 44299550 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32418840 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8204019 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3676691 # number of overall hits -system.cpu0.icache.overall_hits::total 44299550 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 470403 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 136004 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 309613 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916020 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 470403 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 136004 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 309613 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916020 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 470403 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 136004 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 309613 # number of overall misses -system.cpu0.icache.overall_misses::total 916020 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1849388500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4165072081 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6014460581 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1849388500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4165072081 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6014460581 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1849388500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4165072081 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6014460581 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32889243 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8340023 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3986304 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 45215570 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32889243 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8340023 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3986304 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 45215570 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32889243 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8340023 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3986304 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 45215570 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014303 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016307 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.077669 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020259 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014303 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016307 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.077669 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020259 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014303 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016307 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.077669 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020259 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13598.044910 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13452.510331 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6565.861642 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13598.044910 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13452.510331 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6565.861642 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13598.044910 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13452.510331 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6565.861642 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4560 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 891479 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.603901 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43691974 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 891991 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.982528 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8175687500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.614782 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.336202 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.652916 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964091 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014329 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020806 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 31906072 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8054900 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3731002 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43691974 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31906072 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8054900 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3731002 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43691974 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31906072 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8054900 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3731002 # number of overall hits +system.cpu0.icache.overall_hits::total 43691974 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 476577 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 130192 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 309459 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916228 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 476577 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 130192 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 309459 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916228 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 476577 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 130192 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 309459 # number of overall misses +system.cpu0.icache.overall_misses::total 916228 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1761830250 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4180298881 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5942129131 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1761830250 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4180298881 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5942129131 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1761830250 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4180298881 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5942129131 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32382649 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8185092 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4040461 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 44608202 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32382649 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8185092 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4040461 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44608202 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32382649 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8185092 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4040461 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44608202 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014717 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015906 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076590 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020539 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014717 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015906 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076590 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020539 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014717 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015906 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076590 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020539 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13532.553844 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13508.409453 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6485.426260 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13532.553844 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13508.409453 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6485.426260 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13532.553844 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13508.409453 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6485.426260 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4261 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 244 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 235 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.688525 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.131915 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24485 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 24485 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 24485 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 24485 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 24485 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 24485 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 136004 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 285128 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 421132 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 136004 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 285128 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 421132 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 136004 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 285128 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 421132 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1576777500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3389021328 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4965798828 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1576777500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3389021328 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4965798828 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1576777500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3389021328 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4965798828 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016307 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.071527 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009314 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016307 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.071527 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009314 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016307 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.071527 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009314 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11593.611217 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11885.964647 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11791.549509 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11593.611217 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11885.964647 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11791.549509 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11593.611217 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11885.964647 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11791.549509 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24229 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 24229 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 24229 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 24229 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 24229 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 24229 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 130192 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 285230 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 415422 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 130192 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 285230 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 415422 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 130192 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 285230 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 415422 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1500951750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3402203278 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4903155028 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1500951750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3402203278 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4903155028 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1500951750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3402203278 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4903155028 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015906 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070593 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009313 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015906 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070593 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009313 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015906 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070593 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009313 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11528.755607 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11927.929313 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11802.829479 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11528.755607 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11927.929313 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11802.829479 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11528.755607 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11927.929313 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11802.829479 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 629819 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997118 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23234096 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630331 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 36.860151 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.812833 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 10.396627 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.787658 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966431 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.020306 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013257 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6949237 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1880036 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4481409 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13310682 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5977872 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1354370 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2102552 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9434794 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131076 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34176 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73005 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238257 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137394 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35968 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74026 # number of StoreCondReq hits +system.cpu0.dcache.tags.replacements 629636 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997119 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23222123 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 630148 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.851855 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.117005 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.034615 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.845498 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970932 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015693 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013370 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6875315 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1820667 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4627275 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13323257 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5963983 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1316466 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2129753 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9410202 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131811 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33157 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73317 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238285 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138270 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34889 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74229 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247388 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12927109 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3234406 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6583961 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22745476 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12927109 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3234406 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6583961 # number of overall hits -system.cpu0.dcache.overall_hits::total 22745476 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 166432 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 65173 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 288335 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 519940 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 168251 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29715 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 583568 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 781534 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6317 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1793 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3873 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11983 # number of LoadLockedReq misses +system.cpu0.dcache.demand_hits::cpu0.data 12839298 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3137133 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6757028 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22733459 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12839298 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3137133 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6757028 # number of overall hits +system.cpu0.dcache.overall_hits::total 22733459 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 177356 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 63959 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 269175 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 510490 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167727 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 28874 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 609519 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 806120 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6458 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1732 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3768 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11958 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 334683 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94888 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 871903 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1301474 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 334683 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 94888 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 871903 # number of overall misses -system.cpu0.dcache.overall_misses::total 1301474 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 929748000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4191596038 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5121344038 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 926575749 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 20791104854 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21717680603 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 23532750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 51118749 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 74651499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 345083 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 92833 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 878694 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1316610 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 345083 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 92833 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 878694 # number of overall misses +system.cpu0.dcache.overall_misses::total 1316610 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 908429000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3875625037 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4784054037 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 912156249 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 22615267762 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 23527424011 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22739750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 50485499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 73225249 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 39000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1856323749 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 24982700892 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 26839024641 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1856323749 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 24982700892 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 26839024641 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7115669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1945209 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4769744 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13830622 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6146123 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1384085 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2686120 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216328 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137393 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35969 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76878 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250240 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137394 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35968 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74029 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu1.data 1820585249 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 26490892799 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 28311478048 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1820585249 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 26490892799 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 28311478048 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7052671 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1884626 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4896450 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13833747 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6131710 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1345340 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2739272 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216322 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138269 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34889 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77085 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250243 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138270 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34889 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74232 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247391 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13261792 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3329294 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7455864 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24046950 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13261792 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3329294 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7455864 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24046950 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023390 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033504 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.060451 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037593 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027375 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021469 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.217253 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.076499 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045978 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049848 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050379 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047886 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000041 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 13184381 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3229966 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7635722 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24050069 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13184381 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3229966 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7635722 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24050069 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025147 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033937 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.054974 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036902 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027354 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021462 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222511 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.078905 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046706 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049643 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048881 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047786 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000040 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025237 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028501 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116942 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054122 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025237 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028501 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.116942 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054122 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14265.846286 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14537.243269 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9849.875059 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31182.088137 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 35627.561576 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 27788.529486 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13124.790853 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13198.747483 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6229.783777 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026174 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028741 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115077 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054745 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026174 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028741 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.115077 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054745 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14203.302115 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14398.161185 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9371.494127 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31590.920863 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37103.466442 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29186.007060 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13129.185912 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13398.486996 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6123.536461 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19563.314107 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28653.073670 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20622.021370 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19563.314107 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 28653.073670 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 20622.021370 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9525 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3241 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1204 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 49 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.911130 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 66.142857 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19611.401646 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30148.029688 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21503.313850 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19611.401646 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30148.029688 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21503.313850 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7835 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2458 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 871 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 50 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.995408 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 49.160000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597664 # number of writebacks -system.cpu0.dcache.writebacks::total 597664 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 148092 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 148092 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 531664 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 531664 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 435 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 435 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 679756 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 679756 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 679756 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 679756 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65173 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 140243 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 205416 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29715 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 51904 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 81619 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1793 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3438 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5231 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 597529 # number of writebacks +system.cpu0.dcache.writebacks::total 597529 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 138849 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 138849 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556206 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 556206 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 431 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 431 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 695055 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 695055 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 695055 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 695055 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63959 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 130326 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 194285 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28874 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53313 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82187 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1732 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3337 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5069 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 94888 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 192147 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 287035 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 94888 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 192147 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 287035 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 798815000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1812392117 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2611207117 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 862528251 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1666606492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2529134743 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19945250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39526251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59471501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92833 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 183639 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 276472 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92833 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 183639 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 276472 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779964000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1680980850 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2460944850 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 849834751 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1771488501 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2621323252 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19274250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38952001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58226251 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1661343251 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3478998609 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5140341860 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1661343251 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3478998609 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5140341860 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27433716000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28893863250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56327579250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1437767401 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13930226833 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15367994234 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28871483401 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42824090083 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71695573484 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033504 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029403 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014852 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021469 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019323 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007989 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049848 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044720 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020904 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000041 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1629798751 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3452469351 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5082268102 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1629798751 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3452469351 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5082268102 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27446152500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28893354250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56339506750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1446442000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341405748 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14787847748 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28892594500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42234759998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71127354498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033937 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026616 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014044 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021462 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019462 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008045 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049643 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043290 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020256 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000040 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011936 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011936 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12256.839489 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12923.226949 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12711.800040 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29026.695305 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32109.403745 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30987.083191 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11123.954267 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.873473 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11369.050086 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011496 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011496 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12194.749762 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12898.277013 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12666.674473 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29432.525836 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33228.077598 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31894.621436 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11128.319861 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11672.760264 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11486.733281 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1468,26 +1442,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2159851 # DTB read hits -system.cpu1.dtb.read_misses 2083 # DTB read misses -system.cpu1.dtb.write_hits 1460405 # DTB write hits -system.cpu1.dtb.write_misses 373 # DTB write misses +system.cpu1.dtb.read_hits 2098287 # DTB read hits +system.cpu1.dtb.read_misses 2070 # DTB read misses +system.cpu1.dtb.write_hits 1420937 # DTB write hits +system.cpu1.dtb.write_misses 371 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1742 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1726 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 44 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 38 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2161934 # DTB read accesses -system.cpu1.dtb.write_accesses 1460778 # DTB write accesses +system.cpu1.dtb.read_accesses 2100357 # DTB read accesses +system.cpu1.dtb.write_accesses 1421308 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3620256 # DTB hits -system.cpu1.dtb.misses 2456 # DTB misses -system.cpu1.dtb.accesses 3622712 # DTB accesses -system.cpu1.itb.inst_hits 8340023 # ITB inst hits +system.cpu1.dtb.hits 3519224 # DTB hits +system.cpu1.dtb.misses 2441 # DTB misses +system.cpu1.dtb.accesses 3521665 # DTB accesses +system.cpu1.itb.inst_hits 8185092 # ITB inst hits system.cpu1.itb.inst_misses 1172 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1504,66 +1478,66 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8341195 # ITB inst accesses -system.cpu1.itb.hits 8340023 # DTB hits +system.cpu1.itb.inst_accesses 8186264 # ITB inst accesses +system.cpu1.itb.hits 8185092 # DTB hits system.cpu1.itb.misses 1172 # DTB misses -system.cpu1.itb.accesses 8341195 # DTB accesses -system.cpu1.numCycles 580203695 # number of cpu cycles simulated +system.cpu1.itb.accesses 8186264 # DTB accesses +system.cpu1.numCycles 580203625 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8134078 # Number of instructions committed -system.cpu1.committedOps 10379103 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9286356 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2127 # Number of float alu accesses -system.cpu1.num_func_calls 319009 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1149936 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9286356 # number of integer instructions -system.cpu1.num_fp_insts 2127 # number of float instructions -system.cpu1.num_int_register_reads 53580768 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10053974 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1614 # number of times the floating registers were read +system.cpu1.committedInsts 7980801 # Number of instructions committed +system.cpu1.committedOps 10142634 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9072894 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses +system.cpu1.num_func_calls 304668 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1116676 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9072894 # number of integer instructions +system.cpu1.num_fp_insts 2143 # number of float instructions +system.cpu1.num_int_register_reads 52281658 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9864872 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written -system.cpu1.num_mem_refs 3795930 # number of memory refs -system.cpu1.num_load_insts 2256544 # Number of load instructions -system.cpu1.num_store_insts 1539386 # Number of store instructions -system.cpu1.num_idle_cycles 585938491.751716 # Number of idle cycles -system.cpu1.num_busy_cycles -5734796.751716 # Number of busy cycles -system.cpu1.not_idle_fraction -0.009884 # Percentage of non-idle cycles -system.cpu1.idle_fraction 1.009884 # Percentage of idle cycles +system.cpu1.num_mem_refs 3686646 # number of memory refs +system.cpu1.num_load_insts 2191239 # Number of load instructions +system.cpu1.num_store_insts 1495407 # Number of store instructions +system.cpu1.num_idle_cycles 544226668.771142 # Number of idle cycles +system.cpu1.num_busy_cycles 35976956.228858 # Number of busy cycles +system.cpu1.not_idle_fraction 0.062007 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.937993 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4707573 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3829869 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 221083 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3125328 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2519731 # Number of BTB hits +system.cpu2.branchPred.lookups 4715473 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3836739 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223495 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3141743 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2527502 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.622930 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 410392 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21556 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.449037 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 411571 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21589 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10881991 # DTB read hits -system.cpu2.dtb.read_misses 22472 # DTB read misses -system.cpu2.dtb.write_hits 3235005 # DTB write hits -system.cpu2.dtb.write_misses 5987 # DTB write misses +system.cpu2.dtb.read_hits 10976033 # DTB read hits +system.cpu2.dtb.read_misses 22752 # DTB read misses +system.cpu2.dtb.write_hits 3346841 # DTB write hits +system.cpu2.dtb.write_misses 6453 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2290 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 674 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 165 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2303 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 671 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 173 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 480 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10904463 # DTB read accesses -system.cpu2.dtb.write_accesses 3240992 # DTB write accesses +system.cpu2.dtb.perms_faults 460 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10998785 # DTB read accesses +system.cpu2.dtb.write_accesses 3353294 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14116996 # DTB hits -system.cpu2.dtb.misses 28459 # DTB misses -system.cpu2.dtb.accesses 14145455 # DTB accesses -system.cpu2.itb.inst_hits 3987789 # ITB inst hits -system.cpu2.itb.inst_misses 4600 # ITB inst misses +system.cpu2.dtb.hits 14322874 # DTB hits +system.cpu2.dtb.misses 29205 # DTB misses +system.cpu2.dtb.accesses 14352079 # DTB accesses +system.cpu2.itb.inst_hits 4041881 # ITB inst hits +system.cpu2.itb.inst_misses 4586 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1572,290 +1546,290 @@ system.cpu2.itb.flush_tlb 276 # Nu system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1704 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1634 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1012 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1002 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 3992389 # ITB inst accesses -system.cpu2.itb.hits 3987789 # DTB hits -system.cpu2.itb.misses 4600 # DTB misses -system.cpu2.itb.accesses 3992389 # DTB accesses -system.cpu2.numCycles 88356031 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4046467 # ITB inst accesses +system.cpu2.itb.hits 4041881 # DTB hits +system.cpu2.itb.misses 4586 # DTB misses +system.cpu2.itb.accesses 4046467 # DTB accesses +system.cpu2.numCycles 88343562 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9299223 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32583630 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4707573 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2930123 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6845670 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1836223 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50265 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18768642 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 865 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32747 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 722165 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3986309 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 272069 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2032 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36980430 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.055775 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.444098 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9345666 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32463757 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4715473 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2939073 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6849430 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1758819 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50954 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18707448 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 820 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32452 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 720275 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 489 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4040467 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 290046 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2014 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36916106 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.056921 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.443441 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30139736 81.50% 81.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 382786 1.04% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 509834 1.38% 83.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 817196 2.21% 86.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 649833 1.76% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 340544 0.92% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1001875 2.71% 91.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 233328 0.63% 92.14% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2905298 7.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30071749 81.46% 81.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 384570 1.04% 82.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 513519 1.39% 83.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 818109 2.22% 86.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 634612 1.72% 87.83% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 341178 0.92% 88.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1041484 2.82% 91.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 228835 0.62% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2882050 7.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36980430 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053280 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.368777 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9914058 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19374148 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6194025 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 289491 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1207748 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608647 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53413 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36680754 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 180211 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1207748 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10448619 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6814881 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11054882 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5930497 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1522855 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34729839 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2439 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 374808 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 885539 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 119 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37310430 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 158812282 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 158784890 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27392 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25602072 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11708357 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 230914 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207478 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3294482 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6519802 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3791560 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 528920 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 689934 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31598942 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 510602 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34143520 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55455 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7440971 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19631999 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 154198 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36980430 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.923286 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.579350 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36916106 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053377 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367472 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9928442 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19318553 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6233841 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 278394 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1155918 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 607967 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53425 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36920328 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 180410 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1155918 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10478416 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6754031 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11105712 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5942637 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1478447 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34829842 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2448 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 324847 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 890462 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 131 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37304234 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 159387361 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 159360013 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27348 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26430435 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10873798 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231762 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 208068 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3242623 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6608021 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3899448 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 530191 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 761841 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32138723 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 510591 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34782251 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 56051 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7186073 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19057300 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 153940 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36916106 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.942197 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.600639 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24453619 66.13% 66.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3907365 10.57% 76.69% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2316831 6.27% 82.96% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2013006 5.44% 88.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2745101 7.42% 95.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 885827 2.40% 98.22% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 492123 1.33% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 131266 0.35% 99.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35292 0.10% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24329752 65.91% 65.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3820331 10.35% 76.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2317804 6.28% 82.53% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2003808 5.43% 87.96% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2797781 7.58% 95.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 970796 2.63% 98.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 496090 1.34% 99.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144708 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35036 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36980430 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36916106 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 18547 1.21% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407485 91.52% 92.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 111832 7.27% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19314 1.26% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.26% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1407095 91.52% 92.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 111138 7.23% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61314 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19310512 56.56% 56.74% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 26216 0.08% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 4 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 4 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 372 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11345203 33.23% 90.04% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3399891 9.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61377 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19718575 56.69% 56.87% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 27760 0.08% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 9 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 371 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11459171 32.95% 89.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3514969 10.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34143520 # Type of FU issued -system.cpu2.iq.rate 0.386431 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1537865 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.045041 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 106882112 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39555566 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27370238 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7010 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3779 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3144 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35616337 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3734 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206224 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34782251 # Type of FU issued +system.cpu2.iq.rate 0.393716 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1537548 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044205 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108096303 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39840742 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28020326 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6981 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3693 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3127 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36254698 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3724 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 204617 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1563789 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2001 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9138 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 567371 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1527306 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1908 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9375 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562929 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5351721 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 380538 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5348773 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344308 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1207748 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5118466 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 92736 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32192718 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 58170 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6519802 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3791560 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 368228 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31927 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2425 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9138 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105201 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88411 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193612 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33245955 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11093572 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 897565 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1155918 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5077664 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 88593 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32732277 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60627 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6608021 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3899448 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 368370 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29616 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2740 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9375 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107393 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89251 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196644 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33865771 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11188559 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 916480 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 83174 # number of nop insts executed -system.cpu2.iew.exec_refs 14459722 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3671566 # Number of branches executed -system.cpu2.iew.exec_stores 3366150 # Number of stores executed -system.cpu2.iew.exec_rate 0.376273 # Inst execution rate -system.cpu2.iew.wb_sent 32817620 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27373382 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15610718 # num instructions producing a value -system.cpu2.iew.wb_consumers 28284338 # num instructions consuming a value +system.cpu2.iew.exec_nop 82963 # number of nop insts executed +system.cpu2.iew.exec_refs 14669578 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3700003 # Number of branches executed +system.cpu2.iew.exec_stores 3481019 # Number of stores executed +system.cpu2.iew.exec_rate 0.383342 # Inst execution rate +system.cpu2.iew.wb_sent 33465265 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28023453 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16087448 # num instructions producing a value +system.cpu2.iew.wb_consumers 29114707 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.309808 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.551921 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317210 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.552554 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7382656 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356404 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 168463 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35772498 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.686059 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.714745 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7129352 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356651 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 170839 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35759991 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.708498 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.752281 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27202420 76.04% 76.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4136400 11.56% 87.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1256838 3.51% 91.12% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 645513 1.80% 92.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 564789 1.58% 94.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 319868 0.89% 95.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 386889 1.08% 96.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 302652 0.85% 97.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 957129 2.68% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27025739 75.58% 75.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4219923 11.80% 87.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1248297 3.49% 90.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 635334 1.78% 92.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 557295 1.56% 94.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 319233 0.89% 95.09% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 417712 1.17% 96.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 309905 0.87% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1026553 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35772498 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19845047 # Number of instructions committed -system.cpu2.commit.committedOps 24542041 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35759991 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20506693 # Number of instructions committed +system.cpu2.commit.committedOps 25335895 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8180202 # Number of memory references committed -system.cpu2.commit.loads 4956013 # Number of loads committed -system.cpu2.commit.membars 94398 # Number of memory barriers committed -system.cpu2.commit.branches 3153060 # Number of branches committed -system.cpu2.commit.fp_insts 3107 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21774748 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294560 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 957129 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8417234 # Number of memory references committed +system.cpu2.commit.loads 5080715 # Number of loads committed +system.cpu2.commit.membars 94304 # Number of memory barriers committed +system.cpu2.commit.branches 3173719 # Number of branches committed +system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22548127 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294799 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1026553 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66215885 # The number of ROB reads -system.cpu2.rob.rob_writes 65102408 # The number of ROB writes -system.cpu2.timesIdled 362250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51375601 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3556629546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19789566 # Number of Instructions Simulated -system.cpu2.committedOps 24486560 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19789566 # Number of Instructions Simulated -system.cpu2.cpi 4.464779 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.464779 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.223975 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.223975 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153595531 # number of integer regfile reads -system.cpu2.int_regfile_writes 29235365 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22348 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20810 # number of floating regfile writes -system.cpu2.misc_regfile_reads 8997423 # number of misc regfile reads -system.cpu2.misc_regfile_writes 241258 # number of misc regfile writes -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.rob.rob_reads 66675347 # The number of ROB reads +system.cpu2.rob.rob_writes 66130617 # The number of ROB writes +system.cpu2.timesIdled 360964 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51427456 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3556668435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20451214 # Number of Instructions Simulated +system.cpu2.committedOps 25280416 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20451214 # Number of Instructions Simulated +system.cpu2.cpi 4.319722 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.319722 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.231496 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.231496 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 156902302 # number of integer regfile reads +system.cpu2.int_regfile_writes 29839836 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22382 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20836 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9252861 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241910 # number of misc regfile writes +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1864,10 +1838,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1279969503000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1279969503000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1279629373750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1279629373750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index c58b97d9e..62d3d2d33 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,151 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.548515 # Number of seconds simulated -sim_ticks 2548515380000 # Number of ticks simulated -final_tick 2548515380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.548576 # Number of seconds simulated +sim_ticks 2548576209000 # Number of ticks simulated +final_tick 2548576209000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61977 # Simulator instruction rate (inst/s) -host_op_rate 79748 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2618667230 # Simulator tick rate (ticks/s) -host_mem_usage 403588 # Number of bytes of host memory used -host_seconds 973.21 # Real time elapsed on the host -sim_insts 60316341 # Number of instructions simulated -sim_ops 77611368 # Number of ops (including micro ops) simulated +host_inst_rate 60580 # Simulator instruction rate (inst/s) +host_op_rate 77951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2559708219 # Simulator tick rate (ticks/s) +host_mem_usage 399668 # Number of bytes of host memory used +host_seconds 995.65 # Real time elapsed on the host +sim_insts 60316464 # Number of instructions simulated +sim_ops 77611603 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 440128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4850064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 360448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4242200 # Number of bytes read from this memory -system.physmem.bytes_read::total 131005928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 440128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 360448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785088 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1679112 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1336988 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801188 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 483776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5166800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 315264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3924504 # Number of bytes read from this memory +system.physmem.bytes_read::total 131003560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 483776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 315264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799040 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783488 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1522020 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494080 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799588 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6877 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 75816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 66290 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293471 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59142 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 419778 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 334247 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813167 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47521992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 477 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 80765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4926 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 61326 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293434 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59117 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380505 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373520 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813142 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47520858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 728 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 172700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1903094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 141435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1664577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51404802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 172700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 141435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314134 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1485213 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 658859 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 524614 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2668686 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1485213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47521992 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 189822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2027328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 123702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1539881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51402646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 189822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 123702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484550 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 597204 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586241 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2667995 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47520858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 728 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 172700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2561953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 141435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2189191 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54073488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293471 # Total number of read requests seen -system.physmem.writeReqs 813167 # Total number of write requests seen -system.physmem.cpureqs 218464 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978782144 # Total number of bytes read from memory -system.physmem.bytesWritten 52042688 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131005928 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6801188 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4709 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 955865 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955532 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 955892 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 955763 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955786 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955940 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955511 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955116 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956216 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49128 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50979 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51091 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51008 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51204 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51097 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51359 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51272 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51123 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 189822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2624532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 123702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2126122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54070641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293434 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 813142 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15293434 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 813142 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 978779776 # Total number of bytes read from memory +system.physmem.bytesWritten 52041088 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131003560 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799588 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 13 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 955864 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955684 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 955879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 955769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955991 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955868 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 955778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955947 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955508 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955111 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956226 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955972 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956075 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955979 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6690 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6478 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6589 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6842 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6779 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7114 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6901 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6563 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6772 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7070 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6922 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32396 # Number of times wr buffer was full causing retry -system.physmem.totGap 2548513467000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 2548575024500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 42 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154613 # Categorize read packet sizes +system.physmem.readPktSize::6 154576 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754025 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59142 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1060849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 987246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 977477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2806386 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2806166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2776833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 14905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59117 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1061686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 987876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 978214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2813374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2806969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2769477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 43265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 29260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -156,215 +157,205 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32421 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40074 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 25722.964516 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2062.503898 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32877.713086 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 7020 17.52% 17.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3450 8.61% 26.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2302 5.74% 31.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1762 4.40% 36.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1221 3.05% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1083 2.70% 42.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 782 1.95% 43.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 826 2.06% 46.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 552 1.38% 47.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 527 1.32% 48.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 441 1.10% 49.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 399 1.00% 50.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 278 0.69% 51.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 274 0.68% 52.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 181 0.45% 52.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 260 0.65% 53.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 121 0.30% 53.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 146 0.36% 53.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 103 0.26% 54.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 108 0.27% 54.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 77 0.19% 54.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 372 0.93% 55.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 611 1.52% 57.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 461 1.15% 58.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 86 0.21% 58.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 174 0.43% 58.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 54 0.13% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 96 0.24% 59.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 48 0.12% 59.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 68 0.17% 59.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 67 0.17% 59.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 19 0.05% 59.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 52 0.13% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 17 0.04% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 39 0.10% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 17 0.04% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 35 0.09% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 6 0.01% 60.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 5 0.01% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 15 0.04% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 12 0.03% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 19 0.05% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 10 0.02% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 19 0.05% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 14 0.03% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 5 0.01% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 6 0.01% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 5 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 3 0.01% 60.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 12 0.03% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 10 0.02% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 3 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 8 0.02% 60.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 7 0.02% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 6 0.01% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 1 0.00% 60.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 7 0.02% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 35 0.09% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 5 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 2 0.00% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 3 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 7 0.02% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 4 0.01% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 5 0.01% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 1 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 7 0.02% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 1 0.00% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 7 0.02% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 3 0.01% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 3 0.01% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 5 0.01% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 4 0.01% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 2 0.00% 61.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 2 0.00% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 5 0.01% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 4 0.01% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 5 0.01% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5983 1 0.00% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 1 0.00% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 2 0.00% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 4 0.01% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 3 0.01% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6367 2 0.00% 61.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 5 0.01% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 3 0.01% 61.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 4 0.01% 61.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 1 0.00% 61.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 21 0.05% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 4 0.01% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7135 2 0.00% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 3 0.01% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 5 0.01% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 2 0.00% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 3 0.01% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 1 0.00% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 6 0.01% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7775 1 0.00% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 7 0.02% 61.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 7 0.02% 61.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 9 0.02% 61.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 3 0.01% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 305 0.76% 62.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10143 1 0.00% 62.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14111 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16735 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21023 1 0.00% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24799 1 0.00% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26143 1 0.00% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 1 0.00% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27935 2 0.00% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 1 0.00% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30431 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 5 0.01% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34847 1 0.00% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35167 1 0.00% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37663 1 0.00% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39455 1 0.00% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43136-43167 1 0.00% 62.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51487 1 0.00% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56832-56863 1 0.00% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58399 1 0.00% 62.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60864-60895 1 0.00% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14763 36.84% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::126336-126367 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130496-130527 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131008-131039 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 346 0.86% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132127 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::161792-161823 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::168960-168991 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40074 # Bytes accessed per row activation -system.physmem.totQLat 305431681500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 397314004000 # Sum of mem lat for all requests -system.physmem.totBusLat 76467280000 # Total cycles spent in databus access -system.physmem.totBankLat 15415042500 # Total cycles spent in bank access -system.physmem.avgQLat 19971.40 # Average queueing delay per request -system.physmem.avgBankLat 1007.95 # Average bank access latency per request +system.physmem.wrQLenPdf::0 4852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 25091.701456 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2070.748672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31471.829892 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-79 6644 16.91% 16.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-143 3436 8.75% 25.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-207 2300 5.85% 31.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-271 1832 4.66% 36.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-335 1227 3.12% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-399 1105 2.81% 42.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-463 800 2.04% 44.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-527 812 2.07% 46.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-591 554 1.41% 47.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-655 516 1.31% 48.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-719 427 1.09% 50.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-783 432 1.10% 51.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-847 277 0.71% 51.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-911 299 0.76% 52.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-975 172 0.44% 53.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1039 211 0.54% 53.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1103 136 0.35% 53.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1167 132 0.34% 54.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1231 101 0.26% 54.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1295 106 0.27% 54.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1359 70 0.18% 54.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1423 391 1.00% 55.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1487 264 0.67% 56.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1551 450 1.15% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1615 85 0.22% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1679 167 0.43% 58.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1743 56 0.14% 58.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1807 95 0.24% 58.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1871 44 0.11% 58.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1935 79 0.20% 59.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1999 30 0.08% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2063 69 0.18% 59.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2127 18 0.05% 59.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2191 44 0.11% 59.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2255 15 0.04% 59.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2319 32 0.08% 59.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2447 19 0.05% 59.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2511 8 0.02% 59.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2575 26 0.07% 59.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2639 6 0.02% 59.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2703 18 0.05% 59.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2767 15 0.04% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2831 16 0.04% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2895 7 0.02% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2959 13 0.03% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3023 4 0.01% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3087 18 0.05% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3215 6 0.02% 60.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3279 6 0.02% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3343 11 0.03% 60.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3599 6 0.02% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3727 10 0.03% 60.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3791 5 0.01% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3855 3 0.01% 60.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3919 1 0.00% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3983 13 0.03% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4047 4 0.01% 60.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4111 32 0.08% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4175 5 0.01% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4239 4 0.01% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4303 3 0.01% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4367 6 0.02% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4495 5 0.01% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4559 4 0.01% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4623 6 0.02% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4687 3 0.01% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4879 4 0.01% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5007 7 0.02% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5135 8 0.02% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5199 2 0.01% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5263 2 0.01% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5391 3 0.01% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5455 3 0.01% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5519 4 0.01% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5583 1 0.00% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5775 2 0.01% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5903 2 0.01% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6095 1 0.00% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6223 3 0.01% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6287 2 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6351 1 0.00% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6479 2 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6607 1 0.00% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6735 1 0.00% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6799 20 0.05% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6863 3 0.01% 60.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7119 2 0.01% 60.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7311 3 0.01% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7375 2 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7439 4 0.01% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7567 9 0.02% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7631 1 0.00% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7695 7 0.02% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7823 3 0.01% 60.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7887 4 0.01% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7951 2 0.01% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8079 11 0.03% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8143 1 0.00% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8207 311 0.79% 61.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8463 63 0.16% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8527 194 0.49% 62.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8591 13 0.03% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8783 3 0.01% 62.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20495 1 0.00% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25615 2 0.01% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28352-28367 1 0.00% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32207 1 0.00% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33359 1 0.00% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33679 2 0.01% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33807 2 0.01% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34575 1 0.00% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37184-37199 1 0.00% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39503 1 0.00% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45071 1 0.00% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58112-58127 1 0.00% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64768-64783 1 0.00% 62.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65551 14685 37.38% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::68736-68751 1 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73935 9 0.02% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-73999 43 0.11% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74048-74063 33 0.08% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39284 # Bytes accessed per row activation +system.physmem.totQLat 294283871250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 386089225000 # Sum of mem lat for all requests +system.physmem.totBusLat 76467105000 # Total cycles spent in databus access +system.physmem.totBankLat 15338248750 # Total cycles spent in bank access +system.physmem.avgQLat 19242.51 # Average queueing delay per request +system.physmem.avgBankLat 1002.93 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25979.35 # Average memory access latency -system.physmem.avgRdBW 384.06 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25245.45 # Average memory access latency +system.physmem.avgRdBW 384.05 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.40 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 1.11 # Average write queue length over time -system.physmem.readRowHits 15267858 # Number of row buffer hits during reads -system.physmem.writeRowHits 798688 # Number of row buffer hits during writes +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 1.08 # Average write queue length over time +system.physmem.readRowHits 15268174 # Number of row buffer hits during reads +system.physmem.writeRowHits 94166 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes -system.physmem.avgGap 158227.53 # Average gap between requests +system.physmem.writeRowHitRate 11.58 # Row buffer hit rate for writes +system.physmem.avgGap 158231.96 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -377,291 +368,277 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55014417 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346104 # Transaction distribution -system.membus.trans_dist::ReadResp 16346107 # Transaction distribution +system.membus.throughput 55011549 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346066 # Transaction distribution +system.membus.trans_dist::ReadResp 16346069 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59142 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4707 # Transaction distribution +system.membus.trans_dist::Writeback 59117 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4675 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4709 # Transaction distribution -system.membus.trans_dist::ReadExReq 131412 # Transaction distribution -system.membus.trans_dist::ReadExResp 131412 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4677 # Transaction distribution +system.membus.trans_dist::ReadExReq 131414 # Transaction distribution +system.membus.trans_dist::ReadExResp 131414 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382956 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885920 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885757 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272507 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32163552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550300 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550139 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390329 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696588 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19094561 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19090597 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 137807116 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140205089 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140205089 # Total data (bytes) +system.membus.tot_pkt_size::total 140201125 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140201125 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1476111500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475672000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17555240750 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3581500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4707147287 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 17572541000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4757385335 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34172276993 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34173123993 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 64386 # number of replacements -system.l2c.tags.tagsinuse 51442.070809 # Cycle average of tags in use -system.l2c.tags.total_refs 1905390 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129776 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.682145 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2511428822500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36972.715861 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 12.496871 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000368 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4611.296465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3332.598424 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 12.513991 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3606.043873 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2894.404957 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564159 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000191 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070363 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050851 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055024 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044165 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784944 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 33100 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6967 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 497324 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183110 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30320 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6628 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 474382 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 204508 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1436339 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608377 # number of Writeback hits -system.l2c.Writeback_hits::total 608377 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 25 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 20 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.tags.replacements 64349 # number of replacements +system.l2c.tags.tagsinuse 51432.213982 # Cycle average of tags in use +system.l2c.tags.total_refs 1904557 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129741 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.679685 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2511462555500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36971.376669 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 19.336615 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000368 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4863.234399 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3340.353025 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.819885 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3340.869034 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2888.223986 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564138 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000295 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074207 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050970 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000135 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.050978 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044071 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784793 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 31056 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6811 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 489944 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 180708 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 32283 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7013 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 480968 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 206794 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435577 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608201 # number of Writeback hits +system.l2c.Writeback_hits::total 608201 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 22 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 40 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58192 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54720 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112912 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 33100 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6967 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 497324 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 241302 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30320 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6628 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 474382 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 259228 # number of demand (read+write) hits -system.l2c.demand_hits::total 1549251 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 33100 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6967 # number of overall hits -system.l2c.overall_hits::cpu0.inst 497324 # number of overall hits -system.l2c.overall_hits::cpu0.data 241302 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30320 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6628 # number of overall hits -system.l2c.overall_hits::cpu1.inst 474382 # number of overall hits -system.l2c.overall_hits::cpu1.data 259228 # number of overall hits -system.l2c.overall_hits::total 1549251 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 19 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 56719 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56246 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112965 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 31056 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6811 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 489944 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 237427 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 32283 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7013 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 480968 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 263040 # number of demand (read+write) hits +system.l2c.demand_hits::total 1548542 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 31056 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6811 # number of overall hits +system.l2c.overall_hits::cpu0.inst 489944 # number of overall hits +system.l2c.overall_hits::cpu0.data 237427 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 32283 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7013 # number of overall hits +system.l2c.overall_hits::cpu1.inst 480968 # number of overall hits +system.l2c.overall_hits::cpu1.data 263040 # number of overall hits +system.l2c.overall_hits::total 1548542 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6768 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6113 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 19 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5640 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4604 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23165 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1534 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1392 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2926 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses +system.l2c.ReadReq_misses::cpu0.inst 7450 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6327 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4932 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4374 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23125 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1313 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1598 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 70693 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 62500 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133193 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 19 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::cpu0.data 75216 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 57962 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133178 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6768 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 76806 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5640 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 67104 # number of demand (read+write) misses -system.l2c.demand_misses::total 156358 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 19 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7450 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 81543 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4932 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 62336 # number of demand (read+write) misses +system.l2c.demand_misses::total 156303 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6768 # number of overall misses -system.l2c.overall_misses::cpu0.data 76806 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5640 # number of overall misses -system.l2c.overall_misses::cpu1.data 67104 # number of overall misses -system.l2c.overall_misses::total 156358 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2128750 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 7450 # number of overall misses +system.l2c.overall_misses::cpu0.data 81543 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4932 # number of overall misses +system.l2c.overall_misses::cpu1.data 62336 # number of overall misses +system.l2c.overall_misses::total 156303 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2773750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 130250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 500312250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 448378498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2066250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 418450000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 353541000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1725006998 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 186492 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 256989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 443481 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 22999 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 22999 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4862001015 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4300719454 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9162720469 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2128750 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 535863000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 458241999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1150250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 375877250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 330560248 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1704596747 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 185492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 279988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5248575225 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3913924011 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9162499236 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2773750 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 130250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 500312250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 5310379513 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 2066250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 418450000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4654260454 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10887727467 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2128750 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 535863000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5706817224 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1150250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 375877250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4244484259 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10867095983 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2773750 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 130250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 500312250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 5310379513 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 2066250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 418450000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4654260454 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10887727467 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 33119 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6969 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 504092 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 189223 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30339 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6628 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 480022 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 209112 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1459504 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608377 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608377 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1559 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1412 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2971 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 6 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 128885 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 117220 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 33119 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6969 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 504092 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 318108 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30339 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6628 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 480022 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 326332 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1705609 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 33119 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6969 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 504092 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 318108 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30339 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6628 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 480022 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 326332 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1705609 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000574 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000287 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013426 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.032306 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.011749 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.022017 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015872 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.983964 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.985836 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.984854 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.285714 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.153846 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.548497 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.533185 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541204 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000574 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000287 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013426 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.241446 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011749 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.205631 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091673 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000574 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000287 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013426 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.241446 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000626 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011749 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.205631 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091673 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 112039.473684 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 535863000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5706817224 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1150250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 375877250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4244484259 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10867095983 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 31085 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6813 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 497394 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 187035 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 32294 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7013 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 485900 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 211168 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1458702 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 608201 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 608201 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1331 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1620 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 131935 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 114208 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246143 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 31085 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6813 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 497394 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 318970 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 32294 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7013 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 485900 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 325376 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1704845 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 31085 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6813 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 497394 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 318970 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 32294 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7013 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 485900 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 325376 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1704845 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000294 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.033828 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010150 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.020713 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015853 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.986476 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.986420 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.986445 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.570099 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.507513 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541059 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000294 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014978 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.255645 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010150 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.191581 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091682 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000933 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000294 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014978 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.255645 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000341 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010150 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.191581 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091682 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 65125 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73923.204787 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73348.355636 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 108750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74193.262411 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76789.965248 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 74466.090999 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 121.572360 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 184.618534 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 151.565619 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11499.500000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 11499.500000 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68776.272262 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68811.511264 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 68792.807948 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 112039.473684 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71927.919463 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 72426.426268 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76211.932279 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 75573.902149 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 73712.291762 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 141.273420 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 175.211514 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 159.903813 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69780.036495 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67525.689434 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 68798.894983 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 73923.204787 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 69140.165000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 108750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 74193.262411 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 69358.912345 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 69633.325234 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 112039.473684 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 71927.919463 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 69985.372429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76211.932279 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 68090.417399 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 69525.831129 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95646.551724 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 65125 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 73923.204787 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 69140.165000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 108750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 74193.262411 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 69358.912345 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 69633.325234 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 71927.919463 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 69985.372429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 104568.181818 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76211.932279 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 68090.417399 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 69525.831129 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,166 +647,166 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59142 # number of writebacks -system.l2c.writebacks::total 59142 # number of writebacks +system.l2c.writebacks::writebacks 59117 # number of writebacks +system.l2c.writebacks::total 59117 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 41 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 27 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 41 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 27 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 41 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 19 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 27 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 78 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6762 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6072 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5632 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4580 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23086 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1534 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1392 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2926 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7444 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6288 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4926 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4347 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23047 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1313 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1598 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2911 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 70693 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 62500 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133193 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 19 # number of demand (read+write) MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 75216 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 57962 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133178 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6762 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 76765 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5632 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 67080 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156279 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 19 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7444 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 81504 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4926 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 62309 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156225 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6762 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 76765 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5632 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 67080 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156279 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1889250 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 7444 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 81504 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4926 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 62309 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156225 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 105750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 414261000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 369284748 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1823250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 346567500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 294016000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1427947498 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15343534 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13921392 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29264926 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 20002 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 440932000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 376527749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 313110000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 273532998 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1407620997 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13131313 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15986098 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29117411 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20002 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3965209485 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3507280046 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7472489531 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1889250 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4295181775 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3176975989 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7472157764 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 105750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 414261000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4334494233 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1823250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 346567500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3801296046 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8900437029 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1889250 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 440932000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4671709524 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 313110000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3450508987 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8879778761 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2403250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 105750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 414261000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4334494233 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1823250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 346567500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3801296046 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8900437029 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6768250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 82756804500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 84168652000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166932224750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 13405485754 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 10155458000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 23560943754 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 440932000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4671709524 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1009250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 313110000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3450508987 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8879778761 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6023999 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84465244500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82459599500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166930867999 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8917288738 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8449538500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17366827238 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 116250 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 60000 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 60000 # number of StoreCondReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6768250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 96162290254 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 94324110000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 190493168504 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.032089 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021902 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015818 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.983964 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.985836 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.984854 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.548497 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.533185 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541204 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.241317 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.205558 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091627 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000574 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000287 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013414 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.241317 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011733 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.205558 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091627 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6023999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 93382533238 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90909138000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184297695237 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033619 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020586 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015800 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.986476 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986420 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986445 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.570099 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.507513 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541059 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.255522 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.191498 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091636 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000933 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000294 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014966 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.255522 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000341 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010138 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.191498 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091636 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60817.646245 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64195.633188 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61853.395911 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.303781 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.683527 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 59880.367207 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62924.545204 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61076.105220 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.816020 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.545861 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56090.553308 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56116.480736 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56102.719595 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57104.629002 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 54811.358977 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56106.547358 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82870.689655 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59233.207953 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57318.776060 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63562.728380 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55377.377056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 56839.678419 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -852,49 +829,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58503668 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2677420 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2677422 # Transaction distribution +system.toL2Bus.throughput 58475740 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2676749 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2676751 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608377 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2971 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2984 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608201 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2951 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246143 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246143 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969614 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798105 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37248 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149421 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7954388 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62990656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85594465 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54388 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253832 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 148893341 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148893341 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 204156 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4964785971 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967991 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797697 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37845 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149237 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7952770 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62938176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85577189 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55304 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148824185 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148824185 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 205696 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4963674463 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4437766959 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4434137240 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4499076262 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4494378467 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23705637 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24064152 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86451768 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86310594 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48459921 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322133 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322133 # Transaction distribution +system.iobus.throughput 48458766 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322134 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322134 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution system.iobus.trans_dist::WriteResp 8160 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -916,36 +893,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382956 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660586 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660588 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -967,38 +920,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390325 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390329 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500853 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500853 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500857 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500857 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1044,684 +973,684 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374794000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374796000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41501177007 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41501700007 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu0.branchPred.lookups 7460849 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5960235 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 378283 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4914778 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4045811 # Number of BTB hits +system.cpu0.branchPred.lookups 7055231 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5603867 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 360036 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4627391 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3766189 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 82.319303 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 696591 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38344 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.389038 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 696378 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 37374 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25704058 # DTB read hits -system.cpu0.dtb.read_misses 39030 # DTB read misses -system.cpu0.dtb.write_hits 5997479 # DTB write hits -system.cpu0.dtb.write_misses 9591 # DTB write misses -system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 25604020 # DTB read hits +system.cpu0.dtb.read_misses 37101 # DTB read misses +system.cpu0.dtb.write_hits 6019786 # DTB write hits +system.cpu0.dtb.write_misses 10089 # DTB write misses +system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5605 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5563 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1360 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25743088 # DTB read accesses -system.cpu0.dtb.write_accesses 6007070 # DTB write accesses +system.cpu0.dtb.perms_faults 609 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25641121 # DTB read accesses +system.cpu0.dtb.write_accesses 6029875 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31701537 # DTB hits -system.cpu0.dtb.misses 48621 # DTB misses -system.cpu0.dtb.accesses 31750158 # DTB accesses -system.cpu0.itb.inst_hits 6247488 # ITB inst hits -system.cpu0.itb.inst_misses 7199 # ITB inst misses +system.cpu0.dtb.hits 31623806 # DTB hits +system.cpu0.dtb.misses 47190 # DTB misses +system.cpu0.dtb.accesses 31670996 # DTB accesses +system.cpu0.itb.inst_hits 5711817 # ITB inst hits +system.cpu0.itb.inst_misses 6786 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 658 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1719 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1280 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6254687 # ITB inst accesses -system.cpu0.itb.hits 6247488 # DTB hits -system.cpu0.itb.misses 7199 # DTB misses -system.cpu0.itb.accesses 6254687 # DTB accesses -system.cpu0.numCycles 237974378 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5718603 # ITB inst accesses +system.cpu0.itb.hits 5711817 # DTB hits +system.cpu0.itb.misses 6786 # DTB misses +system.cpu0.itb.accesses 5718603 # DTB accesses +system.cpu0.numCycles 240384739 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15699723 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 49234228 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7460849 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4742402 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10819268 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2791638 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 83518 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 47679796 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1910 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 50382 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1297285 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 371 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6245426 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 421717 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2971 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77555768 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.784584 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.151481 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15036708 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 44324460 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7055231 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4462567 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 9979880 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2348952 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 79920 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 48371030 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1557 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 40136 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1395788 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 332 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5710035 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 358939 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3057 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 76524952 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.728839 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.080650 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 66744115 86.06% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 668305 0.86% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 854486 1.10% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1301033 1.68% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1140084 1.47% 91.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 550475 0.71% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1373308 1.77% 93.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 375655 0.48% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4548307 5.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 66552751 86.97% 86.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 648002 0.85% 87.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 843291 1.10% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1146450 1.50% 90.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1051496 1.37% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 533927 0.70% 92.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1248962 1.63% 94.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 369566 0.48% 94.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4130507 5.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77555768 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031351 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.206889 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16771569 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 48649935 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9795097 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 503008 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1834030 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1000504 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90828 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 57451762 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 304997 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1834030 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17711945 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 19691518 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 25851696 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9283653 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3180864 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54475085 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7298 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 545691 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2120831 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 197 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 56755313 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 249403500 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 249355386 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48114 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39528436 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 17226877 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 410327 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 362870 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6606046 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10343576 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6897280 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1045135 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1291149 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49940914 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 982735 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62750040 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92397 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11407526 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 29277622 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 263780 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77555768 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.809096 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.520917 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 76524952 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.029350 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.184390 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15988793 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49427885 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9067900 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 506950 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1531254 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 959604 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 89006 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53104636 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 296594 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1531254 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16866391 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20063365 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 26274348 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8616750 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3170765 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50610961 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7411 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 529520 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2115247 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 208 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 52034450 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 231667374 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 231623806 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 43568 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 38251156 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13783293 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411980 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 362796 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6588533 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9723453 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6830710 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1010499 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1245426 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 47056287 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 968125 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 61041577 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 84130 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9522170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23883479 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 244384 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 76524952 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.797669 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.517362 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55086998 71.03% 71.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6938242 8.95% 79.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3598420 4.64% 84.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3124608 4.03% 88.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6233139 8.04% 96.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1485765 1.92% 98.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 804564 1.04% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 219887 0.28% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 64145 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54759555 71.56% 71.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6733047 8.80% 80.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3420180 4.47% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2920085 3.82% 88.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6164290 8.06% 96.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1467950 1.92% 98.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 772657 1.01% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 222441 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 64747 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77555768 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 76524952 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 31748 0.72% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4146155 94.50% 95.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 209698 4.78% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27542 0.62% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4220431 94.60% 95.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 213140 4.78% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 168420 0.27% 0.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29819854 47.52% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48156 0.08% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 937 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26415371 42.10% 89.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6297270 10.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 171568 0.28% 0.28% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 28242983 46.27% 46.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47431 0.08% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1218 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.63% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26256845 43.01% 89.64% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6321515 10.36% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62750040 # Type of FU issued -system.cpu0.iq.rate 0.263684 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4387604 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.069922 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 207571986 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 62340159 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43794455 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12289 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6579 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5482 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66962707 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6517 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 317894 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 61041577 # Type of FU issued +system.cpu0.iq.rate 0.253933 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4461113 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.073083 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 203189112 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57554843 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 42164489 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11244 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5997 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4944 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 65325122 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6000 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306679 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2428904 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3600 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16156 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 921017 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2052481 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3874 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 14810 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 826086 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 16878789 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 486624 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17207144 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348104 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1834030 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15021196 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 239984 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 51041656 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 102587 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10343576 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6897280 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 695313 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 54984 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10683 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16156 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 184294 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 146657 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 330951 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61443864 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26034265 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1306176 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1531254 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15306015 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 241273 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 48127004 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 101529 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9723453 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6830710 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 683062 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 53931 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 11240 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 14810 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 174193 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 137584 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 311777 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 60001377 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 25939220 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1040200 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118007 # number of nop insts executed -system.cpu0.iew.exec_refs 32275135 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5809455 # Number of branches executed -system.cpu0.iew.exec_stores 6240870 # Number of stores executed -system.cpu0.iew.exec_rate 0.258195 # Inst execution rate -system.cpu0.iew.wb_sent 60834498 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43799937 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23902926 # num instructions producing a value -system.cpu0.iew.wb_consumers 43468500 # num instructions consuming a value +system.cpu0.iew.exec_nop 102592 # number of nop insts executed +system.cpu0.iew.exec_refs 32204815 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5606114 # Number of branches executed +system.cpu0.iew.exec_stores 6265595 # Number of stores executed +system.cpu0.iew.exec_rate 0.249606 # Inst execution rate +system.cpu0.iew.wb_sent 59520960 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 42169433 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22855569 # num instructions producing a value +system.cpu0.iew.wb_consumers 42162980 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184053 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.549891 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.175425 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.542077 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11258567 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 718955 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 288860 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75721738 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.518964 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.500316 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9402485 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 723741 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 272429 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 74993698 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.510414 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.487877 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61785849 81.60% 81.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6716034 8.87% 90.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2031673 2.68% 93.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1100696 1.45% 94.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 996789 1.32% 95.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 567209 0.75% 96.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 697121 0.92% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 401495 0.53% 98.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1424872 1.88% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61390308 81.86% 81.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6607868 8.81% 90.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1921399 2.56% 93.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1064491 1.42% 94.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 990154 1.32% 95.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 565334 0.75% 96.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 721378 0.96% 97.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 343964 0.46% 98.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1388802 1.85% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75721738 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30484303 # Number of instructions committed -system.cpu0.commit.committedOps 39296836 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 74993698 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29384265 # Number of instructions committed +system.cpu0.commit.committedOps 38277857 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13890935 # Number of memory references committed -system.cpu0.commit.loads 7914672 # Number of loads committed -system.cpu0.commit.membars 201566 # Number of memory barriers committed -system.cpu0.commit.branches 4969836 # Number of branches committed -system.cpu0.commit.fp_insts 5449 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34871152 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489123 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1424872 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13675596 # Number of memory references committed +system.cpu0.commit.loads 7670972 # Number of loads committed +system.cpu0.commit.membars 201047 # Number of memory barriers committed +system.cpu0.commit.branches 4859392 # Number of branches committed +system.cpu0.commit.fp_insts 4891 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 33962414 # Number of committed integer instructions. +system.cpu0.commit.function_calls 491145 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1388802 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123917155 # The number of ROB reads -system.cpu0.rob.rob_writes 103001078 # The number of ROB writes -system.cpu0.timesIdled 891630 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 160418610 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2282332434 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 30404601 # Number of Instructions Simulated -system.cpu0.committedOps 39217134 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 30404601 # Number of Instructions Simulated -system.cpu0.cpi 7.826920 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.826920 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.127764 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.127764 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 278728087 # number of integer regfile reads -system.cpu0.int_regfile_writes 45052561 # number of integer regfile writes -system.cpu0.fp_regfile_reads 23012 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19792 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15437173 # number of misc regfile reads -system.cpu0.misc_regfile_writes 403324 # number of misc regfile writes -system.cpu0.icache.tags.replacements 984712 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.392135 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10916124 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 985224 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 11.079840 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6946570250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 153.798869 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 356.593266 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.300388 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.696471 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996860 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5698838 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5217286 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10916124 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5698838 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5217286 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10916124 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5698838 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5217286 # number of overall hits -system.cpu0.icache.overall_hits::total 10916124 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 546469 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 520462 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1066931 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 546469 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 520462 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1066931 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 546469 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 520462 # number of overall misses -system.cpu0.icache.overall_misses::total 1066931 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7505000228 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7078718225 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14583718453 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7505000228 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7078718225 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14583718453 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7505000228 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7078718225 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14583718453 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6245307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5737748 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11983055 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6245307 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5737748 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11983055 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6245307 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5737748 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11983055 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.087501 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.090708 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.089037 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.087501 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.090708 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.089037 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.087501 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090708 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.089037 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13733.624831 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.835844 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13668.848738 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13733.624831 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13600.835844 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13668.848738 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13733.624831 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13600.835844 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13668.848738 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8644 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 575 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 416 # number of cycles access was blocked +system.cpu0.rob.rob_reads 120378043 # The number of ROB reads +system.cpu0.rob.rob_writes 96934970 # The number of ROB writes +system.cpu0.timesIdled 903993 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 163859787 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2252055071 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 29315772 # Number of Instructions Simulated +system.cpu0.committedOps 38209364 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 29315772 # Number of Instructions Simulated +system.cpu0.cpi 8.199843 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.199843 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.121954 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.121954 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 271685631 # number of integer regfile reads +system.cpu0.int_regfile_writes 42795201 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22306 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19768 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15093810 # number of misc regfile reads +system.cpu0.misc_regfile_writes 401151 # number of misc regfile writes +system.cpu0.icache.tags.replacements 983925 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.538497 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10508756 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 984437 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.674889 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6941856250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 321.486243 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 190.052254 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.627903 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.371196 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999099 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5171009 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5337747 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10508756 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5171009 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5337747 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10508756 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5171009 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5337747 # number of overall hits +system.cpu0.icache.overall_hits::total 10508756 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 538904 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 526390 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065294 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 538904 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 526390 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065294 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 538904 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 526390 # number of overall misses +system.cpu0.icache.overall_misses::total 1065294 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7446919215 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7105468986 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14552388201 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7446919215 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 7105468986 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14552388201 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7446919215 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 7105468986 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14552388201 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5709913 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5864137 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11574050 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5709913 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5864137 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11574050 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5709913 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5864137 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11574050 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094380 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089764 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.092042 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094380 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089764 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.092042 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094380 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089764 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.092042 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13818.637856 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13498.487787 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13660.443221 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13818.637856 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13498.487787 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13660.443221 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13818.637856 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13498.487787 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13660.443221 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6869 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1025 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 398 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.778846 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 575 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.258794 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 1025 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41748 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39914 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 81662 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 41748 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39914 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 81662 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 41748 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39914 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 81662 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 504721 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 480548 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 985269 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 504721 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 480548 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 985269 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 504721 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 480548 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 985269 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6095694370 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5754767140 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11850461510 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6095694370 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5754767140 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11850461510 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6095694370 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5754767140 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11850461510 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9176750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9176750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9176750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 9176750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.080816 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.083752 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.082222 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.080816 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.083752 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.082222 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.080816 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.083752 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.082222 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.354360 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11975.426263 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12027.640685 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.354360 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11975.426263 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12027.640685 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.354360 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11975.426263 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12027.640685 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40970 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39858 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 80828 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 40970 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39858 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 80828 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 40970 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39858 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 80828 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 497934 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 486532 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984466 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 497934 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 486532 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984466 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 497934 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 486532 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984466 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6047465345 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5786819388 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11834284733 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6047465345 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5786819388 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11834284733 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6047465345 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5786819388 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11834284733 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8439000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8439000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8439000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8439000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085058 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085058 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087205 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.082967 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085058 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12021.019246 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12021.019246 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12145.114302 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.015991 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12021.019246 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643928 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.992040 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21539454 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644440 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.423521 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 49066250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 194.023961 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 317.968079 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.378953 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.621031 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7084507 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6698400 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13782907 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3631868 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3629961 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261829 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114762 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129152 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243914 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 116493 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131183 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247676 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10716375 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10328361 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21044736 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10716375 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10328361 # number of overall hits -system.cpu0.dcache.overall_hits::total 21044736 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 339050 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 410986 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 750036 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1568875 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1393123 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2961998 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6956 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6622 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1907925 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1804109 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3712034 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1907925 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1804109 # number of overall misses -system.cpu0.dcache.overall_misses::total 3712034 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5404290531 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6065987702 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11470278233 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76728419243 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 66584790588 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 143313209831 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98583999 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 88165249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 186749248 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 116502 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 194502 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 82132709774 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 72650778290 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 154783488064 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 82132709774 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 72650778290 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 154783488064 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7423557 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7109386 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14532943 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5200743 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5023084 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223827 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 121718 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135774 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257492 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 116500 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 131189 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247689 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12624300 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12132470 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24756770 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12624300 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12132470 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24756770 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045672 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057809 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051609 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.301664 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.277344 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289715 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057148 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048772 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052732 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000060 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000046 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000052 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.151131 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.148701 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149940 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.151131 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.148701 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149940 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15939.509013 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14759.596925 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15292.970248 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48906.649187 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 47795.342255 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 48383.965766 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14172.512795 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13313.991090 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13753.811165 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16643.142857 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14961.692308 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43048.185738 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40269.616908 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41697.756018 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43048.185738 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40269.616908 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41697.756018 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36942 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 23867 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3499 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 298 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.557874 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 80.090604 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 643834 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993352 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21533253 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 644346 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.418773 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 42568250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.929916 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.063436 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497910 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502077 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6778619 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6998983 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13777602 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3655456 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3606248 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261704 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113306 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 129840 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243146 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 115957 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 131727 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247684 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10434075 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10605231 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21039306 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10434075 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10605231 # number of overall hits +system.cpu0.dcache.overall_hits::total 21039306 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 328027 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 420957 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 748984 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1610503 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1351638 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2962141 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7363 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6159 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13522 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 8 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1938530 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1772595 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3711125 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1938530 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1772595 # number of overall misses +system.cpu0.dcache.overall_misses::total 3711125 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5252707334 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6136741422 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11389448756 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 82511290457 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 60760612895 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 143271903352 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104363999 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 83076247 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 187440246 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 129002 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 155002 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 87763997791 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 66897354317 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 154661352108 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 87763997791 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 66897354317 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 154661352108 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7106646 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 7419940 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14526586 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5265959 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4957886 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10223845 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 120669 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 135999 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256668 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 115959 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 131735 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247694 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12372605 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12377826 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24750431 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12372605 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12377826 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24750431 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.046158 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.056733 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051560 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.305833 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.272624 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289729 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061018 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045287 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052683 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000061 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.156679 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.143207 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149942 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.156679 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.143207 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149942 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16013.033482 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14578.071922 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15206.531456 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51233.242321 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44953.318044 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 48367.685182 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14174.113676 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13488.593440 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13861.872948 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16125.250000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15500.200000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45273.479281 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37739.785070 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41675.058670 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45273.479281 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37739.785070 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41675.058670 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 36870 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 26211 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3510 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 295 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.504274 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 88.850847 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608377 # number of writebacks -system.cpu0.dcache.writebacks::total 608377 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 156045 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 207748 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 363793 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1438475 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1274543 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2713018 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 694 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 696 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1390 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1594520 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1482291 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3076811 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1594520 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1482291 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3076811 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183005 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 203238 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386243 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130400 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 118580 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248980 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6262 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5926 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 313405 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 321818 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635223 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 313405 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 321818 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635223 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2537438499 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2706851142 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5244289641 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5705098821 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5073968451 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10779067272 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78058501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68010500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146069001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 102498 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 168498 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8242537320 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7780819593 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16023356913 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8242537320 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7780819593 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16023356913 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90382122001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91936686500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182318808501 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 18619452182 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14311531070 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32930983252 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.writebacks::writebacks 608201 # number of writebacks +system.cpu0.dcache.writebacks::total 608201 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 147533 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 215292 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 362825 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1477292 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1235866 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2713158 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 767 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 600 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1367 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1624825 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1451158 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3075983 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1624825 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1451158 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3075983 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 180494 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205665 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386159 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 133211 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 115772 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6596 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5559 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12155 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 313705 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 321437 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635142 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 313705 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 321437 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635142 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2529137468 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2700943395 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5230080863 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6074560248 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4703819078 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10778379326 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82036251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64895003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146931254 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 112998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 134998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8603697716 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7404762473 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16008460189 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8603697716 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7404762473 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16008460189 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 92246094501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90072157750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182318252251 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13667158074 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13097409574 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26764567648 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 155750 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 109001574183 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106248217570 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215249791753 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024652 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028587 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026577 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025073 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105913252575 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103169567324 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209082819899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025398 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027718 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025297 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023351 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051447 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043646 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047334 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000060 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025659 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025659 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13865.405311 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13318.627137 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13577.694977 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43750.757830 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42789.411798 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43292.904137 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12465.426541 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11476.628417 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11984.657122 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14642.571429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12961.384615 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054662 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.040875 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047357 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000061 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025662 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025355 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025969 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025662 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14012.307711 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13132.732332 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13543.853343 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45601.040815 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40630.023477 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43289.619476 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12437.272741 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11673.862745 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12088.132785 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13499.800000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27426.077735 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23036.434738 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25204.537236 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1736,330 +1665,330 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7195832 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5758794 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 347995 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4705708 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3816103 # Number of BTB hits +system.cpu1.branchPred.lookups 7417918 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5931932 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 364646 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4881678 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3917644 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 81.095193 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 703176 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35899 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 80.251995 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 703527 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35801 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25676963 # DTB read hits -system.cpu1.dtb.read_misses 36626 # DTB read misses -system.cpu1.dtb.write_hits 5717501 # DTB write hits -system.cpu1.dtb.write_misses 9454 # DTB write misses +system.cpu1.dtb.read_hits 25617777 # DTB read hits +system.cpu1.dtb.read_misses 38543 # DTB read misses +system.cpu1.dtb.write_hits 5691491 # DTB write hits +system.cpu1.dtb.write_misses 8859 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1965 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5585 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2011 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25713589 # DTB read accesses -system.cpu1.dtb.write_accesses 5726955 # DTB write accesses +system.cpu1.dtb.perms_faults 659 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25656320 # DTB read accesses +system.cpu1.dtb.write_accesses 5700350 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31394464 # DTB hits -system.cpu1.dtb.misses 46080 # DTB misses -system.cpu1.dtb.accesses 31440544 # DTB accesses -system.cpu1.itb.inst_hits 5739661 # ITB inst hits -system.cpu1.itb.inst_misses 6710 # ITB inst misses +system.cpu1.dtb.hits 31309268 # DTB hits +system.cpu1.dtb.misses 47402 # DTB misses +system.cpu1.dtb.accesses 31356670 # DTB accesses +system.cpu1.itb.inst_hits 5866342 # ITB inst hits +system.cpu1.itb.inst_misses 7403 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2611 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 781 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1312 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1687 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5746371 # ITB inst accesses -system.cpu1.itb.hits 5739661 # DTB hits -system.cpu1.itb.misses 6710 # DTB misses -system.cpu1.itb.accesses 5746371 # DTB accesses -system.cpu1.numCycles 238752144 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5873745 # ITB inst accesses +system.cpu1.itb.hits 5866342 # DTB hits +system.cpu1.itb.misses 7403 # DTB misses +system.cpu1.itb.accesses 5873745 # DTB accesses +system.cpu1.numCycles 234836749 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14725732 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45766952 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7195832 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4519279 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10135681 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2420409 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 79807 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 48403648 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1933 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 42395 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1408034 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5737749 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 344300 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2901 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76459821 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.743283 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.100006 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14958684 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46343438 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7417918 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4621171 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10240931 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2382000 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 84846 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47705916 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1885 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 51796 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1300956 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5864138 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 361139 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3128 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 75991069 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.753206 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.110012 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66331645 86.75% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 641052 0.84% 87.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 862069 1.13% 88.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1143637 1.50% 90.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1042629 1.36% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 566145 0.74% 92.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1286339 1.68% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 374523 0.49% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4211782 5.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 65758157 86.53% 86.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 661623 0.87% 87.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 874095 1.15% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1155735 1.52% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1058337 1.39% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 579833 0.76% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1309635 1.72% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 379645 0.50% 94.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4214009 5.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76459821 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030139 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.191692 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15725454 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49459208 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9192415 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 503929 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1576672 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 971007 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86673 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53874532 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286668 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1576672 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16583861 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19404823 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27005764 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8762969 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3123666 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51462507 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13354 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 564319 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2029977 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 529 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53559967 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 234998901 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 234956394 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42507 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38873752 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14686214 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 422468 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 375757 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6418869 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9803560 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6552959 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 903342 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1157992 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47368560 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1003626 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 61323847 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 88809 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9695135 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24547753 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 239591 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76459821 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.802040 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.511450 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 75991069 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.031588 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.197343 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15934805 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 48666188 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9324612 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 504366 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1558997 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1010894 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 88249 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54549781 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 295589 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1558997 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16808618 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19027959 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 26571393 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8885070 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3136997 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 52018175 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13230 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 586421 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2033878 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 525 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 54353089 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 236755846 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 236708688 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 47158 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 40151278 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14201811 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 419760 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 374760 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6443032 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10070258 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6501681 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 951169 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1220754 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 48367033 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1016747 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62006899 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 95474 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9693963 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24244292 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 257471 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 75991069 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.815976 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521890 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54334795 71.06% 71.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6963817 9.11% 80.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3541064 4.63% 84.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3011943 3.94% 88.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6202034 8.11% 96.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1339759 1.75% 98.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 792493 1.04% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 211144 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 62772 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53638566 70.59% 70.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7003056 9.22% 79.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3617950 4.76% 84.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3068918 4.04% 88.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6184871 8.14% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1401826 1.84% 98.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 782382 1.03% 99.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 229717 0.30% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 63783 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76459821 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 75991069 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28001 0.63% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4231917 94.82% 95.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 203383 4.56% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 31911 0.73% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 5 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4158175 94.76% 95.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 198234 4.52% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 195246 0.32% 0.32% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28699765 46.80% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45365 0.07% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1174 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26341683 42.96% 90.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6040595 9.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 192098 0.31% 0.31% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 29460264 47.51% 47.82% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45939 0.07% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 896 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.90% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26296905 42.41% 90.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6010767 9.69% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 61323847 # Type of FU issued -system.cpu1.iq.rate 0.256852 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4463304 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072783 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 203694277 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58075857 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42386346 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11257 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5873 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65585843 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6062 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 307143 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62006899 # Type of FU issued +system.cpu1.iq.rate 0.264043 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4388325 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.070772 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 204523942 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59086561 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 43409940 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11938 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6483 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5383 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 66196788 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6338 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 319760 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2060794 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3248 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14926 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 795522 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2083716 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3064 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15874 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 772589 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17225652 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 391932 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16902604 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 332952 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1576672 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14666749 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 228879 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48476685 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98660 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9803560 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6552959 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 716609 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50437 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 9701 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14926 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 170356 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133051 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 303407 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 60276255 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 26034557 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1047592 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1558997 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14375191 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 227377 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 49504406 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 10070258 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6501681 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 727587 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 51733 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 9370 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15874 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 179251 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 141654 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 320905 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 60955471 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25970384 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1051428 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104499 # number of nop insts executed -system.cpu1.iew.exec_refs 32021114 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5717498 # Number of branches executed -system.cpu1.iew.exec_stores 5986557 # Number of stores executed -system.cpu1.iew.exec_rate 0.252464 # Inst execution rate -system.cpu1.iew.wb_sent 59765334 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42391160 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23307297 # num instructions producing a value -system.cpu1.iew.wb_consumers 43055480 # num instructions consuming a value +system.cpu1.iew.exec_nop 120626 # number of nop insts executed +system.cpu1.iew.exec_refs 31928214 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5888736 # Number of branches executed +system.cpu1.iew.exec_stores 5957830 # Number of stores executed +system.cpu1.iew.exec_rate 0.259565 # Inst execution rate +system.cpu1.iew.wb_sent 60476945 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 43415323 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24094324 # num instructions producing a value +system.cpu1.iew.wb_consumers 44023151 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.177553 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.541332 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.184874 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.547310 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9596314 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 764035 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 262671 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74883149 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.513666 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.490214 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9567264 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 759276 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 277731 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74432072 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.530472 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.515537 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61098286 81.59% 81.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6805438 9.09% 90.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1903916 2.54% 93.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1064936 1.42% 94.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1018174 1.36% 96.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 531111 0.71% 96.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 691593 0.92% 97.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 378534 0.51% 98.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1391161 1.86% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60336914 81.06% 81.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6930423 9.31% 90.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1972494 2.65% 93.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1094851 1.47% 94.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1021489 1.37% 95.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 524731 0.70% 96.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 707921 0.95% 97.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 378966 0.51% 98.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1464283 1.97% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74883149 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29982419 # Number of instructions committed -system.cpu1.commit.committedOps 38464913 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74432072 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31082580 # Number of instructions committed +system.cpu1.commit.committedOps 39484127 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13500203 # Number of memory references committed -system.cpu1.commit.loads 7742766 # Number of loads committed -system.cpu1.commit.membars 202217 # Number of memory barriers committed -system.cpu1.commit.branches 4992962 # Number of branches committed -system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33994528 # Number of committed integer instructions. -system.cpu1.commit.function_calls 502375 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1391161 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13715634 # Number of memory references committed +system.cpu1.commit.loads 7986542 # Number of loads committed +system.cpu1.commit.membars 202747 # Number of memory barriers committed +system.cpu1.commit.branches 5103464 # Number of branches committed +system.cpu1.commit.fp_insts 5321 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 34903456 # Number of committed integer instructions. +system.cpu1.commit.function_calls 500366 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1464283 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120638730 # The number of ROB reads -system.cpu1.rob.rob_writes 97745041 # The number of ROB writes -system.cpu1.timesIdled 886317 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 162292323 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2286407630 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29911740 # Number of Instructions Simulated -system.cpu1.committedOps 38394234 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29911740 # Number of Instructions Simulated -system.cpu1.cpi 7.981888 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.981888 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.125284 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.125284 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 272364887 # number of integer regfile reads -system.cpu1.int_regfile_writes 43577017 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22187 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19914 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14848508 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429527 # number of misc regfile writes -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.rob.rob_reads 121076761 # The number of ROB reads +system.cpu1.rob.rob_writes 99705340 # The number of ROB writes +system.cpu1.timesIdled 873554 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 158845680 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2319747272 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31000692 # Number of Instructions Simulated +system.cpu1.committedOps 39402239 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 31000692 # Number of Instructions Simulated +system.cpu1.cpi 7.575210 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.575210 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.132010 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.132010 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 276194442 # number of integer regfile reads +system.cpu1.int_regfile_writes 44861664 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22699 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19852 # number of floating regfile writes +system.cpu1.misc_regfile_reads 15196533 # number of misc regfile reads +system.cpu1.misc_regfile_writes 431717 # number of misc regfile writes +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2068,10 +1997,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1453044953007 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1453044953007 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1441896554007 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1441896554007 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1441896554007 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 96aff7e7e..820046126 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,142 +1,143 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.630645 # Number of seconds simulated -sim_ticks 2630645085500 # Number of ticks simulated -final_tick 2630645085500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.630640 # Number of seconds simulated +sim_ticks 2630640106500 # Number of ticks simulated +final_tick 2630640106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 281405 # Simulator instruction rate (inst/s) -host_op_rate 358084 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12294669184 # Simulator tick rate (ticks/s) -host_mem_usage 398476 # Number of bytes of host memory used -host_seconds 213.97 # Real time elapsed on the host -sim_insts 60211229 # Number of instructions simulated -sim_ops 76617937 # Number of ops (including micro ops) simulated +host_inst_rate 544255 # Simulator instruction rate (inst/s) +host_op_rate 692557 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23778611565 # Simulator tick rate (ticks/s) +host_mem_usage 394548 # Number of bytes of host memory used +host_seconds 110.63 # Real time elapsed on the host +sim_insts 60211209 # Number of instructions simulated +sim_ops 76617916 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 305952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4748752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 310496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4767440 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 398080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4312560 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 305952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 398080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704032 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690176 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1535008 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1481144 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706328 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 393856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4293936 # Number of bytes read from this memory +system.physmem.bytes_read::total 134022176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 310496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 393856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1534960 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1481192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706776 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10983 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74233 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11054 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 74525 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 67410 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690881 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57659 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 383752 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 370286 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811697 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47234139 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6154 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 67119 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690887 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 383740 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 370298 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811704 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47234229 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 116303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1805166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 118031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1812274 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 151324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1639355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50946360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 116303 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 151324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1402765 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 583510 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 563035 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2549309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1402765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47234139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 149719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1632278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50946603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 118031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 149719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1402938 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 583493 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 563054 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2549484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1402938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47234229 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 116303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2388676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 118031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2395767 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 151324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2202389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53495669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690881 # Total number of read requests seen -system.physmem.writeReqs 811697 # Total number of write requests seen -system.physmem.cpureqs 214350 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1004216384 # Total number of bytes read from memory -system.physmem.bytesWritten 51948608 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 134021792 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6706328 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q +system.physmem.bw_total::cpu1.inst 149719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2195332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53496087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690887 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 811704 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15690887 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 811704 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 1004216768 # Total number of bytes read from memory +system.physmem.bytesWritten 51949056 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 134022176 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6706776 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 29 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 4522 # Reqs where no action is needed system.physmem.perBankRdReqs::0 980391 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 980205 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 980221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 980224 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 980428 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 986950 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 980709 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 980611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 980417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 980420 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 980615 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 980431 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 979815 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 979554 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 979555 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 980154 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 980076 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 980169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 980165 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 980109 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49026 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50948 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51094 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51463 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51294 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51194 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51021 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50517 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50336 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 50808 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50830 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 50810 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 6740 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6615 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6627 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6678 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6754 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7054 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7042 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6898 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7014 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6836 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6333 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6140 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6411 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6640 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6624 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2630640666000 # Total gap between requests +system.physmem.totGap 2630635687000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6680 # Categorize read packet sizes system.physmem.readPktSize::3 15532032 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152169 # Categorize read packet sizes +system.physmem.readPktSize::6 152175 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754038 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57659 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1131442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 973737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1003950 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3836084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2879069 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2878494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2847936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 16166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 44268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 29895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1039 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57666 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1132703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 975077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1005041 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3836885 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2878586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2878042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2847020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29667 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 44009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 29620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -152,30 +153,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -184,183 +185,180 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37996 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 27796.675861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2568.021256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 33333.179984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5396 14.20% 14.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3321 8.74% 22.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2191 5.77% 28.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1656 4.36% 33.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1158 3.05% 36.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1048 2.76% 38.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 789 2.08% 40.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 726 1.91% 42.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 577 1.52% 44.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 474 1.25% 45.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 440 1.16% 46.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 388 1.02% 47.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 251 0.66% 48.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 273 0.72% 49.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 221 0.58% 49.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 258 0.68% 50.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 159 0.42% 50.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 126 0.33% 51.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 108 0.28% 51.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 95 0.25% 51.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 80 0.21% 51.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 156 0.41% 52.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 779 2.05% 54.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 205 0.54% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 146 0.38% 55.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 108 0.28% 55.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 84 0.22% 55.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 80 0.21% 56.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 53 0.14% 56.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 48 0.13% 56.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 45 0.12% 56.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 58 0.15% 56.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 47 0.12% 56.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 19 0.05% 56.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 26 0.07% 56.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 22 0.06% 56.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 18 0.05% 56.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 19 0.05% 56.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 19 0.05% 57.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 11 0.03% 57.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 13 0.03% 57.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 9 0.02% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 7 0.02% 57.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 10 0.03% 57.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 16 0.04% 57.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 3 0.01% 57.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 9 0.02% 57.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 9 0.02% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 4 0.01% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 5 0.01% 57.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 5 0.01% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 15 0.04% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 11 0.03% 57.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 13 0.03% 57.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 8 0.02% 57.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 34 0.09% 57.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 3 0.01% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 1 0.00% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 1 0.00% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 7 0.02% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 6 0.02% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 5 0.01% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 3 0.01% 57.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 6 0.02% 57.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 1 0.00% 57.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 4 0.01% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 2 0.01% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 3 0.01% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 7 0.02% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 6 0.02% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 3 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 2 0.01% 57.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 4 0.01% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 2 0.01% 57.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 1 0.00% 57.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 5 0.01% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 2 0.01% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 1 0.00% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 18 0.05% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 4 0.01% 57.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 4 0.01% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 1 0.00% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 3 0.01% 57.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 3 0.01% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 1 0.00% 57.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 2 0.01% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 17 0.04% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 1 0.00% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 1 0.00% 58.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 3 0.01% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 5 0.01% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 7 0.02% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 3 0.01% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 1 0.00% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 6 0.02% 58.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 2 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 9 0.02% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 4 0.01% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 308 0.81% 58.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 58.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 18 0.05% 59.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11071 2 0.01% 59.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 1 0.00% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14655 1 0.00% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17727 1 0.00% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-19007 1 0.00% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21311 2 0.01% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22079 1 0.00% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 1 0.00% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25151 1 0.00% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26175 1 0.00% 59.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 2 0.01% 59.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 2 0.01% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 1 0.00% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31039 1 0.00% 59.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 2 0.01% 59.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 2 0.01% 59.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 3 0.01% 59.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 15 0.04% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41152-41215 1 0.00% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46143 1 0.00% 59.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47423 1 0.00% 59.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52287 1 0.00% 59.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55872-55935 1 0.00% 59.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57984-58047 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58240-58303 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 15141 39.85% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::72832-72895 1 0.00% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::80704-80767 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::86848-86911 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::101184-101247 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129728-129791 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131135 356 0.94% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136639 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37970 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 26627.977877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2487.931344 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31806.056461 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5445 14.34% 14.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3318 8.74% 23.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2184 5.75% 28.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1677 4.42% 33.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1130 2.98% 36.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1067 2.81% 39.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 805 2.12% 41.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 712 1.88% 43.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 588 1.55% 44.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 469 1.24% 45.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 450 1.19% 47.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 409 1.08% 48.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 266 0.70% 48.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 255 0.67% 49.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 222 0.58% 50.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 208 0.55% 50.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 140 0.37% 50.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 130 0.34% 51.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 95 0.25% 51.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 109 0.29% 51.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 83 0.22% 52.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 158 0.42% 52.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 757 1.99% 54.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 208 0.55% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 141 0.37% 55.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 116 0.31% 55.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 79 0.21% 55.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 86 0.23% 56.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 52 0.14% 56.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 50 0.13% 56.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 43 0.11% 56.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 55 0.14% 56.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 50 0.13% 56.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 19 0.05% 56.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 19 0.05% 56.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 17 0.04% 56.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 20 0.05% 57.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 17 0.04% 57.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 12 0.03% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 10 0.03% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 7 0.02% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 4 0.01% 57.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 9 0.02% 57.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 14 0.04% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 6 0.02% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 9 0.02% 57.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 11 0.03% 57.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 5 0.01% 57.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 7 0.02% 57.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 8 0.02% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 10 0.03% 57.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 14 0.04% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 5 0.01% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 7 0.02% 57.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 5 0.01% 57.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 35 0.09% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 3 0.01% 57.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 2 0.01% 57.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 2 0.01% 57.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 8 0.02% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 5 0.01% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 2 0.01% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 2 0.01% 57.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 7 0.02% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 3 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 2 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 2 0.01% 57.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 8 0.02% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 3 0.01% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 1 0.00% 57.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 5 0.01% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 1 0.00% 57.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 1 0.00% 57.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 4 0.01% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 3 0.01% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 2 0.01% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 8 0.02% 57.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 4 0.01% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 3 0.01% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 2 0.01% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 2 0.01% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 2 0.01% 57.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 2 0.01% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 2 0.01% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 17 0.04% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 1 0.00% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 3 0.01% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 5 0.01% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 6 0.02% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 7 0.02% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 5 0.01% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 5 0.01% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 9 0.02% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 309 0.81% 59.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 22 0.06% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8575 151 0.40% 59.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8639 180 0.47% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8640-8703 3 0.01% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8831 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8895 2 0.01% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11327 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 2 0.01% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 2 0.01% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21055 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 1 0.00% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 7 0.02% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 12 0.03% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55872-55935 1 0.00% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 15142 39.88% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::67392-67455 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37996 # Bytes accessed per row activation -system.physmem.totQLat 300645538000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 395312713000 # Sum of mem lat for all requests -system.physmem.totBusLat 78454275000 # Total cycles spent in databus access -system.physmem.totBankLat 16212900000 # Total cycles spent in bank access -system.physmem.avgQLat 19160.56 # Average queueing delay per request -system.physmem.avgBankLat 1033.27 # Average bank access latency per request +system.physmem.bytesPerActivate::total 37970 # Bytes accessed per row activation +system.physmem.totQLat 300039544000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 394721941500 # Sum of mem lat for all requests +system.physmem.totBusLat 78454290000 # Total cycles spent in databus access +system.physmem.totBankLat 16228107500 # Total cycles spent in bank access +system.physmem.avgQLat 19121.93 # Average queueing delay per request +system.physmem.avgBankLat 1034.24 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25193.83 # Average memory access latency +system.physmem.avgMemAccLat 25156.17 # Average memory access latency system.physmem.avgRdBW 381.74 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.75 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.95 # Average consumed read bandwidth in MB/s @@ -368,12 +366,12 @@ system.physmem.avgConsumedWrBW 2.55 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 1.26 # Average write queue length over time -system.physmem.readRowHits 15666172 # Number of row buffer hits during reads -system.physmem.writeRowHits 798379 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.25 # Average write queue length over time +system.physmem.readRowHits 15666199 # Number of row buffer hits during reads +system.physmem.writeRowHits 93719 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.36 # Row buffer hit rate for writes -system.physmem.avgGap 159407.86 # Average gap between requests +system.physmem.writeRowHitRate 11.55 # Row buffer hit rate for writes +system.physmem.avgGap 159407.43 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -386,259 +384,249 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54407285 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743607 # Transaction distribution -system.membus.trans_dist::ReadResp 16743607 # Transaction distribution +system.membus.throughput 54407704 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743613 # Transaction distribution +system.membus.trans_dist::ReadResp 16743613 # Transaction distribution system.membus.trans_dist::WriteReq 763392 # Transaction distribution system.membus.trans_dist::WriteResp 763392 # Transaction distribution -system.membus.trans_dist::Writeback 57659 # Transaction distribution +system.membus.trans_dist::Writeback 57666 # Transaction distribution system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution system.membus.trans_dist::ReadExReq 131350 # Transaction distribution system.membus.trans_dist::ReadExResp 131350 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892477 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279337 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892496 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279356 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32956541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343401 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35343420 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471864 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18870001 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18870833 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 140728120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143126257 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143126257 # Total data (bytes) +system.membus.tot_pkt_size::total 143127089 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143127089 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1209137000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1209125000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 18109692000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3744500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4946454076 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3743000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 18109707000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4946568726 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35060518750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35058992750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 62055 # number of replacements -system.l2c.tags.tagsinuse 51615.482729 # Cycle average of tags in use -system.l2c.tags.total_refs 1699189 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127440 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.333247 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2575816655500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38219.751550 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000690 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2839.791296 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3005.850612 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4181.982232 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3368.106163 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583187 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.043332 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045866 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.063812 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.051393 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787590 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 10006 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3588 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 435821 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 185768 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9923 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3635 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 408641 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 184604 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241986 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596408 # number of Writeback hits -system.l2c.Writeback_hits::total 596408 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 9 # number of UpgradeReq hits +system.l2c.tags.replacements 62061 # number of replacements +system.l2c.tags.tagsinuse 51615.718916 # Cycle average of tags in use +system.l2c.tags.total_refs 1699022 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127446 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.331309 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2575798778500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38215.031353 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2892.274749 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3021.606158 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4129.656737 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3357.149045 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583115 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.044133 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046106 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.063014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.051226 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787593 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9999 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3590 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 436599 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 185177 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9919 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3623 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 407829 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 185133 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241869 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596358 # number of Writeback hits +system.l2c.Writeback_hits::total 596358 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 59901 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 54618 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114519 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 10006 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3588 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 435821 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 245669 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9923 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3635 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 408641 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 239222 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356505 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 10006 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3588 # number of overall hits -system.l2c.overall_hits::cpu0.inst 435821 # number of overall hits -system.l2c.overall_hits::cpu0.data 245669 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9923 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3635 # number of overall hits -system.l2c.overall_hits::cpu1.inst 408641 # number of overall hits -system.l2c.overall_hits::cpu1.data 239222 # number of overall hits -system.l2c.overall_hits::total 1356505 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 59730 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54783 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114513 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9999 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3590 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 436599 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 244907 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9919 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3623 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 407829 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 239916 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356382 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9999 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3590 # number of overall hits +system.l2c.overall_hits::cpu0.inst 436599 # number of overall hits +system.l2c.overall_hits::cpu0.data 244907 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 9919 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3623 # number of overall hits +system.l2c.overall_hits::cpu1.inst 407829 # number of overall hits +system.l2c.overall_hits::cpu1.data 239916 # number of overall hits +system.l2c.overall_hits::total 1356382 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4367 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5353 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4438 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5378 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6220 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4876 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20819 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1448 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1433 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu1.inst 6154 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4852 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20825 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1446 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1435 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2881 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 69705 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 63286 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 69963 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 63028 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 132991 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 4367 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 75058 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 4438 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 75341 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6220 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 68162 # number of demand (read+write) misses -system.l2c.demand_misses::total 153810 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6154 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 67880 # number of demand (read+write) misses +system.l2c.demand_misses::total 153816 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 4367 # number of overall misses -system.l2c.overall_misses::cpu0.data 75058 # number of overall misses +system.l2c.overall_misses::cpu0.inst 4438 # number of overall misses +system.l2c.overall_misses::cpu0.data 75341 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6220 # number of overall misses -system.l2c.overall_misses::cpu1.data 68162 # number of overall misses -system.l2c.overall_misses::total 153810 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6154 # number of overall misses +system.l2c.overall_misses::cpu1.data 67880 # number of overall misses +system.l2c.overall_misses::total 153816 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 304670500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 371494250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 307218750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 368704500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 433647250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 352819250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1462843000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 431930250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 347894250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1455959500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 232990 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4464429139 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4055832220 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8520261359 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4479114898 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4038724211 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8517839109 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 304670500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4835923389 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 307218750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4847819398 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 433647250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4408651470 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9983104359 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 431930250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4386618461 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9973798609 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 304670500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4835923389 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 307218750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4847819398 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 433647250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4408651470 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9983104359 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 10006 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3590 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 440188 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 191121 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9924 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3635 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 414861 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 189480 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1262805 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 596408 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 596408 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1465 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1442 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 431930250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4386618461 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9973798609 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9999 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3592 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 441037 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 190555 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 9920 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3623 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 413983 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 189985 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1262694 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 596358 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 596358 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1464 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1443 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2907 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 129606 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 117904 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247510 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 10006 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3590 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 440188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 320727 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9924 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3635 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 414861 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 307384 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1510315 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 10006 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3590 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 440188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 320727 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9924 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3635 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 414861 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 307384 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1510315 # number of overall (read+write) accesses +system.l2c.ReadExReq_accesses::cpu0.data 129693 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 117811 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247504 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9999 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3592 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 441037 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 320248 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9920 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3623 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 413983 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 307796 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1510198 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9999 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3592 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 441037 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 320248 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9920 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3623 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 413983 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 307796 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1510198 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000557 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.009921 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028008 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.010063 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.028223 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.014993 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.025734 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016486 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988396 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.993759 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014865 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.025539 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016493 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987705 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.994456 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991056 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.537822 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.536759 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.537316 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.539451 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.534992 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.537329 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000557 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009921 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.234025 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.010063 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.235258 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.014993 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.221749 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.101840 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014865 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.220536 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.101852 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000557 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009921 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.234025 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.010063 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.235258 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000101 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.014993 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.221749 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.101840 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014865 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.220536 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.101852 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69766.544539 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 69399.262096 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69224.594412 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 68557.921160 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 69718.207395 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 72358.336751 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 70264.806187 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 160.559392 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 162.588974 # average UpgradeReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70186.910952 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 71701.205688 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 69914.021609 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 160.781466 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 162.362369 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 161.568900 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 64047.473481 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64087.352969 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 64066.450805 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 64021.195460 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64078.254284 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 64048.237166 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 69766.544539 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 64429.153308 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 69224.594412 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 64345.036541 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 69718.207395 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 64679.021596 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 64905.431110 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 70186.910952 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 64623.135843 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 64842.400069 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 69766.544539 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 64429.153308 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 69224.594412 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 64345.036541 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 69718.207395 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 64679.021596 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 64905.431110 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 70186.910952 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 64623.135843 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 64842.400069 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -647,127 +635,127 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57659 # number of writebacks -system.l2c.writebacks::total 57659 # number of writebacks +system.l2c.writebacks::writebacks 57666 # number of writebacks +system.l2c.writebacks::total 57666 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 4367 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5353 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 4438 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5378 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6220 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4876 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 20819 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1448 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1433 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6154 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4852 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 20825 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1446 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1435 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 2881 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 69705 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 63286 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 69963 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 63028 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 132991 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 4367 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 75058 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 4438 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 75341 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6220 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 68162 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153810 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6154 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 67880 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 153816 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 4367 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 75058 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 4438 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 75341 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6220 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 68162 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153810 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6154 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 67880 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 153816 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 249527000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 303784750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 251180750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 300683500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 355119750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 290840750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1199446000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14481448 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14335433 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 28816881 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3590732861 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3262490780 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6853223641 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 354229750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 286200750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1192468500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14461446 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14352435 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 28813881 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3602203602 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3248593789 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6850797391 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 249527000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3894517611 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 251180750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3902887102 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 355119750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3553331530 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8052669641 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 354229750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3534794539 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8043265891 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 249527000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3894517611 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 251180750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3902887102 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 355119750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3553331530 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8052669641 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 339357750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84087677750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82573258250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167000293750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8396360092 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8303354060 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16699714152 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 339357750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92484037842 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90876612310 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183700007902 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 354229750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3534794539 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8043265891 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 322980250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84062460250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82598359000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166983799500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8379652001 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8320086501 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16699738502 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 322980250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92442112251 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 90918445501 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183683538002 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009921 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028008 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028223 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014993 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025734 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016486 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988396 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.993759 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025539 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016493 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987705 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.994456 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.991056 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.537822 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.536759 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537316 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.539451 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.534992 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537329 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009921 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.234025 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.235258 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014993 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.221749 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101840 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.220536 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101852 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009921 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.234025 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010063 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.235258 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014993 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.221749 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101840 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014865 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.220536 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101852 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57139.226013 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 56750.373622 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 55909.910747 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57093.207395 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59647.405660 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 57613.045775 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58986.139736 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 57261.392557 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.791347 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.388407 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 51513.275389 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51551.540309 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 51531.484394 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.696864 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.347102 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 51487.266155 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51542.073190 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 51513.240678 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57139.226013 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51886.775707 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51802.963884 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57093.207395 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52130.681758 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 52354.656011 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57139.226013 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51886.775707 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56597.735466 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51802.963884 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57093.207395 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52130.681758 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 52354.656011 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57560.895353 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52074.168223 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 52291.477421 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -786,39 +774,39 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52767546 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471907 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471907 # Transaction distribution +system.toL2Bus.throughput 52764048 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471787 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471787 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596408 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596358 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247510 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247510 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1724962 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5753498 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 20327 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50707 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7549494 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 54749620 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 83783741 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 28900 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 79720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 138641981 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138641981 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 170704 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808390000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadExReq 247504 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247504 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1724904 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753314 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20307 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50676 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549201 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54747764 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83776253 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28860 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79676 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138632553 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138632553 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 170668 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808102000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865864500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865742750 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4428402674 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4428115774 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13102500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13092500 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30777250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30757250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48142811 # Throughput (bytes/s) +system.iobus.throughput 48142902 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16715359 # Transaction distribution system.iobus.trans_dist::ReadResp 16715359 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution @@ -849,30 +837,6 @@ system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 1 system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 33447052 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) @@ -900,30 +864,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 126646649 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 126646649 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) @@ -976,139 +916,139 @@ system.iobus.reqLayer25.occupancy 15532032000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374821000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42579543250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42581193250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7541054 # DTB read hits -system.cpu0.dtb.read_misses 7077 # DTB read misses -system.cpu0.dtb.write_hits 5712165 # DTB write hits -system.cpu0.dtb.write_misses 1789 # DTB write misses +system.cpu0.dtb.read_hits 7542817 # DTB read hits +system.cpu0.dtb.read_misses 7082 # DTB read misses +system.cpu0.dtb.write_hits 5717425 # DTB write hits +system.cpu0.dtb.write_misses 1778 # DTB write misses system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6540 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 6542 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 146 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 149 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7548131 # DTB read accesses -system.cpu0.dtb.write_accesses 5713954 # DTB write accesses +system.cpu0.dtb.read_accesses 7549899 # DTB read accesses +system.cpu0.dtb.write_accesses 5719203 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13253219 # DTB hits -system.cpu0.dtb.misses 8866 # DTB misses -system.cpu0.dtb.accesses 13262085 # DTB accesses -system.cpu0.itb.inst_hits 30586267 # ITB inst hits -system.cpu0.itb.inst_misses 3713 # ITB inst misses +system.cpu0.dtb.hits 13260242 # DTB hits +system.cpu0.dtb.misses 8860 # DTB misses +system.cpu0.dtb.accesses 13269102 # DTB accesses +system.cpu0.itb.inst_hits 30610477 # ITB inst hits +system.cpu0.itb.inst_misses 3712 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 734 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2774 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2775 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30589980 # ITB inst accesses -system.cpu0.itb.hits 30586267 # DTB hits -system.cpu0.itb.misses 3713 # DTB misses -system.cpu0.itb.accesses 30589980 # DTB accesses -system.cpu0.numCycles 2629433969 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30614189 # ITB inst accesses +system.cpu0.itb.hits 30610477 # DTB hits +system.cpu0.itb.misses 3712 # DTB misses +system.cpu0.itb.accesses 30614189 # DTB accesses +system.cpu0.numCycles 2629428479 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29984771 # Number of instructions committed -system.cpu0.committedOps 38337194 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34488518 # Number of integer alu accesses +system.cpu0.committedInsts 30009354 # Number of instructions committed +system.cpu0.committedOps 38372334 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34511671 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5157 # Number of float alu accesses -system.cpu0.num_func_calls 1080132 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3980914 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34488518 # number of integer instructions +system.cpu0.num_func_calls 1080838 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3989390 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34511671 # number of integer instructions system.cpu0.num_fp_insts 5157 # number of float instructions -system.cpu0.num_int_register_reads 197896297 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36953400 # number of times the integer registers were written +system.cpu0.num_int_register_reads 198034256 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36980567 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3554 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1606 # number of times the floating registers were written -system.cpu0.num_mem_refs 13834370 # number of memory refs -system.cpu0.num_load_insts 7870253 # Number of load instructions -system.cpu0.num_store_insts 5964117 # Number of store instructions -system.cpu0.num_idle_cycles -1415422.936618 # Number of idle cycles -system.cpu0.num_busy_cycles 2630849391.936618 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000538 # Percentage of non-idle cycles -system.cpu0.idle_fraction -0.000538 # Percentage of idle cycles +system.cpu0.num_mem_refs 13842126 # number of memory refs +system.cpu0.num_load_insts 7871888 # Number of load instructions +system.cpu0.num_store_insts 5970238 # Number of store instructions +system.cpu0.num_idle_cycles 2283161569.446249 # Number of idle cycles +system.cpu0.num_busy_cycles 346266909.553751 # Number of busy cycles +system.cpu0.not_idle_fraction 0.131689 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.868311 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856159 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.881074 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60648644 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856671 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.795724 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 19966906250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 210.109344 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 300.771730 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.410370 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.587445 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997815 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 30145271 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30503373 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60648644 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30145271 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30503373 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60648644 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30145271 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30503373 # number of overall hits -system.cpu0.icache.overall_hits::total 60648644 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 440996 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 415675 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856671 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 440996 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 415675 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856671 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 440996 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 415675 # number of overall misses -system.cpu0.icache.overall_misses::total 856671 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6006488500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5787528750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11794017250 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6006488500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 5787528750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11794017250 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6006488500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 5787528750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11794017250 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30586267 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 30919048 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61505315 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30586267 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 30919048 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61505315 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30586267 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 30919048 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61505315 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014418 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013444 # miss rate for ReadReq accesses +system.cpu0.icache.tags.replacements 856130 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.884273 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60648659 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856642 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.798139 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 19947189250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 210.188035 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 300.696238 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.410524 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.587297 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997821 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 30168630 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30480029 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60648659 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30168630 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30480029 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60648659 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30168630 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30480029 # number of overall hits +system.cpu0.icache.overall_hits::total 60648659 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 441847 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 414795 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 856642 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 441847 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 414795 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 856642 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 441847 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 414795 # number of overall misses +system.cpu0.icache.overall_misses::total 856642 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6019417250 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5775014750 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11794432000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6019417250 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 5775014750 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11794432000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6019417250 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 5775014750 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11794432000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30610477 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 30894824 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61505301 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30610477 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 30894824 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61505301 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30610477 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 30894824 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61505301 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014435 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013426 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013928 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014418 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013444 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014435 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013426 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013928 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014418 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013444 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014435 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013426 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013928 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13620.278869 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13923.206231 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13767.265671 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13620.278869 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13923.206231 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13767.265671 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13620.278869 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13923.206231 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13767.265671 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13623.306823 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13922.575610 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13768.215894 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13623.306823 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13922.575610 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13768.215894 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13623.306823 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13922.575610 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13768.215894 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1117,158 +1057,158 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 440996 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 415675 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856671 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 440996 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 415675 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856671 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 440996 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 415675 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 856671 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5122351500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 4953145250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10075496750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5122351500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 4953145250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10075496750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5122351500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 4953145250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10075496750 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 430705250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 430705250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 430705250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 430705250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014418 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013444 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 441847 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 414795 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 856642 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 441847 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 414795 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 856642 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 441847 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 414795 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 856642 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5133544750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 4942408250 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10075953000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5133544750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 4942408250 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10075953000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5133544750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 4942408250 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10075953000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 414413750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 414413750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 414413750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 414413750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013928 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014418 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013444 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.013928 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014418 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013444 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014435 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013426 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013928 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11615.414879 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11915.908462 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11761.220760 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11615.414879 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11915.908462 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11761.220760 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11615.414879 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.908462 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11761.220760 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11762.151517 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11762.151517 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11618.376384 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.303343 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11762.151517 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627599 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.878483 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23660456 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628111 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.669227 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 657290250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.795545 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 329.082938 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.357023 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642740 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999763 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6630954 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6567853 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13198807 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5069666 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4905119 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9974785 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 121275 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 114924 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236199 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127469 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 120289 # number of StoreCondReq hits +system.cpu0.dcache.tags.replacements 627532 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.881676 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23660522 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628044 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.673351 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 640880250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.734555 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 329.147121 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.356903 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642865 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999769 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6634061 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6564802 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13198863 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5075609 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4899184 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9974793 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 120623 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 115578 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236201 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126785 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 120973 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247758 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11700620 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11472972 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23173592 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11700620 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11472972 # number of overall hits -system.cpu0.dcache.overall_hits::total 23173592 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 184928 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 184113 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 369041 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 131071 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 119346 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250417 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6193 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5367 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11560 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 315999 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 303459 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 619458 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 315999 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 303459 # number of overall misses -system.cpu0.dcache.overall_misses::total 619458 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2735325750 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2703937250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5439263000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5524163309 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5023911213 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10548074522 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82678500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77263500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 159942000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8259489059 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 7727848463 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15987337522 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8259489059 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 7727848463 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15987337522 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6815882 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6751966 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13567848 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5200737 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5024465 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10225202 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 127468 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 120291 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_hits::cpu0.data 11709670 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 11463986 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23173656 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11709670 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 11463986 # number of overall hits +system.cpu0.dcache.overall_hits::total 23173656 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 184394 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 184588 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 368982 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 131157 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 119254 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250411 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6161 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5397 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11558 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 315551 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 303842 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 619393 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 315551 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 303842 # number of overall misses +system.cpu0.dcache.overall_misses::total 619393 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2725468500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2705402500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5430871000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5537493548 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5008087224 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10545580772 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82157000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77679750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 159836750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8262962048 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 7713489724 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15976451772 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8262962048 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 7713489724 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15976451772 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6818455 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6749390 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13567845 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5206766 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5018438 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10225204 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126784 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 120975 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247759 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127469 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120289 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126785 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120973 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247758 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12016619 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11776431 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23793050 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12016619 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11776431 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23793050 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027132 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027268 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027200 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025202 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023753 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12025221 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11767828 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23793049 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12025221 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11767828 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23793049 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027043 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027349 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027195 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025190 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023763 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048585 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044617 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046658 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026297 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025768 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026297 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025768 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14791.301209 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14686.291843 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14738.912479 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42146.342890 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42095.346413 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42122.038528 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13350.314872 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14396.031302 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13835.813149 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26137.706319 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25465.873357 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25808.589964 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26137.706319 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 25465.873357 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25808.589964 # average overall miss latency +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048594 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044613 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046650 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026241 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025820 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026241 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025820 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14780.678872 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14656.437580 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14718.525565 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42220.343161 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41995.129924 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42113.089169 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13335.010550 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14393.135075 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13829.101056 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25793.723487 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26185.821145 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 25386.515768 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25793.723487 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1277,77 +1217,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596408 # number of writebacks -system.cpu0.dcache.writebacks::total 596408 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184928 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 184113 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369041 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131071 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 119346 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250417 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6193 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5367 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11560 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 315999 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 303459 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619458 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 315999 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 303459 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619458 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2362872250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2333419750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4696292000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5228333691 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4754653787 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9982987478 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70279500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66466500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136746000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7591205941 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7088073537 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 14679279478 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7591205941 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7088073537 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14679279478 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91858515750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90196579000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182055094750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13241304408 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12994136940 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235441348 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105099820158 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103190715940 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208290536098 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027132 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027268 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025202 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023753 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.writebacks::writebacks 596358 # number of writebacks +system.cpu0.dcache.writebacks::total 596358 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184394 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 184588 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 368982 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131157 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 119254 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250411 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6161 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5397 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11558 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 315551 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 303842 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619393 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 315551 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 303842 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619393 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2354074500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2333925500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4688000000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5241357452 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4739135776 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9980493228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69822000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66822250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136644250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7595431952 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7073061276 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14668493228 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7595431952 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7073061276 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14668493228 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91831657250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90223318750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182054976000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13223525999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13011841499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235367498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105055183249 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103235160249 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208290343498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027043 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027349 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027195 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023763 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048585 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044617 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046658 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026297 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025768 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026297 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025768 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12777.255202 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12673.845682 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12725.664628 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39889.324801 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39839.238743 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39865.454334 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11348.215727 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12384.292901 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11829.238754 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24022.879633 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23357.598677 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23696.972963 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24022.879633 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23357.598677 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23696.972963 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048594 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044613 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046650 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026241 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025820 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12766.546092 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12643.971981 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.226813 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39962.468278 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.847519 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39856.448910 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11332.900503 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12381.369279 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.482263 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24070.378329 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23278.747757 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23682.045532 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1360,76 +1300,76 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7458653 # DTB read hits -system.cpu1.dtb.read_misses 7094 # DTB read misses -system.cpu1.dtb.write_hits 5520448 # DTB write hits -system.cpu1.dtb.write_misses 1859 # DTB write misses +system.cpu1.dtb.read_hits 7456887 # DTB read hits +system.cpu1.dtb.read_misses 7096 # DTB read misses +system.cpu1.dtb.write_hits 5515190 # DTB write hits +system.cpu1.dtb.write_misses 1853 # DTB write misses system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6666 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 6662 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7465747 # DTB read accesses -system.cpu1.dtb.write_accesses 5522307 # DTB write accesses +system.cpu1.dtb.read_accesses 7463983 # DTB read accesses +system.cpu1.dtb.write_accesses 5517043 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12979101 # DTB hits -system.cpu1.dtb.misses 8953 # DTB misses -system.cpu1.dtb.accesses 12988054 # DTB accesses -system.cpu1.itb.inst_hits 30919048 # ITB inst hits -system.cpu1.itb.inst_misses 3673 # ITB inst misses +system.cpu1.dtb.hits 12972077 # DTB hits +system.cpu1.dtb.misses 8949 # DTB misses +system.cpu1.dtb.accesses 12981026 # DTB accesses +system.cpu1.itb.inst_hits 30894824 # ITB inst hits +system.cpu1.itb.inst_misses 3669 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 705 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2817 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2813 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30922721 # ITB inst accesses -system.cpu1.itb.hits 30919048 # DTB hits -system.cpu1.itb.misses 3673 # DTB misses -system.cpu1.itb.accesses 30922721 # DTB accesses -system.cpu1.numCycles 2631856202 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30898493 # ITB inst accesses +system.cpu1.itb.hits 30894824 # DTB hits +system.cpu1.itb.misses 3669 # DTB misses +system.cpu1.itb.accesses 30898493 # DTB accesses +system.cpu1.numCycles 2631851734 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30226458 # Number of instructions committed -system.cpu1.committedOps 38280743 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34395206 # Number of integer alu accesses +system.cpu1.committedInsts 30201855 # Number of instructions committed +system.cpu1.committedOps 38245582 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34372038 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5112 # Number of float alu accesses -system.cpu1.num_func_calls 1060216 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3968456 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34395206 # number of integer instructions +system.cpu1.num_func_calls 1059508 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3959978 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34372038 # number of integer instructions system.cpu1.num_fp_insts 5112 # number of float instructions -system.cpu1.num_int_register_reads 196952140 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37242776 # number of times the integer registers were written +system.cpu1.num_int_register_reads 196814123 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37215593 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3939 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1174 # number of times the floating registers were written -system.cpu1.num_mem_refs 13565505 # number of memory refs -system.cpu1.num_load_insts 7793640 # Number of load instructions -system.cpu1.num_store_insts 5771865 # Number of store instructions -system.cpu1.num_idle_cycles 4920851591.451757 # Number of idle cycles -system.cpu1.num_busy_cycles -2288995389.451757 # Number of busy cycles -system.cpu1.not_idle_fraction -0.869727 # Percentage of non-idle cycles -system.cpu1.idle_fraction 1.869727 # Percentage of idle cycles +system.cpu1.num_mem_refs 13557754 # number of memory refs +system.cpu1.num_load_insts 7792008 # Number of load instructions +system.cpu1.num_store_insts 5765746 # Number of store instructions +system.cpu1.num_idle_cycles 2293589601.195636 # Number of idle cycles +system.cpu1.num_busy_cycles 338262132.804364 # Number of busy cycles +system.cpu1.not_idle_fraction 0.128526 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.871474 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1438,10 +1378,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478947388250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1478947388250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478947388250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1478947388250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1478384126250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478384126250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1478384126250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |