diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
| commit | 9954eb74df98c4749651eb78098595f78d642105 (patch) | |
| tree | 74766341f05f999e2ad00626284e09dc6d0a2c58 /tests/long/fs/10.linux-boot/ref/arm | |
| parent | 67925a833445a8b2ddce0fae4c86677ce0f4298d (diff) | |
| download | gem5-9954eb74df98c4749651eb78098595f78d642105.tar.xz | |
stats: update stale config.ini files, eio and few other stats.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
33 files changed, 1063 insertions, 1249 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini index d9c429968..4e40ecf7a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -188,7 +188,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -647,7 +647,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -757,7 +757,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -918,7 +918,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -1377,7 +1377,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -1487,7 +1487,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -1600,7 +1600,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1635,7 +1635,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini index 23230d1e0..ec83c8fb6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -188,7 +188,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -647,7 +647,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -757,7 +757,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -845,7 +845,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 4dbc37659..6227da137 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -44,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -87,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -363,7 +361,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -374,7 +372,6 @@ size=32768 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -446,9 +443,9 @@ opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList1] type=FUDesc @@ -460,23 +457,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste [system.cpu.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=IntDiv opLat=12 +pipelined=false [system.cpu.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=IprAccess opLat=3 +pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc @@ -488,9 +485,9 @@ opList=system.cpu.fuPool.FUList2.opList [system.cpu.fuPool.FUList2.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=2 +pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc @@ -502,9 +499,9 @@ opList=system.cpu.fuPool.FUList3.opList [system.cpu.fuPool.FUList3.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=2 +pipelined=true [system.cpu.fuPool.FUList4] type=FUDesc @@ -516,184 +513,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys [system.cpu.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList21] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=9 opClass=FloatDiv opLat=9 +pipelined=false [system.cpu.fuPool.FUList4.opList24] type=OpDesc eventq_index=0 -issueLat=33 opClass=FloatSqrt opLat=33 +pipelined=false [system.cpu.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu.icache] type=BaseCache @@ -705,7 +702,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -716,7 +713,6 @@ size=32768 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -816,7 +812,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -827,7 +823,6 @@ size=4194304 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -905,7 +900,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -916,7 +911,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1284,7 +1278,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1314,6 +1309,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 9332ae5c7..06829ebfc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -210,7 +210,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -551,7 +551,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -661,7 +661,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -844,7 +844,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -1185,7 +1185,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -1295,7 +1295,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -1408,7 +1408,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1443,7 +1443,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index d6745503c..b6712dc14 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -23,6 +23,7 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[4], opc1[4], crm[0], opc2[0] warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR warn: instruction 'mcr bpiall' unimplemented @@ -31,6 +32,7 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: allocating bonus target for snoop warn: Returning zero for read from miscreg pmcr warn: Ignoring write to miscreg pmcntenclr warn: Ignoring write to miscreg pmintenclr diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index cd7aeb29d..3ad068601 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2625378187500 because m5_exit instruction encountered +Exiting @ tick 2625394935000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 51ea3fd8c..82662bafe 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.625395 # Nu sim_ticks 2625394935000 # Number of ticks simulated final_tick 2625394935000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95356 # Simulator instruction rate (inst/s) -host_op_rate 115687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2080724894 # Simulator tick rate (ticks/s) -host_mem_usage 655064 # Number of bytes of host memory used -host_seconds 1261.77 # Real time elapsed on the host +host_inst_rate 71798 # Simulator instruction rate (inst/s) +host_op_rate 87106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1566670818 # Simulator tick rate (ticks/s) +host_mem_usage 647044 # Number of bytes of host memory used +host_seconds 1675.78 # Real time elapsed on the host sim_insts 120317196 # Number of instructions simulated sim_ops 145970023 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -774,9 +774,9 @@ system.cpu0.iew.iewDispNonSpecInsts 851631 # Nu system.cpu0.iew.iewIQFullEvents 24928 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 129599 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 18950 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 275041 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 275039 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 375413 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 650454 # Number of branch mispredicts detected at execute +system.cpu0.iew.branchMispredicts 650452 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 126634007 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 22982824 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 968597 # Number of squashed instructions skipped in execute diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 67d41e91a..367b2246b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -212,7 +212,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -223,7 +223,6 @@ size=32768 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -295,9 +294,9 @@ opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList1] type=FUDesc @@ -309,23 +308,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste [system.cpu.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=IntDiv opLat=12 +pipelined=false [system.cpu.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=IprAccess opLat=3 +pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc @@ -337,9 +336,9 @@ opList=system.cpu.fuPool.FUList2.opList [system.cpu.fuPool.FUList2.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=2 +pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc @@ -351,9 +350,9 @@ opList=system.cpu.fuPool.FUList3.opList [system.cpu.fuPool.FUList3.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=2 +pipelined=true [system.cpu.fuPool.FUList4] type=FUDesc @@ -365,184 +364,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys [system.cpu.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList21] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=9 opClass=FloatDiv opLat=9 +pipelined=false [system.cpu.fuPool.FUList4.opList24] type=OpDesc eventq_index=0 -issueLat=33 opClass=FloatSqrt opLat=33 +pipelined=false [system.cpu.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu.icache] type=BaseCache @@ -554,7 +553,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -565,7 +564,6 @@ size=32768 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -665,7 +663,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -676,7 +674,6 @@ size=4194304 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -754,7 +751,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -765,7 +762,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1133,7 +1129,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1163,6 +1160,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index ab972f12d..7a0ceb162 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -8,6 +8,8 @@ warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index 200432120..13794ff0e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -147,7 +147,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -158,7 +158,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -224,7 +223,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -235,7 +234,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -637,9 +635,9 @@ opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu2.fuPool.FUList1] type=FUDesc @@ -651,16 +649,16 @@ opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu2.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=19 opClass=IntDiv opLat=20 +pipelined=false [system.cpu2.fuPool.FUList2] type=FUDesc @@ -672,23 +670,23 @@ opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 sys [system.cpu2.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=2 +pipelined=true [system.cpu2.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=2 +pipelined=true [system.cpu2.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=2 +pipelined=true [system.cpu2.fuPool.FUList3] type=FUDesc @@ -700,23 +698,23 @@ opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 sys [system.cpu2.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu2.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=FloatDiv opLat=12 +pipelined=false [system.cpu2.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 -issueLat=24 opClass=FloatSqrt opLat=24 +pipelined=false [system.cpu2.fuPool.FUList4] type=FUDesc @@ -728,9 +726,9 @@ opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5] type=FUDesc @@ -742,142 +740,142 @@ opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 s [system.cpu2.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=1 +pipelined=true [system.cpu2.fuPool.FUList6] type=FUDesc @@ -889,9 +887,9 @@ opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu2.fuPool.FUList7] type=FUDesc @@ -903,16 +901,16 @@ opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu2.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu2.fuPool.FUList8] type=FUDesc @@ -924,9 +922,9 @@ opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc eventq_index=0 -issueLat=3 opClass=IprAccess opLat=3 +pipelined=false [system.cpu2.isa] type=ArmISA @@ -1046,7 +1044,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1057,7 +1055,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1082,7 +1079,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1093,7 +1090,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -1461,7 +1457,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1491,6 +1488,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index 2ca4d069e..1fcf437ee 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -39,11 +39,11 @@ Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 7183, Bank: 4 +Command: 0, Timestamp: 7330, Bank: 4 WARNING: Bank is already active! -Command: 0, Timestamp: 9208, Bank: 3 +Command: 0, Timestamp: 9347, Bank: 3 WARNING: Bank is already active! -Command: 0, Timestamp: 9352, Bank: 2 +Command: 0, Timestamp: 9490, Bank: 2 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 @@ -55,12 +55,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 7 -WARNING: Bank is already active! -Command: 0, Timestamp: 6590, Bank: 5 -WARNING: Bank is already active! -Command: 0, Timestamp: 6595, Bank: 6 warn: Returning zero for read from miscreg pmcr warn: Ignoring write to miscreg pmcntenclr warn: Ignoring write to miscreg pmintenclr @@ -68,6 +62,8 @@ warn: Ignoring write to miscreg pmovsr warn: Ignoring write to miscreg pmcr WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2] WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 @@ -93,8 +89,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 9610, Bank: 2 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -104,31 +100,41 @@ Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: instruction 'mcr bpiall' unimplemented -WARNING: Bank is already active! -Command: 0, Timestamp: 7104, Bank: 5 -WARNING: Bank is already active! -Command: 0, Timestamp: 7593, Bank: 6 -WARNING: Bank is already active! -Command: 0, Timestamp: 8685, Bank: 7 -WARNING: Bank is already active! -Command: 0, Timestamp: 8108, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 10142, Bank: 1 warn: instruction 'mcr dcisw' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 7230, Bank: 7 +Command: 0, Timestamp: 6533, Bank: 1 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index f06fb64e9..df306f02a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -213,7 +213,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -596,7 +596,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -1270,7 +1270,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1305,7 +1305,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index 750274093..b551fcaf9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -26,7 +26,7 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[3] +warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5] warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] @@ -34,6 +34,7 @@ warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1] +warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[0] warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3] warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3] warn: Returning zero for read from miscreg pmcr @@ -41,9 +42,9 @@ warn: Ignoring write to miscreg pmcntenclr warn: Ignoring write to miscreg pmintenclr warn: Ignoring write to miscreg pmovsr warn: Ignoring write to miscreg pmcr -warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2] warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] -warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0] +warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3] +warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3] warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[2] warn: instruction 'mcr bpiall' unimplemented warn: User mode does not have SPSR @@ -54,3 +55,11 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index a839f8e59..d8bee446b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1727,9 +1727,9 @@ system.cpu1.iew.iewDispNonSpecInsts 585452 # Nu system.cpu1.iew.iewIQFullEvents 40704 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 687401 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 51353 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 260476 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 222264 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 482740 # Number of branch mispredicts detected at execute +system.cpu1.iew.predictedTakenIncorrect 260478 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 222263 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 482741 # Number of branch mispredicts detected at execute system.cpu1.iew.iewExecutedInsts 79065408 # Number of executed instructions system.cpu1.iew.iewExecLoadInsts 14638962 # Number of load instructions executed system.cpu1.iew.iewExecSquashedInsts 552436 # Number of squashed instructions skipped in execute diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini index 33618dc77..66f5e8613 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini @@ -165,7 +165,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -179,7 +179,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu0.dcache] type=BaseCache @@ -191,7 +190,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -202,7 +201,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu0.dcache_port mem_side=system.cpu0.toL2Bus.slave[1] @@ -649,9 +647,9 @@ assoc=2 clk_domain=system.cpu_clk_domain demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -662,7 +660,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.cpu0.toL2Bus.slave[0] @@ -762,7 +759,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -773,7 +770,6 @@ size=1048576 system=system tags=system.cpu0.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.toL2Bus.master[0] mem_side=system.toL2Bus.slave[0] @@ -899,7 +895,7 @@ dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side [system.cpu1.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -913,7 +909,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu1.dcache] type=BaseCache @@ -925,7 +920,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -936,7 +931,6 @@ size=32768 system=system tags=system.cpu1.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu1.dcache_port mem_side=system.cpu1.toL2Bus.slave[1] @@ -1383,9 +1377,9 @@ assoc=2 clk_domain=system.cpu_clk_domain demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -1396,7 +1390,6 @@ size=32768 system=system tags=system.cpu1.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.cpu1.toL2Bus.slave[0] @@ -1496,7 +1489,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -1507,7 +1500,6 @@ size=1048576 system=system tags=system.cpu1.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.toL2Bus.master[0] mem_side=system.toL2Bus.slave[1] @@ -1610,7 +1602,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1621,7 +1613,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1646,7 +1637,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1657,7 +1648,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -1686,7 +1676,7 @@ system=system use_default_range=false width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -2025,7 +2015,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -2038,7 +2029,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -2056,6 +2046,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] @@ -2225,7 +2216,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -2407,7 +2398,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini index ef40366e9..7ef33a7a5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini @@ -165,7 +165,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.branchPred] -type=BranchPredictor +type=TournamentBP BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -179,7 +179,6 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament [system.cpu.dcache] type=BaseCache @@ -191,7 +190,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -202,7 +201,6 @@ size=32768 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -651,7 +649,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -662,7 +660,6 @@ size=32768 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -762,7 +759,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -773,7 +770,6 @@ size=4194304 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -851,7 +847,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -862,7 +858,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -891,7 +886,7 @@ system=system use_default_range=false width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -1230,7 +1225,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1243,7 +1239,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1261,6 +1256,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] @@ -1430,7 +1426,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -1612,7 +1608,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini index 4d2b2f309..b4c7e90f4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini @@ -363,7 +363,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -374,7 +374,6 @@ size=32768 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -446,9 +445,9 @@ opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList1] type=FUDesc @@ -460,23 +459,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste [system.cpu.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=IntDiv opLat=12 +pipelined=false [system.cpu.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=IprAccess opLat=3 +pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc @@ -488,9 +487,9 @@ opList=system.cpu.fuPool.FUList2.opList [system.cpu.fuPool.FUList2.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=2 +pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc @@ -502,9 +501,9 @@ opList=system.cpu.fuPool.FUList3.opList [system.cpu.fuPool.FUList3.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=2 +pipelined=true [system.cpu.fuPool.FUList4] type=FUDesc @@ -516,184 +515,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys [system.cpu.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList21] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=9 opClass=FloatDiv opLat=9 +pipelined=false [system.cpu.fuPool.FUList4.opList24] type=OpDesc eventq_index=0 -issueLat=33 opClass=FloatSqrt opLat=33 +pipelined=false [system.cpu.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu.icache] type=BaseCache @@ -705,7 +704,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -716,7 +715,6 @@ size=32768 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -816,7 +814,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -827,7 +825,6 @@ size=4194304 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -905,7 +902,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -916,7 +913,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1284,7 +1280,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1314,6 +1311,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr index c2a0ed9be..d76e2074b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr @@ -7,95 +7,88 @@ warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist -warn: 12458605972000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0 -warn: 12458609273000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0 +warn: 12461855003000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0 +warn: 12461858210000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist -warn: 13847380989000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13886976040500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13909524462000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13910098545500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13910493556500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13910725565500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13910949758000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13919499191000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13969109987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 14211548964500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14211549180000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14219621260500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14227403410000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14227403653500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14227403893000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14227404099500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14235187327500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14235187571000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14235187810500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14235188017000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14240340342500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14240340582000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14246517945500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14246518185000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14256052185500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14256052714000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14256052957500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14256053197000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14256053403500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14267019457500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14267019664000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14276718921000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14276719431500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14276719666000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14276719896500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14276720103000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14292023524000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14292024562000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14292024768500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14297044932500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14297045442000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14297045676000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14297045906000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14297046112500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14313983409500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14313983919000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14313984153000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14313984383000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14313984589500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14376592133500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14376592349000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14434071886000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14434072706000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14434072954500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14434073170000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14562296155000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14562381650500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14562381898500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14562382116000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14562382402000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 -warn: 14562382961000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14562383216500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14562383439500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14562383728500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14562384237500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14562385304500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14562385789500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14562386108000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14563103347000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14563103608000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42 -warn: 14563103812500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14563174588000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 -warn: 14563174798000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14563175069000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 -warn: 14563175639500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14563175895000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 -warn: 14563176118500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14563176407500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14563176916500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14563177979500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14563178471000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14563178773000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14611314421000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 -warn: 14611314697500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14611314949500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14611315194000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14611315463500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14611315702500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: 13850221736500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13887901759500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13889201357500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13891026528000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13912972124000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13922135264000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 13972304377500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 +warn: 14214756028000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14214756243500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14222804811500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14230560980500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14230561210500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14230561417000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14238296234000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14238296464000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14238296670500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14243468378000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14243468608000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14249670454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14249670684500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14259219992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14259220222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14259220428500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14270200247500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14270200481500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14270200711500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14270200918000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14279912002500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14279912512000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14279912746000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14279912976000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14279913182500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14295232623000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14295232862500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14300292322000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14300292552000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14307240927500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14307241161500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14307241391500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14307241598000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14317300126000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14317300896500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14317301130500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14317301360500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14317301567000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14379824982500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14379825231000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14379825446500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14437325800500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14437326869000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14437327084500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14565495184000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14565581739000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 +warn: 14565581956000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14565582249000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 +warn: 14565582808000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14565583286500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14565583575500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14565584084500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14565585151500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14565585961500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14566302033500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14566302294500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42 +warn: 14566302499000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14566373295000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14566373505000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14566373776000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 +warn: 14566374346500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14566374602000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 +warn: 14566374825500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14566375114500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14566375623500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14566376687000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14566377185000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14566377487000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 +warn: 14614511931000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: 14614512222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14614512481000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14614512725500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14614512987500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 +warn: 14614513217000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini index 05f59cec5..d3e5a5093 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini @@ -212,7 +212,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -223,7 +223,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu0.dcache_port mem_side=system.cpu0.toL2Bus.slave[1] @@ -295,9 +294,9 @@ opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu0.fuPool.FUList1] type=FUDesc @@ -309,23 +308,23 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 sys [system.cpu0.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu0.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=IntDiv opLat=12 +pipelined=false [system.cpu0.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=IprAccess opLat=3 +pipelined=true [system.cpu0.fuPool.FUList2] type=FUDesc @@ -337,9 +336,9 @@ opList=system.cpu0.fuPool.FUList2.opList [system.cpu0.fuPool.FUList2.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=2 +pipelined=true [system.cpu0.fuPool.FUList3] type=FUDesc @@ -351,9 +350,9 @@ opList=system.cpu0.fuPool.FUList3.opList [system.cpu0.fuPool.FUList3.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=2 +pipelined=true [system.cpu0.fuPool.FUList4] type=FUDesc @@ -365,184 +364,184 @@ opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 s [system.cpu0.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=4 +pipelined=true [system.cpu0.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=4 +pipelined=true [system.cpu0.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=4 +pipelined=true [system.cpu0.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=4 +pipelined=true [system.cpu0.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=9 +pipelined=true [system.cpu0.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=3 +pipelined=true [system.cpu0.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=9 +pipelined=true [system.cpu0.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList21] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=5 +pipelined=true [system.cpu0.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=9 opClass=FloatDiv opLat=9 +pipelined=false [system.cpu0.fuPool.FUList4.opList24] type=OpDesc eventq_index=0 -issueLat=33 opClass=FloatSqrt opLat=33 +pipelined=false [system.cpu0.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu0.icache] type=BaseCache @@ -554,7 +553,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -565,7 +564,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.cpu0.toL2Bus.slave[0] @@ -665,7 +663,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -676,7 +674,6 @@ size=1048576 system=system tags=system.cpu0.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.toL2Bus.master[0] mem_side=system.toL2Bus.slave[0] @@ -849,7 +846,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -860,7 +857,6 @@ size=32768 system=system tags=system.cpu1.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu1.dcache_port mem_side=system.cpu1.toL2Bus.slave[1] @@ -932,9 +928,9 @@ opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu1.fuPool.FUList1] type=FUDesc @@ -946,23 +942,23 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 sys [system.cpu1.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu1.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=IntDiv opLat=12 +pipelined=false [system.cpu1.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=IprAccess opLat=3 +pipelined=true [system.cpu1.fuPool.FUList2] type=FUDesc @@ -974,9 +970,9 @@ opList=system.cpu1.fuPool.FUList2.opList [system.cpu1.fuPool.FUList2.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=2 +pipelined=true [system.cpu1.fuPool.FUList3] type=FUDesc @@ -988,9 +984,9 @@ opList=system.cpu1.fuPool.FUList3.opList [system.cpu1.fuPool.FUList3.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=2 +pipelined=true [system.cpu1.fuPool.FUList4] type=FUDesc @@ -1002,184 +998,184 @@ opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 s [system.cpu1.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=4 +pipelined=true [system.cpu1.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=4 +pipelined=true [system.cpu1.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=4 +pipelined=true [system.cpu1.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=4 +pipelined=true [system.cpu1.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=9 +pipelined=true [system.cpu1.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=3 +pipelined=true [system.cpu1.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=9 +pipelined=true [system.cpu1.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList21] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=5 +pipelined=true [system.cpu1.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=9 opClass=FloatDiv opLat=9 +pipelined=false [system.cpu1.fuPool.FUList4.opList24] type=OpDesc eventq_index=0 -issueLat=33 opClass=FloatSqrt opLat=33 +pipelined=false [system.cpu1.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu1.icache] type=BaseCache @@ -1191,7 +1187,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -1202,7 +1198,6 @@ size=32768 system=system tags=system.cpu1.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.cpu1.toL2Bus.slave[0] @@ -1302,7 +1297,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -1313,7 +1308,6 @@ size=1048576 system=system tags=system.cpu1.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.toL2Bus.master[0] mem_side=system.toL2Bus.slave[1] @@ -1416,7 +1410,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1427,7 +1421,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1452,7 +1445,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1463,7 +1456,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -1831,7 +1823,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1861,6 +1854,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini index 852c1bc63..2c9a47114 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini @@ -12,25 +12,23 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -44,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -87,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -212,7 +210,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -223,7 +221,6 @@ size=32768 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -295,9 +292,9 @@ opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu.fuPool.FUList1] type=FUDesc @@ -309,23 +306,23 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 syste [system.cpu.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=IntDiv opLat=12 +pipelined=false [system.cpu.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=IprAccess opLat=3 +pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc @@ -337,9 +334,9 @@ opList=system.cpu.fuPool.FUList2.opList [system.cpu.fuPool.FUList2.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=2 +pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc @@ -351,9 +348,9 @@ opList=system.cpu.fuPool.FUList3.opList [system.cpu.fuPool.FUList3.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=2 +pipelined=true [system.cpu.fuPool.FUList4] type=FUDesc @@ -365,184 +362,184 @@ opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 sys [system.cpu.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=4 +pipelined=true [system.cpu.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=3 +pipelined=true [system.cpu.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=9 +pipelined=true [system.cpu.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList21] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=5 +pipelined=true [system.cpu.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=9 opClass=FloatDiv opLat=9 +pipelined=false [system.cpu.fuPool.FUList4.opList24] type=OpDesc eventq_index=0 -issueLat=33 opClass=FloatSqrt opLat=33 +pipelined=false [system.cpu.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu.icache] type=BaseCache @@ -554,7 +551,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -565,7 +562,6 @@ size=32768 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -665,7 +661,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -676,7 +672,6 @@ size=4194304 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -754,7 +749,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -765,7 +760,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1133,7 +1127,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1163,6 +1158,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini index e9cf6e0ce..c1a5b024a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini @@ -146,7 +146,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -157,7 +157,6 @@ size=32768 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -223,7 +222,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -234,7 +233,6 @@ size=32768 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -334,7 +332,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -345,7 +343,6 @@ size=4194304 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -423,7 +420,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -434,7 +431,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -769,6 +765,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] @@ -1156,7 +1153,6 @@ port=3456 [system.vncserver] type=VncServer -capture_exit_frame=-1 eventq_index=0 frame_capture=false number=0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini index 6a2ebe226..d35c4ce4c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini @@ -14,7 +14,6 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl io atags_addr=134217728 boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb @@ -23,7 +22,6 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false @@ -147,7 +145,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -158,7 +156,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu0.dcache_port mem_side=system.cpu0.toL2Bus.slave[1] @@ -222,9 +219,9 @@ assoc=2 clk_domain=system.cpu_clk_domain demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -235,7 +232,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.cpu0.toL2Bus.slave[0] @@ -335,7 +331,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -346,7 +342,6 @@ size=1048576 system=system tags=system.cpu0.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.toL2Bus.master[0] mem_side=system.toL2Bus.slave[0] @@ -454,7 +449,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -465,7 +460,6 @@ size=32768 system=system tags=system.cpu1.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu1.dcache_port mem_side=system.cpu1.toL2Bus.slave[1] @@ -529,9 +523,9 @@ assoc=2 clk_domain=system.cpu_clk_domain demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -542,7 +536,6 @@ size=32768 system=system tags=system.cpu1.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.cpu1.toL2Bus.slave[0] @@ -642,7 +635,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -653,7 +646,6 @@ size=1048576 system=system tags=system.cpu1.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.toL2Bus.master[0] mem_side=system.toL2Bus.slave[1] @@ -756,7 +748,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -767,7 +759,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -792,7 +783,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -803,7 +794,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -832,7 +822,7 @@ system=system use_default_range=false width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -1107,7 +1097,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1120,7 +1111,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1138,6 +1128,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] @@ -1307,7 +1298,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -1489,7 +1480,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini index f454bf736..b6cf1914a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini @@ -14,7 +14,6 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus io atags_addr=134217728 boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb @@ -23,7 +22,6 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false @@ -147,7 +145,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -158,7 +156,6 @@ size=32768 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -224,7 +221,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -235,7 +232,6 @@ size=32768 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -335,7 +331,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -346,7 +342,6 @@ size=4194304 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -424,7 +419,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -435,7 +430,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -464,7 +458,7 @@ system=system use_default_range=false width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -739,7 +733,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -752,7 +747,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -770,6 +764,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] @@ -939,7 +934,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -1121,7 +1116,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini index 1dec8a2fa..314709801 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini @@ -14,7 +14,6 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl io atags_addr=134217728 boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb @@ -23,7 +22,6 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false @@ -143,7 +141,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -154,7 +152,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu0.dcache_port mem_side=system.cpu0.toL2Bus.slave[1] @@ -218,9 +215,9 @@ assoc=2 clk_domain=system.cpu_clk_domain demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -231,7 +228,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.cpu0.toL2Bus.slave[0] @@ -331,7 +327,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -342,7 +338,6 @@ size=1048576 system=system tags=system.cpu0.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu0.toL2Bus.master[0] mem_side=system.toL2Bus.slave[0] @@ -446,7 +441,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -457,7 +452,6 @@ size=32768 system=system tags=system.cpu1.dcache.tags tgts_per_mshr=8 -two_queue=false write_buffers=16 cpu_side=system.cpu1.dcache_port mem_side=system.cpu1.toL2Bus.slave[1] @@ -521,9 +515,9 @@ assoc=2 clk_domain=system.cpu_clk_domain demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true +forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -534,7 +528,6 @@ size=32768 system=system tags=system.cpu1.icache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port mem_side=system.cpu1.toL2Bus.slave[0] @@ -634,7 +627,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -645,7 +638,6 @@ size=1048576 system=system tags=system.cpu1.l2cache.tags tgts_per_mshr=8 -two_queue=false write_buffers=8 cpu_side=system.cpu1.toL2Bus.master[0] mem_side=system.toL2Bus.slave[1] @@ -748,7 +740,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -759,7 +751,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -784,7 +775,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -795,7 +786,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -824,7 +814,7 @@ system=system use_default_range=false width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -1163,7 +1153,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1176,7 +1167,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1194,6 +1184,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] @@ -1363,7 +1354,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -1545,7 +1536,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini index 9587f8b73..e55c12b7f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini @@ -14,7 +14,6 @@ children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus io atags_addr=134217728 boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb @@ -23,7 +22,6 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false @@ -143,7 +141,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -154,7 +152,6 @@ size=32768 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -220,7 +217,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -231,7 +228,6 @@ size=32768 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -331,7 +327,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -342,7 +338,6 @@ size=4194304 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -420,7 +415,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -431,7 +426,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -460,7 +454,7 @@ system=system use_default_range=false width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -799,7 +793,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -812,7 +807,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -830,6 +824,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] @@ -999,7 +994,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -1181,7 +1176,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini index 7b6dda94d..a9d46c0d8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini @@ -14,7 +14,6 @@ children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl io atags_addr=134217728 boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb @@ -23,7 +22,6 @@ enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false @@ -147,7 +145,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -158,7 +156,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -224,7 +221,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -235,7 +232,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -524,7 +520,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -535,7 +531,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -560,7 +555,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -571,7 +566,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -600,7 +594,7 @@ system=system use_default_range=false width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -875,7 +869,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -888,7 +883,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -906,6 +900,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] @@ -1075,7 +1070,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -1257,7 +1252,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr index 3137dc2c1..e6c37927e 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr @@ -568,3 +568,39 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini index 7bee47df1..e3aa5b681 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini @@ -147,7 +147,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -158,7 +158,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -224,7 +223,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -235,7 +234,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -637,9 +635,9 @@ opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu2.fuPool.FUList1] type=FUDesc @@ -651,16 +649,16 @@ opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu2.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=19 opClass=IntDiv opLat=20 +pipelined=false [system.cpu2.fuPool.FUList2] type=FUDesc @@ -672,23 +670,23 @@ opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 sys [system.cpu2.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=2 +pipelined=true [system.cpu2.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=2 +pipelined=true [system.cpu2.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=2 +pipelined=true [system.cpu2.fuPool.FUList3] type=FUDesc @@ -700,23 +698,23 @@ opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 sys [system.cpu2.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu2.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=FloatDiv opLat=12 +pipelined=false [system.cpu2.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 -issueLat=24 opClass=FloatSqrt opLat=24 +pipelined=false [system.cpu2.fuPool.FUList4] type=FUDesc @@ -728,9 +726,9 @@ opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5] type=FUDesc @@ -742,142 +740,142 @@ opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 s [system.cpu2.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu2.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=1 +pipelined=true [system.cpu2.fuPool.FUList6] type=FUDesc @@ -889,9 +887,9 @@ opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu2.fuPool.FUList7] type=FUDesc @@ -903,16 +901,16 @@ opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu2.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu2.fuPool.FUList8] type=FUDesc @@ -924,9 +922,9 @@ opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc eventq_index=0 -issueLat=3 opClass=IprAccess opLat=3 +pipelined=false [system.cpu2.isa] type=ArmISA @@ -1046,7 +1044,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1057,7 +1055,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1082,7 +1079,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1093,7 +1090,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -1461,7 +1457,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1491,6 +1488,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr index ce311b5c7..0db002d40 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr @@ -7,20 +7,20 @@ warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7336, Bank: 7 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +WARNING: Bank is already active! +Command: 0, Timestamp: 7858, Bank: 6 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 11898, Bank: 3 -WARNING: Bank is already active! -Command: 0, Timestamp: 8890, Bank: 1 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -33,6 +33,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 9145, Bank: 4 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -43,26 +45,28 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: Tried to read RealView I/O at offset 0x8 that doesn't exist -warn: Tried to read RealView I/O at offset 0x48 that doesn't exist +WARNING: Bank is already active! +Command: 0, Timestamp: 9168, Bank: 3 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 10682, Bank: 5 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: Tried to read RealView I/O at offset 0x8 that doesn't exist +warn: Tried to read RealView I/O at offset 0x48 that doesn't exist WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 10118, Bank: 1 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -81,6 +85,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -121,10 +127,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -161,14 +163,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -181,16 +175,14 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -219,8 +211,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -235,6 +225,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -245,18 +237,22 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 6745, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: Bank is already active! -Command: 0, Timestamp: 7910, Bank: 6 +Command: 0, Timestamp: 7145, Bank: 1 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -265,22 +261,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6501, Bank: 1 -WARNING: Bank is already active! -Command: 0, Timestamp: 9251, Bank: 5 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 7678, Bank: 1 -WARNING: Bank is already active! -Command: 0, Timestamp: 6735, Bank: 1 -WARNING: Bank is already active! -Command: 0, Timestamp: 7557, Bank: 6 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -295,18 +281,38 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 9101, Bank: 7 +WARNING: Bank is already active! +Command: 0, Timestamp: 9235, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 7617, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 8572, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 6448, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 10110, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7448, Bank: 6 +WARNING: Bank is already active! +Command: 0, Timestamp: 10610, Bank: 5 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -321,8 +327,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 1 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -331,22 +335,24 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 8438, Bank: 3 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 3 +Command: 0, Timestamp: 10259, Bank: 6 +WARNING: Bank is already active! +Command: 0, Timestamp: 10259, Bank: 1 WARNING: Bank is already active! -Command: 0, Timestamp: 6449, Bank: 1 +Command: 0, Timestamp: 10264, Bank: 4 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -357,8 +363,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 11346, Bank: 6 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -367,14 +371,12 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 6718, Bank: 7 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +Command: 0, Timestamp: 8662, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 8576, Bank: 2 +WARNING: Bank is already active! +Command: 0, Timestamp: 8938, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -389,20 +391,22 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 8596, Bank: 2 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 9274, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -415,30 +419,32 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 7950, Bank: 1 +WARNING: Bank is already active! +Command: 0, Timestamp: 8022, Bank: 6 +WARNING: Bank is already active! +Command: 0, Timestamp: 6606, Bank: 1 +WARNING: Bank is already active! +Command: 0, Timestamp: 7878, Bank: 5 +WARNING: Bank is already active! +Command: 0, Timestamp: 9487, Bank: 6 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 8427, Bank: 5 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7189, Bank: 3 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -452,17 +458,7 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: Bank is already active! -Command: 0, Timestamp: 10975, Bank: 5 -WARNING: Bank is already active! -Command: 0, Timestamp: 11256, Bank: 2 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +Command: 0, Timestamp: 9249, Bank: 5 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -487,16 +483,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6729, Bank: 3 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: Bank is already active! -Command: 0, Timestamp: 12439, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -515,18 +505,16 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7135, Bank: 3 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 6921, Bank: 2 +WARNING: Bank is already active! +Command: 0, Timestamp: 7517, Bank: 5 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -535,16 +523,20 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 11967, Bank: 5 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -559,8 +551,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -573,6 +563,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -589,30 +583,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 11356, Bank: 5 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 9054, Bank: 7 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -627,16 +603,12 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6571, Bank: 6 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -657,8 +629,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -667,16 +637,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -701,14 +665,22 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 10927, Bank: 6 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7539, Bank: 3 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -723,10 +695,26 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -735,6 +723,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -759,38 +751,42 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 6681, Bank: 7 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7983, Bank: 5 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -807,8 +803,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 7384, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -825,14 +819,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 10124, Bank: 1 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -845,24 +831,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 3 -WARNING: Bank is already active! -Command: 0, Timestamp: 6758, Bank: 2 -WARNING: Bank is already active! -Command: 0, Timestamp: 8359, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6936, Bank: 1 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -875,6 +847,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -891,14 +867,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -907,6 +883,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -927,6 +915,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -963,10 +955,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -985,10 +975,18 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1019,6 +1017,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1039,6 +1039,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1057,6 +1065,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1073,14 +1093,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1089,16 +1101,18 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1117,10 +1131,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1141,6 +1151,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1199,16 +1213,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1219,8 +1223,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 8631, Bank: 7 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1229,6 +1233,10 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1245,6 +1253,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1257,10 +1267,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1291,24 +1297,20 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 11511, Bank: 2 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -1323,8 +1325,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 9988, Bank: 2 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR @@ -1332,39 +1334,23 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: Bank is already active! -Command: 0, Timestamp: 7482, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +Command: 0, Timestamp: 6448, Bank: 5 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 8240, Bank: 5 -WARNING: Bank is already active! -Command: 0, Timestamp: 6884, Bank: 4 -WARNING: Bank is already active! -Command: 0, Timestamp: 7065, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 7992, Bank: 0 +Command: 0, Timestamp: 9255, Bank: 4 +WARNING: Bank is already active! +Command: 0, Timestamp: 11880, Bank: 6 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 6 -WARNING: Bank is already active! -Command: 0, Timestamp: 6861, Bank: 4 -WARNING: Bank is already active! -Command: 0, Timestamp: 6994, Bank: 7 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +Command: 0, Timestamp: 7102, Bank: 7 WARNING: Bank is already active! -Command: 0, Timestamp: 7102, Bank: 2 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +Command: 0, Timestamp: 7405, Bank: 1 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1375,12 +1361,14 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1393,24 +1381,20 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +WARNING: Bank is already active! +Command: 0, Timestamp: 9173, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1435,10 +1419,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1457,8 +1437,6 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 9034, Bank: 2 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR @@ -1479,8 +1457,8 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 10338, Bank: 2 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini index 7721c6927..2214964bc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini @@ -215,7 +215,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -226,7 +226,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -298,9 +297,9 @@ opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu0.fuPool.FUList1] type=FUDesc @@ -312,16 +311,16 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu0.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=19 opClass=IntDiv opLat=20 +pipelined=false [system.cpu0.fuPool.FUList2] type=FUDesc @@ -333,23 +332,23 @@ opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 sys [system.cpu0.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=2 +pipelined=true [system.cpu0.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=2 +pipelined=true [system.cpu0.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=2 +pipelined=true [system.cpu0.fuPool.FUList3] type=FUDesc @@ -361,23 +360,23 @@ opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 sys [system.cpu0.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu0.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=FloatDiv opLat=12 +pipelined=false [system.cpu0.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 -issueLat=24 opClass=FloatSqrt opLat=24 +pipelined=false [system.cpu0.fuPool.FUList4] type=FUDesc @@ -389,9 +388,9 @@ opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5] type=FUDesc @@ -403,142 +402,142 @@ opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 s [system.cpu0.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu0.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=1 +pipelined=true [system.cpu0.fuPool.FUList6] type=FUDesc @@ -550,9 +549,9 @@ opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu0.fuPool.FUList7] type=FUDesc @@ -564,16 +563,16 @@ opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu0.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu0.fuPool.FUList8] type=FUDesc @@ -585,9 +584,9 @@ opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc eventq_index=0 -issueLat=3 opClass=IprAccess opLat=3 +pipelined=false [system.cpu0.icache] type=BaseCache @@ -599,7 +598,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -610,7 +609,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -865,9 +863,9 @@ opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntAlu opLat=1 +pipelined=true [system.cpu1.fuPool.FUList1] type=FUDesc @@ -879,16 +877,16 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=IntMult opLat=3 +pipelined=true [system.cpu1.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=19 opClass=IntDiv opLat=20 +pipelined=false [system.cpu1.fuPool.FUList2] type=FUDesc @@ -900,23 +898,23 @@ opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 sys [system.cpu1.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatAdd opLat=2 +pipelined=true [system.cpu1.fuPool.FUList2.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCmp opLat=2 +pipelined=true [system.cpu1.fuPool.FUList2.opList2] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatCvt opLat=2 +pipelined=true [system.cpu1.fuPool.FUList3] type=FUDesc @@ -928,23 +926,23 @@ opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 sys [system.cpu1.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=FloatMult opLat=4 +pipelined=true [system.cpu1.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 -issueLat=12 opClass=FloatDiv opLat=12 +pipelined=false [system.cpu1.fuPool.FUList3.opList2] type=OpDesc eventq_index=0 -issueLat=24 opClass=FloatSqrt opLat=24 +pipelined=false [system.cpu1.fuPool.FUList4] type=FUDesc @@ -956,9 +954,9 @@ opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5] type=FUDesc @@ -970,142 +968,142 @@ opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 s [system.cpu1.fuPool.FUList5.opList00] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAdd opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList01] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAddAcc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList02] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdAlu opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList03] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCmp opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList04] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdCvt opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList05] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMisc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList06] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMult opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList07] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdMultAcc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList08] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShift opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList09] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdShiftAcc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList10] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdSqrt opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList11] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAdd opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList12] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatAlu opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList13] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCmp opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList14] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatCvt opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList15] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatDiv opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList16] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMisc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList17] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMult opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList18] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatMultAcc opLat=1 +pipelined=true [system.cpu1.fuPool.FUList5.opList19] type=OpDesc eventq_index=0 -issueLat=1 opClass=SimdFloatSqrt opLat=1 +pipelined=true [system.cpu1.fuPool.FUList6] type=FUDesc @@ -1117,9 +1115,9 @@ opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu1.fuPool.FUList7] type=FUDesc @@ -1131,16 +1129,16 @@ opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemRead opLat=1 +pipelined=true [system.cpu1.fuPool.FUList7.opList1] type=OpDesc eventq_index=0 -issueLat=1 opClass=MemWrite opLat=1 +pipelined=true [system.cpu1.fuPool.FUList8] type=FUDesc @@ -1152,9 +1150,9 @@ opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc eventq_index=0 -issueLat=3 opClass=IprAccess opLat=3 +pipelined=false [system.cpu1.isa] type=ArmISA @@ -1274,7 +1272,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1285,7 +1283,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -1310,7 +1307,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1321,7 +1318,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -1689,7 +1685,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -1719,6 +1716,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr index 68af87dfe..4d4e040d3 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr @@ -433,3 +433,67 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini index 6cf886297..5a83a4136 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini @@ -12,38 +12,37 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64 +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 flags_addr=469827632 gic_cpu_addr=738205696 -have_generic_timer=false have_large_asid_64=false have_lpae=false have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing mem_ranges=2147483648:2415919103 -memories=system.realview.nvmem system.physmem system.realview.vram +memories=system.physmem system.realview.nvmem system.realview.vram +mmap_using_noreserve=false multi_proc=true num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5.latest/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img +image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -138,10 +137,11 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -152,7 +152,6 @@ size=32768 system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -172,6 +171,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu0.dtb [system.cpu0.dstage2_mmu.stage2_tlb] @@ -189,7 +189,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[5] [system.cpu0.dtb] type=ArmTLB @@ -214,10 +213,11 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -228,7 +228,6 @@ size=32768 system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -282,6 +281,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu0.itb [system.cpu0.istage2_mmu.stage2_tlb] @@ -299,7 +299,6 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB @@ -360,6 +359,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +sys=system tlb=system.cpu1.dtb [system.cpu1.dstage2_mmu.stage2_tlb] @@ -429,6 +429,7 @@ type=ArmStage2MMU children=stage2_tlb eventq_index=0 stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +sys=system tlb=system.cpu1.itb [system.cpu1.istage2_mmu.stage2_tlb] @@ -492,9 +493,11 @@ sys=system type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=1 +frontend_latency=2 +response_latency=2 use_default_range=true -width=8 +width=16 default=system.realview.pciconfig.pio master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma @@ -505,10 +508,11 @@ children=tags addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -519,7 +523,6 @@ size=1024 system=system tags=system.iocache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.iobus.master[27] mem_side=system.membus.slave[3] @@ -540,10 +543,11 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -554,7 +558,6 @@ size=4194304 system=system tags=system.l2c.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -574,13 +577,16 @@ type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 -header_cycles=1 +forward_latency=4 +frontend_latency=3 +response_latency=2 snoop_filter=Null +snoop_response_latency=4 system=system use_default_range=false -width=8 +width=16 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] @@ -628,7 +634,7 @@ IDD62=0.000000 VDD=1.500000 VDD2=0.000000 activation_limit=4 -addr_mapping=RoRaBaChCo +addr_mapping=RoRaBaCoCh bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 @@ -919,7 +925,8 @@ pio=system.iobus.master[25] type=GenericTimer eventq_index=0 gic=system.realview.gic -int_num=29 +int_phys=29 +int_virt=27 system=system [system.realview.gic] @@ -932,7 +939,6 @@ dist_pio_delay=10000 eventq_index=0 int_latency=10000 it_lines=128 -msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -950,6 +956,7 @@ pio_latency=10000 pixel_clock=7299 system=system vnc=system.vncserver +workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] @@ -1119,7 +1126,7 @@ int_num_watchdog=30 pio_addr=738721792 pio_latency=100000 system=system -pio=system.membus.master[3] +pio=system.membus.master[4] [system.realview.mmc_fake] type=AmbaFake @@ -1301,7 +1308,7 @@ platform=system.realview ppint=25 system=system vcpu_addr=738222080 -pio=system.membus.master[4] +pio=system.membus.master[3] [system.realview.vram] type=SimpleMemory @@ -1339,13 +1346,16 @@ port=3456 type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 -header_cycles=1 +forward_latency=0 +frontend_latency=1 +response_latency=1 snoop_filter=Null +snoop_response_latency=1 system=system use_default_range=false -width=8 +width=32 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port [system.vncserver] type=VncServer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr index 35422844e..bc8b17326 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr @@ -1533,215 +1533,3 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR |