diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:36:45 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-21 10:36:45 -0500 |
| commit | 3c666083c6f5fecc38699a6f0c5f4f25b23e18c9 (patch) | |
| tree | e554e37e76714f9ae9c9faa07ef645db0f9a6d93 /tests/long/fs/10.linux-boot/ref/arm | |
| parent | 8e2a8fbb7e4751260c88fccd19ebe8d1138d0695 (diff) | |
| download | gem5-3c666083c6f5fecc38699a6f0c5f4f25b23e18c9.tar.xz | |
ARM: Update stats for IT and conditional branch changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
10 files changed, 2816 insertions, 2817 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 1946d5bbf..655130261 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -579,7 +579,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -673,7 +673,7 @@ port=system.membus.master[2] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -913,13 +913,16 @@ proc_id1=201327138 system=system pio=system.iobus.master[1] -[system.realview.rtc_fake] -type=AmbaFake -amba_id=266289 -ignore_access=false +[system.realview.rtc] +type=PL031 +amba_id=3412017 +gic=system.realview.gic +int_delay=100000 +int_num=42 pio_addr=268529664 pio_latency=1000 system=system +time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] [system.realview.sci_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index c3520687e..047da4193 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,13 +10,12 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 5655885500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 5665876500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 5705833500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 5722480500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6171915000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 5654850500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5664849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5704830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 5721485500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 warn: LCD dual screen mode not supported -warn: 53400472000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 53386624000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 51386a35a..37a41903b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,15 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:47:04 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 18:15:21 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -The currently selected ARM platforms doesn't support - the amount of DRAM you've selected. Please try - another platform Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503099557500 because m5_exit instruction encountered +Exiting @ tick 2501676293500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index d91423395..ec9717e88 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503100 # Number of seconds simulated -sim_ticks 2503099557500 # Number of ticks simulated -final_tick 2503099557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.501676 # Number of seconds simulated +sim_ticks 2501676293500 # Number of ticks simulated +final_tick 2501676293500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68083 # Simulator instruction rate (inst/s) -host_op_rate 87941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2866621111 # Simulator tick rate (ticks/s) -host_mem_usage 384248 # Number of bytes of host memory used -host_seconds 873.19 # Real time elapsed on the host -sim_insts 59449445 # Number of instructions simulated -sim_ops 76789092 # Number of ops (including micro ops) simulated +host_inst_rate 79857 # Simulator instruction rate (inst/s) +host_op_rate 103150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3360326389 # Simulator tick rate (ticks/s) +host_mem_usage 381664 # Number of bytes of host memory used +host_seconds 744.47 # Real time elapsed on the host +sim_insts 59451291 # Number of instructions simulated +sim_ops 76792341 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,148 +20,151 @@ system.realview.nvmem.num_other 0 # Nu system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 130740776 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1120320 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9586312 # Number of bytes written to this memory -system.physmem.num_reads 15115704 # Number of read requests responded to by this memory -system.physmem.num_writes 856678 # Number of write requests responded to by this memory +system.physmem.bytes_read 129652968 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1121024 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9585096 # Number of bytes written to this memory +system.physmem.num_reads 14979455 # Number of read requests responded to by this memory +system.physmem.num_writes 856659 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52231553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 447573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3829777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56061329 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119794 # number of replacements -system.l2c.tagsinuse 26073.611012 # Cycle average of tags in use -system.l2c.total_refs 1840774 # Total number of references to valid blocks. -system.l2c.sampled_refs 150725 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.212798 # Average number of references to valid blocks. +system.physmem.bw_read 51826437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 448109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3831469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 55657906 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 119784 # number of replacements +system.l2c.tagsinuse 25999.615357 # Cycle average of tags in use +system.l2c.total_refs 1826145 # Total number of references to valid blocks. +system.l2c.sampled_refs 150763 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.112687 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14308.761179 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 64.610993 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.928498 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6189.887268 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5509.423074 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.218334 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000986 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 14272.421964 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 65.344146 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.932012 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6169.201034 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5491.716201 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.217780 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000997 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.094450 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.084067 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.397852 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 152848 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11656 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 998872 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 377319 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1540695 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 633173 # number of Writeback hits -system.l2c.Writeback_hits::total 633173 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 44 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 105891 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105891 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 152848 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11656 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 998872 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 483210 # number of demand (read+write) hits -system.l2c.demand_hits::total 1646586 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 152848 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11656 # number of overall hits -system.l2c.overall_hits::cpu.inst 998872 # number of overall hits -system.l2c.overall_hits::cpu.data 483210 # number of overall hits -system.l2c.overall_hits::total 1646586 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 147 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 17382 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 19146 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36687 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 3313 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3313 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 140346 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140346 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 147 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 17382 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 159492 # number of demand (read+write) misses -system.l2c.demand_misses::total 177033 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 147 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu.inst 17382 # number of overall misses -system.l2c.overall_misses::cpu.data 159492 # number of overall misses -system.l2c.overall_misses::total 177033 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7686500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 617000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 910008500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1001033000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1919345000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 1206000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1206000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7379766500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7379766500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 7686500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 617000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 910008500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8380799500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9299111500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 7686500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 617000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 910008500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8380799500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9299111500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 152995 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11668 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1016254 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 396465 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1577382 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 633173 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 633173 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 3357 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3357 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246237 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246237 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 152995 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11668 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1016254 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 642702 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1823619 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 152995 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11668 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1016254 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 642702 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1823619 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001028 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.017104 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.048292 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.986893 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.569963 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001028 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.017104 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.248159 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001028 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.017104 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.248159 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52289.115646 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 51416.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52353.497871 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52284.184686 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.020525 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52582.663560 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52546.833070 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52546.833070 # average overall miss latency +system.l2c.occ_percent::cpu.inst 0.094135 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.083797 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.396723 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 141919 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 12116 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 995766 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 377927 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1527728 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 634955 # number of Writeback hits +system.l2c.Writeback_hits::total 634955 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 46 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 7 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 105770 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105770 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 141919 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 12116 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 995766 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 483697 # number of demand (read+write) hits +system.l2c.demand_hits::total 1633498 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 141919 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 12116 # number of overall hits +system.l2c.overall_hits::cpu.inst 995766 # number of overall hits +system.l2c.overall_hits::cpu.data 483697 # number of overall hits +system.l2c.overall_hits::total 1633498 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 157 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 17392 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 19166 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36728 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 3302 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3302 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 140335 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140335 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 157 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 17392 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 159501 # number of demand (read+write) misses +system.l2c.demand_misses::total 177063 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 157 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 13 # number of overall misses +system.l2c.overall_misses::cpu.inst 17392 # number of overall misses +system.l2c.overall_misses::cpu.data 159501 # number of overall misses +system.l2c.overall_misses::total 177063 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 8196500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 677000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 910933000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1001503500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1921310000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1203000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1203000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7367598500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7367598500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 8196500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 677000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 910933000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8369102000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9288908500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 8196500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 677000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 910933000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8369102000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9288908500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 142076 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 12129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1013158 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 397093 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1564456 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 634955 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 634955 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3348 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3348 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 10 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246105 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 142076 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 12129 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1013158 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 643198 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1810561 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 142076 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 12129 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1013158 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 643198 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1810561 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001105 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001072 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.017166 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.048266 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.986260 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.300000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.570224 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.001105 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001072 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.017166 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.247981 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.001105 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001072 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.017166 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.247981 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52207.006369 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52076.923077 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52376.552438 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52254.174058 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.324652 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52500.078384 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -170,100 +173,97 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102660 # number of writebacks -system.l2c.writebacks::total 102660 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.data 79 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.data 79 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 93 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 147 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 17369 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 19067 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 3313 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3313 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 140346 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140346 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 147 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 17369 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 159413 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 176940 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 147 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 17369 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 159413 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 176940 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 5904000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 442000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 697218500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 765075000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1468639500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 133817000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 133817000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5636526500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5636526500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 442000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 697218500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6401601500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7105166000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5904000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 442000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 697218500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6401601500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7105166000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5507000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131763880500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131769387500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348463263 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32348463263 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5507000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164112343763 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164117850763 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048093 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986893 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569963 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40141.545282 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40125.609692 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40391.488077 # average UpgradeReq mshr miss latency +system.l2c.writebacks::writebacks 102641 # number of writebacks +system.l2c.writebacks::total 102641 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 91 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 157 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 13 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 17382 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 19085 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 36637 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 3302 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3302 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 140335 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140335 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 157 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 17382 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 159420 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176972 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 157 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 17382 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 159420 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176972 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 6288500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 521000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 698170500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 765243500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1470223500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 132738500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 132738500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5623589000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5623589000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 6288500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 521000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 698170500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6388832500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7093812500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 6288500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 521000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 698170500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6388832500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7093812500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765321500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131770748500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346079731 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32346079731 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164111401231 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164116828231 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048062 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986260 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.300000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.570224 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.247855 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.247855 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40166.292717 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.594184 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40199.424591 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40161.646930 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40072.604838 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40166.292717 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.476728 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40166.292717 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.476728 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -278,26 +278,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15016256 # DTB read hits -system.cpu.checker.dtb.read_misses 7312 # DTB read misses -system.cpu.checker.dtb.write_hits 11274185 # DTB write hits -system.cpu.checker.dtb.write_misses 2190 # DTB write misses +system.cpu.checker.dtb.read_hits 15017081 # DTB read hits +system.cpu.checker.dtb.read_misses 7305 # DTB read misses +system.cpu.checker.dtb.write_hits 11274838 # DTB write hits +system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15023568 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11276375 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15024386 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11277029 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26290441 # DTB hits -system.cpu.checker.dtb.misses 9502 # DTB misses -system.cpu.checker.dtb.accesses 26299943 # DTB accesses -system.cpu.checker.itb.inst_hits 60615999 # ITB inst hits +system.cpu.checker.dtb.hits 26291919 # DTB hits +system.cpu.checker.dtb.misses 9496 # DTB misses +system.cpu.checker.dtb.accesses 26301415 # DTB accesses +system.cpu.checker.itb.inst_hits 60617853 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -314,36 +314,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 60620470 # ITB inst accesses -system.cpu.checker.itb.hits 60615999 # DTB hits +system.cpu.checker.itb.inst_accesses 60622324 # ITB inst accesses +system.cpu.checker.itb.hits 60617853 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 60620470 # DTB accesses -system.cpu.checker.numCycles 77067453 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 60622324 # DTB accesses +system.cpu.checker.numCycles 77070710 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51948606 # DTB read hits -system.cpu.dtb.read_misses 101816 # DTB read misses -system.cpu.dtb.write_hits 11910706 # DTB write hits -system.cpu.dtb.write_misses 24423 # DTB write misses +system.cpu.dtb.read_hits 52069399 # DTB read hits +system.cpu.dtb.read_misses 92258 # DTB read misses +system.cpu.dtb.write_hits 11926847 # DTB write hits +system.cpu.dtb.write_misses 25023 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7999 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5598 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 665 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 8152 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 5662 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 693 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2849 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52050422 # DTB read accesses -system.cpu.dtb.write_accesses 11935129 # DTB write accesses +system.cpu.dtb.perms_faults 2731 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52161657 # DTB read accesses +system.cpu.dtb.write_accesses 11951870 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63859312 # DTB hits -system.cpu.dtb.misses 126239 # DTB misses -system.cpu.dtb.accesses 63985551 # DTB accesses -system.cpu.itb.inst_hits 13611127 # ITB inst hits -system.cpu.itb.inst_misses 11794 # ITB inst misses +system.cpu.dtb.hits 63996246 # DTB hits +system.cpu.dtb.misses 117281 # DTB misses +system.cpu.dtb.accesses 64113527 # DTB accesses +system.cpu.itb.inst_hits 13699541 # ITB inst hits +system.cpu.itb.inst_misses 12131 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -352,504 +352,504 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5224 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5248 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 6917 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 6936 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13622921 # ITB inst accesses -system.cpu.itb.hits 13611127 # DTB hits -system.cpu.itb.misses 11794 # DTB misses -system.cpu.itb.accesses 13622921 # DTB accesses -system.cpu.numCycles 414035717 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13711672 # ITB inst accesses +system.cpu.itb.hits 13699541 # DTB hits +system.cpu.itb.misses 12131 # DTB misses +system.cpu.itb.accesses 13711672 # DTB accesses +system.cpu.numCycles 411150559 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15526652 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12489737 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 928336 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10678484 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8212324 # Number of BTB hits +system.cpu.BPredUnit.lookups 15631672 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12342234 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 929456 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10552810 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8288947 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1312295 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 195061 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32929499 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 102163781 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15526652 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9524619 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22440538 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6579937 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 148688 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93080203 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 137545 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 217702 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13603433 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 995292 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6599 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 153452703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.827416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.209875 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1323523 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 194787 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32982972 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 102837345 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15631672 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9612470 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22590084 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6692504 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 158663 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 89850563 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2746 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 143204 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 218934 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 483 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13691858 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 996334 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6838 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150553763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.848436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.233477 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131028378 85.39% 85.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1463837 0.95% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1832687 1.19% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2690815 1.75% 89.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1870921 1.22% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1178749 0.77% 91.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2936419 1.91% 93.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 835625 0.54% 93.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9615272 6.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 127980574 85.01% 85.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1480097 0.98% 85.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1855620 1.23% 87.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2694532 1.79% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1893570 1.26% 90.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1188011 0.79% 91.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2948135 1.96% 93.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 848652 0.56% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9664572 6.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 153452703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.037501 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.246751 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34954549 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92988756 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20078806 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1116855 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4313737 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2248287 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 185454 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119076129 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 599477 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4313737 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37045133 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36926846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49909637 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19098925 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6158425 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 111441141 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3427 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 975111 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4036126 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 44783 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115828569 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 512776978 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 512681517 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 95461 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77492759 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38335809 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1177287 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1072928 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13010963 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21488170 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14015818 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1893787 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2361029 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101216530 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1853504 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 125772492 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 220452 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25469081 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 69618284 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 353864 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 153452703 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819617 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.525568 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150553763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.038019 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.250121 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35091688 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89690975 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20321625 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1025705 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4423770 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2273029 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 186320 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119828190 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 605140 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4423770 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37165531 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37166387 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46484492 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19226681 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6086902 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 112339029 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3754 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1012932 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4107831 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 44905 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 116884712 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 516607430 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 516512877 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 94553 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77495227 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 39389484 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 939636 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 835400 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12435347 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21635443 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14050113 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1939177 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2494760 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 102209700 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1618930 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126189021 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 231742 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26205661 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 71388624 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 331981 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150553763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.838166 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.542583 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107878797 70.30% 70.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14731235 9.60% 79.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7302555 4.76% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5766685 3.76% 88.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12704866 8.28% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2797979 1.82% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1703854 1.11% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 430247 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 136485 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 105343416 69.97% 69.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14065037 9.34% 79.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7354541 4.88% 84.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5909522 3.93% 88.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12758140 8.47% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2807768 1.86% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1730475 1.15% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 446826 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 138038 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 153452703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150553763 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 55588 0.63% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8410763 94.57% 95.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 427006 4.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60599 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8416262 94.64% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 416317 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59380040 47.21% 47.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95959 0.08% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 34 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 46 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2266 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53622551 42.63% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12565056 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59665616 47.28% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95635 0.08% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 36 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 48 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2270 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53732100 42.58% 90.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12586768 9.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 125772492 # Type of FU issued -system.cpu.iq.rate 0.303772 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8893360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070710 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 414213065 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128557320 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86496982 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24084 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13214 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10457 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134546484 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12838 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 592105 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126189021 # Type of FU issued +system.cpu.iq.rate 0.306917 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8893180 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070475 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 412149363 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 130053896 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86886822 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24048 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13080 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10409 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134962848 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12823 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 636825 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5807721 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11311 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32412 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2237013 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5953964 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11249 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33793 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2270680 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34115378 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1150417 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34115287 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1151875 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4313737 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28451597 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 431255 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103286909 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 337253 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21488170 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14015818 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1227531 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 94319 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11225 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32412 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 548239 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 349587 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 897826 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122535537 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52641416 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3236955 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4423770 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28606306 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 435959 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 104089793 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 334839 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21635443 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14050113 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 991881 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 95881 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11592 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33793 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 550966 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 345374 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 896340 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122956903 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52760819 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3232118 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 216875 # number of nop insts executed -system.cpu.iew.exec_refs 65061832 # number of memory reference insts executed -system.cpu.iew.exec_branches 11533456 # Number of branches executed -system.cpu.iew.exec_stores 12420416 # Number of stores executed -system.cpu.iew.exec_rate 0.295954 # Inst execution rate -system.cpu.iew.wb_sent 121007788 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86507439 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46901063 # num instructions producing a value -system.cpu.iew.wb_consumers 86866563 # num instructions consuming a value +system.cpu.iew.exec_nop 261163 # number of nop insts executed +system.cpu.iew.exec_refs 65197273 # number of memory reference insts executed +system.cpu.iew.exec_branches 11589071 # Number of branches executed +system.cpu.iew.exec_stores 12436454 # Number of stores executed +system.cpu.iew.exec_rate 0.299056 # Inst execution rate +system.cpu.iew.wb_sent 121403477 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86897231 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47438485 # num instructions producing a value +system.cpu.iew.wb_consumers 88321921 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.208937 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.539921 # average fanout of values written-back +system.cpu.iew.wb_rate 0.211351 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.537109 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59599826 # The number of committed instructions -system.cpu.commit.commitCommittedOps 76939473 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26171914 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1499640 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 790317 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149221313 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.515606 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.482610 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59601672 # The number of committed instructions +system.cpu.commit.commitCommittedOps 76942722 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26965943 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1286949 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 790517 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146212348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.526240 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.505087 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120951257 81.05% 81.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14347270 9.61% 90.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4034652 2.70% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2127712 1.43% 94.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1768055 1.18% 95.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1033434 0.69% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1556613 1.04% 97.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657865 0.44% 98.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2744455 1.84% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118498573 81.05% 81.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13699176 9.37% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3966547 2.71% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2244227 1.53% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1750329 1.20% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1033206 0.71% 96.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1542131 1.05% 97.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 667633 0.46% 98.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2810526 1.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149221313 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59599826 # Number of instructions committed -system.cpu.commit.committedOps 76939473 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146212348 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59601672 # Number of instructions committed +system.cpu.commit.committedOps 76942722 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27459254 # Number of memory references committed -system.cpu.commit.loads 15680449 # Number of loads committed -system.cpu.commit.membars 413031 # Number of memory barriers committed -system.cpu.commit.branches 9890920 # Number of branches committed +system.cpu.commit.refs 27460912 # Number of memory references committed +system.cpu.commit.loads 15681479 # Number of loads committed +system.cpu.commit.membars 413077 # Number of memory barriers committed +system.cpu.commit.branches 9891359 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68492585 # Number of committed integer instructions. -system.cpu.commit.function_calls 995546 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2744455 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68495555 # Number of committed integer instructions. +system.cpu.commit.function_calls 995632 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2810526 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 247831805 # The number of ROB reads -system.cpu.rob.rob_writes 210661614 # The number of ROB writes -system.cpu.timesIdled 1891867 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260583014 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592075418 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59449445 # Number of Instructions Simulated -system.cpu.committedOps 76789092 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59449445 # Number of Instructions Simulated -system.cpu.cpi 6.964501 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.964501 # CPI: Total CPI of All Threads -system.cpu.ipc 0.143585 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.143585 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 555570057 # number of integer regfile reads -system.cpu.int_regfile_writes 88783659 # number of integer regfile writes -system.cpu.fp_regfile_reads 8868 # number of floating regfile reads -system.cpu.fp_regfile_writes 2963 # number of floating regfile writes -system.cpu.misc_regfile_reads 134383864 # number of misc regfile reads -system.cpu.misc_regfile_writes 912266 # number of misc regfile writes -system.cpu.icache.replacements 1016880 # number of replacements -system.cpu.icache.tagsinuse 511.619498 # Cycle average of tags in use -system.cpu.icache.total_refs 12495254 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1017392 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.281652 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6291400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.619498 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999257 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999257 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12495254 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12495254 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12495254 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12495254 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12495254 # number of overall hits -system.cpu.icache.overall_hits::total 12495254 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1108036 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1108036 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1108036 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1108036 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1108036 # number of overall misses -system.cpu.icache.overall_misses::total 1108036 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16316535479 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16316535479 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16316535479 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16316535479 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16316535479 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16316535479 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13603290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13603290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13603290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13603290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13603290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13603290 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081454 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081454 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081454 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14725.636603 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2951482 # number of cycles access was blocked +system.cpu.rob.rob_reads 245553933 # The number of ROB reads +system.cpu.rob.rob_writes 212368242 # The number of ROB writes +system.cpu.timesIdled 1894262 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260596796 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592114044 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59451291 # Number of Instructions Simulated +system.cpu.committedOps 76792341 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59451291 # Number of Instructions Simulated +system.cpu.cpi 6.915755 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.915755 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144597 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144597 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 557431991 # number of integer regfile reads +system.cpu.int_regfile_writes 89182975 # number of integer regfile writes +system.cpu.fp_regfile_reads 8912 # number of floating regfile reads +system.cpu.fp_regfile_writes 2994 # number of floating regfile writes +system.cpu.misc_regfile_reads 135303561 # number of misc regfile reads +system.cpu.misc_regfile_writes 912352 # number of misc regfile writes +system.cpu.icache.replacements 1013837 # number of replacements +system.cpu.icache.tagsinuse 511.616166 # Cycle average of tags in use +system.cpu.icache.total_refs 12585526 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1014349 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.407491 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6289783000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.616166 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999250 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999250 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12585526 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12585526 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12585526 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12585526 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12585526 # number of overall hits +system.cpu.icache.overall_hits::total 12585526 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1106194 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1106194 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1106194 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1106194 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1106194 # number of overall misses +system.cpu.icache.overall_misses::total 1106194 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16291440480 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16291440480 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16291440480 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16291440480 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16291440480 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16291440480 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13691720 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13691720 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13691720 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13691720 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13691720 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13691720 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080793 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.080793 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.080793 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14727.471384 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3199983 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 405 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 416 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7287.609877 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7692.266827 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 58719 # number of writebacks -system.cpu.icache.writebacks::total 58719 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90611 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 90611 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 90611 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 90611 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 90611 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 90611 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1017425 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1017425 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1017425 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1017425 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1017425 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1017425 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12153604482 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12153604482 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12153604482 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12153604482 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12153604482 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12153604482 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7398500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7398500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7398500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7398500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11945.454930 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 59844 # number of writebacks +system.cpu.icache.writebacks::total 59844 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91810 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 91810 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 91810 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 91810 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 91810 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 91810 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1014384 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1014384 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1014384 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1014384 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1014384 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1014384 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12127535483 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12127535483 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12127535483 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12127535483 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12127535483 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12127535483 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11955.566613 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11955.566613 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11955.566613 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644925 # number of replacements -system.cpu.dcache.tagsinuse 511.991557 # Cycle average of tags in use -system.cpu.dcache.total_refs 21957407 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645437 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.019443 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 49249000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991557 # Average occupied blocks per requestor +system.cpu.dcache.replacements 645435 # number of replacements +system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use +system.cpu.dcache.total_refs 22022963 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645947 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.094071 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 14117520 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14117520 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7264910 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7264910 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 285961 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 285961 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285492 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285492 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21382430 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21382430 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21382430 # number of overall hits -system.cpu.dcache.overall_hits::total 21382430 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 735373 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 735373 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2966010 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966010 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13726 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13726 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3701383 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3701383 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3701383 # number of overall misses -system.cpu.dcache.overall_misses::total 3701383 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11086457500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11086457500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110422837752 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110422837752 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223704000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 223704000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 187500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 187500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121509295252 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121509295252 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121509295252 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121509295252 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14852893 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14852893 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10230920 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10230920 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299687 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 299687 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285500 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285500 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 25083813 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25083813 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 25083813 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25083813 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049510 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289906 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045801 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000028 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.147561 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.147561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15075.964850 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37229.421935 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.828938 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 23437.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16342936 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7612500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2868 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5698.373780 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 28404.850746 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 14182326 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14182326 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7265741 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7265741 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 285851 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 285851 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285519 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285519 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21448067 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21448067 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21448067 # number of overall hits +system.cpu.dcache.overall_hits::total 21448067 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 745935 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 745935 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2965804 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2965804 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13758 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13758 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 10 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3711739 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3711739 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3711739 # number of overall misses +system.cpu.dcache.overall_misses::total 3711739 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11230893500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11230893500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110142219264 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110142219264 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224423500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224423500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 267500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 267500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121373112764 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121373112764 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121373112764 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121373112764 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14928261 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14928261 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10231545 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10231545 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 299609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285529 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285529 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 25159806 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 25159806 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 25159806 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 25159806 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049968 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289869 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045920 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000035 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.147527 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.147527 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15056.128885 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37137.389815 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16312.218346 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16852944 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7563500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2993 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 267 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5630.786502 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28327.715356 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 574454 # number of writebacks -system.cpu.dcache.writebacks::total 574454 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 348401 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 348401 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716534 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2716534 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1379 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1379 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064935 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064935 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064935 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064935 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386972 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386972 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249476 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249476 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12347 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12347 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636448 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636448 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636448 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636448 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265104500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265104500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8925107436 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8925107436 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165722000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165722000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14190211936 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14190211936 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14190211936 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14190211936 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147157757000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147157757000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42274928970 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42274928970 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189432685970 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189432685970 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026054 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041200 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.905595 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35775.415014 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13422.045841 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 575111 # number of writebacks +system.cpu.dcache.writebacks::total 575111 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358347 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 358347 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716460 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2716460 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1395 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1395 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3074807 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3074807 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3074807 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3074807 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387588 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387588 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249344 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249344 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12363 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12363 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636932 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636932 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636932 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636932 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5281773000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5281773000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8909514444 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8909514444 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 166180500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 166180500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 235000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 235000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191287444 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14191287444 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191287444 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14191287444 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159264500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159264500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42252638495 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42252638495 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189411902995 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189411902995 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025963 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041264 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13627.287223 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35731.818067 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13441.761708 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency @@ -868,14 +868,14 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307788731818 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307788731818 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1296055922339 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1296055922339 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 87981 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index ab2042d3e..54fc0a20c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -962,7 +962,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -1056,7 +1056,7 @@ port=system.membus.master[2] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -1296,13 +1296,16 @@ proc_id1=201327138 system=system pio=system.iobus.master[1] -[system.realview.rtc_fake] -type=AmbaFake -amba_id=266289 -ignore_access=false +[system.realview.rtc] +type=PL031 +amba_id=3412017 +gic=system.realview.gic +int_delay=100000 +int_num=42 pio_addr=268529664 pio_latency=1000 system=system +time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] [system.realview.sci_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 231285393..b8d0cb88a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,15 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:49:08 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 18:22:04 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -The currently selected ARM platforms doesn't support - the amount of DRAM you've selected. Please try - another platform Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2572151538500 because m5_exit instruction encountered +Exiting @ tick 2570828403500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 3baa592c1..c5e5a6be8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.572152 # Number of seconds simulated -sim_ticks 2572151538500 # Number of ticks simulated -final_tick 2572151538500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.570828 # Number of seconds simulated +sim_ticks 2570828403500 # Number of ticks simulated +final_tick 2570828403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81031 # Simulator instruction rate (inst/s) -host_op_rate 104662 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3370719075 # Simulator tick rate (ticks/s) -host_mem_usage 387768 # Number of bytes of host memory used -host_seconds 763.09 # Real time elapsed on the host -sim_insts 61833482 # Number of instructions simulated -sim_ops 79866272 # Number of ops (including micro ops) simulated +host_inst_rate 96885 # Simulator instruction rate (inst/s) +host_op_rate 125154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4026902595 # Simulator tick rate (ticks/s) +host_mem_usage 385208 # Number of bytes of host memory used +host_seconds 638.41 # Real time elapsed on the host +sim_insts 61852501 # Number of instructions simulated +sim_ops 79899751 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,249 +20,249 @@ system.realview.nvmem.num_other 0 # Nu system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 131401380 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1182400 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10205328 # Number of bytes written to this memory -system.physmem.num_reads 15127677 # Number of read requests responded to by this memory -system.physmem.num_writes 869412 # Number of write requests responded to by this memory +system.physmem.bytes_read 131418468 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1192320 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10172560 # Number of bytes written to this memory +system.physmem.num_reads 15127944 # Number of read requests responded to by this memory +system.physmem.num_writes 868900 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51086174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 459693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3967623 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55053797 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 130950 # number of replacements -system.l2c.tagsinuse 27519.569663 # Cycle average of tags in use -system.l2c.total_refs 1851108 # Total number of references to valid blocks. -system.l2c.sampled_refs 160575 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.527996 # Average number of references to valid blocks. +system.physmem.bw_read 51119113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 463788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3956919 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 55076032 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 130877 # number of replacements +system.l2c.tagsinuse 27573.095607 # Cycle average of tags in use +system.l2c.total_refs 1846037 # Total number of references to valid blocks. +system.l2c.sampled_refs 160860 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.476047 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 15169.344330 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 19.734111 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.051736 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2916.125169 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 1448.526960 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 25.001568 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.040261 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3299.000824 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4641.744705 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.231466 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000301 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.044497 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.022103 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000381 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.050339 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.070827 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.419915 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 54633 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5368 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 354592 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 139013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 116525 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6709 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 686591 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 224265 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1587696 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 603288 # number of Writeback hits -system.l2c.Writeback_hits::total 603288 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 917 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 938 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1855 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 350 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 564 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 36690 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 64535 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 101225 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 54633 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5368 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 354592 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 175703 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 116525 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6709 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 686591 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 288800 # number of demand (read+write) hits -system.l2c.demand_hits::total 1688921 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 54633 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5368 # number of overall hits -system.l2c.overall_hits::cpu0.inst 354592 # number of overall hits -system.l2c.overall_hits::cpu0.data 175703 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 116525 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6709 # number of overall hits -system.l2c.overall_hits::cpu1.inst 686591 # number of overall hits -system.l2c.overall_hits::cpu1.data 288800 # number of overall hits -system.l2c.overall_hits::total 1688921 # number of overall hits +system.l2c.occ_blocks::writebacks 15182.704930 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 18.055930 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.023183 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2139.633455 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 1078.266225 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 23.228189 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.012320 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4084.926228 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5046.245146 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.231670 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000276 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.032648 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.016453 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000354 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.062331 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.077000 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.420732 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 49525 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7421 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 332040 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 132891 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 112998 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7553 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 699861 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 231630 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1573919 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 605876 # number of Writeback hits +system.l2c.Writeback_hits::total 605876 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 897 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1121 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2018 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 196 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 382 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 578 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 35379 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 65973 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 101352 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 49525 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7421 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 332040 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 168270 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 112998 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7553 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 699861 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 297603 # number of demand (read+write) hits +system.l2c.demand_hits::total 1675271 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 49525 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7421 # number of overall hits +system.l2c.overall_hits::cpu0.inst 332040 # number of overall hits +system.l2c.overall_hits::cpu0.data 168270 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 112998 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7553 # number of overall hits +system.l2c.overall_hits::cpu1.inst 699861 # number of overall hits +system.l2c.overall_hits::cpu1.data 297603 # number of overall hits +system.l2c.overall_hits::total 1675271 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 81 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 9406 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9212 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 53 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 8899 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 12145 # number of ReadReq misses -system.l2c.ReadReq_misses::total 39808 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5322 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5511 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10833 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 766 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 527 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1293 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 66272 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 81260 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147532 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 8347 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8839 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 55 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 10114 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 12836 # number of ReadReq misses +system.l2c.ReadReq_misses::total 40278 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5127 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5687 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 10814 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 762 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 599 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1361 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 65841 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 81581 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 147422 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 81 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 9406 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 75484 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 53 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 8899 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 93405 # number of demand (read+write) misses -system.l2c.demand_misses::total 187340 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 8347 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 74680 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 55 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 10114 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 94417 # number of demand (read+write) misses +system.l2c.demand_misses::total 187700 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 81 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 9406 # number of overall misses -system.l2c.overall_misses::cpu0.data 75484 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 53 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu1.inst 8899 # number of overall misses -system.l2c.overall_misses::cpu1.data 93405 # number of overall misses -system.l2c.overall_misses::total 187340 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 4223500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 8347 # number of overall misses +system.l2c.overall_misses::cpu0.data 74680 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 55 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 10114 # number of overall misses +system.l2c.overall_misses::cpu1.data 94417 # number of overall misses +system.l2c.overall_misses::total 187700 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 4226000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 261000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 491867500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 480714000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2767000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 364500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 465541000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 634495500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2080234000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 18082000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 37415000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 55497000 # number of UpgradeReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 436472500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 461376000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2870500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 52000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 529146500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 670533000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2104937500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 17145500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 38360500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 55506000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1985000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5173000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 7158000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3474814999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4268858500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7743673499 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 4223500 # number of demand (read+write) miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5435500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 7420500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3452457999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4285420500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7737878499 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 4226000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 261000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 491867500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3955528999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 2767000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 364500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 465541000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4903354000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9823907499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 4223500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 436472500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3913833999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 2870500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 52000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 529146500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4955953500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9842815999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 4226000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 261000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 491867500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3955528999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 2767000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 364500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 465541000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4903354000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9823907499 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 54714 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 5373 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 363998 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 148225 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 116578 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6716 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 695490 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 236410 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1627504 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 603288 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 603288 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6239 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 6449 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 12688 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 980 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 877 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1857 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 102962 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 145795 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 248757 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 54714 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5373 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 363998 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 251187 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 116578 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6716 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 695490 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 382205 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1876261 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 54714 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5373 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 363998 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 251187 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 116578 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6716 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 695490 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 382205 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1876261 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001480 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000931 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.025841 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.062149 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.001042 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.012795 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.051373 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.853021 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.854551 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.781633 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.600912 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.643655 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.557358 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001480 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000931 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.025841 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.300509 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.001042 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.012795 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.244385 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001480 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000931 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.025841 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.300509 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000455 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.001042 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.012795 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.244385 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52141.975309 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 436472500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3913833999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 2870500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 52000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 529146500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4955953500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9842815999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 49606 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7426 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 340387 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 141730 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 113053 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7554 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 709975 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 244466 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1614197 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 605876 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 605876 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6024 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 6808 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 12832 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 958 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 981 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1939 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 101220 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 147554 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 248774 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 49606 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7426 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 340387 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 242950 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 113053 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7554 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 709975 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 392020 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1862971 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 49606 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7426 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 340387 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 242950 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 113053 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7554 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 709975 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 392020 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1862971 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001633 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000673 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.024522 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.062365 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000486 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000132 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014246 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.052506 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.851096 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835341 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.795407 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.610601 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.650474 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.552889 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001633 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000673 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.024522 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.307388 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000486 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000132 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014246 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.240847 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001633 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000673 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.024522 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.307388 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000486 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000132 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014246 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.240847 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52172.839506 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52200 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52292.951308 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52183.456361 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52207.547170 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52071.428571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52313.855489 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52243.351173 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3397.594889 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6789.148975 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2591.383812 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9815.939279 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52432.626132 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52533.331282 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52141.975309 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52290.942854 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52197.759928 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52190.909091 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52318.222266 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52238.469928 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3344.158377 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6745.296290 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2604.986877 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9074.290484 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52436.293480 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52529.639254 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52172.839506 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52292.951308 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52402.217675 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52207.547170 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52071.428571 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52313.855489 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52495.626572 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52141.975309 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52290.942854 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52408.061047 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52190.909091 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52318.222266 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52490.054757 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52172.839506 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52292.951308 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52402.217675 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52207.547170 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52071.428571 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52313.855489 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52495.626572 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52290.942854 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52408.061047 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52190.909091 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52318.222266 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52490.054757 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -271,168 +271,168 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 112128 # number of writebacks -system.l2c.writebacks::total 112128 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 51 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 13 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 32 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 51 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 32 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 98 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 51 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 32 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 98 # number of overall MSHR hits +system.l2c.writebacks::writebacks 111616 # number of writebacks +system.l2c.writebacks::total 111616 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 42 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 35 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 42 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 35 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 42 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 35 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 91 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 81 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 9404 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 9161 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 53 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 8886 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 12113 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 39710 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5322 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 5511 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 10833 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 766 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 527 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1293 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 66272 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 81260 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 147532 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 8343 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8797 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 55 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 10104 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 12801 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 40187 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5127 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 5687 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 10814 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 762 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 599 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1361 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 65841 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 81581 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 147422 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 81 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 9404 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 75433 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 53 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 7 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 8886 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 93373 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 187242 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 8343 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 74638 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 55 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 10104 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 94382 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 187609 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 81 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 9404 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 75433 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 53 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 7 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 8886 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 93373 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 187242 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3242500 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 8343 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 74638 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 55 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 10104 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 94382 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 187609 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3244000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 201000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 376846000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 366960000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2126500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 356559500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 485221000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1591436500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 213132000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 220571000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 433703000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 30672000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21105000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 51777000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2653014999 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3258420500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5911435499 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3242500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 334368500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 352448500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2202500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 40000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 405321000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 512811000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1610636500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 205370000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 227611500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 432981500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 30499500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23997000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 54496500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2635763499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3271199500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5906962999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3244000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 201000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 376846000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3019974999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2126500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 280000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 356559500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3743641500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7502871999 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3242500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 334368500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2988211999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2202500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 40000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 405321000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3784010500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7517599499 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3244000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 201000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 376846000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3019974999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2126500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 280000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 356559500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3743641500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7502871999 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5748500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8468888000 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 334368500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2988211999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2202500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 40000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 405321000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3784010500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7517599499 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5668500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8247511500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1931000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123493861000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131970428500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 744865480 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31777562693 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32522428173 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5748500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9213753480 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123718931000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131974042000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 707206480 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31817900108 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32525106588 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5668500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8954717980 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1931000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155271423693 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164492856673 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.061805 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051237 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.853021 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.854551 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.781633 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.600912 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.643655 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.557358 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.300306 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244301 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001480 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000931 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.025835 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.300306 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000455 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.001042 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012777 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244301 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155536831108 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164499148588 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001633 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000673 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.024510 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.062069 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000486 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014231 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.052363 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.851096 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835341 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.795407 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.610601 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.650474 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.552889 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001633 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000673 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.024510 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.307215 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014231 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.240758 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001633 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000673 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.024510 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.307215 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000132 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014231 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.240758 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40049.382716 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40056.762362 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40064.624304 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40057.871708 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.350620 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.770641 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.775457 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40047.438330 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.215702 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40098.701698 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40060.229670 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40056.563292 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40023.122912 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40025.590551 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.769616 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.251925 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40097.565610 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40049.382716 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40035.196784 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40036.067405 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40093.404946 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40030.864198 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.501748 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40049.382716 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40072.947682 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40035.196784 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40122.641509 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40077.729833 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40036.067405 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40045.454545 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40125.984695 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40093.404946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40114.904988 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.501748 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -452,27 +452,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7779192 # DTB read hits -system.cpu0.dtb.read_misses 37115 # DTB read misses -system.cpu0.dtb.write_hits 4594295 # DTB write hits -system.cpu0.dtb.write_misses 6419 # DTB write misses +system.cpu0.dtb.read_hits 7527759 # DTB read hits +system.cpu0.dtb.read_misses 31435 # DTB read misses +system.cpu0.dtb.write_hits 4435696 # DTB write hits +system.cpu0.dtb.write_misses 6033 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2014 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 4597 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2072 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 4328 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 228 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 800 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7816307 # DTB read accesses -system.cpu0.dtb.write_accesses 4600714 # DTB write accesses +system.cpu0.dtb.perms_faults 803 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7559194 # DTB read accesses +system.cpu0.dtb.write_accesses 4441729 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12373487 # DTB hits -system.cpu0.dtb.misses 43534 # DTB misses -system.cpu0.dtb.accesses 12417021 # DTB accesses -system.cpu0.itb.inst_hits 4018220 # ITB inst hits -system.cpu0.itb.inst_misses 4575 # ITB inst misses +system.cpu0.dtb.hits 11963455 # DTB hits +system.cpu0.dtb.misses 37468 # DTB misses +system.cpu0.dtb.accesses 12000923 # DTB accesses +system.cpu0.itb.inst_hits 3809486 # ITB inst hits +system.cpu0.itb.inst_misses 6280 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -481,531 +481,531 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1380 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1835 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1824 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4022795 # ITB inst accesses -system.cpu0.itb.hits 4018220 # DTB hits -system.cpu0.itb.misses 4575 # DTB misses -system.cpu0.itb.accesses 4022795 # DTB accesses -system.cpu0.numCycles 58073431 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 3815766 # ITB inst accesses +system.cpu0.itb.hits 3809486 # DTB hits +system.cpu0.itb.misses 6280 # DTB misses +system.cpu0.itb.accesses 3815766 # DTB accesses +system.cpu0.numCycles 55441069 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 5437293 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4256353 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 316271 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3600228 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2674120 # Number of BTB hits +system.cpu0.BPredUnit.lookups 5212892 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 3951494 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 295394 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3415998 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2549557 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 485080 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 65250 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 11048158 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 28487074 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5437293 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3159200 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 6739880 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1438397 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 59633 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 18694595 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 6724 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 30266 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 80153 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 218 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4016097 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 175657 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3180 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 37672027 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.986348 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.372863 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 460779 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 62243 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 10453565 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 27421447 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5212892 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3010336 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 6440117 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1388454 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 65669 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 17512846 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 6544 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 31892 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 74131 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 3807333 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 161414 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 4002 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 35574590 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004938 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.398361 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30938102 82.12% 82.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 539295 1.43% 83.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 754456 2.00% 85.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 605374 1.61% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 572205 1.52% 88.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 499727 1.33% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 619840 1.65% 91.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 357335 0.95% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2785693 7.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 29140690 81.91% 81.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 530074 1.49% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 686036 1.93% 85.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 575113 1.62% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 516761 1.45% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 484002 1.36% 89.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 574923 1.62% 91.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 349762 0.98% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2717229 7.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 37672027 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.093628 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.490535 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 11376766 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18792478 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6048489 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 500890 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 953404 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 867804 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 60437 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 35787038 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 193524 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 953404 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 11914000 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 4629145 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12457249 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6001220 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1717009 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 34527596 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 766 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 354930 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 888723 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 49 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 34587688 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 157020073 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 156979210 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 40863 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 26885692 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7701996 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 453005 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 414730 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4495926 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 6704710 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5162827 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 858153 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 869893 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 32576471 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 727676 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 32778157 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81649 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5740307 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13396786 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 126207 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 37672027 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.870093 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.506550 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 35574590 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.094026 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.494605 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 10814757 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 17563508 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 5782354 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 479006 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 934965 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 835529 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 55823 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 34470555 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 179479 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 934965 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 11326555 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 4595002 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 11316835 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 5729017 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1672216 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 33303546 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 955 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 363738 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 882856 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 34 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 33389165 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 151283000 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 151242578 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 40422 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 25698465 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7690700 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 390539 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 354252 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4298434 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6455423 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4976732 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 849969 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 853540 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 31433505 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 659467 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 31580110 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81056 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5706071 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 12925708 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 117932 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 35574590 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.887715 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519071 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 24340985 64.61% 64.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5232872 13.89% 78.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2696429 7.16% 85.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2005933 5.32% 90.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1857666 4.93% 95.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 789251 2.10% 98.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 535159 1.42% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 163101 0.43% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 50631 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 22796169 64.08% 64.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4955890 13.93% 78.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2593205 7.29% 85.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 1941493 5.46% 90.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1799462 5.06% 95.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 771833 2.17% 97.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 508602 1.43% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 158782 0.45% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 49154 0.14% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 37672027 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 35574590 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 17215 1.80% 1.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 476 0.05% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 744103 77.93% 79.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 193089 20.22% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 35384 3.74% 3.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 453 0.05% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 728574 76.99% 80.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 181906 19.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14281 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 19588840 59.76% 59.81% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 43482 0.13% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 8 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1004 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.94% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8219170 25.08% 85.02% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4911355 14.98% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14281 0.05% 0.05% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 18843805 59.67% 59.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 42255 0.13% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 7 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 650 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.85% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7938571 25.14% 84.99% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4740521 15.01% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 32778157 # Type of FU issued -system.cpu0.iq.rate 0.564426 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 954883 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.029132 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 104296789 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 39048181 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 30070598 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 10781 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5570 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4438 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 33712886 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5873 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 258573 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 31580110 # Type of FU issued +system.cpu0.iq.rate 0.569616 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 946317 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.029966 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 99788129 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 37802639 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 28957807 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 10678 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5536 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4399 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 32506335 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5811 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 253441 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1274599 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3983 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 9698 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 554608 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1254358 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3684 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 9621 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 525059 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1948828 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5242 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1901492 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5043 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 953404 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 3530697 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 77233 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 33359153 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 131395 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 6704710 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5162827 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 457179 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 36756 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4503 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 9698 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 188494 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 122646 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 311140 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 32365577 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8053232 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 412580 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 934965 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 3498549 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 78984 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 32152208 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 119958 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 6455423 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 4976732 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 398786 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 38665 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4398 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 9621 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 177464 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 119524 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 296988 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 31195619 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7789216 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 384491 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 55006 # number of nop insts executed -system.cpu0.iew.exec_refs 12911062 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4264405 # Number of branches executed -system.cpu0.iew.exec_stores 4857830 # Number of stores executed -system.cpu0.iew.exec_rate 0.557322 # Inst execution rate -system.cpu0.iew.wb_sent 32156724 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 30075036 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 16051487 # num instructions producing a value -system.cpu0.iew.wb_consumers 31416706 # num instructions consuming a value +system.cpu0.iew.exec_nop 59236 # number of nop insts executed +system.cpu0.iew.exec_refs 12477007 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4073990 # Number of branches executed +system.cpu0.iew.exec_stores 4687791 # Number of stores executed +system.cpu0.iew.exec_rate 0.562681 # Inst execution rate +system.cpu0.iew.wb_sent 30989414 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 28962206 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 15536163 # num instructions producing a value +system.cpu0.iew.wb_consumers 30480637 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.517879 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.510922 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.522396 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.509706 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 20629701 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 27347563 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 5860569 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 601469 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 274713 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 36749403 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.744163 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.705264 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 19711221 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 26183930 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 5818378 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 541535 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 256688 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 34668404 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.755268 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.722296 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 26406070 71.85% 71.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5210331 14.18% 86.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1671532 4.55% 90.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 813872 2.21% 92.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 646917 1.76% 94.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 387096 1.05% 95.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 442946 1.21% 96.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 193384 0.53% 97.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 977255 2.66% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 24842291 71.66% 71.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 4903680 14.14% 85.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1598724 4.61% 90.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 790644 2.28% 92.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 613460 1.77% 94.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 370313 1.07% 95.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 401864 1.16% 96.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 185143 0.53% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 962285 2.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 36749403 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 20629701 # Number of instructions committed -system.cpu0.commit.committedOps 27347563 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 34668404 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 19711221 # Number of instructions committed +system.cpu0.commit.committedOps 26183930 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10038330 # Number of memory references committed -system.cpu0.commit.loads 5430111 # Number of loads committed -system.cpu0.commit.membars 201113 # Number of memory barriers committed -system.cpu0.commit.branches 3777893 # Number of branches committed +system.cpu0.commit.refs 9652738 # Number of memory references committed +system.cpu0.commit.loads 5201065 # Number of loads committed +system.cpu0.commit.membars 194494 # Number of memory barriers committed +system.cpu0.commit.branches 3582933 # Number of branches committed system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 24270810 # Number of committed integer instructions. -system.cpu0.commit.function_calls 441070 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 977255 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 23269679 # Number of committed integer instructions. +system.cpu0.commit.function_calls 421897 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 962285 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 68333926 # The number of ROB reads -system.cpu0.rob.rob_writes 67371686 # The number of ROB writes -system.cpu0.timesIdled 379272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 20401404 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5085475083 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 20605147 # Number of Instructions Simulated -system.cpu0.committedOps 27323009 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 20605147 # Number of Instructions Simulated -system.cpu0.cpi 2.818394 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.818394 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.354812 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.354812 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 150871425 # number of integer regfile reads -system.cpu0.int_regfile_writes 29495246 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4612 # number of floating regfile reads -system.cpu0.fp_regfile_writes 442 # number of floating regfile writes -system.cpu0.misc_regfile_reads 40364553 # number of misc regfile reads -system.cpu0.misc_regfile_writes 457015 # number of misc regfile writes -system.cpu0.icache.replacements 364779 # number of replacements -system.cpu0.icache.tagsinuse 511.052726 # Cycle average of tags in use -system.cpu0.icache.total_refs 3619396 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 365291 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.908254 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6333280000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.052726 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998150 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998150 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3619396 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3619396 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3619396 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3619396 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3619396 # number of overall hits -system.cpu0.icache.overall_hits::total 3619396 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 396554 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 396554 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 396554 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 396554 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 396554 # number of overall misses -system.cpu0.icache.overall_misses::total 396554 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6048062987 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6048062987 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6048062987 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6048062987 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6048062987 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6048062987 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4015950 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4015950 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4015950 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4015950 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4015950 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4015950 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.098745 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.098745 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.098745 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15251.549567 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15251.549567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15251.549567 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1568990 # number of cycles access was blocked +system.cpu0.rob.rob_reads 65094034 # The number of ROB reads +system.cpu0.rob.rob_writes 64941259 # The number of ROB writes +system.cpu0.timesIdled 360737 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 19866479 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5085563503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 19686667 # Number of Instructions Simulated +system.cpu0.committedOps 26159376 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 19686667 # Number of Instructions Simulated +system.cpu0.cpi 2.816173 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.816173 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.355092 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.355092 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 145393582 # number of integer regfile reads +system.cpu0.int_regfile_writes 28417758 # number of integer regfile writes +system.cpu0.fp_regfile_reads 4580 # number of floating regfile reads +system.cpu0.fp_regfile_writes 450 # number of floating regfile writes +system.cpu0.misc_regfile_reads 38939704 # number of misc regfile reads +system.cpu0.misc_regfile_writes 443716 # number of misc regfile writes +system.cpu0.icache.replacements 341473 # number of replacements +system.cpu0.icache.tagsinuse 511.631456 # Cycle average of tags in use +system.cpu0.icache.total_refs 3435816 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 341985 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 10.046686 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6333594000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.631456 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999280 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999280 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3435816 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3435816 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3435816 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3435816 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3435816 # number of overall hits +system.cpu0.icache.overall_hits::total 3435816 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 371369 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 371369 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 371369 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 371369 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 371369 # number of overall misses +system.cpu0.icache.overall_misses::total 371369 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5641865987 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5641865987 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5641865987 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5641865987 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5641865987 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5641865987 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 3807185 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 3807185 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 3807185 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 3807185 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 3807185 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 3807185 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097544 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097544 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097544 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15192.075771 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15192.075771 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1691991 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 211 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 206 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7435.971564 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8213.548544 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 18696 # number of writebacks -system.cpu0.icache.writebacks::total 18696 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31138 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31138 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31138 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31138 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31138 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31138 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 365416 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 365416 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 365416 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 365416 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 365416 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 365416 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4532086990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4532086990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4532086990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4532086990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4532086990 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4532086990 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7723000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7723000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7723000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7723000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090991 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090991 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090991 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12402.541186 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12402.541186 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12402.541186 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 19233 # number of writebacks +system.cpu0.icache.writebacks::total 19233 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 29370 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 29370 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 29370 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 29370 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 29370 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 29370 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 341999 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 341999 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 341999 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 341999 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 341999 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 341999 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4224982491 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4224982491 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4224982491 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4224982491 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4224982491 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4224982491 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7615500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089830 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12353.786096 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 240620 # number of replacements -system.cpu0.dcache.tagsinuse 465.804609 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8050384 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 241002 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.403806 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 49733000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 465.804609 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.909775 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.909775 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4986735 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 4986735 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2710782 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2710782 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 158772 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 158772 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 156309 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 156309 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7697517 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7697517 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7697517 # number of overall hits -system.cpu0.dcache.overall_hits::total 7697517 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 337926 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 337926 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1466374 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1466374 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8662 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8662 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7736 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7736 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1804300 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1804300 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1804300 # number of overall misses -system.cpu0.dcache.overall_misses::total 1804300 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4785519500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4785519500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60142300903 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60142300903 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99268000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 99268000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83415000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 83415000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 64927820403 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 64927820403 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 64927820403 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 64927820403 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5324661 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5324661 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4177156 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4177156 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167434 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 167434 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 164045 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 164045 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9501817 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9501817 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9501817 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9501817 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063464 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351046 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051734 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047158 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.189890 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.189890 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14161.442150 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41014.298469 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11460.170861 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10782.704240 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35985.047056 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35985.047056 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4268990 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2272500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 373 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 104 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11445.013405 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21850.961538 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 231957 # number of replacements +system.cpu0.dcache.tagsinuse 430.483417 # Cycle average of tags in use +system.cpu0.dcache.total_refs 7734943 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 232325 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.293632 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 49672000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 430.483417 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.840788 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.840788 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 4799900 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 4799900 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 2590245 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2590245 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154697 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 154697 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152346 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 152346 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7390145 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 7390145 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7390145 # number of overall hits +system.cpu0.dcache.overall_hits::total 7390145 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 331500 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 331500 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1445399 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1445399 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8824 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8824 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7928 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7928 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1776899 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1776899 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1776899 # number of overall misses +system.cpu0.dcache.overall_misses::total 1776899 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4661132500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4661132500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59622143898 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 59622143898 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 99172000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 99172000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83748000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 83748000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 64283276398 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 64283276398 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 64283276398 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 64283276398 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5131400 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5131400 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4035644 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4035644 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163521 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 163521 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160274 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 160274 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9167044 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9167044 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9167044 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9167044 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064602 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.358158 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053962 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049465 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193836 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193836 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14060.731523 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41249.609207 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11238.893926 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10563.572149 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36177.225829 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36177.225829 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3382986 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2017500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 334 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 95 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10128.700599 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21236.842105 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 213485 # number of writebacks -system.cpu0.dcache.writebacks::total 213485 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 174573 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 174573 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1346571 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1346571 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 614 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1521144 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1521144 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1521144 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1521144 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 163353 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 163353 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119803 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 119803 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8048 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8048 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7735 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7735 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 283156 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 283156 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 283156 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 283156 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2116822500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2116822500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4307053989 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4307053989 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66689500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66689500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60159000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60159000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6423876489 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6423876489 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6423876489 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6423876489 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9482121000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9482121000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 884869891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 884869891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10366990891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10366990891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030679 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028681 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048067 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047152 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029800 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029800 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12958.577437 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35951.136357 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8286.468688 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7777.504848 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22686.704463 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22686.704463 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 207854 # number of writebacks +system.cpu0.dcache.writebacks::total 207854 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 173784 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 173784 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1326908 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1326908 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 637 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 637 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1500692 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1500692 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1500692 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1500692 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 157716 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 157716 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 118491 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 118491 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8187 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8187 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7924 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7924 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 276207 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 276207 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 276207 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 276207 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2028922000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2028922000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4262146485 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4262146485 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66363000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66363000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 59926500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 59926500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6291068485 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6291068485 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6291068485 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6291068485 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9234849500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9234849500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 843734891 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843734891 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10078584391 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10078584391 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030735 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029361 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050067 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049440 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030130 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030130 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12864.401836 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35970.212801 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8105.899597 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7562.657749 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22776.643912 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22776.643912 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 44907962 # DTB read hits -system.cpu1.dtb.read_misses 73330 # DTB read misses -system.cpu1.dtb.write_hits 7780018 # DTB write hits -system.cpu1.dtb.write_misses 20100 # DTB write misses +system.cpu1.dtb.read_hits 45296976 # DTB read hits +system.cpu1.dtb.read_misses 68040 # DTB read misses +system.cpu1.dtb.write_hits 7958541 # DTB write hits +system.cpu1.dtb.write_misses 20787 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2652 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 7203 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 561 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2725 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 7868 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 603 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 1824 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 44981292 # DTB read accesses -system.cpu1.dtb.write_accesses 7800118 # DTB write accesses +system.cpu1.dtb.perms_faults 1726 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 45365016 # DTB read accesses +system.cpu1.dtb.write_accesses 7979328 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 52687980 # DTB hits -system.cpu1.dtb.misses 93430 # DTB misses -system.cpu1.dtb.accesses 52781410 # DTB accesses -system.cpu1.itb.inst_hits 10156376 # ITB inst hits -system.cpu1.itb.inst_misses 7457 # ITB inst misses +system.cpu1.dtb.hits 53255517 # DTB hits +system.cpu1.dtb.misses 88827 # DTB misses +system.cpu1.dtb.accesses 53344344 # DTB accesses +system.cpu1.itb.inst_hits 10421118 # ITB inst hits +system.cpu1.itb.inst_misses 7923 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1014,507 +1014,507 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1545 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1559 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 5007 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 4993 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10163833 # ITB inst accesses -system.cpu1.itb.hits 10156376 # DTB hits -system.cpu1.itb.misses 7457 # DTB misses -system.cpu1.itb.accesses 10163833 # DTB accesses -system.cpu1.numCycles 361463197 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10429041 # ITB inst accesses +system.cpu1.itb.hits 10421118 # DTB hits +system.cpu1.itb.misses 7923 # DTB misses +system.cpu1.itb.accesses 10429041 # DTB accesses +system.cpu1.numCycles 361284565 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 10782508 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 8772381 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 635923 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7402063 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5909244 # Number of BTB hits +system.cpu1.BPredUnit.lookups 11160075 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 8957573 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 655963 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7602711 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 6100291 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 873700 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 139717 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 23605299 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 77286787 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 10782508 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6782944 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 16557542 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 5336622 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 96051 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 76350866 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 106359 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 159348 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 263 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 10151102 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 836280 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 4015 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 120517405 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.782275 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.157111 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 909624 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 143125 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 24152579 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 79243321 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 11160075 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 7009915 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 17005367 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 5503080 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 106407 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 74478012 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 116210 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 165404 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10415863 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 850791 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 4371 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 119805091 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.807068 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.185605 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 103969658 86.27% 86.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 987113 0.82% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1198247 0.99% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2181121 1.81% 89.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1404675 1.17% 91.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 731318 0.61% 91.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2384511 1.98% 93.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 517678 0.43% 94.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 7143084 5.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 102809911 85.81% 85.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 1026487 0.86% 86.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1244623 1.04% 87.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2220450 1.85% 89.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1447523 1.21% 90.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 762352 0.64% 91.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2446430 2.04% 93.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 545220 0.46% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 7302095 6.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 120517405 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.029830 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.213816 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 25233877 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76283550 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 14821072 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 657863 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3521043 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1494975 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 117774 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 87693964 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 382895 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3521043 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 26831414 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32478721 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 39236731 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 13889721 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4559775 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 81167341 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2581 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 635823 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3200516 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 46226 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 85740662 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 375398775 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 375349065 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 49710 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 53651640 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 32089021 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 776045 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 700116 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8935980 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15610664 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 9406979 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1201620 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1579608 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 72666150 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1193677 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 96590201 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 142158 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 20735703 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 58926609 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 234264 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 120517405 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.801463 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.526860 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 119805091 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030890 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.219338 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 25854345 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 74385490 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15310008 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 600331 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3654917 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1553748 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 123029 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 89962683 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 400925 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3654917 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 27463225 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32802291 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 37038310 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 14280523 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4565825 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 83469542 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3103 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 679234 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3297923 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 45820 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 88189114 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 385593776 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 385544391 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 49385 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 54868386 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 33320727 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 602216 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 524905 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8650801 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 16023709 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 9632090 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1276299 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1729146 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 74907136 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1031599 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 98321113 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 155877 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 21592981 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 61005208 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 224170 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 119805091 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.820676 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.545860 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 86833748 72.05% 72.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9975019 8.28% 80.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4940804 4.10% 84.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4069487 3.38% 87.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 11024826 9.15% 96.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 2090694 1.73% 98.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1200483 1.00% 99.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 289311 0.24% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 93033 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 85906342 71.71% 71.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9617362 8.03% 79.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 5105765 4.26% 83.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4221138 3.52% 87.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 11132119 9.29% 96.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 2139642 1.79% 98.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1275484 1.06% 99.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 308695 0.26% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 98544 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 120517405 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 119805091 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 40307 0.50% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 997 0.01% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7705811 95.37% 95.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 333073 4.12% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 44454 0.55% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 993 0.01% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7729676 95.36% 95.92% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 330610 4.08% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 92768 0.10% 0.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 42073039 43.56% 43.65% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 68661 0.07% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 25 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 44 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1453 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.73% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 46174618 47.80% 91.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 8179589 8.47% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 92819 0.09% 0.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 43197176 43.93% 44.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 69729 0.07% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 31 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 38 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 4 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1798 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.10% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 46580491 47.38% 91.48% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 8379023 8.52% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 96590201 # Type of FU issued -system.cpu1.iq.rate 0.267220 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 8080188 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.083654 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 322001182 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 94611209 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 59943384 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12160 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6852 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5542 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 104571300 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6321 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 377653 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 98321113 # Type of FU issued +system.cpu1.iq.rate 0.272143 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 8105733 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.082441 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 324785513 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 97548571 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 61562518 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11987 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6778 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5521 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 106327792 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6235 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 430499 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4689619 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6336 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 23311 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1773508 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4865573 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7656 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 24407 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1834498 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 32175805 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1149678 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 32207869 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1151172 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3521043 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25065136 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 359091 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 74029865 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 214492 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15610664 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 9406979 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 810165 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 59786 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 8576 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 23311 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 385716 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 238696 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 624412 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 93721321 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 45339640 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2868880 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3654917 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25274079 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 368524 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 76147540 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 230680 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 16023709 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 9632090 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 636792 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64221 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 8659 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 24407 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 397735 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 243587 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 641322 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 95426692 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 45740593 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2894421 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 170038 # number of nop insts executed -system.cpu1.iew.exec_refs 53422835 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7793526 # Number of branches executed -system.cpu1.iew.exec_stores 8083195 # Number of stores executed -system.cpu1.iew.exec_rate 0.259283 # Inst execution rate -system.cpu1.iew.wb_sent 92395030 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 59948926 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 32815937 # num instructions producing a value -system.cpu1.iew.wb_consumers 59243985 # num instructions consuming a value +system.cpu1.iew.exec_nop 208805 # number of nop insts executed +system.cpu1.iew.exec_refs 54014697 # number of memory reference insts executed +system.cpu1.iew.exec_branches 8051531 # Number of branches executed +system.cpu1.iew.exec_stores 8274104 # Number of stores executed +system.cpu1.iew.exec_rate 0.264132 # Inst execution rate +system.cpu1.iew.wb_sent 94059839 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 61568039 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 33920997 # num instructions producing a value +system.cpu1.iew.wb_consumers 61750617 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.165851 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.553912 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.170414 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.549322 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 41354162 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 52669090 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 21302262 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 959413 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 549125 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 117050265 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.449970 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.406060 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 42291661 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 53866202 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 22216320 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 807429 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 565831 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 116206088 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.463540 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.434749 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 97973751 83.70% 83.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9696174 8.28% 91.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2557084 2.18% 94.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1440070 1.23% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1185226 1.01% 96.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 698819 0.60% 97.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1094067 0.93% 97.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 501455 0.43% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1903619 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 97183761 83.63% 83.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9338835 8.04% 91.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2558958 2.20% 93.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1577703 1.36% 95.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1195507 1.03% 96.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 711645 0.61% 96.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1133703 0.98% 97.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 513937 0.44% 98.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1992039 1.71% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 117050265 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 41354162 # Number of instructions committed -system.cpu1.commit.committedOps 52669090 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 116206088 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 42291661 # Number of instructions committed +system.cpu1.commit.committedOps 53866202 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 18554516 # Number of memory references committed -system.cpu1.commit.loads 10921045 # Number of loads committed -system.cpu1.commit.membars 235754 # Number of memory barriers committed -system.cpu1.commit.branches 6572629 # Number of branches committed +system.cpu1.commit.refs 18955728 # Number of memory references committed +system.cpu1.commit.loads 11158136 # Number of loads committed +system.cpu1.commit.membars 242500 # Number of memory barriers committed +system.cpu1.commit.branches 6770430 # Number of branches committed system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 46931412 # Number of committed integer instructions. -system.cpu1.commit.function_calls 612362 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1903619 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 47963823 # Number of committed integer instructions. +system.cpu1.commit.function_calls 631876 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1992039 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 187930171 # The number of ROB reads -system.cpu1.rob.rob_writes 151588010 # The number of ROB writes -system.cpu1.timesIdled 1544590 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 240945792 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4782780444 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 41228335 # Number of Instructions Simulated -system.cpu1.committedOps 52543263 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 41228335 # Number of Instructions Simulated -system.cpu1.cpi 8.767349 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.767349 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.114060 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.114060 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 421568276 # number of integer regfile reads -system.cpu1.int_regfile_writes 62748878 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4369 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2038 # number of floating regfile writes -system.cpu1.misc_regfile_reads 99504542 # number of misc regfile reads -system.cpu1.misc_regfile_writes 498546 # number of misc regfile writes -system.cpu1.icache.replacements 696735 # number of replacements -system.cpu1.icache.tagsinuse 498.773379 # Cycle average of tags in use -system.cpu1.icache.total_refs 9395224 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 697247 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.474743 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74291126000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.773379 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974167 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974167 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 9395224 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9395224 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9395224 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9395224 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9395224 # number of overall hits -system.cpu1.icache.overall_hits::total 9395224 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 755826 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 755826 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 755826 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 755826 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 755826 # number of overall misses -system.cpu1.icache.overall_misses::total 755826 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11037584991 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11037584991 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11037584991 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11037584991 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11037584991 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11037584991 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10151050 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10151050 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10151050 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10151050 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10151050 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10151050 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074458 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074458 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074458 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14603.341233 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14603.341233 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14603.341233 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1489994 # number of cycles access was blocked +system.cpu1.rob.rob_reads 189074073 # The number of ROB reads +system.cpu1.rob.rob_writes 155943577 # The number of ROB writes +system.cpu1.timesIdled 1562911 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 241479474 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4780310719 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 42165834 # Number of Instructions Simulated +system.cpu1.committedOps 53740375 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 42165834 # Number of Instructions Simulated +system.cpu1.cpi 8.568183 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.568183 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.116711 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.116711 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 429426444 # number of integer regfile reads +system.cpu1.int_regfile_writes 64384425 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4325 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2046 # number of floating regfile writes +system.cpu1.misc_regfile_reads 102104658 # number of misc regfile reads +system.cpu1.misc_regfile_writes 512737 # number of misc regfile writes +system.cpu1.icache.replacements 711552 # number of replacements +system.cpu1.icache.tagsinuse 498.766119 # Cycle average of tags in use +system.cpu1.icache.total_refs 9643450 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 712064 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.542954 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74281042000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.766119 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974153 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974153 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 9643450 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9643450 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9643450 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9643450 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9643450 # number of overall hits +system.cpu1.icache.overall_hits::total 9643450 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 772363 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 772363 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 772363 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 772363 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 772363 # number of overall misses +system.cpu1.icache.overall_misses::total 772363 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11329505492 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 11329505492 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 11329505492 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 11329505492 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11329505492 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11329505492 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10415813 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10415813 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10415813 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10415813 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10415813 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10415813 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074153 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074153 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074153 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.627953 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.627953 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.627953 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1533994 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 235 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 234 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6340.400000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6555.529915 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 33229 # number of writebacks -system.cpu1.icache.writebacks::total 33229 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 58554 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 58554 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 58554 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 58554 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 58554 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 58554 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 697272 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 697272 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 697272 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 697272 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 697272 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 697272 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8249763494 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8249763494 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8249763494 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8249763494 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8249763494 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8249763494 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2572500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068690 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068690 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068690 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11831.485409 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11831.485409 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11831.485409 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 32964 # number of writebacks +system.cpu1.icache.writebacks::total 32964 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 60264 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 60264 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 60264 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 60264 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 60264 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 60264 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 712099 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 712099 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 712099 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 712099 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 712099 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 712099 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8466389994 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8466389994 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8466389994 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8466389994 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8466389994 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8466389994 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2573500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2573500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2573500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2573500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068367 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068367 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068367 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11889.344029 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11889.344029 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11889.344029 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 407382 # number of replacements -system.cpu1.dcache.tagsinuse 452.475492 # Cycle average of tags in use -system.cpu1.dcache.total_refs 14784663 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 407894 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.246336 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 72560362000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 452.475492 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.883741 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.883741 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 9748444 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9748444 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4751218 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4751218 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 123467 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 123467 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 116541 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 116541 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 14499662 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 14499662 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 14499662 # number of overall hits -system.cpu1.dcache.overall_hits::total 14499662 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 454636 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 454636 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1699248 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1699248 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14155 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14155 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10110 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10110 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 2153884 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 2153884 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 2153884 # number of overall misses -system.cpu1.dcache.overall_misses::total 2153884 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6834637000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6834637000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56740092404 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 56740092404 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 170503000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 170503000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 85674000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 85674000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 63574729404 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 63574729404 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 63574729404 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 63574729404 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10203080 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10203080 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6450466 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6450466 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 137622 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 137622 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 126651 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 126651 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16653546 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16653546 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16653546 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16653546 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044559 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.263430 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102854 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.079826 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.129335 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.129335 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15033.206785 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33391.295681 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12045.425645 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8474.183976 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29516.320008 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29516.320008 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 14003056 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5014500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3116 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 133 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4493.920411 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 37703.007519 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 416651 # number of replacements +system.cpu1.dcache.tagsinuse 465.227268 # Cycle average of tags in use +system.cpu1.dcache.total_refs 15192855 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 417163 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.419469 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 72551040000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 465.227268 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.908647 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.908647 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 10025124 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10025124 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4871876 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4871876 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 126729 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 126729 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 119900 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 119900 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 14897000 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 14897000 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 14897000 # number of overall hits +system.cpu1.dcache.overall_hits::total 14897000 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 473956 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 473956 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1726769 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1726769 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14662 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14662 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10568 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10568 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2200725 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2200725 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2200725 # number of overall misses +system.cpu1.dcache.overall_misses::total 2200725 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7150775500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 7150775500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 57296789383 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 57296789383 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 176168500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 176168500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 91818000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 91818000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 64447564883 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 64447564883 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 64447564883 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 64447564883 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10499080 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10499080 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6598645 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6598645 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 141391 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 141391 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 130468 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 130468 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 17097725 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 17097725 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 17097725 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 17097725 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045143 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.261685 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.103698 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081001 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128714 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128714 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15087.424782 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33181.502206 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12015.311690 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.304315 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29284.697035 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29284.697035 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 15243046 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5411000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3282 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 148 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4644.438147 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 36560.810811 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 337879 # number of writebacks -system.cpu1.dcache.writebacks::total 337879 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 192117 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 192117 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1524857 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1524857 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1136 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1136 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1716974 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1716974 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1716974 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1716974 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 262519 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 262519 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 174391 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 174391 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13019 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13019 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10105 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10105 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 436910 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 436910 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 436910 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 436910 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3282878000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3282878000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5492297055 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5492297055 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 117597000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 117597000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55303500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 55303500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2501 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2501 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8775175055 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8775175055 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8775175055 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8775175055 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137933377000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137933377000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41618372048 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41618372048 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179551749048 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179551749048 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025729 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027035 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094600 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.079786 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12505.296759 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31494.154257 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9032.721407 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5472.884711 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 345826 # number of writebacks +system.cpu1.dcache.writebacks::total 345826 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 203766 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 203766 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1549585 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1549585 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1246 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1246 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1753351 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1753351 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1753351 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1753351 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 270190 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 270190 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 177184 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 177184 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13416 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13416 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10560 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10560 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 447374 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 447374 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 447374 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 447374 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3410102500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3410102500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5540518545 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5540518545 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 120430000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 120430000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60079000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60079000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8950621045 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8950621045 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8950621045 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8950621045 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 138186102000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 138186102000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41660941677 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41660941677 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179847043677 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179847043677 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025735 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026852 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.094886 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080939 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026166 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026166 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12621.127725 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31269.858142 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8976.595110 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5689.299242 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20084.628539 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20084.628539 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20007.021072 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20007.021072 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -1533,16 +1533,16 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308183454966 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1308183454966 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308183454966 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1308183454966 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308112364906 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1308112364906 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308112364906 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1308112364906 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 38029 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 36030 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 59437 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 61524 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index e0ab5975e..7b28f6e69 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,13 +10,13 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_loader_mem=system.realview.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -63,7 +63,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -520,7 +520,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -614,7 +614,7 @@ port=system.membus.master[2] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -854,13 +854,16 @@ proc_id1=201327138 system=system pio=system.iobus.master[1] -[system.realview.rtc_fake] -type=AmbaFake -amba_id=266289 -ignore_access=false +[system.realview.rtc] +type=PL031 +amba_id=3412017 +gic=system.realview.gic +int_delay=100000 +int_num=42 pio_addr=268529664 pio_latency=1000 system=system +time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] [system.realview.sci_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 9c3dda86e..16435a5eb 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,15 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 10:15:20 -gem5 started Mar 9 2012 10:45:32 -gem5 executing on zizzer +gem5 compiled Mar 17 2012 11:46:05 +gem5 started Mar 17 2012 18:11:20 +gem5 executing on u200540-lin command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -The currently selected ARM platforms doesn't support - the amount of DRAM you've selected. Please try - another platform Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503099557500 because m5_exit instruction encountered +Exiting @ tick 2501676293500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index f897e20de..356c695d2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503100 # Number of seconds simulated -sim_ticks 2503099557500 # Number of ticks simulated -final_tick 2503099557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.501676 # Number of seconds simulated +sim_ticks 2501676293500 # Number of ticks simulated +final_tick 2501676293500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80117 # Simulator instruction rate (inst/s) -host_op_rate 103484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3373282088 # Simulator tick rate (ticks/s) -host_mem_usage 383952 # Number of bytes of host memory used -host_seconds 742.04 # Real time elapsed on the host -sim_insts 59449445 # Number of instructions simulated -sim_ops 76789092 # Number of ops (including micro ops) simulated +host_inst_rate 93944 # Simulator instruction rate (inst/s) +host_op_rate 121345 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3953091411 # Simulator tick rate (ticks/s) +host_mem_usage 381372 # Number of bytes of host memory used +host_seconds 632.84 # Real time elapsed on the host +sim_insts 59451291 # Number of instructions simulated +sim_ops 76792341 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,148 +20,151 @@ system.realview.nvmem.num_other 0 # Nu system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 130740776 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1120320 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9586312 # Number of bytes written to this memory -system.physmem.num_reads 15115704 # Number of read requests responded to by this memory -system.physmem.num_writes 856678 # Number of write requests responded to by this memory +system.physmem.bytes_read 129652968 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1121024 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9585096 # Number of bytes written to this memory +system.physmem.num_reads 14979455 # Number of read requests responded to by this memory +system.physmem.num_writes 856659 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52231553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 447573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3829777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56061329 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119794 # number of replacements -system.l2c.tagsinuse 26073.611012 # Cycle average of tags in use -system.l2c.total_refs 1840774 # Total number of references to valid blocks. -system.l2c.sampled_refs 150725 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.212798 # Average number of references to valid blocks. +system.physmem.bw_read 51826437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 448109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3831469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 55657906 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 119784 # number of replacements +system.l2c.tagsinuse 25999.615357 # Cycle average of tags in use +system.l2c.total_refs 1826145 # Total number of references to valid blocks. +system.l2c.sampled_refs 150763 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.112687 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14308.761179 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 64.610993 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.928498 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6189.887268 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5509.423074 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.218334 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000986 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 14272.421964 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 65.344146 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.932012 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 6169.201034 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5491.716201 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.217780 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000997 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.094450 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.084067 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.397852 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 152848 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11656 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 998872 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 377319 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1540695 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 633173 # number of Writeback hits -system.l2c.Writeback_hits::total 633173 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 44 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 105891 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105891 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 152848 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11656 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 998872 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 483210 # number of demand (read+write) hits -system.l2c.demand_hits::total 1646586 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 152848 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11656 # number of overall hits -system.l2c.overall_hits::cpu.inst 998872 # number of overall hits -system.l2c.overall_hits::cpu.data 483210 # number of overall hits -system.l2c.overall_hits::total 1646586 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 147 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 17382 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 19146 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36687 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 3313 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3313 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 140346 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140346 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 147 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 17382 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 159492 # number of demand (read+write) misses -system.l2c.demand_misses::total 177033 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 147 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu.inst 17382 # number of overall misses -system.l2c.overall_misses::cpu.data 159492 # number of overall misses -system.l2c.overall_misses::total 177033 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7686500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 617000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 910008500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1001033000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1919345000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 1206000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1206000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7379766500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7379766500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 7686500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 617000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 910008500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8380799500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9299111500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 7686500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 617000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 910008500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8380799500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9299111500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 152995 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11668 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1016254 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 396465 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1577382 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 633173 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 633173 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 3357 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3357 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246237 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246237 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 152995 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11668 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1016254 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 642702 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1823619 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 152995 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11668 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1016254 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 642702 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1823619 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001028 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.017104 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.048292 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.986893 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.569963 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000961 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001028 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.017104 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.248159 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000961 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001028 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.017104 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.248159 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52289.115646 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 51416.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52353.497871 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52284.184686 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.020525 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52582.663560 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52546.833070 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52289.115646 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 51416.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52353.497871 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52546.833070 # average overall miss latency +system.l2c.occ_percent::cpu.inst 0.094135 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.083797 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.396723 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 141919 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 12116 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 995766 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 377927 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1527728 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 634955 # number of Writeback hits +system.l2c.Writeback_hits::total 634955 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 46 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 7 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 105770 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105770 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 141919 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 12116 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 995766 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 483697 # number of demand (read+write) hits +system.l2c.demand_hits::total 1633498 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 141919 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 12116 # number of overall hits +system.l2c.overall_hits::cpu.inst 995766 # number of overall hits +system.l2c.overall_hits::cpu.data 483697 # number of overall hits +system.l2c.overall_hits::total 1633498 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 157 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 17392 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 19166 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36728 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 3302 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3302 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 140335 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140335 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 157 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 17392 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 159501 # number of demand (read+write) misses +system.l2c.demand_misses::total 177063 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 157 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 13 # number of overall misses +system.l2c.overall_misses::cpu.inst 17392 # number of overall misses +system.l2c.overall_misses::cpu.data 159501 # number of overall misses +system.l2c.overall_misses::total 177063 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 8196500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 677000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 910933000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1001503500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1921310000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1203000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1203000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7367598500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7367598500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 8196500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 677000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 910933000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8369102000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 9288908500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 8196500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 677000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 910933000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8369102000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 9288908500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 142076 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 12129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1013158 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 397093 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1564456 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 634955 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 634955 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3348 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3348 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 10 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246105 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 142076 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 12129 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1013158 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 643198 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1810561 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 142076 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 12129 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1013158 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 643198 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1810561 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001105 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001072 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.017166 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.048266 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.986260 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.300000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.570224 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.001105 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.001072 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.017166 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.247981 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.001105 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.001072 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.017166 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.247981 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52207.006369 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52076.923077 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52376.552438 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52254.174058 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.324652 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52500.078384 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -170,100 +173,97 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102660 # number of writebacks -system.l2c.writebacks::total 102660 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.data 79 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.data 79 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 93 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 147 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 17369 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 19067 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 3313 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3313 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 140346 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140346 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 147 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 17369 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 159413 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 176940 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 147 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 17369 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 159413 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 176940 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 5904000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 442000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 697218500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 765075000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1468639500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 133817000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 133817000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 80000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 80000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5636526500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5636526500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 442000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 697218500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 6401601500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 7105166000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5904000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 442000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 697218500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 6401601500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 7105166000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5507000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131763880500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131769387500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32348463263 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32348463263 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5507000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164112343763 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164117850763 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048093 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986893 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569963 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000961 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000943 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.017091 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.248036 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40141.545282 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40125.609692 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40391.488077 # average UpgradeReq mshr miss latency +system.l2c.writebacks::writebacks 102641 # number of writebacks +system.l2c.writebacks::total 102641 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 91 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 157 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 13 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 17382 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 19085 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 36637 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 3302 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3302 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 140335 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140335 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 157 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 17382 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 159420 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176972 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 157 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 17382 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 159420 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176972 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 6288500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 521000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 698170500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 765243500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1470223500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 132738500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 132738500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5623589000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5623589000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 6288500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 521000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 698170500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6388832500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7093812500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 6288500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 521000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 698170500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6388832500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7093812500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765321500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131770748500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346079731 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32346079731 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 164111401231 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 164116828231 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048062 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986260 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.300000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.570224 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.247855 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001105 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001072 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.017156 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.247855 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40166.292717 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.594184 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40199.424591 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40161.646930 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40163.265306 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40181.818182 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40141.545282 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40157.336604 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40072.604838 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40166.292717 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.476728 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40054.140127 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40076.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40166.292717 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.476728 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -278,27 +278,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51948606 # DTB read hits -system.cpu.dtb.read_misses 101816 # DTB read misses -system.cpu.dtb.write_hits 11910706 # DTB write hits -system.cpu.dtb.write_misses 24423 # DTB write misses +system.cpu.dtb.read_hits 52069399 # DTB read hits +system.cpu.dtb.read_misses 92258 # DTB read misses +system.cpu.dtb.write_hits 11926847 # DTB write hits +system.cpu.dtb.write_misses 25023 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4440 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5598 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 665 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4540 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 5662 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 693 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2849 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52050422 # DTB read accesses -system.cpu.dtb.write_accesses 11935129 # DTB write accesses +system.cpu.dtb.perms_faults 2731 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52161657 # DTB read accesses +system.cpu.dtb.write_accesses 11951870 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63859312 # DTB hits -system.cpu.dtb.misses 126239 # DTB misses -system.cpu.dtb.accesses 63985551 # DTB accesses -system.cpu.itb.inst_hits 13611127 # ITB inst hits -system.cpu.itb.inst_misses 11794 # ITB inst misses +system.cpu.dtb.hits 63996246 # DTB hits +system.cpu.dtb.misses 117281 # DTB misses +system.cpu.dtb.accesses 64113527 # DTB accesses +system.cpu.itb.inst_hits 13699541 # ITB inst hits +system.cpu.itb.inst_misses 12131 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -307,504 +307,504 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2614 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2626 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 6917 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 6936 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13622921 # ITB inst accesses -system.cpu.itb.hits 13611127 # DTB hits -system.cpu.itb.misses 11794 # DTB misses -system.cpu.itb.accesses 13622921 # DTB accesses -system.cpu.numCycles 414035717 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13711672 # ITB inst accesses +system.cpu.itb.hits 13699541 # DTB hits +system.cpu.itb.misses 12131 # DTB misses +system.cpu.itb.accesses 13711672 # DTB accesses +system.cpu.numCycles 411150559 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15526652 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12489737 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 928336 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10678484 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8212324 # Number of BTB hits +system.cpu.BPredUnit.lookups 15631672 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12342234 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 929456 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10552810 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8288947 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1312295 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 195061 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32929499 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 102163781 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15526652 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9524619 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22440538 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6579937 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 148688 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93080203 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2936 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 137545 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 217702 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13603433 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 995292 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6599 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 153452703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.827416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.209875 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1323523 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 194787 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32982972 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 102837345 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15631672 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9612470 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22590084 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6692504 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 158663 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 89850563 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2746 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 143204 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 218934 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 483 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13691858 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 996334 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6838 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150553763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.848436 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.233477 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131028378 85.39% 85.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1463837 0.95% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1832687 1.19% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2690815 1.75% 89.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1870921 1.22% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1178749 0.77% 91.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2936419 1.91% 93.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 835625 0.54% 93.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9615272 6.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 127980574 85.01% 85.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1480097 0.98% 85.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1855620 1.23% 87.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2694532 1.79% 89.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1893570 1.26% 90.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1188011 0.79% 91.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2948135 1.96% 93.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 848652 0.56% 93.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9664572 6.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 153452703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.037501 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.246751 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34954549 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92988756 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20078806 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1116855 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4313737 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2248287 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 185454 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119076129 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 599477 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4313737 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37045133 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36926846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49909637 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19098925 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6158425 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 111441141 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3427 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 975111 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4036126 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 44783 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115828569 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 512776978 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 512681517 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 95461 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77492759 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38335809 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1177287 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1072928 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13010963 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21488170 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14015818 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1893787 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2361029 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101216530 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1853504 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 125772492 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 220452 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25469081 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 69618284 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 353864 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 153452703 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819617 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.525568 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150553763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.038019 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.250121 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35091688 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89690975 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20321625 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1025705 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4423770 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2273029 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 186320 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119828190 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 605140 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4423770 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37165531 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37166387 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46484492 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19226681 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6086902 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 112339029 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3754 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1012932 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4107831 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 44905 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 116884712 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 516607430 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 516512877 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 94553 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77495227 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 39389484 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 939636 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 835400 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12435347 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21635443 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14050113 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1939177 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2494760 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 102209700 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1618930 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126189021 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 231742 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26205661 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 71388624 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 331981 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150553763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.838166 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.542583 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107878797 70.30% 70.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14731235 9.60% 79.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7302555 4.76% 84.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5766685 3.76% 88.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12704866 8.28% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2797979 1.82% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1703854 1.11% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 430247 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 136485 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 105343416 69.97% 69.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14065037 9.34% 79.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7354541 4.88% 84.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5909522 3.93% 88.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12758140 8.47% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2807768 1.86% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1730475 1.15% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 446826 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 138038 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 153452703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150553763 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 55588 0.63% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8410763 94.57% 95.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 427006 4.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60599 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8416262 94.64% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 416317 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 59380040 47.21% 47.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95959 0.08% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 34 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 46 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2266 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53622551 42.63% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12565056 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59665616 47.28% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95635 0.08% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 36 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 48 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2270 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53732100 42.58% 90.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12586768 9.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 125772492 # Type of FU issued -system.cpu.iq.rate 0.303772 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8893360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070710 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 414213065 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128557320 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86496982 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24084 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13214 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10457 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134546484 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12838 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 592105 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126189021 # Type of FU issued +system.cpu.iq.rate 0.306917 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8893180 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070475 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 412149363 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 130053896 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86886822 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 24048 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13080 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10409 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134962848 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12823 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 636825 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5807721 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11311 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32412 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2237013 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5953964 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11249 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33793 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2270680 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34115378 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1150417 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34115287 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1151875 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4313737 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28451597 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 431255 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103286909 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 337253 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21488170 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14015818 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1227531 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 94319 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11225 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32412 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 548239 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 349587 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 897826 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 122535537 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52641416 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3236955 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4423770 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28606306 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 435959 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 104089793 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 334839 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21635443 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14050113 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 991881 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 95881 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11592 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33793 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 550966 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 345374 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 896340 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 122956903 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52760819 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3232118 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 216875 # number of nop insts executed -system.cpu.iew.exec_refs 65061832 # number of memory reference insts executed -system.cpu.iew.exec_branches 11533456 # Number of branches executed -system.cpu.iew.exec_stores 12420416 # Number of stores executed -system.cpu.iew.exec_rate 0.295954 # Inst execution rate -system.cpu.iew.wb_sent 121007788 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86507439 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46901063 # num instructions producing a value -system.cpu.iew.wb_consumers 86866563 # num instructions consuming a value +system.cpu.iew.exec_nop 261163 # number of nop insts executed +system.cpu.iew.exec_refs 65197273 # number of memory reference insts executed +system.cpu.iew.exec_branches 11589071 # Number of branches executed +system.cpu.iew.exec_stores 12436454 # Number of stores executed +system.cpu.iew.exec_rate 0.299056 # Inst execution rate +system.cpu.iew.wb_sent 121403477 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86897231 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47438485 # num instructions producing a value +system.cpu.iew.wb_consumers 88321921 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.208937 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.539921 # average fanout of values written-back +system.cpu.iew.wb_rate 0.211351 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.537109 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59599826 # The number of committed instructions -system.cpu.commit.commitCommittedOps 76939473 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26171914 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1499640 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 790317 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149221313 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.515606 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.482610 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59601672 # The number of committed instructions +system.cpu.commit.commitCommittedOps 76942722 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26965943 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1286949 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 790517 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146212348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.526240 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.505087 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120951257 81.05% 81.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14347270 9.61% 90.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4034652 2.70% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2127712 1.43% 94.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1768055 1.18% 95.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1033434 0.69% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1556613 1.04% 97.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657865 0.44% 98.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2744455 1.84% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118498573 81.05% 81.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13699176 9.37% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3966547 2.71% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2244227 1.53% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1750329 1.20% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1033206 0.71% 96.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1542131 1.05% 97.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 667633 0.46% 98.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2810526 1.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149221313 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59599826 # Number of instructions committed -system.cpu.commit.committedOps 76939473 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146212348 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59601672 # Number of instructions committed +system.cpu.commit.committedOps 76942722 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27459254 # Number of memory references committed -system.cpu.commit.loads 15680449 # Number of loads committed -system.cpu.commit.membars 413031 # Number of memory barriers committed -system.cpu.commit.branches 9890920 # Number of branches committed +system.cpu.commit.refs 27460912 # Number of memory references committed +system.cpu.commit.loads 15681479 # Number of loads committed +system.cpu.commit.membars 413077 # Number of memory barriers committed +system.cpu.commit.branches 9891359 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68492585 # Number of committed integer instructions. -system.cpu.commit.function_calls 995546 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2744455 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68495555 # Number of committed integer instructions. +system.cpu.commit.function_calls 995632 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2810526 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 247831805 # The number of ROB reads -system.cpu.rob.rob_writes 210661614 # The number of ROB writes -system.cpu.timesIdled 1891867 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260583014 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4592075418 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59449445 # Number of Instructions Simulated -system.cpu.committedOps 76789092 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59449445 # Number of Instructions Simulated -system.cpu.cpi 6.964501 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.964501 # CPI: Total CPI of All Threads -system.cpu.ipc 0.143585 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.143585 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 555570054 # number of integer regfile reads -system.cpu.int_regfile_writes 88783658 # number of integer regfile writes -system.cpu.fp_regfile_reads 8868 # number of floating regfile reads -system.cpu.fp_regfile_writes 2963 # number of floating regfile writes -system.cpu.misc_regfile_reads 134383864 # number of misc regfile reads -system.cpu.misc_regfile_writes 912266 # number of misc regfile writes -system.cpu.icache.replacements 1016880 # number of replacements -system.cpu.icache.tagsinuse 511.619498 # Cycle average of tags in use -system.cpu.icache.total_refs 12495254 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1017392 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.281652 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6291400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.619498 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999257 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999257 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12495254 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12495254 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12495254 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12495254 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12495254 # number of overall hits -system.cpu.icache.overall_hits::total 12495254 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1108036 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1108036 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1108036 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1108036 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1108036 # number of overall misses -system.cpu.icache.overall_misses::total 1108036 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16316535479 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16316535479 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16316535479 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16316535479 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16316535479 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16316535479 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13603290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13603290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13603290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13603290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13603290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13603290 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081454 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081454 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081454 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14725.636603 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14725.636603 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2951482 # number of cycles access was blocked +system.cpu.rob.rob_reads 245553933 # The number of ROB reads +system.cpu.rob.rob_writes 212368242 # The number of ROB writes +system.cpu.timesIdled 1894262 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260596796 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4592114044 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59451291 # Number of Instructions Simulated +system.cpu.committedOps 76792341 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59451291 # Number of Instructions Simulated +system.cpu.cpi 6.915755 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.915755 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144597 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144597 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 557431988 # number of integer regfile reads +system.cpu.int_regfile_writes 89182974 # number of integer regfile writes +system.cpu.fp_regfile_reads 8912 # number of floating regfile reads +system.cpu.fp_regfile_writes 2994 # number of floating regfile writes +system.cpu.misc_regfile_reads 135303561 # number of misc regfile reads +system.cpu.misc_regfile_writes 912352 # number of misc regfile writes +system.cpu.icache.replacements 1013837 # number of replacements +system.cpu.icache.tagsinuse 511.616166 # Cycle average of tags in use +system.cpu.icache.total_refs 12585526 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1014349 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.407491 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6289783000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.616166 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999250 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999250 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12585526 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12585526 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12585526 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12585526 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12585526 # number of overall hits +system.cpu.icache.overall_hits::total 12585526 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1106194 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1106194 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1106194 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1106194 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1106194 # number of overall misses +system.cpu.icache.overall_misses::total 1106194 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16291440480 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16291440480 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16291440480 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16291440480 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16291440480 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16291440480 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13691720 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13691720 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13691720 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13691720 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13691720 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13691720 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080793 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.080793 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.080793 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14727.471384 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3199983 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 405 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 416 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7287.609877 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7692.266827 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 58719 # number of writebacks -system.cpu.icache.writebacks::total 58719 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90611 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 90611 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 90611 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 90611 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 90611 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 90611 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1017425 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1017425 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1017425 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1017425 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1017425 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1017425 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12153604482 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12153604482 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12153604482 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12153604482 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12153604482 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12153604482 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7398500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7398500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7398500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7398500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074793 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11945.454930 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11945.454930 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 59844 # number of writebacks +system.cpu.icache.writebacks::total 59844 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91810 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 91810 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 91810 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 91810 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 91810 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 91810 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1014384 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1014384 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1014384 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1014384 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1014384 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1014384 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12127535483 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12127535483 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12127535483 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12127535483 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12127535483 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12127535483 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074087 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11955.566613 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11955.566613 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11955.566613 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644925 # number of replacements -system.cpu.dcache.tagsinuse 511.991557 # Cycle average of tags in use -system.cpu.dcache.total_refs 21957407 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645437 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.019443 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 49249000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991557 # Average occupied blocks per requestor +system.cpu.dcache.replacements 645435 # number of replacements +system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use +system.cpu.dcache.total_refs 22022963 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 645947 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.094071 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 14117520 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14117520 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7264910 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7264910 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 285961 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 285961 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285492 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285492 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21382430 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21382430 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21382430 # number of overall hits -system.cpu.dcache.overall_hits::total 21382430 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 735373 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 735373 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2966010 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966010 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13726 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13726 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3701383 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3701383 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3701383 # number of overall misses -system.cpu.dcache.overall_misses::total 3701383 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11086457500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11086457500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110422837752 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110422837752 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223704000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 223704000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 187500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 187500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 121509295252 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 121509295252 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 121509295252 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 121509295252 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14852893 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14852893 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10230920 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10230920 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299687 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 299687 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285500 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285500 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 25083813 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25083813 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 25083813 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25083813 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049510 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289906 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045801 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000028 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.147561 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.147561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15075.964850 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37229.421935 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.828938 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 23437.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32828.079464 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16342936 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7612500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2868 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5698.373780 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 28404.850746 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 14182326 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14182326 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7265741 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7265741 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 285851 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 285851 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285519 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285519 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21448067 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21448067 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21448067 # number of overall hits +system.cpu.dcache.overall_hits::total 21448067 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 745935 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 745935 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2965804 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2965804 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13758 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13758 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 10 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3711739 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3711739 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3711739 # number of overall misses +system.cpu.dcache.overall_misses::total 3711739 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11230893500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11230893500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110142219264 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110142219264 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224423500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 224423500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 267500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 267500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 121373112764 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 121373112764 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 121373112764 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 121373112764 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14928261 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14928261 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10231545 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10231545 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 299609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285529 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285529 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 25159806 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 25159806 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 25159806 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 25159806 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049968 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289869 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045920 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000035 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.147527 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.147527 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15056.128885 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37137.389815 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16312.218346 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32699.797255 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16852944 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7563500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2993 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 267 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5630.786502 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28327.715356 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 574454 # number of writebacks -system.cpu.dcache.writebacks::total 574454 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 348401 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 348401 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716534 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2716534 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1379 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1379 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064935 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064935 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064935 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064935 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386972 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386972 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249476 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249476 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12347 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12347 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636448 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636448 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636448 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636448 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5265104500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5265104500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8925107436 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8925107436 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165722000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165722000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14190211936 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14190211936 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14190211936 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14190211936 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147157757000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147157757000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42274928970 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42274928970 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189432685970 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189432685970 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026054 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041200 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000028 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025373 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13605.905595 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35775.415014 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13422.045841 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20312.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22295.948665 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 575111 # number of writebacks +system.cpu.dcache.writebacks::total 575111 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358347 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 358347 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716460 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2716460 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1395 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1395 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3074807 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3074807 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3074807 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3074807 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387588 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387588 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249344 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249344 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12363 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12363 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636932 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636932 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636932 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636932 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5281773000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5281773000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8909514444 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8909514444 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 166180500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 166180500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 235000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 235000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14191287444 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14191287444 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14191287444 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14191287444 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159264500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159264500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42252638495 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42252638495 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189411902995 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 189411902995 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025963 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041264 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025315 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13627.287223 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35731.818067 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13441.761708 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22280.694712 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency @@ -823,14 +823,14 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1307788731818 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307788731818 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1307788731818 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1296055922339 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1296055922339 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 87981 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |