diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-30 03:42:27 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-30 03:42:27 -0400 |
| commit | d8f732273ecda73122ad3ba184e358ed265fa875 (patch) | |
| tree | 6ef605febd4e2299d75d76897386ff4ad7288fec /tests/long/fs/10.linux-boot/ref/arm | |
| parent | 6fac40ceb03d4ab5b13affac3927cd876947cc78 (diff) | |
| download | gem5-d8f732273ecda73122ad3ba184e358ed265fa875.tar.xz | |
stats: Update stats for clean eviction addition
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
7 files changed, 13726 insertions, 13804 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index b25b92aa6..5b4459bdf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,166 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846047 # Number of seconds simulated -sim_ticks 2846047385500 # Number of ticks simulated -final_tick 2846047385500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846057 # Number of seconds simulated +sim_ticks 2846057099000 # Number of ticks simulated +final_tick 2846057099000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159625 # Simulator instruction rate (inst/s) -host_op_rate 193311 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3563510303 # Simulator tick rate (ticks/s) -host_mem_usage 654020 # Number of bytes of host memory used -host_seconds 798.66 # Real time elapsed on the host -sim_insts 127487011 # Number of instructions simulated -sim_ops 154390534 # Number of ops (including micro ops) simulated +host_inst_rate 155095 # Simulator instruction rate (inst/s) +host_op_rate 187821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3461671389 # Simulator tick rate (ticks/s) +host_mem_usage 654788 # Number of bytes of host memory used +host_seconds 822.16 # Real time elapsed on the host +sim_insts 127513349 # Number of instructions simulated +sim_ops 154419501 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 7424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 7744 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1468992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1221616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8255360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 381888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 706136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 588160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1469184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1233972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8227712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 383104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 711064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 574528 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12633224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1468992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 381888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1850880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8928128 # Number of bytes written to this memory +system.physmem.bytes_read::total 12611084 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1469184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 383104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1852288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8917568 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8945692 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 116 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8935132 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 121 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22953 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 128990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11055 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 9190 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22956 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 128558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5986 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11132 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 8977 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197938 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 139502 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197593 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 139337 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143893 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2609 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 143728 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2721 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 516152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 429232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2900640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 134182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 248111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 206659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 516217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 433572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2890916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 134609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 249842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 201868 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4438866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 516152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 134182 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 650334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3137027 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4431072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 516217 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 134609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 650826 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3133306 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3143199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3137027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3139477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3133306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2721 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 516152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 435390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2900640 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 134182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 248125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 206659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 516217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 439730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2890916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 134609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 249856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 201868 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7582065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197938 # Number of read requests accepted -system.physmem.writeReqs 143893 # Number of write requests accepted -system.physmem.readBursts 197938 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 143893 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12658432 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 8958080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12633224 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8945692 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 51249 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12124 # Per bank write bursts -system.physmem.perBankRdBursts::1 12298 # Per bank write bursts -system.physmem.perBankRdBursts::2 12956 # Per bank write bursts -system.physmem.perBankRdBursts::3 12344 # Per bank write bursts -system.physmem.perBankRdBursts::4 15465 # Per bank write bursts -system.physmem.perBankRdBursts::5 12573 # Per bank write bursts -system.physmem.perBankRdBursts::6 12691 # Per bank write bursts -system.physmem.perBankRdBursts::7 13082 # Per bank write bursts -system.physmem.perBankRdBursts::8 12243 # Per bank write bursts -system.physmem.perBankRdBursts::9 12357 # Per bank write bursts -system.physmem.perBankRdBursts::10 11723 # Per bank write bursts -system.physmem.perBankRdBursts::11 11147 # Per bank write bursts -system.physmem.perBankRdBursts::12 12049 # Per bank write bursts -system.physmem.perBankRdBursts::13 11871 # Per bank write bursts -system.physmem.perBankRdBursts::14 11344 # Per bank write bursts -system.physmem.perBankRdBursts::15 11521 # Per bank write bursts -system.physmem.perBankWrBursts::0 8574 # Per bank write bursts -system.physmem.perBankWrBursts::1 8801 # Per bank write bursts -system.physmem.perBankWrBursts::2 9504 # Per bank write bursts -system.physmem.perBankWrBursts::3 8801 # Per bank write bursts -system.physmem.perBankWrBursts::4 8786 # Per bank write bursts -system.physmem.perBankWrBursts::5 8838 # Per bank write bursts -system.physmem.perBankWrBursts::6 9085 # Per bank write bursts -system.physmem.perBankWrBursts::7 9267 # Per bank write bursts -system.physmem.perBankWrBursts::8 8941 # Per bank write bursts -system.physmem.perBankWrBursts::9 8908 # Per bank write bursts -system.physmem.perBankWrBursts::10 8524 # Per bank write bursts -system.physmem.perBankWrBursts::11 8283 # Per bank write bursts -system.physmem.perBankWrBursts::12 8972 # Per bank write bursts -system.physmem.perBankWrBursts::13 8287 # Per bank write bursts -system.physmem.perBankWrBursts::14 8306 # Per bank write bursts -system.physmem.perBankWrBursts::15 8093 # Per bank write bursts +system.physmem.bw_total::total 7570549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197593 # Number of read requests accepted +system.physmem.writeReqs 143728 # Number of write requests accepted +system.physmem.readBursts 197593 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 143728 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12635520 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10432 # Total number of bytes read from write queue +system.physmem.bytesWritten 8947648 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12611084 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8935132 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 163 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 51189 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12157 # Per bank write bursts +system.physmem.perBankRdBursts::1 12292 # Per bank write bursts +system.physmem.perBankRdBursts::2 12950 # Per bank write bursts +system.physmem.perBankRdBursts::3 12405 # Per bank write bursts +system.physmem.perBankRdBursts::4 15321 # Per bank write bursts +system.physmem.perBankRdBursts::5 12434 # Per bank write bursts +system.physmem.perBankRdBursts::6 12677 # Per bank write bursts +system.physmem.perBankRdBursts::7 13084 # Per bank write bursts +system.physmem.perBankRdBursts::8 12267 # Per bank write bursts +system.physmem.perBankRdBursts::9 12426 # Per bank write bursts +system.physmem.perBankRdBursts::10 11655 # Per bank write bursts +system.physmem.perBankRdBursts::11 11073 # Per bank write bursts +system.physmem.perBankRdBursts::12 11997 # Per bank write bursts +system.physmem.perBankRdBursts::13 11769 # Per bank write bursts +system.physmem.perBankRdBursts::14 11320 # Per bank write bursts +system.physmem.perBankRdBursts::15 11603 # Per bank write bursts +system.physmem.perBankWrBursts::0 8631 # Per bank write bursts +system.physmem.perBankWrBursts::1 8804 # Per bank write bursts +system.physmem.perBankWrBursts::2 9518 # Per bank write bursts +system.physmem.perBankWrBursts::3 8865 # Per bank write bursts +system.physmem.perBankWrBursts::4 8658 # Per bank write bursts +system.physmem.perBankWrBursts::5 8780 # Per bank write bursts +system.physmem.perBankWrBursts::6 9135 # Per bank write bursts +system.physmem.perBankWrBursts::7 9275 # Per bank write bursts +system.physmem.perBankWrBursts::8 8996 # Per bank write bursts +system.physmem.perBankWrBursts::9 8951 # Per bank write bursts +system.physmem.perBankWrBursts::10 8409 # Per bank write bursts +system.physmem.perBankWrBursts::11 8136 # Per bank write bursts +system.physmem.perBankWrBursts::12 8895 # Per bank write bursts +system.physmem.perBankWrBursts::13 8304 # Per bank write bursts +system.physmem.perBankWrBursts::14 8310 # Per bank write bursts +system.physmem.perBankWrBursts::15 8140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 26 # Number of times write queue was full causing retry -system.physmem.totGap 2846046899000 # Total gap between requests +system.physmem.numWrRetry 40 # Number of times write queue was full causing retry +system.physmem.totGap 2846056522500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 554 # Read request sizes (log2) +system.physmem.readPktSize::2 555 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 197356 # Read request sizes (log2) +system.physmem.readPktSize::6 197010 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 139502 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 97008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 48975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9719 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 280 # What read queue length does an incoming req see +system.physmem.writePktSize::6 139337 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 84527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9638 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 746 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,157 +184,159 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 297 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 238.739707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 135.462322 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 300.134416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 48559 53.63% 53.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17642 19.48% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6276 6.93% 80.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3581 3.95% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2857 3.16% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1437 1.59% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 927 1.02% 89.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1107 1.22% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8158 9.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90544 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6994 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.279525 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 555.958801 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6993 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6994 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6994 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.012868 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.560049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.293161 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5872 83.96% 83.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 361 5.16% 89.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 205 2.93% 92.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 59 0.84% 92.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 60 0.86% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 157 2.24% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.31% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.11% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.20% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.10% 96.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.11% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 162 2.32% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 9 0.13% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.04% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 12 0.17% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6994 # Writes before turning the bus around for reads -system.physmem.totQLat 5635724944 # Total ticks spent queuing -system.physmem.totMemAccLat 9344249944 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 988940000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28493.77 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5520 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 106 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 238.790065 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 135.540737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 300.321787 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48391 53.54% 53.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17645 19.52% 73.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6369 7.05% 80.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3664 4.05% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2743 3.03% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1397 1.55% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 884 0.98% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1036 1.15% 90.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8256 9.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90385 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.264567 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 537.756673 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6984 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6985 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.015319 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.579154 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.029266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5867 83.99% 83.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 359 5.14% 89.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 198 2.83% 91.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 50 0.72% 92.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 72 1.03% 93.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 159 2.28% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 19 0.27% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.17% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.16% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.11% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.07% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 162 2.32% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.09% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 10 0.14% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.20% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6985 # Writes before turning the bus around for reads +system.physmem.totQLat 5478181174 # Total ticks spent queuing +system.physmem.totMemAccLat 9179993674 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 987150000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27747.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47243.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.44 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 46497.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.43 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing -system.physmem.readRowHits 164502 # Number of row buffer hits during reads -system.physmem.writeRowHits 82711 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.08 # Row buffer hit rate for writes -system.physmem.avgGap 8325888.81 # Average gap between requests +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.99 # Average write queue length when enqueuing +system.physmem.readRowHits 164056 # Number of row buffer hits during reads +system.physmem.writeRowHits 82794 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.21 # Row buffer hit rate for writes +system.physmem.avgGap 8338357.51 # Average gap between requests system.physmem.pageHitRate 73.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 356257440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 194386500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 807557400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 464330880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185889868320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83150566875 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634688457500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905551424915 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.543458 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719326804644 # Time in different power states -system.physmem_0.memoryStateTime::REF 95035720000 # Time in different power states +system.physmem_0.actEnergy 356771520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 194667000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 805888200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 464395680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185890376880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83219414895 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634632736250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905564250425 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.546132 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719229075521 # Time in different power states +system.physmem_0.memoryStateTime::REF 95035980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31683407856 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31791929979 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328255200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179107500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 735181200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 442674720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185889868320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82066427730 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635639456750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905280971420 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.448430 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720915660225 # Time in different power states -system.physmem_1.memoryStateTime::REF 95035720000 # Time in different power states +system.physmem_1.actEnergy 326539080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 178171125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 734050200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 441553680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185890376880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82136174355 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635582947250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905289812570 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.449705 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720812978493 # Time in different power states +system.physmem_1.memoryStateTime::REF 95035980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30095909775 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30205644507 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory @@ -364,15 +362,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 19568417 # Number of BP lookups -system.cpu0.branchPred.condPredicted 12741959 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 982246 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 12413476 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8819135 # Number of BTB hits +system.cpu0.branchPred.lookups 19599196 # Number of BP lookups +system.cpu0.branchPred.condPredicted 12768904 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 991514 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 12558764 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8839837 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.044847 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3284365 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 198035 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 70.387795 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3295346 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 199810 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -403,58 +401,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 67683 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 67683 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45041 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22642 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 67683 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 67683 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 67683 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6748 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10568.612922 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9555.209008 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5781.304513 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6579 97.50% 97.50% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 156 2.31% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6748 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 67395 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 67395 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44710 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22685 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 67395 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 67395 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 67395 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6692 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10409.593545 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9352.624092 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5969.180600 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6501 97.15% 97.15% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 173 2.59% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 11 0.16% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6692 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 327753000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 327753000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 327753000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5177 76.72% 76.72% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1571 23.28% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6748 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67683 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5137 76.76% 76.76% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1555 23.24% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6692 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67395 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67683 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6748 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67395 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6692 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6748 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 74431 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6692 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 74087 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 16473000 # DTB read hits -system.cpu0.dtb.read_misses 62137 # DTB read misses -system.cpu0.dtb.write_hits 13870452 # DTB write hits -system.cpu0.dtb.write_misses 5546 # DTB write misses +system.cpu0.dtb.read_hits 16492967 # DTB read hits +system.cpu0.dtb.read_misses 61485 # DTB read misses +system.cpu0.dtb.write_hits 13879033 # DTB write hits +system.cpu0.dtb.write_misses 5910 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3508 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1130 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1591 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3512 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1104 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1584 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16535137 # DTB read accesses -system.cpu0.dtb.write_accesses 13875998 # DTB write accesses +system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 16554452 # DTB read accesses +system.cpu0.dtb.write_accesses 13884943 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 30343452 # DTB hits -system.cpu0.dtb.misses 67683 # DTB misses -system.cpu0.dtb.accesses 30411135 # DTB accesses +system.cpu0.dtb.hits 30372000 # DTB hits +system.cpu0.dtb.misses 67395 # DTB misses +system.cpu0.dtb.accesses 30439395 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -484,36 +482,36 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3854 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3854 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walks 3867 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3867 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3547 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3854 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3854 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3854 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2418 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10984.077750 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9918.433232 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7783.469031 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 2416 99.92% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3867 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3867 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3867 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10756.092524 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9615.276250 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7885.681727 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 2419 99.92% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::32768-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2418 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 327059500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 327059500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 327059500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2118 87.59% 87.59% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 300 12.41% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2418 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2121 87.61% 87.61% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 300 12.39% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3854 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3854 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3867 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3867 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2418 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2418 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6272 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 36667532 # ITB inst hits -system.cpu0.itb.inst_misses 3854 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6288 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 36759532 # ITB inst hits +system.cpu0.itb.inst_misses 3867 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -522,131 +520,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2221 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7326 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7295 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 36671386 # ITB inst accesses -system.cpu0.itb.hits 36667532 # DTB hits -system.cpu0.itb.misses 3854 # DTB misses -system.cpu0.itb.accesses 36671386 # DTB accesses -system.cpu0.numCycles 154642199 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 36763399 # ITB inst accesses +system.cpu0.itb.hits 36759532 # DTB hits +system.cpu0.itb.misses 3867 # DTB misses +system.cpu0.itb.accesses 36763399 # DTB accesses +system.cpu0.numCycles 154883476 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 75578579 # Number of instructions committed -system.cpu0.committedOps 90977347 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 4937651 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 2060 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5537489017 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.046111 # CPI: cycles per instruction -system.cpu0.ipc 0.488732 # IPC: instructions per cycle +system.cpu0.committedInsts 75627253 # Number of instructions committed +system.cpu0.committedOps 91033342 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 4957970 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 2062 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5537267530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.047985 # CPI: cycles per instruction +system.cpu0.ipc 0.488285 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2062 # number of quiesce instructions executed -system.cpu0.tickCycles 120829876 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 33812323 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 679563 # number of replacements -system.cpu0.dcache.tags.tagsinuse 486.133146 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28909958 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 680075 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.509956 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 345411000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.133146 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949479 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.949479 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 2064 # number of quiesce instructions executed +system.cpu0.tickCycles 121009607 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 33873869 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 680149 # number of replacements +system.cpu0.dcache.tags.tagsinuse 489.017964 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28930962 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 680661 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.504216 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 345600000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.017964 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.955113 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.955113 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 60679422 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 60679422 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 14995018 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 14995018 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 12788335 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 12788335 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306891 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 306891 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 356622 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 356622 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352102 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 352102 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27783353 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27783353 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 28090244 # number of overall hits -system.cpu0.dcache.overall_hits::total 28090244 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 441719 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 441719 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 557349 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 557349 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131939 # 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number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15451551 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 15451551 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13352612 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13352612 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438566 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 438566 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 377975 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 377975 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373545 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 373545 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 28804163 # 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average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15224.837739 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22601.714070 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22601.714070 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14679.544335 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14679.544335 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12967.084200 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12967.084200 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14773.543058 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14773.543058 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13051.996038 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13051.996038 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,149 +653,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 493293 # number of writebacks -system.cpu0.dcache.writebacks::total 493293 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69842 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 69842 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244235 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 244235 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15018 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15018 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 314077 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 314077 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 314077 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 314077 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371877 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 371877 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9298436000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10921907000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10921907000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3751545500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3751545500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2725656000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725656000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6477201500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6477201500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024090 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024090 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226411 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226411 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016375 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016375 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057066 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057066 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023799 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023799 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026842 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026842 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11778.713123 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11778.713123 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15707.389321 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15707.389321 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16339.939209 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16339.939209 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15239.776952 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15239.776952 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21572.809611 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21572.809611 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 493052 # number of writebacks +system.cpu0.dcache.writebacks::total 493052 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69962 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 69962 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244118 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 244118 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15072 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15072 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 314080 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 314080 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 314080 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 314080 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372783 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 372783 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312954 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312954 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99314 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 99314 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6190 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6190 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21236 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21236 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 685737 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 685737 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 785051 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 785051 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 18001 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18001 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16756 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16756 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34757 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34757 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4391149500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4391149500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4970740000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4970740000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1612906500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1612906500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94756000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94756000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 458745000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 458745000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 434000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 434000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9361889500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9361889500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10974796000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10974796000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3751362500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3751362500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2725552500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725552500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6476915000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6476915000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024126 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024126 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023438 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023438 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226452 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226452 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016377 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016377 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056850 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056850 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023807 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023807 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026846 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026846 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11779.371645 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11779.371645 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15883.292752 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15883.292752 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16240.474656 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16240.474656 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15307.915994 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15307.915994 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21602.232059 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21602.232059 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13574.537476 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13574.537476 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13924.840664 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13924.840664 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208396.039329 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208396.039329 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162648.048693 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162648.048693 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186340.664557 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186340.664557 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13652.303288 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13652.303288 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13979.723610 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13979.723610 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208397.450142 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208397.450142 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162661.285510 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162661.285510 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 186348.505337 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186348.505337 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1878063 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.785549 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 34781277 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1878575 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.514713 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6156628000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.785549 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 1879741 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.785261 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 34871642 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1880253 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.546250 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6165545000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.785261 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999581 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999581 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 75198332 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 75198332 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 34781277 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34781277 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 34781277 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34781277 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 34781277 # number of overall hits -system.cpu0.icache.overall_hits::total 34781277 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1878593 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1878593 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1878593 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1878593 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1878593 # number of overall misses -system.cpu0.icache.overall_misses::total 1878593 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17494191500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 17494191500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 17494191500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 17494191500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 17494191500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 17494191500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 36659870 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 36659870 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 36659870 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 36659870 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 36659870 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 36659870 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051244 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.051244 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051244 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.051244 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051244 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.051244 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9312.390443 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9312.390443 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9312.390443 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9312.390443 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9312.390443 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9312.390443 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 75384087 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 75384087 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 34871642 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 34871642 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 34871642 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 34871642 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 34871642 # number of overall hits +system.cpu0.icache.overall_hits::total 34871642 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1880268 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1880268 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1880268 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1880268 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1880268 # number of overall misses +system.cpu0.icache.overall_misses::total 1880268 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17494991000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 17494991000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 17494991000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 17494991000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 17494991000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 17494991000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 36751910 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 36751910 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 36751910 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 36751910 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 36751910 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 36751910 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051161 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.051161 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051161 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.051161 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051161 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.051161 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9304.519888 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9304.519888 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9304.519888 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9304.519888 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9304.519888 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9304.519888 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,463 +804,463 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1878593 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1878593 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1878593 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1878593 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1878593 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1878593 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1880268 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1880268 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1880268 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1880268 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1880268 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1880268 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3426 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3426 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3426 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3426 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16554895500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 16554895500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16554895500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 16554895500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16554895500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 16554895500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16554857500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16554857500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16554857500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16554857500 # 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mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.051161 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051161 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.051161 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8804.520154 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8804.520154 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8804.520154 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8804.520154 # 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Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.532424 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002645 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 8613.892017 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 45.679204 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.072727 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4663.239886 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1620.721287 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1120.836170 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.525750 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002788 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4328 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7768 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2750 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063721 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000916 # 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number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1814336 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 589047 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2487864 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 723 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 114 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 837 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27851 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 27851 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19535 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19535 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4239 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7941 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2698 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927673 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 85389688 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 85389688 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 78899 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4233 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 83132 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 493050 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 493050 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28200 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28200 # 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mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010380 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.496435 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.496435 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.916792 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.916792 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.496815 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.496815 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.919896 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.919896 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159959 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159959 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034169 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211559 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211559 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008951 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025071 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193502 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076766 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008951 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025071 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034169 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193502 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.161497 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.161497 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034003 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.210450 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.210450 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009628 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.024205 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193343 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076664 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009628 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.024205 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034003 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193343 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163865 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26946.236559 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60156.033695 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19996.750566 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19996.750566 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15280.445354 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15280.445354 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 325999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 325999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38421.519264 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38421.519264 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38723.765384 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22652.249421 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22652.249421 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27214.123844 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30779.712833 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28293.914246 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18399.122807 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38723.765384 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27214.123844 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60156.033695 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46394.080031 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163323 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26951.261468 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59209.883112 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19925.169702 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19925.169702 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15261.518378 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15261.518378 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 351500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 351500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40248.391217 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40248.391217 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38668.335028 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22684.615737 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22684.615737 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27811.306664 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31161.797592 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28127.118644 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18361.904762 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38668.335028 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27811.306664 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59209.883112 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46044.070914 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200391.623153 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.803061 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155132.324860 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155132.324860 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200392.006000 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181739.254212 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155145.738840 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155145.738840 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83733.362522 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178571.849827 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170063.059760 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 178579.235837 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 170069.114527 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 136409 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2524037 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16758 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 866064 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2177189 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 293784 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 92828 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43742 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114509 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 285377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 271332 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1878593 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603707 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 136175 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2526619 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 16756 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 865136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2178805 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 280675 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 92865 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43660 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114593 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 285252 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 271172 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1880268 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 604912 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5608538 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2465365 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11948 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 171096 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8256947 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120449152 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82718835 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18188 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 323084 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 203509259 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1215113 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 6486372 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.185022 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.388316 # Request fanout histogram +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5613549 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2467613 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11765 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 169746 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8262673 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120556352 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82765674 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17352 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 318664 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 203658042 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1202366 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 6476462 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.183069 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.386723 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 5286248 81.50% 81.50% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1200124 18.50% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 5290820 81.69% 81.69% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1185642 18.31% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 6486372 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3193659992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 6476462 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3195593995 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113350499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113765999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2823287977 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2825774529 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1167322846 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1168364927 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7403495 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7430992 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 90327994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 90084491 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 20515510 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7101066 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 968769 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 10637682 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 7757881 # Number of BTB hits +system.cpu1.branchPred.lookups 20439224 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7037667 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 906738 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 10483361 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 7695105 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.928303 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8827818 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 689615 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.403034 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8822837 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 629691 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1292,60 +1290,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 30617 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 30617 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22895 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7722 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 30617 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 30617 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 30617 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2694 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10773.014105 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9833.978032 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6170.794386 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 858 31.85% 31.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1697 62.99% 94.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 63 2.34% 97.18% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 63 2.34% 99.52% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 7 0.26% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.15% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2694 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1565807264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1565807264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1565807264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2001 74.28% 74.28% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 693 25.72% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2694 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30617 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 30282 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 30282 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22625 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7657 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 30282 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 30282 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 30282 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2657 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10518.253670 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9441.717442 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7245.373074 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 2512 94.54% 94.54% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 130 4.89% 99.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 7 0.26% 99.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-98303 5 0.19% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-114687 2 0.08% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2657 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1594102264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1594102264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1594102264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1972 74.22% 74.22% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 685 25.78% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2657 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30282 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30617 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2694 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30282 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2657 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2694 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 33311 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2657 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 32939 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12131046 # DTB read hits -system.cpu1.dtb.read_misses 27925 # DTB read misses -system.cpu1.dtb.write_hits 7724726 # DTB write hits -system.cpu1.dtb.write_misses 2692 # DTB write misses +system.cpu1.dtb.read_hits 12124185 # DTB read hits +system.cpu1.dtb.read_misses 27903 # DTB read misses +system.cpu1.dtb.write_hits 7716793 # DTB write hits +system.cpu1.dtb.write_misses 2379 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 318 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 531 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2053 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 374 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 549 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 287 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12158971 # DTB read accesses -system.cpu1.dtb.write_accesses 7727418 # DTB write accesses +system.cpu1.dtb.perms_faults 291 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12152088 # DTB read accesses +system.cpu1.dtb.write_accesses 7719172 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19855772 # DTB hits -system.cpu1.dtb.misses 30617 # DTB misses -system.cpu1.dtb.accesses 19886389 # DTB accesses +system.cpu1.dtb.hits 19840978 # DTB hits +system.cpu1.dtb.misses 30282 # DTB misses +system.cpu1.dtb.accesses 19871260 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1375,39 +1371,41 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2297 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2297 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walks 2290 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2290 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 182 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2115 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2297 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2297 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2297 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10860.516934 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10080.267537 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5206.907244 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 274 24.42% 24.42% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 814 72.55% 96.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 4 0.36% 97.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 27 2.41% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 2 0.18% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1565238764 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1565238764 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1565238764 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 953 84.94% 84.94% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 169 15.06% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2108 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2290 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2290 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2290 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10627.337489 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9754.511529 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5025.096618 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 329 29.30% 29.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 526 46.84% 76.14% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 229 20.39% 96.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 96.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 14 1.25% 97.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.87% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1593536764 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1593536764 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1593536764 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 954 84.95% 84.95% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 169 15.05% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2297 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2297 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2290 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2290 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3419 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 41950603 # ITB inst hits -system.cpu1.itb.inst_misses 2297 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3413 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 41919801 # ITB inst hits +system.cpu1.itb.inst_misses 2290 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1416,130 +1414,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1160 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1848 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1868 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 41952900 # ITB inst accesses -system.cpu1.itb.hits 41950603 # DTB hits -system.cpu1.itb.misses 2297 # DTB misses -system.cpu1.itb.accesses 41952900 # DTB accesses -system.cpu1.numCycles 125141481 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 41922091 # ITB inst accesses +system.cpu1.itb.hits 41919801 # DTB hits +system.cpu1.itb.misses 2290 # DTB misses +system.cpu1.itb.accesses 41922091 # DTB accesses +system.cpu1.numCycles 125017818 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51908432 # Number of instructions committed -system.cpu1.committedOps 63413187 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5363692 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2715 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5566331294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.410812 # CPI: cycles per instruction -system.cpu1.ipc 0.414798 # IPC: instructions per cycle +system.cpu1.committedInsts 51886096 # Number of instructions committed +system.cpu1.committedOps 63386159 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5353179 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2738 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5566469050 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.409467 # CPI: cycles per instruction +system.cpu1.ipc 0.415030 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed -system.cpu1.tickCycles 105428618 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 19712863 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 231919 # number of replacements -system.cpu1.dcache.tags.tagsinuse 484.812111 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19337078 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 232252 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 83.259038 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90437090000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.812111 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.946899 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.946899 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 279 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 54 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.650391 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39720944 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39720944 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11670097 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11670097 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7386354 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7386354 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66295 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 66295 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88787 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88787 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80732 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80732 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19056451 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19056451 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19122746 # number of overall hits -system.cpu1.dcache.overall_hits::total 19122746 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 184750 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 184750 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 167503 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 167503 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35001 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 35001 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17741 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17741 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23478 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23478 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 352253 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 352253 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 387254 # number of overall misses -system.cpu1.dcache.overall_misses::total 387254 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2719987000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2719987000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4150031500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4150031500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326839500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 326839500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548823500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 548823500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 416500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 416500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6870018500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6870018500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6870018500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6870018500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11854847 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11854847 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7553857 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7553857 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 101296 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 101296 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106528 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 106528 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104210 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 104210 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19408704 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19408704 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19510000 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19510000 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015584 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.015584 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022174 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.022174 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.345532 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.345532 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.166538 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.166538 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225295 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225295 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.018149 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.018149 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019849 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.019849 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14722.527740 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14722.527740 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24775.863716 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24775.863716 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18422.834113 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18422.834113 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23376.075475 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23376.075475 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed +system.cpu1.tickCycles 105304281 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 19713537 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 231375 # number of replacements +system.cpu1.dcache.tags.tagsinuse 483.037999 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19321104 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 231701 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 83.388091 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90467560500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 483.037999 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.943434 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.943434 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 326 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 253 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 73 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.636719 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 39693132 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39693132 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11664966 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11664966 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7379255 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7379255 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66113 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 66113 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88582 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 88582 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80498 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 80498 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19044221 # 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number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 548137000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 684500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 684500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6872885000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6872885000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6872885000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6872885000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11849308 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11849308 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7546523 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7546523 # 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number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015557 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.015557 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022165 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.022165 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.346031 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.346031 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.166350 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.166350 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225594 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225594 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.018128 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.018128 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019828 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.019828 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14751.790151 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14751.790151 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24831.471052 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24831.471052 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18429.112921 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18429.112921 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23374.712154 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23374.712154 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19503.080172 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19503.080172 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17740.342256 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17740.342256 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19546.898552 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19546.898552 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17778.135605 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17778.135605 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1548,148 +1546,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 138789 # number of writebacks -system.cpu1.dcache.writebacks::total 138789 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18309 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 18309 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62144 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 62144 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12262 # 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number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5479 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23478 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23478 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 271800 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 271800 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 305289 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 305289 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17142 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17142 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14413 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14413 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31555 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31555 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2292018500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2292018500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2517101000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2517101000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 540422500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 540422500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93861500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93861500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 525354500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 525354500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 407500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 407500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4809119500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4809119500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5349542000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5349542000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2935336500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2935336500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2447202500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2447202500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5382539000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5382539000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014040 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014040 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013948 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013948 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.330605 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.330605 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051432 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051432 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225295 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225295 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014004 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014004 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015648 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015648 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.756604 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.756604 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23890.707011 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23890.707011 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16137.313745 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16137.313745 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17131.137069 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17131.137069 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22376.458813 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22376.458813 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 138377 # number of writebacks +system.cpu1.dcache.writebacks::total 138377 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18221 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 18221 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62038 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 62038 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12225 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12225 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 80259 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 80259 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 80259 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 80259 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166121 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166121 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105230 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105230 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33463 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 33463 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5451 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5451 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23450 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23450 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 271351 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 271351 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 304814 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 304814 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17128 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17128 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14405 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14405 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31533 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31533 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2295109000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2295109000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2517034000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2517034000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 544638000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 544638000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 92810500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 92810500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524700000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524700000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 671500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 671500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4812143000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4812143000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5356781000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5356781000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2934873000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2934873000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2446602500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2446602500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5381475500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5381475500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014019 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014019 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013944 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013944 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331005 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331005 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051300 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051300 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225594 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225594 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013990 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013990 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015634 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015634 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13815.887215 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13815.887215 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23919.357598 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23919.357598 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16275.827033 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16275.827033 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17026.325445 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17026.325445 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22375.266525 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22375.266525 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17693.596394 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17693.596394 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17522.878322 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17522.878322 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171236.524326 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171236.524326 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169791.334212 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169791.334212 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170576.422120 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170576.422120 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17734.016090 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17734.016090 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17573.933612 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17573.933612 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171349.427837 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171349.427837 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169843.977785 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169843.977785 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170661.703612 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170661.703612 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 1046573 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.334165 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 40901496 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 1047085 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.062250 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72079197500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.334165 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975262 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975262 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 1042125 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.329120 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 40875126 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 1042637 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.203602 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72106351500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.329120 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975252 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975252 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 461 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 84944247 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 84944247 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 40901496 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 40901496 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 40901496 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 40901496 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 40901496 # number of overall hits -system.cpu1.icache.overall_hits::total 40901496 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 1047085 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 1047085 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 1047085 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 1047085 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 1047085 # number of overall misses -system.cpu1.icache.overall_misses::total 1047085 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9273780500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9273780500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9273780500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9273780500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9273780500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9273780500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 41948581 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 41948581 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 41948581 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 41948581 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 41948581 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 41948581 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024961 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024961 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024961 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024961 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024961 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024961 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8856.759957 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8856.759957 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8856.759957 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8856.759957 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8856.759957 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8856.759957 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 84878163 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 84878163 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 40875126 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 40875126 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 40875126 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 40875126 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 40875126 # number of overall hits +system.cpu1.icache.overall_hits::total 40875126 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 1042637 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 1042637 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 1042637 # 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average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8859.858704 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8859.858704 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8859.858704 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8859.858704 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8859.858704 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1698,443 +1696,453 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # 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number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10126000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024873 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024873 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024873 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024873 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8359.858704 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8359.858704 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8359.858704 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8359.858704 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89610.619469 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89610.619469 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89610.619469 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 270311 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 270335 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 270674 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 270706 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 70297 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 69395 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15632.228782 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 2434679 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 84293 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 28.883525 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 70190 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 69559 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15624.003278 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 2421583 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 84278 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 28.733276 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6105.214353 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.591846 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.935526 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5648.623425 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2320.323151 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1496.540481 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.372633 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003698 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000057 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.344765 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.141621 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.091342 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.954116 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1218 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13618 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 684 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 526 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 6091.947681 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 59.671167 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.103493 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5612.930096 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2321.677903 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1537.672938 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.371823 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003642 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.342586 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.141704 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093852 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.953613 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1225 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13444 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 697 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 522 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 28 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6069 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7234 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074341 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.831177 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 43042452 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 43042452 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 33942 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2703 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 36645 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 138788 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 138788 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2017 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2017 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1035 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1035 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37928 # 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number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 904893000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1316095995 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1316095995 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 14241000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3131500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 904893000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2483854995 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3406120495 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 14241000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3131500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 904893000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2483854995 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1238467331 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4644587826 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9222000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2797805500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2807027500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2338455000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2338455000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9222000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5136260500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5145482500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025922 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.935580 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.935580 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955916 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955916 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.483363 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.483363 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026383 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.358091 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.358091 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020292 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.075581 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.391286 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101089 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020292 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.075581 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026383 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.391286 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.934999 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.934999 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.956841 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.956841 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.484774 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.484774 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026454 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.360188 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.360188 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393169 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.101738 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021530 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.078816 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026454 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393169 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.126861 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18192.640693 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36634.064770 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17117.161062 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17117.161062 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15518.669518 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15518.669518 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32552.159580 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32552.159580 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32780.923077 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17762.970036 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17762.970036 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22604.066814 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24613.243928 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19367.709815 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14454.751131 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32780.923077 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22604.066814 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36634.064770 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27055.237992 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163234.395053 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162701.506810 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162282.557413 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162282.557413 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81862.831858 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162799.635557 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162510.831123 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.127654 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18325.421941 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35187.729600 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17114.680114 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17114.680114 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15512.078802 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15512.078802 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 287000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 287000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32631.727491 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32631.727491 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32807.374375 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17821.205078 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17821.205078 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22655.468961 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24652.378262 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19588.720770 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14169.683258 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32807.374375 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22655.468961 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35187.729600 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26791.268133 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163346.888136 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162811.176846 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162336.341548 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162336.341548 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81610.619469 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162885.247201 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 162595.035708 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 81434 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1353329 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 14413 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 511562 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1270278 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 44724 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 77037 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43004 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89317 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 97290 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 79982 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1047085 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 561570 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 81005 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1348099 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 14405 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 510462 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1265020 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 43516 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 77320 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42972 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89288 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 97251 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 79776 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1042637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 559861 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3121460 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1041902 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7336 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 72984 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 4243682 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67020672 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29874703 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11696 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 138580 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 97045651 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 1176077 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 3823827 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.296126 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.456547 # Request fanout histogram +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3108261 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1040223 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7202 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71706 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 4227392 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66736000 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29812791 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11216 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135068 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 96695075 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 1172897 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 3809713 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.296141 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.456554 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2691491 70.39% 70.39% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1132336 29.61% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2681500 70.39% 70.39% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1128213 29.61% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 3823827 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1513117496 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 3809713 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1507501992 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 87426499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 87443999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1570862868 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1564193862 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 471839695 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 470956198 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4412000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4398499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 38355467 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 37948980 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31014 # Transaction distribution -system.iobus.trans_dist::ReadResp 31014 # Transaction distribution +system.iobus.trans_dist::ReadReq 31013 # Transaction distribution +system.iobus.trans_dist::ReadResp 31013 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 59422 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) @@ -2142,7 +2150,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2158,16 +2166,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2183,10 +2191,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484073 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -2197,7 +2205,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2227,23 +2235,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187550442 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187545199 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36446 # number of replacements -system.iocache.tags.tagsinuse 14.479147 # Cycle average of tags in use +system.iocache.tags.replacements 36462 # number of replacements +system.iocache.tags.tagsinuse 14.479963 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36462 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270355599000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.479147 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904947 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904947 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270370198000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.479963 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904998 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904998 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2257,14 +2265,14 @@ system.iocache.demand_misses::realview.ide 256 # system.iocache.demand_misses::total 256 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 256 # number of overall misses system.iocache.overall_misses::total 256 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32686877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32686877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4278417565 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4278417565 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32686877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32686877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32686877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32686877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32688877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32688877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4277206322 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4277206322 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32688877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32688877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32688877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32688877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2281,24 +2289,24 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 127683.113281 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 127683.113281 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118110.025536 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118110.025536 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 127683.113281 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 127683.113281 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 127683.113281 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 127683.113281 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 127690.925781 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 127690.925781 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118076.587953 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118076.587953 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 127690.925781 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127690.925781 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 127690.925781 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127690.925781 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5.250000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses @@ -2307,14 +2315,14 @@ system.iocache.demand_mshr_misses::realview.ide 256 system.iocache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 256 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 256 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19886877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19886877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2467217565 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2467217565 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19886877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19886877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19886877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19886877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19888877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19888877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2466006322 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2466006322 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19888877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19888877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19888877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19888877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2323,602 +2331,576 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77683.113281 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 77683.113281 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68110.025536 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68110.025536 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 77683.113281 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 77683.113281 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 77683.113281 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 77683.113281 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 77690.925781 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 77690.925781 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68076.587953 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68076.587953 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 77690.925781 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 77690.925781 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 77690.925781 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 77690.925781 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 135320 # number of replacements -system.l2c.tags.tagsinuse 64080.552826 # Cycle average of tags in use -system.l2c.tags.total_refs 445963 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 199765 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.232438 # Average number of references to valid blocks. +system.l2c.tags.replacements 134724 # number of replacements +system.l2c.tags.tagsinuse 64068.233504 # Cycle average of tags in use +system.l2c.tags.total_refs 443602 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 199053 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.228562 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12788.353662 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.367527 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034390 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7205.553479 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2096.784928 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32107.700654 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 26.808299 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851993 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4024.713832 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1527.951308 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4232.432754 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.195135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001058 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.109948 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.031994 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.489925 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000409 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061412 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023315 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.977792 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 29238 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 35135 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5585 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23534 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 72 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3030 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31767 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.446136 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.536118 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5845545 # Number of tag accesses -system.l2c.tags.data_accesses 5845545 # Number of data accesses -system.l2c.Writeback_hits::writebacks 233248 # number of Writeback hits -system.l2c.Writeback_hits::total 233248 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3007 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 942 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3949 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 254 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 81 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 335 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2177 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6272 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 343 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 65 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 44646 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 47683 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46675 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 154 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 31 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 21738 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11221 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8044 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 180600 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 343 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 65 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 44646 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51778 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 46675 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 154 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 31 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 21738 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13398 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 8044 # number of demand (read+write) hits -system.l2c.demand_hits::total 186872 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 343 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 65 # number of overall hits -system.l2c.overall_hits::cpu0.inst 44646 # number of overall hits -system.l2c.overall_hits::cpu0.data 51778 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46675 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 154 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 31 # number of overall hits -system.l2c.overall_hits::cpu1.inst 21738 # number of overall hits -system.l2c.overall_hits::cpu1.data 13398 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 8044 # number of overall hits -system.l2c.overall_hits::total 186872 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 8773 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4095 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12868 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 811 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1218 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2029 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 10812 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8416 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19228 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 116 # number of ReadSharedReq misses +system.l2c.tags.occ_blocks::writebacks 12835.902941 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.531822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.025215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7257.127456 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2101.817094 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32009.024605 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 30.126345 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4045.876721 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1535.093827 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4184.707478 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.195860 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001046 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.110735 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.032071 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.488419 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000460 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061735 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023424 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.063854 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.977604 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 29296 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 34966 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 113 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5383 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 23800 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 66 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 313 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2923 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 31711 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.447021 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.001022 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.533539 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5827626 # Number of tag accesses +system.l2c.tags.data_accesses 5827626 # Number of data accesses +system.l2c.Writeback_hits::writebacks 232709 # number of Writeback hits +system.l2c.Writeback_hits::total 232709 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3025 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 939 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3964 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 83 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 340 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4055 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2183 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6238 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 387 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 52 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 44381 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 47292 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46189 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 171 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 33 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 21681 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11241 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8230 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 179657 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 387 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 52 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 44381 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 51347 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 46189 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 171 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 21681 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13424 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 8230 # number of demand (read+write) hits +system.l2c.demand_hits::total 185895 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 387 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 52 # number of overall hits +system.l2c.overall_hits::cpu0.inst 44381 # number of overall hits +system.l2c.overall_hits::cpu0.data 51347 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 46189 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 171 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits +system.l2c.overall_hits::cpu1.inst 21681 # number of overall hits +system.l2c.overall_hits::cpu1.data 13424 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 8230 # number of overall hits +system.l2c.overall_hits::total 185895 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 8753 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4074 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12827 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 797 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1213 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2010 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 10969 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8454 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19423 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 121 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 19540 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 8519 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 129160 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 40 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 5871 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 2660 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 9190 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 175098 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 116 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 19546 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8542 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 128715 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 43 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 5890 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 2696 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8977 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 174531 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 121 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 19540 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 19331 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 129160 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 40 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5871 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 11076 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 9190 # number of demand (read+write) misses -system.l2c.demand_misses::total 194326 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 116 # number of overall misses +system.l2c.demand_misses::cpu0.inst 19546 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19511 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 128715 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 43 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5890 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 11150 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 8977 # number of demand (read+write) misses +system.l2c.demand_misses::total 193954 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 121 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 19540 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.193442 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.492738 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.238189 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.018868 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.305677 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.275354 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735918 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.453732 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.510584 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.238189 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.018868 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.305677 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.275354 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735918 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200935 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.213485 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.453732 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521706 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.510584 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20769.507597 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.255032 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20767.521712 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20885.821832 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20753.915911 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20806.218905 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89188.348983 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72345.398628 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 81857.334088 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77691.337011 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78237.406015 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 89927.343100 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77710.489347 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79111.646884 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88461.079428 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79837.204490 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73271.578187 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 88670.663637 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76340.517241 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84163.292502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73981.434978 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 87799.734481 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75884.297521 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 293000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70210.743167 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79837.204490 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 93208.507208 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82637.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72396.539969 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73271.578187 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111831.236888 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 88670.663637 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69736.860959 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84163.292502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91525.863287 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82139.534884 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72162.844037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73981.434978 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109176.730645 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 87799.734481 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.262082 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145268.963706 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154989.231883 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138126.775272 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145282.453341 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141435.452825 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182391.728237 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145381.657323 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 155041.433892 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138140.158749 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145335.820896 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141466.544719 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62733.362522 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161051.093211 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60858.407080 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145275.125986 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 148940.773085 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161058.491815 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60606.194690 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145360.715532 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 148983.329753 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 38679 # Transaction distribution -system.membus.trans_dist::ReadResp 214027 # Transaction distribution -system.membus.trans_dist::WriteReq 31171 # Transaction distribution -system.membus.trans_dist::WriteResp 31171 # Transaction distribution -system.membus.trans_dist::Writeback 139502 # Transaction distribution -system.membus.trans_dist::CleanEvict 18408 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78648 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41625 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15041 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 39591 # Transaction distribution -system.membus.trans_dist::ReadExResp 19084 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 175348 # Transaction distribution +system.membus.trans_dist::ReadReq 38664 # Transaction distribution +system.membus.trans_dist::ReadResp 213442 # Transaction distribution +system.membus.trans_dist::WriteReq 31161 # Transaction distribution +system.membus.trans_dist::WriteResp 31161 # Transaction distribution +system.membus.trans_dist::Writeback 139337 # Transaction distribution +system.membus.trans_dist::CleanEvict 18210 # Transaction distribution +system.membus.trans_dist::UpgradeReq 78893 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41609 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14967 # Transaction distribution +system.membus.trans_dist::ReadExReq 39746 # Transaction distribution +system.membus.trans_dist::ReadExResp 19293 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174778 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 682494 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 805212 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 914134 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 681524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 804190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108938 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108938 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 913128 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19261796 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19455462 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21772582 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 126350 # Total snoops (count) -system.membus.snoop_fanout::samples 599467 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29428 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19228072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19421637 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21739781 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 126569 # Total snoops (count) +system.membus.snoop_fanout::samples 598906 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 599467 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 598906 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 599467 # Request fanout histogram -system.membus.reqLayer0.occupancy 91393000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 598906 # Request fanout histogram +system.membus.reqLayer0.occupancy 91147500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 24328 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12942500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12904500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1014707988 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1003618732 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1166663343 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1163956699 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64473559 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64493538 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2951,46 +2933,46 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 38683 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 520875 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31171 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31171 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 372774 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 100063 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 82453 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41960 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 124413 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51599 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51599 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 482207 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 38668 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 519865 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31161 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31161 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 372085 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 99404 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 82727 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 124676 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 24 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 24 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51768 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51768 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 481212 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1095171 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 404182 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1499353 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32852839 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6925951 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39778790 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 466118 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1289558 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.161505 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.367996 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1091980 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 404567 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1496547 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32727326 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6930535 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39657861 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 466410 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1287380 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.161360 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.367862 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1081288 83.85% 83.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 208270 16.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1079649 83.86% 83.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 207731 16.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1289558 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 856703495 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1287380 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 861414818 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 361500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 633166148 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 631551677 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 285761511 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 286263459 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 82662bafe..409c3a759 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.625395 # Number of seconds simulated -sim_ticks 2625394935000 # Number of ticks simulated -final_tick 2625394935000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.825406 # Number of seconds simulated +sim_ticks 2825405893500 # Number of ticks simulated +final_tick 2825405893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71798 # Simulator instruction rate (inst/s) -host_op_rate 87106 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1566670818 # Simulator tick rate (ticks/s) -host_mem_usage 647044 # Number of bytes of host memory used -host_seconds 1675.78 # Real time elapsed on the host -sim_insts 120317196 # Number of instructions simulated -sim_ops 145970023 # Number of ops (including micro ops) simulated +host_inst_rate 89977 # Simulator instruction rate (inst/s) +host_op_rate 109159 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2115602490 # Simulator tick rate (ticks/s) +host_mem_usage 657340 # Number of bytes of host memory used +host_seconds 1335.51 # Real time elapsed on the host +sim_insts 120165205 # Number of instructions simulated +sim_ops 145782922 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1152320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1224232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8325184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 318816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 736276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 690624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1275648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1290856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8427776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 182944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 606480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 427776 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12451228 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1152320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 318816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1471136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9003520 # Number of bytes written to this memory +system.physmem.bytes_read::total 12214872 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1275648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 182944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1458592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8756928 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9021084 # Number of bytes written to this memory +system.physmem.bytes_written::total 8774492 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 20252 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19649 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 130081 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11525 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 10791 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22179 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20690 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131684 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2926 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9496 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6684 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197406 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 140680 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193712 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 136827 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145071 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 438913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 466304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3171022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 121435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 263055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4742611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 438913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 121435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 560348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3429396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6675 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3436086 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3429396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 438913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 472979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3171022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 121435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 280459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 263055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8178698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197407 # Number of read requests accepted -system.physmem.writeReqs 145071 # Number of write requests accepted -system.physmem.readBursts 197407 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 145071 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12624448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 9033728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12451292 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9021084 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 141218 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 451492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 456875 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2982855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 214652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 151403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4323227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 451492 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3099352 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3105569 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3099352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 451492 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 463077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2982855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 214667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 151403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7428796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 193713 # Number of read requests accepted +system.physmem.writeReqs 141218 # Number of write requests accepted +system.physmem.readBursts 193713 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141218 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12387136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10496 # Total number of bytes read from write queue +system.physmem.bytesWritten 8786752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12214936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8774492 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 50333 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12702 # Per bank write bursts -system.physmem.perBankRdBursts::1 12398 # Per bank write bursts -system.physmem.perBankRdBursts::2 12869 # Per bank write bursts -system.physmem.perBankRdBursts::3 12803 # Per bank write bursts -system.physmem.perBankRdBursts::4 14881 # Per bank write bursts -system.physmem.perBankRdBursts::5 12147 # Per bank write bursts -system.physmem.perBankRdBursts::6 12755 # Per bank write bursts -system.physmem.perBankRdBursts::7 12276 # Per bank write bursts -system.physmem.perBankRdBursts::8 11968 # Per bank write bursts -system.physmem.perBankRdBursts::9 12044 # Per bank write bursts -system.physmem.perBankRdBursts::10 11861 # Per bank write bursts -system.physmem.perBankRdBursts::11 11195 # Per bank write bursts -system.physmem.perBankRdBursts::12 11579 # Per bank write bursts -system.physmem.perBankRdBursts::13 12354 # Per bank write bursts -system.physmem.perBankRdBursts::14 11791 # Per bank write bursts -system.physmem.perBankRdBursts::15 11634 # Per bank write bursts -system.physmem.perBankWrBursts::0 9169 # Per bank write bursts -system.physmem.perBankWrBursts::1 9145 # Per bank write bursts -system.physmem.perBankWrBursts::2 9512 # Per bank write bursts -system.physmem.perBankWrBursts::3 9193 # Per bank write bursts -system.physmem.perBankWrBursts::4 8772 # Per bank write bursts -system.physmem.perBankWrBursts::5 8759 # Per bank write bursts -system.physmem.perBankWrBursts::6 9221 # Per bank write bursts -system.physmem.perBankWrBursts::7 8821 # Per bank write bursts -system.physmem.perBankWrBursts::8 8638 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 49946 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12421 # Per bank write bursts +system.physmem.perBankRdBursts::1 11965 # Per bank write bursts +system.physmem.perBankRdBursts::2 12291 # Per bank write bursts +system.physmem.perBankRdBursts::3 13088 # Per bank write bursts +system.physmem.perBankRdBursts::4 14558 # Per bank write bursts +system.physmem.perBankRdBursts::5 12211 # Per bank write bursts +system.physmem.perBankRdBursts::6 11940 # Per bank write bursts +system.physmem.perBankRdBursts::7 12041 # Per bank write bursts +system.physmem.perBankRdBursts::8 12092 # Per bank write bursts +system.physmem.perBankRdBursts::9 12171 # Per bank write bursts +system.physmem.perBankRdBursts::10 11769 # Per bank write bursts +system.physmem.perBankRdBursts::11 10768 # Per bank write bursts +system.physmem.perBankRdBursts::12 11340 # Per bank write bursts +system.physmem.perBankRdBursts::13 12292 # Per bank write bursts +system.physmem.perBankRdBursts::14 11321 # Per bank write bursts +system.physmem.perBankRdBursts::15 11281 # Per bank write bursts +system.physmem.perBankWrBursts::0 9078 # Per bank write bursts +system.physmem.perBankWrBursts::1 8838 # Per bank write bursts +system.physmem.perBankWrBursts::2 9120 # Per bank write bursts +system.physmem.perBankWrBursts::3 9597 # Per bank write bursts +system.physmem.perBankWrBursts::4 8379 # Per bank write bursts +system.physmem.perBankWrBursts::5 8806 # Per bank write bursts +system.physmem.perBankWrBursts::6 8536 # Per bank write bursts +system.physmem.perBankWrBursts::7 8489 # Per bank write bursts +system.physmem.perBankWrBursts::8 8658 # Per bank write bursts system.physmem.perBankWrBursts::9 8679 # Per bank write bursts -system.physmem.perBankWrBursts::10 8601 # Per bank write bursts -system.physmem.perBankWrBursts::11 8338 # Per bank write bursts -system.physmem.perBankWrBursts::12 8547 # Per bank write bursts -system.physmem.perBankWrBursts::13 8875 # Per bank write bursts -system.physmem.perBankWrBursts::14 8631 # Per bank write bursts -system.physmem.perBankWrBursts::15 8251 # Per bank write bursts +system.physmem.perBankWrBursts::10 8573 # Per bank write bursts +system.physmem.perBankWrBursts::11 8021 # Per bank write bursts +system.physmem.perBankWrBursts::12 8348 # Per bank write bursts +system.physmem.perBankWrBursts::13 8584 # Per bank write bursts +system.physmem.perBankWrBursts::14 7909 # Per bank write bursts +system.physmem.perBankWrBursts::15 7678 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 2625394672500 # Total gap between requests +system.physmem.numWrRetry 13 # Number of times write queue was full causing retry +system.physmem.totGap 2825405630500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 551 # Read request sizes (log2) +system.physmem.readPktSize::2 550 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3086 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 193742 # Read request sizes (log2) +system.physmem.readPktSize::6 190049 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 140680 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 60453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 775 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 136827 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 58643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71509 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,159 +188,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90794 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 238.541225 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.856216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 301.373578 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 48956 53.92% 53.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17750 19.55% 73.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6013 6.62% 80.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3452 3.80% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2808 3.09% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1564 1.72% 88.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 893 0.98% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 995 1.10% 90.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8363 9.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90794 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7077 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.872686 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 551.008017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7075 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87370 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.346618 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.604135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 304.406981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46631 53.37% 53.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17108 19.58% 72.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5841 6.69% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3374 3.86% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2711 3.10% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1534 1.76% 88.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 893 1.02% 89.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1014 1.16% 90.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8264 9.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87370 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6825 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.358242 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 561.081040 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6823 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7077 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7077 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.945175 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.553311 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.579174 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5904 83.43% 83.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 368 5.20% 88.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 217 3.07% 91.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 59 0.83% 92.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 82 1.16% 93.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 159 2.25% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 25 0.35% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.17% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.18% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.16% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 10 0.14% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.08% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 165 2.33% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.08% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.08% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.14% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.07% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7077 # Writes before turning the bus around for reads -system.physmem.totQLat 6986626052 # Total ticks spent queuing -system.physmem.totMemAccLat 10685194802 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 986285000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35418.90 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6825 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6825 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.116190 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.646323 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.038338 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5646 82.73% 82.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 406 5.95% 88.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 199 2.92% 91.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 55 0.81% 92.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 78 1.14% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 151 2.21% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 25 0.37% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.16% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 15 0.22% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 9 0.13% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 2.39% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.10% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 8 0.12% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.23% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6825 # Writes before turning the bus around for reads +system.physmem.totQLat 6500326386 # Total ticks spent queuing +system.physmem.totMemAccLat 10129370136 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 967745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33584.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54168.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.44 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.74 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52334.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.34 # Average write queue length when enqueuing -system.physmem.readRowHits 164764 # Number of row buffer hits during reads -system.physmem.writeRowHits 82850 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.69 # Row buffer hit rate for writes -system.physmem.avgGap 7665878.31 # Average gap between requests -system.physmem.pageHitRate 73.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 357081480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 194836125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 802081800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 470396160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 75099546585 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1509358032750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1757759761380 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.522942 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2510844795677 # Time in different power states -system.physmem_0.memoryStateTime::REF 87667580000 # Time in different power states +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.47 # Average write queue length when enqueuing +system.physmem.readRowHits 161846 # Number of row buffer hits during reads +system.physmem.writeRowHits 81625 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.44 # Row buffer hit rate for writes +system.physmem.avgGap 8435784.18 # Average gap between requests +system.physmem.pageHitRate 73.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 343821240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 187600875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 784017000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 459062640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184541675760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79593993450 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625423449500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1891333620465 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.402761 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2703936458200 # Time in different power states +system.physmem_0.memoryStateTime::REF 94346460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 26879018073 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27121665550 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 329321160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179689125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 736515000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 444268800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74435410800 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1509940608000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1757543599365 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.440607 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2511823665901 # Time in different power states -system.physmem_1.memoryStateTime::REF 87667580000 # Time in different power states +system.physmem_1.actEnergy 316695960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 172800375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 725657400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 430596000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184541675760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 78590048175 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626304103250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1891081576920 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.313555 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705408031049 # Time in different power states +system.physmem_1.memoryStateTime::REF 94346460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 25903669599 # Time in different power states +system.physmem_1.memoryStateTime::ACT 25651382451 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory @@ -351,30 +352,30 @@ system.realview.nvmem.bytes_inst_read::total 320 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 51763361 # Number of BP lookups -system.cpu0.branchPred.condPredicted 23412597 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 921572 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 31250401 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 23297364 # Number of BTB hits +system.cpu0.branchPred.lookups 24021626 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15717395 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 977579 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 14633586 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 10784998 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 74.550608 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15315613 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29376 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.700308 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3879887 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32532 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -405,80 +406,78 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 63347 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 63347 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 24259 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18763 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 20325 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 43022 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 472.792990 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2838.942862 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 41882 97.35% 97.35% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 877 2.04% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 115 0.27% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 113 0.26% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 6 0.01% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 23 0.05% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-73727 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 43022 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 16160 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9833.168317 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8304.443400 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6846.428458 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 15169 93.87% 93.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 911 5.64% 99.50% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 54 0.33% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 3 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 20 0.12% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 16160 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 95658285656 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.461466 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.505385 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 95607533656 99.95% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 37952000 0.04% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 6012000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 3722000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 1321500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 760000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 604000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 360500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 20000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 95658285656 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5176 77.00% 77.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1546 23.00% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6722 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 63347 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 65547 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 65547 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26411 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18806 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 20330 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 45217 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 420.151713 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2682.973536 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 44150 97.64% 97.64% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 821 1.82% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 92 0.20% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 122 0.27% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 7 0.02% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 22 0.05% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 45217 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 15532 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9209.084471 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 7773.401889 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5863.053322 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 14685 94.55% 94.55% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 794 5.11% 99.66% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 47 0.30% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 15532 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 89510783948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.549501 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.505567 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 89461994948 99.95% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 35577000 0.04% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 6153500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 3637000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1264000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 750500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 798000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 605000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 4000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 89510783948 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5141 79.20% 79.20% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1350 20.80% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6491 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65547 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 63347 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6722 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65547 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6491 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6722 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 70069 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6491 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 72038 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22737235 # DTB read hits -system.cpu0.dtb.read_misses 54172 # DTB read misses -system.cpu0.dtb.write_hits 16921500 # DTB write hits -system.cpu0.dtb.write_misses 9175 # DTB write misses +system.cpu0.dtb.read_hits 17771522 # DTB read hits +system.cpu0.dtb.read_misses 55962 # DTB read misses +system.cpu0.dtb.write_hits 14661221 # DTB write hits +system.cpu0.dtb.write_misses 9585 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 141 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1882 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 322 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2338 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 854 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 22791407 # DTB read accesses -system.cpu0.dtb.write_accesses 16930675 # DTB write accesses +system.cpu0.dtb.perms_faults 800 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17827484 # DTB read accesses +system.cpu0.dtb.write_accesses 14670806 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 39658735 # DTB hits -system.cpu0.dtb.misses 63347 # DTB misses -system.cpu0.dtb.accesses 39722082 # DTB accesses +system.cpu0.dtb.hits 32432743 # DTB hits +system.cpu0.dtb.misses 65547 # DTB misses +system.cpu0.dtb.accesses 32498290 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -508,62 +507,57 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 10275 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10275 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4076 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6085 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 114 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 10161 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 480.267690 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2390.213266 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9738 95.84% 95.84% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 133 1.31% 97.15% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 215 2.12% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 37 0.36% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 9 0.09% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 15 0.15% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 10161 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11438.934123 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 10140.740913 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6204.580963 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 871 32.24% 32.24% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1681 62.21% 94.45% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 53 1.96% 96.41% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 85 3.15% 99.56% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.26% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 22643799124 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.979659 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.141451 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 461404000 2.04% 2.04% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 22181693124 97.96% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 593000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 109000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 22643799124 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2268 87.64% 87.64% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 320 12.36% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2588 # Table walker page sizes translated +system.cpu0.itb.walker.walks 10460 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10460 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4240 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6125 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 95 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 10365 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 435.745297 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2168.024140 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9957 96.06% 96.06% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 147 1.42% 97.48% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 193 1.86% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 32 0.31% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 11 0.11% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 17 0.16% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 3 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 10365 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2678 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10848.207618 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9582.239797 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5620.252827 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1037 38.72% 38.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1516 56.61% 95.33% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 52 1.94% 97.27% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 65 2.43% 99.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 5 0.19% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2678 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 20779406712 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.976236 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.152563 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 494503000 2.38% 2.38% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 20284294712 97.62% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 517000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 92000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 20779406712 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2260 87.50% 87.50% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 323 12.50% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2583 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10275 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10275 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10460 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10460 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2588 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 12863 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 70928349 # ITB inst hits -system.cpu0.itb.inst_misses 10275 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2583 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2583 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13043 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 37759439 # ITB inst hits +system.cpu0.itb.inst_misses 10460 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -572,1041 +566,1029 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2365 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2357 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1936 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1912 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 70938624 # ITB inst accesses -system.cpu0.itb.hits 70928349 # DTB hits -system.cpu0.itb.misses 10275 # DTB misses -system.cpu0.itb.accesses 70938624 # DTB accesses -system.cpu0.numCycles 192976868 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 37769899 # ITB inst accesses +system.cpu0.itb.hits 37759439 # DTB hits +system.cpu0.itb.misses 10460 # DTB misses +system.cpu0.itb.accesses 37769899 # DTB accesses +system.cpu0.numCycles 130135672 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19363908 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 190332929 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 51763361 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 38612977 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 166709106 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5608958 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 145099 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 54692 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 348676 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 420281 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 85262 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 70928958 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 257958 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 4691 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 189931503 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.225932 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.310916 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 18741348 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 112674064 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 24021626 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 14664885 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 105564363 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2824766 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 148935 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 59402 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 359448 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 427042 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 91226 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 37760092 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 271445 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 4846 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 126804147 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.071967 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.260919 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 88125904 46.40% 46.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 29232702 15.39% 61.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14108338 7.43% 69.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 58464559 30.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64261882 50.68% 50.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 21462384 16.93% 67.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8772204 6.92% 74.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 32307677 25.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 189931503 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.268236 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.986299 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 24608865 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 101406874 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 56677604 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4757932 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2480228 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 2944179 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 328448 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 148845488 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3759445 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2480228 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 33020653 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11928133 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 79389996 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 52895431 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10217062 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 132354164 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1007004 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1382043 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 149840 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 52195 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6188026 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 135879963 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 611395498 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 146969281 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9373 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 124973310 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10906650 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2656416 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2518561 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 22027855 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 23660512 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 18424443 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1639164 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2432445 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 129487187 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1661777 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 127665829 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 454854 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10484678 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21309646 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 116701 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 189931503 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.672168 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.963951 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 126804147 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.184589 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.865820 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19721438 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 59617090 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 41434685 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4962697 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1068237 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3055964 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 348356 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 110795648 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3978318 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1068237 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 25470078 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12211623 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 36823403 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 40512045 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10718761 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 105720614 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1057290 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1452767 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 161700 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 58122 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6514709 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 109806374 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 482725120 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 121004760 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9383 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 98259136 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11547235 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1229554 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1088238 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12335468 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18754417 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 16214275 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1701393 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2256069 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 102765106 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1695392 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 100794287 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 484302 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9532947 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22407435 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 122350 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 126804147 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.794882 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.031887 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 116041258 61.10% 61.10% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 32572628 17.15% 78.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 29941917 15.76% 94.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 10293469 5.42% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1082195 0.57% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 70515231 55.61% 55.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 23338464 18.41% 74.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 22507800 17.75% 91.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 9330414 7.36% 99.12% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1112209 0.88% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 29 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 189931503 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 126804147 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 10298963 43.90% 43.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 129 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5415712 23.09% 66.99% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 7742693 33.01% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 9354884 40.60% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 74 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5601126 24.31% 64.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8088042 35.10% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 86175456 67.50% 67.50% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 106512 0.08% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 7179 0.01% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 23410232 18.34% 85.93% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 17964178 14.07% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 66470143 65.95% 65.95% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 93430 0.09% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.04% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8105 0.01% 66.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18478690 18.33% 84.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 15741645 15.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 127665829 # Type of FU issued -system.cpu0.iq.rate 0.661560 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 23457497 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.183741 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 469142790 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 141641253 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 124187141 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32722 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11272 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 151099696 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21358 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 349091 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 100794287 # Type of FU issued +system.cpu0.iq.rate 0.774532 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 23044126 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228625 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 351888789 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 114001116 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 98678663 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32360 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9725 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 123815106 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21034 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 363531 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1883461 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2555 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18950 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 972383 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1999131 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2544 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19035 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1014690 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 113459 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 340118 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 107294 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 362990 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2480228 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1536268 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 176000 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 131320075 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1068237 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1634305 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 175316 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 104635112 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 23660512 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 18424443 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 851631 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 24928 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 129599 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18950 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 275039 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 375413 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 650452 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 126634007 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 22982824 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 968597 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 18754417 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 16214275 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 876681 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 26796 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 125236 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19035 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 291770 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 399939 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 691709 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 99697701 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 18022679 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1031168 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 171111 # number of nop insts executed -system.cpu0.iew.exec_refs 40767921 # number of memory reference insts executed -system.cpu0.iew.exec_branches 24572908 # Number of branches executed -system.cpu0.iew.exec_stores 17785097 # Number of stores executed -system.cpu0.iew.exec_rate 0.656213 # Inst execution rate -system.cpu0.iew.wb_sent 126104266 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 124196865 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 63208416 # num instructions producing a value -system.cpu0.iew.wb_consumers 102222094 # num instructions consuming a value +system.cpu0.iew.exec_nop 174614 # number of nop insts executed +system.cpu0.iew.exec_refs 33573838 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16859604 # Number of branches executed +system.cpu0.iew.exec_stores 15551159 # Number of stores executed +system.cpu0.iew.exec_rate 0.766106 # Inst execution rate +system.cpu0.iew.wb_sent 99140543 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 98688388 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 51348142 # num instructions producing a value +system.cpu0.iew.wb_consumers 84871692 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.643584 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.618344 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.758350 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.605009 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9488534 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1545076 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 597321 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 186809549 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.646573 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.344397 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 8492759 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1573042 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 633433 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 125053157 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.760074 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.473514 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 128903317 69.00% 69.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 31993486 17.13% 86.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12242174 6.55% 92.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3077822 1.65% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4650551 2.49% 96.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2601023 1.39% 98.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1367878 0.73% 98.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 526295 0.28% 99.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1447003 0.77% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 80626724 64.47% 64.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 24772258 19.81% 84.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 8266840 6.61% 90.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3238221 2.59% 93.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3432782 2.75% 96.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1539199 1.23% 97.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1134355 0.91% 98.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 546479 0.44% 98.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1496299 1.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 186809549 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 99693903 # Number of instructions committed -system.cpu0.commit.committedOps 120785976 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 125053157 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 78998098 # Number of instructions committed +system.cpu0.commit.committedOps 95049599 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 39229111 # Number of memory references committed -system.cpu0.commit.loads 21777051 # Number of loads committed -system.cpu0.commit.membars 629182 # Number of memory barriers committed -system.cpu0.commit.branches 23976855 # Number of branches committed +system.cpu0.commit.refs 31954871 # Number of memory references committed +system.cpu0.commit.loads 16755286 # Number of loads committed +system.cpu0.commit.membars 647733 # Number of memory barriers committed +system.cpu0.commit.branches 16226575 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 105625598 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4749745 # Number of function calls committed. +system.cpu0.commit.int_insts 81983360 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1932291 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 81445291 67.43% 67.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 104395 0.09% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 7179 0.01% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.52% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 21777051 18.03% 85.55% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 17452060 14.45% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 62995577 66.28% 66.28% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 91046 0.10% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.37% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8105 0.01% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 16755286 17.63% 84.01% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 15199585 15.99% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 120785976 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1447003 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 292572702 # The number of ROB reads -system.cpu0.rob.rob_writes 263669539 # The number of ROB writes -system.cpu0.timesIdled 123127 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3045365 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5057813082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 99572209 # Number of Instructions Simulated -system.cpu0.committedOps 120664282 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.938060 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.938060 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.515980 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.515980 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 137228019 # number of integer regfile reads -system.cpu0.int_regfile_writes 78727155 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8192 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 446969794 # number of cc regfile reads -system.cpu0.cc_regfile_writes 47254034 # number of cc regfile writes -system.cpu0.misc_regfile_reads 263157526 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1194331 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 673421 # number of replacements -system.cpu0.dcache.tags.tagsinuse 483.801587 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 36230548 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 673933 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 53.759866 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 274448500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.801587 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.944925 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.944925 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 95049599 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1496299 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 222908078 # The number of ROB reads +system.cpu0.rob.rob_writes 208834787 # The number of ROB writes +system.cpu0.timesIdled 129596 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3331525 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5520676264 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 78876046 # Number of Instructions Simulated +system.cpu0.committedOps 94927547 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.649876 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.649876 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.606106 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.606106 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 110754452 # number of integer regfile reads +system.cpu0.int_regfile_writes 59798186 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8167 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes +system.cpu0.cc_regfile_reads 351214590 # number of cc regfile reads +system.cpu0.cc_regfile_writes 41113323 # number of cc regfile writes +system.cpu0.misc_regfile_reads 177297499 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1225193 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 713718 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.250179 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28854841 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 714230 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.399929 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 274766500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.250179 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965332 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.965332 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 78023145 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 78023145 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 20647656 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 20647656 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14394101 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14394101 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 296444 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 296444 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354739 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 354739 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351671 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 351671 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 35041757 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 35041757 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35338201 # number of overall hits -system.cpu0.dcache.overall_hits::total 35338201 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 609728 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 609728 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1806132 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1806132 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141710 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141710 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24359 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 24359 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21165 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21165 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2415860 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2415860 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2557570 # number of overall misses -system.cpu0.dcache.overall_misses::total 2557570 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8120126000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8120126000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26313440366 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 26313440366 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385463000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 385463000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480627500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 480627500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 430000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 430000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34433566366 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34433566366 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34433566366 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34433566366 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21257384 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21257384 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16200233 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16200233 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438154 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 438154 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379098 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 379098 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372836 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 372836 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 37457617 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 37457617 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 37895771 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 37895771 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028683 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028683 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111488 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.111488 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323425 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323425 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064255 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064255 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056768 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056768 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.064496 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.064496 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067490 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.067490 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13317.620316 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13317.620316 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14568.946437 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14568.946437 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15824.253869 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15824.253869 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22708.599102 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22708.599102 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63563549 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63563549 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15604955 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15604955 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 12027073 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 12027073 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 310316 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 310316 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363058 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363058 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361354 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361354 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27632028 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27632028 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 27942344 # number of overall hits +system.cpu0.dcache.overall_hits::total 27942344 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 644494 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 644494 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1893203 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1893203 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147485 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 147485 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25333 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25333 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20104 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20104 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2537697 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2537697 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2685182 # number of overall misses +system.cpu0.dcache.overall_misses::total 2685182 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8536879000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8536879000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27482436369 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 27482436369 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389618000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 389618000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 450883500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 450883500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 36019315369 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 36019315369 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 36019315369 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 36019315369 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16249449 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16249449 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13920276 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13920276 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457801 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 457801 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388391 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388391 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381458 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381458 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30169725 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30169725 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30627526 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30627526 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039663 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.039663 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136003 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.136003 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.322160 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.322160 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065226 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065226 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052703 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052703 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084114 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.084114 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087672 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.087672 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13245.862646 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13245.862646 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14516.370600 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14516.370600 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15379.860261 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15379.860261 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22427.551731 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22427.551731 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14253.129886 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14253.129886 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13463.391565 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13463.391565 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 747 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3913122 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 47 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 192454 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.893617 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20.332765 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14193.702152 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14193.702152 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13414.105773 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13414.105773 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 682 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4150493 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 202595 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.208333 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 20.486651 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 491417 # number of writebacks -system.cpu0.dcache.writebacks::total 491417 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 243049 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 243049 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1494093 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1494093 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18165 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18165 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1737142 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1737142 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1737142 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1737142 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366679 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 366679 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312039 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 312039 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98387 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 98387 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6194 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6194 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21165 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21165 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 678718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 678718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 777105 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 777105 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29394 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26127 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55521 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4291687500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4291687500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5394914387 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5394914387 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1614083000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1614083000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96183500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96183500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459474500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459474500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 418000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 418000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9686601887 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9686601887 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11300684887 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11300684887 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5681056500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5681056500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4312326500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4312326500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9993383000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9993383000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017249 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017249 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019261 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019261 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224549 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224549 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016339 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016339 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056768 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056768 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018120 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018120 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020506 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020506 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11704.208586 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11704.208586 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17289.231112 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17289.231112 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16405.449907 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16405.449907 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15528.495318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15528.495318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21709.166076 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21709.166076 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 517170 # number of writebacks +system.cpu0.dcache.writebacks::total 517170 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 254611 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 254611 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1567828 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1567828 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18755 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18755 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1822439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822439 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1822439 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 389883 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 389883 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325375 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325375 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102048 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102048 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6578 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6578 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20104 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20104 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 715258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 715258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 817306 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 817306 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20386 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19086 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19086 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39472 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4555035000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4555035000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5512912898 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5512912898 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1660765500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1660765500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101006000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101006000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 430792500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 430792500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 441000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 441000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10067947898 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10067947898 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11728713398 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11728713398 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4315293000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4315293000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3299266500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3299266500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7614559500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7614559500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023994 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023994 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023374 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023374 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222909 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222909 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016937 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016937 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052703 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052703 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023708 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023708 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026685 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026685 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11683.081848 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11683.081848 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16943.259003 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16943.259003 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16274.356185 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16274.356185 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15355.123138 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15355.123138 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21428.198368 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21428.198368 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14271.909522 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14271.909522 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14542.030854 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14542.030854 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193272.657685 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193272.657685 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165052.493589 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165052.493589 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179992.849552 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179992.849552 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14075.966851 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14075.966851 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14350.455518 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14350.455518 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 211679.240655 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211679.240655 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172863.171959 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172863.171959 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 192910.404844 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 192910.404844 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1208444 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.748718 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 69666115 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1208956 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 57.625021 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6421480000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748718 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999509 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999509 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1264231 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.765651 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36438607 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1264743 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.811076 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6439669000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.765651 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999542 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999542 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 143059850 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 143059850 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 69666115 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 69666115 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 69666115 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 69666115 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 69666115 # number of overall hits -system.cpu0.icache.overall_hits::total 69666115 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1259322 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1259322 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1259322 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1259322 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1259322 # number of overall misses -system.cpu0.icache.overall_misses::total 1259322 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12306647041 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12306647041 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12306647041 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12306647041 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12306647041 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12306647041 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 70925437 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 70925437 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 70925437 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 70925437 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 70925437 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 70925437 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017756 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.017756 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017756 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.017756 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017756 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.017756 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9772.438694 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9772.438694 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9772.438694 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9772.438694 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9772.438694 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9772.438694 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1459740 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 453 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 110714 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.184782 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 45.300000 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 76777836 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 76777836 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36438607 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36438607 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36438607 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36438607 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36438607 # number of overall hits +system.cpu0.icache.overall_hits::total 36438607 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1317920 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1317920 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1317920 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1317920 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1317920 # number of overall misses +system.cpu0.icache.overall_misses::total 1317920 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13045197783 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13045197783 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13045197783 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13045197783 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13045197783 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13045197783 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37756527 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37756527 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37756527 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37756527 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37756527 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37756527 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034906 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.034906 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034906 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.034906 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034906 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.034906 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9898.322951 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9898.322951 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9898.322951 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9898.322951 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9898.322951 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9898.322951 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1585730 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 630 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 117915 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.448077 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 57.272727 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50344 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 50344 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 50344 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 50344 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 50344 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 50344 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1208978 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1208978 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1208978 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1208978 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1208978 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1208978 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53136 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 53136 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 53136 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 53136 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 53136 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 53136 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264784 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1264784 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264784 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1264784 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264784 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1264784 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11179466333 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11179466333 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11179466333 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11179466333 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11179466333 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11179466333 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11837775153 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11837775153 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11837775153 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11837775153 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11837775153 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11837775153 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265874998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265874998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265874998 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 265874998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017046 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.017046 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.017046 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9247.038683 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9247.038683 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9247.038683 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033498 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033498 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033498 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9359.523170 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9359.523170 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9359.523170 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88506.990013 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88506.990013 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1763942 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1769107 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 4567 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1848695 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1851312 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2366 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 220637 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 266650 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16052.098762 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3449668 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 282876 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 12.194983 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 9287.877050 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.757624 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.215297 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4106.053527 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1602.376504 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1041.818760 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.566887 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000840 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.250614 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.097801 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063588 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.979742 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1056 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15158 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 44 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 321 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 415 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 276 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 414 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4651 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7186 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2852 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.064453 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925171 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 63497786 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 63497786 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 50315 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12479 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 62794 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 491416 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 491416 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28453 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28453 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1608 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1608 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210730 # 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number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1158323 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 583419 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1804536 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 419 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 174 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 593 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27292 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 27292 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19556 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19556 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45826 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 45826 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 50641 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 50641 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 98477 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 98477 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 419 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 174 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 50641 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 144303 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 195537 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 419 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 174 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 50641 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 144303 # number of overall misses -system.cpu0.l2cache.overall_misses::total 195537 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11008500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4405500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 15414000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502449500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 502449500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396768500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396768500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 399000 # 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number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5484599996 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7924897995 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11008500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4405500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2424883999 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5484599996 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7924897995 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50734 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12653 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 63387 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 491416 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 491416 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55745 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55745 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21164 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 21164 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256556 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 256556 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1208964 # 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mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7305308958 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7548650958 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.008441 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.489587 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.489587 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924022 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924022 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155023 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155023 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041863 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.207494 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.207494 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.188995 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094366 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.188995 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.478142 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.478142 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.913251 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.913251 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154654 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154654 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.044138 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.195183 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.195183 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180928 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093119 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180928 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210631 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20024.534687 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65488.832640 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19765.957057 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19765.957057 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15314.148957 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15314.148957 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 327000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 327000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41441.227497 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41441.227497 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41898.875719 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22611.472505 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22611.472505 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28056.570629 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31743.300220 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28056.570629 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50370.397075 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210162 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20030.685921 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61225.985181 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.148175 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20390.148175 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15177.750436 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15177.750436 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41393.930698 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41393.930698 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42300.596500 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23675.774564 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23675.774564 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29002.494683 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32774.794969 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29002.494683 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48619.756450 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185269.340682 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175601.858139 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157441.151223 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157441.151223 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203674.286275 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 187919.880291 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165210.361417 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165210.361417 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172173.987464 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167494.471730 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185075.723500 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 177715.673745 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 116134 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1839025 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26127 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 864426 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1492254 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 304971 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 91775 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43512 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114568 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 284553 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 270414 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1208978 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 592867 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 118491 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1915950 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 30902 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19086 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 881917 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1558941 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 295049 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88486 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42808 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113105 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 298585 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285519 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1264784 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 601994 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3608808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2486821 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28899 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 112519 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6237047 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 77421632 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82196692 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50612 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 202936 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 159871872 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1179844 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 5097277 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.224281 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.417108 # Request fanout histogram +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3774932 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2575467 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29033 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 117114 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6496546 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80991872 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86506920 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50172 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 212364 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 167761328 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1157195 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 5250259 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.213502 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.409779 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3954053 77.57% 77.57% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1143224 22.43% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 4129320 78.65% 78.65% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1120939 21.35% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 5097277 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2520550941 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 5250259 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2631653442 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 112317000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114940499 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1816757420 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1900515323 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1173564387 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1221760496 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 16253983 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 16493992 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 61816936 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 64044457 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 6152669 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3868120 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 360109 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3337115 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 2452438 # Number of BTB hits +system.cpu1.branchPred.lookups 33870827 # Number of BP lookups +system.cpu1.branchPred.condPredicted 11547618 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 303923 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 18735544 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 14949091 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.489766 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 1042883 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 10537 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 79.790002 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12480037 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7268 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1636,91 +1618,92 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 24322 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 24322 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11233 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5990 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7099 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 17223 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 438.425361 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 2740.461547 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 16689 96.90% 96.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 124 0.72% 97.62% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 219 1.27% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 86 0.50% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.12% 99.51% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 13 0.08% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 39 0.23% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 13 0.08% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 16 0.09% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 17223 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5609 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10144.232484 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8674.966878 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6379.427582 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 2437 43.45% 43.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2571 45.84% 89.29% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 453 8.08% 97.36% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 115 2.05% 99.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 3 0.05% 99.47% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.45% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.07% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 21101 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21101 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8660 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5796 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 6645 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14456 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 508.058937 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 2886.331667 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 13910 96.22% 96.22% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 137 0.95% 97.17% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 242 1.67% 98.84% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 68 0.47% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.14% 99.45% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 12 0.08% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 37 0.26% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 11 0.08% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 15 0.10% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14456 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5194 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9424.913362 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8003.762670 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6175.333367 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2569 49.46% 49.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2132 41.05% 90.51% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 361 6.95% 97.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 99 1.91% 99.36% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 3 0.06% 99.42% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 27 0.52% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.04% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5609 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 69613371380 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.373428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.487046 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 43658416792 62.72% 62.72% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 25935559588 37.26% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 12091000 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 3523500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 1046500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 593000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 908500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 323500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 151000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 143500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 80500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 88500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 153000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 38000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 28000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 226500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 69613371380 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1968 73.85% 73.85% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 697 26.15% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2665 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24322 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 5194 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 72058045764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.162272 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.372420 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 60402096044 83.82% 83.82% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 11637981720 16.15% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 11426500 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 2950500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 950000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 753000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 773000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 312500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 161500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 148500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 75000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 48000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 134500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 51500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 27000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 156500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 72058045764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1910 75.91% 75.91% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 606 24.09% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2516 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21101 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24322 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2665 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21101 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2516 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2665 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 26987 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2516 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 23617 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5224196 # DTB read hits -system.cpu1.dtb.read_misses 21002 # DTB read misses -system.cpu1.dtb.write_hits 4300766 # DTB write hits -system.cpu1.dtb.write_misses 3320 # DTB write misses +system.cpu1.dtb.read_hits 10151644 # DTB read hits +system.cpu1.dtb.read_misses 18305 # DTB read misses +system.cpu1.dtb.write_hits 6523716 # DTB write hits +system.cpu1.dtb.write_misses 2796 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2043 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 67 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 616 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 50 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 456 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 364 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5245198 # DTB read accesses -system.cpu1.dtb.write_accesses 4304086 # DTB write accesses +system.cpu1.dtb.perms_faults 384 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10169949 # DTB read accesses +system.cpu1.dtb.write_accesses 6526512 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9524962 # DTB hits -system.cpu1.dtb.misses 24322 # DTB misses -system.cpu1.dtb.accesses 9549284 # DTB accesses +system.cpu1.dtb.hits 16675360 # DTB hits +system.cpu1.dtb.misses 21101 # DTB misses +system.cpu1.dtb.accesses 16696461 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1750,58 +1733,60 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 6842 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6842 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4094 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2680 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 68 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6774 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 241.142604 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1918.263476 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 6651 98.18% 98.18% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 49 0.72% 98.91% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 35 0.52% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 15 0.22% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.07% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-24575 10 0.15% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.07% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-53247 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6774 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1233 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11141.524736 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9875.363796 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6280.061079 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 357 28.95% 28.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 797 64.64% 93.59% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 18 1.46% 95.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 48 3.89% 98.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.41% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.57% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1233 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 18042065828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.988332 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.107619 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 210878764 1.17% 1.17% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 17830879064 98.83% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 267500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 19000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 21500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 18042065828 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 995 85.41% 85.41% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 170 14.59% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated +system.cpu1.itb.walker.walks 6899 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6899 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4113 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2729 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 57 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6842 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 198.333821 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1594.183488 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 6730 98.36% 98.36% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 59 0.86% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 21 0.31% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 14 0.20% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 7 0.10% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.07% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 4 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6842 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1221 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10738.329238 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9530.760976 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5854.425690 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 35 2.87% 2.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 374 30.63% 33.50% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 497 40.70% 74.20% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 243 19.90% 94.10% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 3 0.25% 94.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 9 0.74% 95.09% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 37 3.03% 98.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.31% 99.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 2 0.16% 99.59% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.25% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.08% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::53248-57343 1 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1221 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 11897679120 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.980675 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.137806 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 230157764 1.93% 1.93% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 11667291856 98.06% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 229500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 11897679120 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 997 85.65% 85.65% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 167 14.35% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1164 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6842 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6842 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6899 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 8007 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 10488200 # ITB inst hits -system.cpu1.itb.inst_misses 6842 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1164 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1164 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 8063 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 43584522 # ITB inst hits +system.cpu1.itb.inst_misses 6899 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1810,1035 +1795,1025 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1196 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1193 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 530 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 547 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10495042 # ITB inst accesses -system.cpu1.itb.hits 10488200 # DTB hits -system.cpu1.itb.misses 6842 # DTB misses -system.cpu1.itb.accesses 10495042 # DTB accesses -system.cpu1.numCycles 43023242 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 43591421 # ITB inst accesses +system.cpu1.itb.hits 43584522 # DTB hits +system.cpu1.itb.misses 6899 # DTB misses +system.cpu1.itb.accesses 43591421 # DTB accesses +system.cpu1.numCycles 105332010 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9545006 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 31536140 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 6152669 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 3495321 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 31308638 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 988880 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 91081 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 40105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 214294 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 338691 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 30719 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 10487595 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 131638 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2429 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 42062974 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.911933 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.224898 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 10132151 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108981973 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 33870827 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 27429128 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 92017725 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3770452 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 88186 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 36483 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 195284 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 298638 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 22598 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 43583923 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 117443 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2417 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104676291 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.289820 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.339564 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 24350235 57.89% 57.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 6287044 14.95% 72.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2205515 5.24% 78.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 9220180 21.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 47827120 45.69% 45.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 14002469 13.38% 59.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7529046 7.19% 66.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 35317656 33.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 42062974 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.143008 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.733002 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8267663 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 20626897 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11490517 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1337775 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 340122 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 874675 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 157334 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 30100708 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1379443 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 340122 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 10041900 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2603998 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 14921640 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11019721 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3135593 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 28621166 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 281517 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 330506 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 50454 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 20125 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1923436 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 29030542 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 132294985 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 32813170 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1657 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 25609862 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 3420680 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 453393 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 375590 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3438293 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 5562789 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 4719499 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 701110 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 705314 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 27634808 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 626900 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 27144127 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 143701 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2955966 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 6891737 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 53840 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 42062974 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.645321 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.965357 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 104676291 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.321563 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.034652 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 13137871 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 61997568 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 26684640 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1104927 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1751285 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 750757 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 136902 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 67935331 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1160131 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1751285 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17557644 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2234457 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 57207184 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 23346153 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2579568 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 55040039 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 231549 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 250107 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 36576 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 14638 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1569614 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 54888875 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 259969011 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 58535420 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1673 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 52136282 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2752593 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1876398 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1803595 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13068910 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10432997 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6892596 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 625658 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 847753 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 54148527 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 587967 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 53807238 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 110933 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3881118 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 5762517 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 48708 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104676291 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.514035 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.850765 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 26343154 62.63% 62.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7337268 17.44% 80.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 5660550 13.46% 93.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2402263 5.71% 99.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 319725 0.76% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 14 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 71469096 68.28% 68.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16529250 15.79% 84.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 13041841 12.46% 96.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3350126 3.20% 99.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 285962 0.27% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 42062974 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104676291 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1996325 32.40% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 609 0.01% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 32.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1885144 30.59% 63.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 2280359 37.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2912792 45.01% 45.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 674 0.01% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.02% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1671813 25.83% 70.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1886405 29.15% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 17084879 62.94% 62.94% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 34880 0.13% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.07% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4083 0.02% 63.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 63.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.09% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 5473288 20.16% 83.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 4546930 16.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36660342 68.13% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45736 0.08% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3323 0.01% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 10366546 19.27% 87.49% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6731225 12.51% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 27144127 # Type of FU issued -system.cpu1.iq.rate 0.630918 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6162437 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.227027 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 102651570 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 31226183 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 26510239 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 5796 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 33302783 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 3714 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 106694 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 53807238 # Type of FU issued +system.cpu1.iq.rate 0.510835 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6471684 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.120275 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 218867204 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58625584 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 51813824 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 6180 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2068 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 60274803 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 4053 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 90118 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 599497 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 782 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10594 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 400513 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 483730 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10069 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 351136 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 46755 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 99859 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 51537 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 78201 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 340122 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 663664 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 112730 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 28316728 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1751285 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 538520 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 104583 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 54788620 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 5562789 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 4719499 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 329074 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 12650 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 90576 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10594 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 71921 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 150578 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 222499 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 26808358 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 5342958 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 311471 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 10432997 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6892596 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 301008 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 9394 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 87795 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10069 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 55171 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 126265 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 181436 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 53538867 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10265396 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 247288 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 55020 # number of nop insts executed -system.cpu1.iew.exec_refs 9813397 # number of memory reference insts executed -system.cpu1.iew.exec_branches 4108906 # Number of branches executed -system.cpu1.iew.exec_stores 4470439 # Number of stores executed -system.cpu1.iew.exec_rate 0.623113 # Inst execution rate -system.cpu1.iew.wb_sent 26632744 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 26512023 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 13415515 # num instructions producing a value -system.cpu1.iew.wb_consumers 21195279 # num instructions consuming a value +system.cpu1.iew.exec_nop 52126 # number of nop insts executed +system.cpu1.iew.exec_refs 16932944 # number of memory reference insts executed +system.cpu1.iew.exec_branches 11793778 # Number of branches executed +system.cpu1.iew.exec_stores 6667548 # Number of stores executed +system.cpu1.iew.exec_rate 0.508287 # Inst execution rate +system.cpu1.iew.wb_sent 53390597 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 51815609 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25160275 # num instructions producing a value +system.cpu1.iew.wb_consumers 38370093 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.616226 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.632948 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.491927 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.655726 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2659330 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 573060 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 205791 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 41503303 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.610529 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.356545 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3631838 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 539259 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 169982 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 102749355 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.495266 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.156980 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 29410485 70.86% 70.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7042051 16.97% 87.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2116509 5.10% 92.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 864843 2.08% 95.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 769424 1.85% 96.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 435639 1.05% 97.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 276731 0.67% 98.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 147889 0.36% 98.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 439732 1.06% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 77230128 75.16% 75.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 14246960 13.87% 89.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6071957 5.91% 94.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 703815 0.68% 95.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1976351 1.92% 97.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1539288 1.50% 99.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 468880 0.46% 99.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 125021 0.12% 99.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 386955 0.38% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 41503303 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 20778200 # Number of instructions committed -system.cpu1.commit.committedOps 25338954 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 102749355 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41322014 # Number of instructions committed +system.cpu1.commit.committedOps 50888230 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 9282278 # Number of memory references committed -system.cpu1.commit.loads 4963292 # Number of loads committed -system.cpu1.commit.membars 229830 # Number of memory barriers committed -system.cpu1.commit.branches 3902679 # Number of branches committed +system.cpu1.commit.refs 16490727 # Number of memory references committed +system.cpu1.commit.loads 9949267 # Number of loads committed +system.cpu1.commit.membars 209363 # Number of memory barriers committed +system.cpu1.commit.branches 11627773 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 22267919 # Number of committed integer instructions. -system.cpu1.commit.function_calls 549742 # Number of function calls committed. +system.cpu1.commit.int_insts 45743033 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3362907 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 16018762 63.22% 63.22% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 33831 0.13% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4083 0.02% 63.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.37% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 4963292 19.59% 82.96% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 4318986 17.04% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 34349326 67.50% 67.50% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 44854 0.09% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3323 0.01% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9949267 19.55% 87.15% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6541460 12.85% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 25338954 # Class of committed instruction -system.cpu1.commit.bw_lim_events 439732 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 67911551 # The number of ROB reads -system.cpu1.rob.rob_writes 56552827 # The number of ROB writes -system.cpu1.timesIdled 67532 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 960268 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5207215501 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 20744987 # Number of Instructions Simulated -system.cpu1.committedOps 25305741 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.073910 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.073910 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.482181 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.482181 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 29917814 # number of integer regfile reads -system.cpu1.int_regfile_writes 16874088 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1382 # number of floating regfile reads +system.cpu1.commit.op_class_0::total 50888230 # Class of committed instruction +system.cpu1.commit.bw_lim_events 386955 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 136861200 # The number of ROB reads +system.cpu1.rob.rob_writes 110963404 # The number of ROB writes +system.cpu1.timesIdled 59136 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 655719 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5544933026 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41289159 # Number of Instructions Simulated +system.cpu1.committedOps 50855375 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.551082 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.551082 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.391991 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.391991 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 56164709 # number of integer regfile reads +system.cpu1.int_regfile_writes 35664798 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1398 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 95785070 # number of cc regfile reads -system.cpu1.cc_regfile_writes 9455596 # number of cc regfile writes -system.cpu1.misc_regfile_reads 60806398 # number of misc regfile reads -system.cpu1.misc_regfile_writes 422782 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 228231 # number of replacements -system.cpu1.dcache.tags.tagsinuse 478.409113 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8403253 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 228545 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.768483 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 103444079500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.409113 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934393 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.934393 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.613281 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18586968 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18586968 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 4548259 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4548259 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3563356 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3563356 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 63759 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 63759 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87271 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 87271 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79516 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79516 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8111615 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8111615 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8175374 # number of overall hits -system.cpu1.dcache.overall_hits::total 8175374 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 254647 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 254647 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 480567 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 480567 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35928 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 35928 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19211 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 19211 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23462 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23462 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 735214 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 735214 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 771142 # number of overall misses -system.cpu1.dcache.overall_misses::total 771142 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4017153000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4017153000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11025282924 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 11025282924 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 376163500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 376163500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545526500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 545526500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 528500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 528500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15042435924 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15042435924 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15042435924 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15042435924 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4802906 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4802906 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4043923 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4043923 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 99687 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 99687 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106482 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 106482 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102978 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 102978 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8846829 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8846829 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 8946516 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 8946516 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.053019 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.053019 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118837 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.118837 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.360408 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.360408 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.180415 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.180415 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227835 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227835 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083105 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.083105 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.086195 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.086195 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15775.379250 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15775.379250 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22942.238905 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22942.238905 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19580.630889 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19580.630889 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23251.491774 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23251.491774 # average StoreCondReq miss latency +system.cpu1.cc_regfile_reads 190801964 # number of cc regfile reads +system.cpu1.cc_regfile_writes 15538939 # number of cc regfile writes +system.cpu1.misc_regfile_reads 145958777 # number of misc regfile reads +system.cpu1.misc_regfile_writes 388038 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 188683 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.137779 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 15712566 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 189037 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 83.118998 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 93446032500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.137779 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916285 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.916285 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 32914145 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 32914145 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 9558582 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9558582 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5897409 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5897409 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49196 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49196 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78850 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78850 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70461 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70461 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15455991 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15455991 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15505187 # number of overall hits +system.cpu1.dcache.overall_hits::total 15505187 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 218229 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 218229 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 396239 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 396239 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 29850 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 29850 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18125 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18125 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23674 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23674 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 614468 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 614468 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 644318 # number of overall misses +system.cpu1.dcache.overall_misses::total 644318 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3487669000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3487669000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9663134455 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9663134455 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 358154500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 358154500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554726500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 554726500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 887500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 887500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13150803455 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13150803455 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13150803455 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13150803455 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9776811 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9776811 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6293648 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6293648 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79046 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79046 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96975 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96975 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94135 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94135 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16070459 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16070459 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16149505 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16149505 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022321 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.022321 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062959 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.062959 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377628 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377628 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186904 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186904 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.251490 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.251490 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038236 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038236 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039897 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039897 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15981.693542 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15981.693542 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24387.136185 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24387.136185 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19760.248276 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19760.248276 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23431.887303 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.887303 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20459.942172 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20459.942172 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19506.700354 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19506.700354 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 359 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1638919 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 40 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 49248 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.975000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 33.278895 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21401.933795 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21401.933795 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20410.423820 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20410.423820 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1417697 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39735 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.823529 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 35.678797 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 137260 # number of writebacks -system.cpu1.dcache.writebacks::total 137260 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 91413 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 91413 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375801 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 375801 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13808 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13808 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 467214 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 467214 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 467214 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 467214 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163234 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163234 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104766 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 104766 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32551 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 32551 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5403 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5403 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23462 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23462 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 268000 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 268000 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 300551 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 300551 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5603 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5603 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4908 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10511 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10511 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2247760000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2247760000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2639771935 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2639771935 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 542309000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 542309000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 101732500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 101732500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 522075500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 522075500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 517500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 517500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4887531935 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4887531935 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5429840935 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5429840935 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 989470000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 989470000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 857954500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 857954500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1847424500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1847424500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033987 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033987 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025907 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025907 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.326532 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.326532 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050741 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050741 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227835 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227835 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030293 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030293 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033594 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033594 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.170430 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.170430 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25196.838049 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25196.838049 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16660.286934 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16660.286934 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18828.891357 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18828.891357 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22251.960617 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22251.960617 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 116769 # number of writebacks +system.cpu1.dcache.writebacks::total 116769 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 80049 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 80049 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306072 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 306072 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13108 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13108 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 386121 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 386121 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 386121 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 386121 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 138180 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 138180 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90167 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 90167 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28614 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28614 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5017 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5017 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23674 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23674 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 228347 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 228347 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 256961 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 256961 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14486 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14486 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11815 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11815 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26301 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26301 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1915104500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1915104500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2355138466 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2355138466 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 482351500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 482351500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90011000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90011000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 531068500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 531068500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 871500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 871500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4270242966 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4270242966 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4752594466 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4752594466 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2349248500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2349248500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1864740000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1864740000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4213988500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4213988500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014133 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014133 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014327 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014327 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361992 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361992 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051735 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051735 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.251490 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.251490 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014209 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014209 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015911 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015911 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.491243 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.491243 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26119.738552 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26119.738552 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16857.185294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16857.185294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17941.199920 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17941.199920 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22432.563149 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22432.563149 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18237.059459 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18237.059459 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18066.288034 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18066.288034 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176596.466179 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176596.466179 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174807.355338 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174807.355338 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175761.059842 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 175761.059842 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18700.674701 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18700.674701 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18495.392165 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18495.392165 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162173.719453 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162173.719453 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157828.184511 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157828.184511 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 160221.607543 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 160221.607543 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 661426 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.525577 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 9800007 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 661938 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 14.805023 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 78861824000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.525577 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973683 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973683 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 603214 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.475238 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 42957427 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 603726 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 71.153846 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 78885354000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.475238 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975538 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975538 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21636569 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21636569 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 9800007 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9800007 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9800007 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9800007 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9800007 # number of overall hits -system.cpu1.icache.overall_hits::total 9800007 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 687303 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 687303 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 687303 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 687303 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 687303 # number of overall misses -system.cpu1.icache.overall_misses::total 687303 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6263235013 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6263235013 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6263235013 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6263235013 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6263235013 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6263235013 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10487310 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10487310 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10487310 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10487310 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10487310 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10487310 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.065537 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.065537 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.065537 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.065537 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.065537 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.065537 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9112.771242 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9112.771242 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9112.771242 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9112.771242 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9112.771242 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9112.771242 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 638996 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 564 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 53890 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 87771063 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 87771063 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 42957427 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 42957427 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 42957427 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 42957427 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 42957427 # number of overall hits +system.cpu1.icache.overall_hits::total 42957427 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 626240 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 626240 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 626240 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 626240 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 626240 # number of overall misses +system.cpu1.icache.overall_misses::total 626240 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5487739407 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5487739407 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5487739407 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5487739407 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5487739407 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5487739407 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43583667 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43583667 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43583667 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43583667 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43583667 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43583667 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014369 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014369 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014369 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014369 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014369 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014369 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8762.997265 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8762.997265 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8762.997265 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8762.997265 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8762.997265 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8762.997265 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 503899 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 46132 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.857413 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 564 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.922982 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 26 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 25354 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 25354 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 25354 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 25354 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 25354 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 25354 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 661949 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 661949 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 661949 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 661949 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 661949 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 661949 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22511 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 22511 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 22511 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 22511 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 22511 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 22511 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 603729 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 603729 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 603729 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 603729 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 603729 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 603729 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5721508360 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5721508360 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5721508360 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5721508360 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5721508360 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5721508360 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8594000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8594000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8594000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8594000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.063119 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.063119 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.063119 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8643.427757 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8643.427757 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8643.427757 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 84254.901961 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 84254.901961 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5031797233 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5031797233 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5031797233 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5031797233 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5031797233 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5031797233 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9110000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9110000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9110000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9110000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013852 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013852 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013852 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8334.529620 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8334.529620 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8334.529620 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89313.725490 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89313.725490 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 269622 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 270613 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 884 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 189065 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 189671 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 541 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 67787 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 66660 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15577.889137 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1655246 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 81265 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.368498 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 56769 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 48663 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15171.630527 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1474911 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63236 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 23.323914 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6747.638156 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 12.637913 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.167789 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4673.355619 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2625.058292 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1517.031368 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.411843 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000771 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000132 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.285239 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.160221 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.092592 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.950799 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1291 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13290 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 868 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 406 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8605 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4215 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078796 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811157 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 30536660 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 30536660 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19077 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7323 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 26400 # 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number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7323 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 639615 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 165768 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 831783 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19077 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7323 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 639615 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 165768 # number of overall hits -system.cpu1.l2cache.overall_hits::total 831783 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 431 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 286 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 717 # number of ReadReq misses +system.cpu1.l2cache.tags.occ_blocks::writebacks 8232.224686 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.332834 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.684874 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3831.793838 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2451.411988 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 641.182307 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.502455 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000692 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000225 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.233874 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.149622 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.039135 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.926003 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1118 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 35 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13420 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 930 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 167 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8633 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4319 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068237 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002136 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.819092 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 27275895 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 27275895 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 15350 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7200 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 22550 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 116768 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 116768 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1559 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1559 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 954 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 954 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27353 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27353 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 586865 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 586865 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101704 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 101704 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 15350 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7200 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 586865 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 129057 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 738472 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 15350 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7200 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 586865 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 129057 # number of overall hits +system.cpu1.l2cache.overall_hits::total 738472 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 400 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 278 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 678 # number of ReadReq misses system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29127 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29127 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22358 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22358 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35752 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 35752 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 22316 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 22316 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73485 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 73485 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 431 # 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mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028586 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000009 # mshr miss rate for Writeback accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.922909 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.922909 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952986 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.952986 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.472604 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.472604 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033692 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.364585 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.364585 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393589 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136139 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393589 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.947568 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947568 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.959703 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.959703 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.545480 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.545480 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027920 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.407539 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.407539 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443730 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140563 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443730 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174968 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15515.625000 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43273.811557 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17026.384454 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.384454 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15446.887020 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15446.887020 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 435000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 435000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34830.663648 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34830.663648 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34082.571070 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17729.346450 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17729.346450 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23243.087039 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25043.552120 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23243.087039 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29089.208942 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168545.243619 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166904.119194 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167283.108802 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 167283.108802 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 167955.903149 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167079.383586 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168104 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15677.710843 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43832.203539 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16437.249335 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16437.249335 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15533.516725 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15533.516725 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33620.278419 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33620.278419 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30019.844566 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16199.480061 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16199.480061 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.173442 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22928.274145 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.173442 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26353.016452 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154160.258180 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153654.407732 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150318.070080 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150318.070080 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152434.260979 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 152161.439912 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 70770 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 942311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4908 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 510267 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 868505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 48336 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 75730 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43006 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 67801 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 858839 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 30901 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11815 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 481520 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 790490 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 28803 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75635 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42021 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86708 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 96740 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 79738 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 661949 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 536905 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 83417 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 65666 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 603729 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 520017 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1973224 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 988189 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17063 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42721 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3021197 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 42365216 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29405313 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30436 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78032 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 71878997 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 1156869 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2994555 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.368102 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.482289 # Request fanout histogram +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1799792 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 888351 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17049 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 36002 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2741194 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38640160 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25264094 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29912 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 63000 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 63997166 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 1119232 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2773999 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.384160 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.486396 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1892252 63.19% 63.19% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1102303 36.81% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1708339 61.58% 61.58% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1065660 38.42% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2994555 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1102178989 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2773999 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 991762490 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 87567999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 81878499 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 993110829 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 905763364 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 449674318 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 398007900 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9464978 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 9580481 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 23224976 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20262978 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31011 # Transaction distribution -system.iobus.trans_dist::ReadResp 31011 # Transaction distribution +system.iobus.trans_dist::ReadReq 31012 # Transaction distribution +system.iobus.trans_dist::ReadResp 31012 # Transaction distribution system.iobus.trans_dist::WriteReq 59421 # Transaction distribution system.iobus.trans_dist::WriteResp 59421 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) @@ -2846,7 +2821,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2862,16 +2837,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2887,10 +2862,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484041 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40089000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -2901,7 +2876,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 505000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2935,19 +2910,19 @@ system.iobus.reqLayer27.occupancy 187554438 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84715000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.446879 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.557293 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 254837974000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.446879 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.902930 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.902930 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 254755320000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.557293 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909831 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909831 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2961,14 +2936,14 @@ system.iocache.demand_misses::realview.ide 252 # system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32277877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32277877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4275018561 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4275018561 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32277877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32277877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32277877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32277877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32401877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32401877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4274240561 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4274240561 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32401877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32401877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32401877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32401877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2985,14 +2960,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128086.813492 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128086.813492 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118016.192607 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118016.192607 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128086.813492 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128086.813492 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128086.813492 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128086.813492 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 128578.876984 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128578.876984 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117994.715134 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117994.715134 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128578.876984 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128578.876984 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128578.876984 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128578.876984 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -3011,14 +2986,14 @@ system.iocache.demand_mshr_misses::realview.ide 252 system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19677877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19677877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2463818561 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2463818561 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19677877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19677877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19677877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19677877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19801877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19801877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2463040561 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2463040561 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19801877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19801877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19801877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19801877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3027,603 +3002,601 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78086.813492 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 78086.813492 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68016.192607 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68016.192607 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 78086.813492 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 78086.813492 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 78086.813492 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 78086.813492 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78578.876984 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78578.876984 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67994.715134 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67994.715134 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78578.876984 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78578.876984 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78578.876984 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78578.876984 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 136014 # number of replacements -system.l2c.tags.tagsinuse 64041.678257 # Cycle average of tags in use -system.l2c.tags.total_refs 410908 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 200324 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.051217 # Average number of references to valid blocks. +system.l2c.tags.replacements 130408 # number of replacements +system.l2c.tags.tagsinuse 64065.129893 # Cycle average of tags in use +system.l2c.tags.total_refs 410009 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 194847 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.104261 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12985.002975 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 12.737581 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 3.016987 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6471.116722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1893.814522 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32628.788989 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.896219 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 1.746917 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3305.203826 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1817.254812 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4915.098707 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.198135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.098741 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.028897 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.497876 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000120 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000027 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.050433 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.027729 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.074998 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.977198 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30547 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33736 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6158 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 24257 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5063 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 28206 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.466110 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.514771 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5562101 # Number of tag accesses -system.l2c.tags.data_accesses 5562101 # Number of data accesses -system.l2c.Writeback_hits::writebacks 232311 # number of Writeback hits -system.l2c.Writeback_hits::total 232311 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2454 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 792 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3246 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 65 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3756 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1862 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5618 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83457.394002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75174.421627 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 95764.025369 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83457.394002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75174.421627 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 95764.025369 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.776756 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829719 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.788941 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.804220 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.882186 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.852785 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.743801 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.844773 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.783594 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.120773 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.037037 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.343749 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.160240 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742436 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.166667 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.110857 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.587449 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.518829 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.120773 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.037037 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.343749 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.283213 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742436 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.166667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.466179 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.587449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.537530 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.120773 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.037037 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.343749 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.283213 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.742436 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.166667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.466179 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.587449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.537530 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20731.818807 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20750.971388 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20736.453077 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20896.504373 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20765.888978 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20812.339036 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 91782.205869 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72764.402304 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 83702.233440 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 87860 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72626.811269 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80185.034612 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 300000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82129.184549 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 94948.121679 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 87860 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72626.811269 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86603.312071 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 300000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73913.183110 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 93790.184063 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 87860 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72626.811269 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86603.312071 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 300000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73913.183110 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 93790.184063 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167269.238620 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150627.767857 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156312.047244 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140439.412944 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150282.498370 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141996.038150 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185674.188168 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136198.763983 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156774.687944 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148207.955674 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133317.520186 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142514.596388 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154643.694134 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150466.501903 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 149885.528951 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167558.042207 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134904.247671 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 150376.849989 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 38100 # Transaction distribution -system.membus.trans_dist::ReadResp 212196 # Transaction distribution -system.membus.trans_dist::WriteReq 31035 # Transaction distribution -system.membus.trans_dist::WriteResp 31035 # Transaction distribution -system.membus.trans_dist::Writeback 140680 # Transaction distribution -system.membus.trans_dist::CleanEvict 16716 # Transaction distribution -system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41581 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14111 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 40212 # Transaction distribution -system.membus.trans_dist::ReadExResp 20215 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174097 # Transaction distribution +system.membus.trans_dist::ReadReq 37974 # Transaction distribution +system.membus.trans_dist::ReadResp 209076 # Transaction distribution +system.membus.trans_dist::WriteReq 30901 # Transaction distribution +system.membus.trans_dist::WriteResp 30901 # Transaction distribution +system.membus.trans_dist::Writeback 136827 # Transaction distribution +system.membus.trans_dist::CleanEvict 16300 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76178 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40718 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13724 # Transaction distribution +system.membus.trans_dist::ReadExReq 39427 # Transaction distribution +system.membus.trans_dist::ReadExResp 19516 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171103 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 677829 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 799987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13686 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663947 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 785587 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 908921 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 894521 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28412 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19154168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19345693 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27372 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18671220 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18861706 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21663837 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125106 # Total snoops (count) -system.membus.snoop_fanout::samples 595969 # Request fanout histogram +system.membus.pkt_size::total 21179850 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123655 # Total snoops (count) +system.membus.snoop_fanout::samples 585907 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 595969 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 585907 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 595969 # Request fanout histogram -system.membus.reqLayer0.occupancy 81639500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 585907 # Request fanout histogram +system.membus.reqLayer0.occupancy 81623000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11797490 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11432490 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1030129184 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 989982724 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1147298884 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1127040159 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64422049 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64467297 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3656,50 +3629,50 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 38103 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 495292 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 373006 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 88968 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 80200 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41893 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 122093 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50895 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50895 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 457205 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 37978 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 489550 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30901 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30901 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 364752 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 88216 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 79213 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41051 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 120264 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50507 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50507 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 451588 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1082088 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 352339 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1434427 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31351112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6763093 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 38114205 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 462700 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1239270 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.168619 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.374415 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1086474 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 331144 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1417618 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32384412 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5153902 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 37538314 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 454329 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1220605 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.166616 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.372633 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1030306 83.14% 83.14% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 208964 16.86% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1017233 83.34% 83.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 203372 16.66% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1239270 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 822017005 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1220605 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 824158889 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 615196241 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 620803562 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 261600624 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 245897316 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2069 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2769 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index d8bee446b..3557587c2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.804297 # Nu sim_ticks 2804296829000 # Number of ticks simulated final_tick 2804296829000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111214 # Simulator instruction rate (inst/s) -host_op_rate 134984 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2666624096 # Simulator tick rate (ticks/s) -host_mem_usage 631592 # Number of bytes of host memory used -host_seconds 1051.63 # Real time elapsed on the host +host_inst_rate 103542 # Simulator instruction rate (inst/s) +host_op_rate 125673 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2482681694 # Simulator tick rate (ticks/s) +host_mem_usage 631560 # Number of bytes of host memory used +host_seconds 1129.54 # Real time elapsed on the host sim_insts 116955586 # Number of instructions simulated sim_ops 141953418 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index d3ad4a453..0c25a081b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.482330 # Number of seconds simulated -sim_ticks 47482329862000 # Number of ticks simulated -final_tick 47482329862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.411962 # Number of seconds simulated +sim_ticks 47411962285000 # Number of ticks simulated +final_tick 47411962285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176341 # Simulator instruction rate (inst/s) -host_op_rate 207374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9393535208 # Simulator tick rate (ticks/s) -host_mem_usage 769764 # Number of bytes of host memory used -host_seconds 5054.79 # Real time elapsed on the host -sim_insts 891365561 # Number of instructions simulated -sim_ops 1048233259 # Number of ops (including micro ops) simulated +host_inst_rate 170497 # Simulator instruction rate (inst/s) +host_op_rate 200546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9509503550 # Simulator tick rate (ticks/s) +host_mem_usage 769500 # Number of bytes of host memory used +host_seconds 4985.75 # Real time elapsed on the host +sim_insts 850056300 # Number of instructions simulated +sim_ops 999871495 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 124416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 101184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8041216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 40378184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15310528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 143616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 132928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3236032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 17140560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 13345792 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 446144 # Number of bytes read from this memory -system.physmem.bytes_read::total 98400600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8041216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3236032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11277248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78262528 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 75328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 71168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7498816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 38111304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10728384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 51264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 47808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2878784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12174608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 7747264 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 431104 # Number of bytes read from this memory +system.physmem.bytes_read::total 79815832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7498816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2878784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10377600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 62807296 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 78283112 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1581 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 125644 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 630922 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 239227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2244 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 50563 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 267834 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 208528 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6971 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1537535 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1222852 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 62827880 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 117169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 595502 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 167631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 801 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 190241 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 121051 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6736 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1247148 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 981364 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1225426 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 169352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 850383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 322447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 68152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 360988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 281069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2072363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 169352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 68152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 237504 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1648245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 983938 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 158163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 803833 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 226280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 60719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 256783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 163403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1683453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 158163 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 60719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 218881 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1324714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1648679 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1648245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 169352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 850817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 322447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 68152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 360988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 281069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3721041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1537535 # Number of read requests accepted -system.physmem.writeReqs 1225426 # Number of write requests accepted -system.physmem.readBursts 1537535 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1225426 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 98362112 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 40128 # Total number of bytes read from write queue -system.physmem.bytesWritten 78282112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 98400600 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78283112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 627 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1325148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1324714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 158163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 804267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 226280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 60719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 256784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 163403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3008602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1247148 # Number of read requests accepted +system.physmem.writeReqs 983938 # Number of write requests accepted +system.physmem.readBursts 1247148 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 983938 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 79775360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 42112 # Total number of bytes read from write queue +system.physmem.bytesWritten 62826240 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 79815832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 62827880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 658 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 220170 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 94941 # Per bank write bursts -system.physmem.perBankRdBursts::1 98803 # Per bank write bursts -system.physmem.perBankRdBursts::2 90365 # Per bank write bursts -system.physmem.perBankRdBursts::3 103122 # Per bank write bursts -system.physmem.perBankRdBursts::4 90513 # Per bank write bursts -system.physmem.perBankRdBursts::5 102407 # Per bank write bursts -system.physmem.perBankRdBursts::6 86370 # Per bank write bursts -system.physmem.perBankRdBursts::7 97727 # Per bank write bursts -system.physmem.perBankRdBursts::8 90531 # Per bank write bursts -system.physmem.perBankRdBursts::9 141203 # Per bank write bursts -system.physmem.perBankRdBursts::10 86748 # Per bank write bursts -system.physmem.perBankRdBursts::11 95428 # Per bank write bursts -system.physmem.perBankRdBursts::12 92596 # Per bank write bursts -system.physmem.perBankRdBursts::13 93840 # Per bank write bursts -system.physmem.perBankRdBursts::14 85305 # Per bank write bursts -system.physmem.perBankRdBursts::15 87009 # Per bank write bursts -system.physmem.perBankWrBursts::0 77173 # Per bank write bursts -system.physmem.perBankWrBursts::1 80360 # Per bank write bursts -system.physmem.perBankWrBursts::2 74652 # Per bank write bursts -system.physmem.perBankWrBursts::3 83758 # Per bank write bursts -system.physmem.perBankWrBursts::4 75004 # Per bank write bursts -system.physmem.perBankWrBursts::5 81344 # Per bank write bursts -system.physmem.perBankWrBursts::6 71841 # Per bank write bursts -system.physmem.perBankWrBursts::7 79366 # Per bank write bursts -system.physmem.perBankWrBursts::8 74851 # Per bank write bursts -system.physmem.perBankWrBursts::9 75375 # Per bank write bursts -system.physmem.perBankWrBursts::10 73319 # Per bank write bursts -system.physmem.perBankWrBursts::11 78054 # Per bank write bursts -system.physmem.perBankWrBursts::12 76445 # Per bank write bursts -system.physmem.perBankWrBursts::13 77751 # Per bank write bursts -system.physmem.perBankWrBursts::14 70793 # Per bank write bursts -system.physmem.perBankWrBursts::15 73072 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 218244 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 71187 # Per bank write bursts +system.physmem.perBankRdBursts::1 77028 # Per bank write bursts +system.physmem.perBankRdBursts::2 72273 # Per bank write bursts +system.physmem.perBankRdBursts::3 78219 # Per bank write bursts +system.physmem.perBankRdBursts::4 70385 # Per bank write bursts +system.physmem.perBankRdBursts::5 81119 # Per bank write bursts +system.physmem.perBankRdBursts::6 72267 # Per bank write bursts +system.physmem.perBankRdBursts::7 76746 # Per bank write bursts +system.physmem.perBankRdBursts::8 71370 # Per bank write bursts +system.physmem.perBankRdBursts::9 123762 # Per bank write bursts +system.physmem.perBankRdBursts::10 72044 # Per bank write bursts +system.physmem.perBankRdBursts::11 80747 # Per bank write bursts +system.physmem.perBankRdBursts::12 73100 # Per bank write bursts +system.physmem.perBankRdBursts::13 79351 # Per bank write bursts +system.physmem.perBankRdBursts::14 74612 # Per bank write bursts +system.physmem.perBankRdBursts::15 72280 # Per bank write bursts +system.physmem.perBankWrBursts::0 58860 # Per bank write bursts +system.physmem.perBankWrBursts::1 62909 # Per bank write bursts +system.physmem.perBankWrBursts::2 59749 # Per bank write bursts +system.physmem.perBankWrBursts::3 64358 # Per bank write bursts +system.physmem.perBankWrBursts::4 59245 # Per bank write bursts +system.physmem.perBankWrBursts::5 66477 # Per bank write bursts +system.physmem.perBankWrBursts::6 59553 # Per bank write bursts +system.physmem.perBankWrBursts::7 62082 # Per bank write bursts +system.physmem.perBankWrBursts::8 58790 # Per bank write bursts +system.physmem.perBankWrBursts::9 60994 # Per bank write bursts +system.physmem.perBankWrBursts::10 60508 # Per bank write bursts +system.physmem.perBankWrBursts::11 63849 # Per bank write bursts +system.physmem.perBankWrBursts::12 60193 # Per bank write bursts +system.physmem.perBankWrBursts::13 63756 # Per bank write bursts +system.physmem.perBankWrBursts::14 60310 # Per bank write bursts +system.physmem.perBankWrBursts::15 60027 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 43 # Number of times write queue was full causing retry -system.physmem.totGap 47482327991500 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 47411960356500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1537505 # Read request sizes (log2) +system.physmem.readPktSize::6 1247118 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1222852 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 944383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 373776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 27146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 25089 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 22356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 19759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 863 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 981364 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 795503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 313068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 17861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 16010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 11987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -188,164 +188,150 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 57274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 64486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 68059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 69963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 74225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 75616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 79113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 78742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 81088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 80039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 81169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 88387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 80912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 76308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 72380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 122 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 940608 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 187.797442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 115.260175 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 246.189901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 561167 59.66% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 186793 19.86% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 62478 6.64% 86.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 31194 3.32% 89.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21090 2.24% 91.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13303 1.41% 93.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10059 1.07% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 10062 1.07% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 44462 4.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 940608 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 69828 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.009810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 322.555489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 69825 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 14920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 38389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 48185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 52683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 54849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 56160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 63775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 64447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 68672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 57038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 86 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 737647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 193.317834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 117.156586 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 253.851861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 435526 59.04% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146539 19.87% 78.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49058 6.65% 85.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 25178 3.41% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15871 2.15% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10341 1.40% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7959 1.08% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8404 1.14% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 38771 5.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 737647 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 55115 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.615186 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 363.032286 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 55112 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 69828 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 69828 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.516727 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.040521 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.611414 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 66194 94.80% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1213 1.74% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 484 0.69% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 227 0.33% 97.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 283 0.41% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 499 0.71% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 107 0.15% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 41 0.06% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 40 0.06% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 28 0.04% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 48 0.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 19 0.03% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 437 0.63% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 59 0.08% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 38 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 18 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 30 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 69828 # Writes before turning the bus around for reads -system.physmem.totQLat 47438420321 # Total ticks spent queuing -system.physmem.totMemAccLat 76255445321 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7684540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30866.14 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 55115 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 55115 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.811122 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.212895 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.489514 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 52725 95.66% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 682 1.24% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 764 1.39% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 154 0.28% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 76 0.14% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 61 0.11% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 472 0.86% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 111 0.20% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 10 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 8 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 31 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 55115 # Writes before turning the bus around for reads +system.physmem.totQLat 32865022462 # Total ticks spent queuing +system.physmem.totMemAccLat 56236709962 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6232450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26366.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 49616.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.07 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45116.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.68 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing -system.physmem.readRowHits 1237162 # Number of row buffer hits during reads -system.physmem.writeRowHits 582295 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.61 # Row buffer hit rate for writes -system.physmem.avgGap 17185305.18 # Average gap between requests -system.physmem.pageHitRate 65.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3664415160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1999432875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5961079800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4040267040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1200459376170 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27436362274500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31753801677225 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.749891 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45642197013620 # Time in different power states -system.physmem_0.memoryStateTime::REF 1585539280000 # Time in different power states +system.physmem.avgWrQLen 23.59 # Average write queue length when enqueuing +system.physmem.readRowHits 1009662 # Number of row buffer hits during reads +system.physmem.writeRowHits 480836 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 48.98 # Row buffer hit rate for writes +system.physmem.avgGap 21250619.81 # Average gap between requests +system.physmem.pageHitRate 66.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2808479520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1532404500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4673861400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3196149840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3096718466400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1173181763970 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27418066728000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31700177853630 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.611477 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45611956984095 # Time in different power states +system.physmem_0.memoryStateTime::REF 1583189400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 254592941380 # Time in different power states +system.physmem_0.memoryStateTime::ACT 216810169905 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3446581320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1880575125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6026748000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3885796800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3101314831680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1189099091205 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27446327436750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31751981060880 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.711548 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45658799171891 # Time in different power states -system.physmem_1.memoryStateTime::REF 1585539280000 # Time in different power states +system.physmem_1.actEnergy 2768124240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1510385250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5048596800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3165006960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3096718466400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1175060323800 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27416418868500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31700689771950 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.622274 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45609169557313 # Time in different power states +system.physmem_1.memoryStateTime::REF 1583189400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 237989586859 # Time in different power states +system.physmem_1.memoryStateTime::ACT 219597434187 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -376,18 +362,18 @@ system.realview.nvmem.bw_total::total 28 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 132987745 # Number of BP lookups -system.cpu0.branchPred.condPredicted 94268605 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6098049 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 100013530 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 72636793 # Number of BTB hits +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 130279608 # Number of BP lookups +system.cpu0.branchPred.condPredicted 91518189 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6235368 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 97695080 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 70156250 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.626967 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15695407 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1093856 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.811446 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15568853 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1041049 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -418,66 +404,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 275636 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 275636 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8285 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76005 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 275636 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 275636 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 275636 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 84290 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 20584.826195 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18820.617576 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14196.942212 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 79742 94.60% 94.60% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3631 4.31% 98.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 417 0.49% 99.41% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 355 0.42% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 30 0.04% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 13 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 32 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 8 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 18 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 24 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 84290 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 272738 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 272738 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8357 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 77299 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 272738 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 272738 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 272738 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 85656 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 20319.907537 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18687.643521 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 12933.686898 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 84887 99.10% 99.10% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 657 0.77% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 28 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 42 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 27 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 85656 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 669754704 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 669754704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 669754704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 76005 90.17% 90.17% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8285 9.83% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 84290 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 275636 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 77299 90.24% 90.24% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8357 9.76% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 85656 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 272738 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 275636 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 84290 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 272738 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85656 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 84290 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 359926 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85656 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 358394 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 84907220 # DTB read hits -system.cpu0.dtb.read_misses 227423 # DTB read misses -system.cpu0.dtb.write_hits 75575788 # DTB write hits -system.cpu0.dtb.write_misses 48213 # DTB write misses +system.cpu0.dtb.read_hits 83911764 # DTB read hits +system.cpu0.dtb.read_misses 226051 # DTB read misses +system.cpu0.dtb.write_hits 74892635 # DTB write hits +system.cpu0.dtb.write_misses 46687 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35105 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1851 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8962 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 35474 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1932 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8858 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10953 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 85134643 # DTB read accesses -system.cpu0.dtb.write_accesses 75624001 # DTB write accesses +system.cpu0.dtb.perms_faults 11487 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 84137815 # DTB read accesses +system.cpu0.dtb.write_accesses 74939322 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 160483008 # DTB hits -system.cpu0.dtb.misses 275636 # DTB misses -system.cpu0.dtb.accesses 160758644 # DTB accesses +system.cpu0.dtb.hits 158804399 # DTB hits +system.cpu0.dtb.misses 272738 # DTB misses +system.cpu0.dtb.accesses 159077137 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,193 +488,190 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 64906 # Table walker walks requested -system.cpu0.itb.walker.walksLong 64906 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 453 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52493 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 64906 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 64906 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 64906 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52946 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 23323.187776 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21129.664435 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 16367.746814 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 48035 90.72% 90.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3919 7.40% 98.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 305 0.58% 98.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 573 1.08% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 22 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 23 0.04% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 32 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 11 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52946 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 68078 # Table walker walks requested +system.cpu0.itb.walker.walksLong 68078 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 722 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61066 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 68078 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 68078 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 68078 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 61788 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 22737.489480 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21008.732396 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 13692.086470 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 57025 92.29% 92.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3907 6.32% 98.61% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 284 0.46% 99.07% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 503 0.81% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 9 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 25 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 61788 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 669040204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 669040204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 669040204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 52493 99.14% 99.14% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 453 0.86% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52946 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 61066 98.83% 98.83% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 722 1.17% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 61788 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64906 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64906 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 68078 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 68078 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52946 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52946 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 117852 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 238223958 # ITB inst hits -system.cpu0.itb.inst_misses 64906 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61788 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61788 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 129866 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 232943519 # ITB inst hits +system.cpu0.itb.inst_misses 68078 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24846 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25164 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 205008 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 198596 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 238288864 # ITB inst accesses -system.cpu0.itb.hits 238223958 # DTB hits -system.cpu0.itb.misses 64906 # DTB misses -system.cpu0.itb.accesses 238288864 # DTB accesses -system.cpu0.numCycles 971262699 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 233011597 # ITB inst accesses +system.cpu0.itb.hits 232943519 # DTB hits +system.cpu0.itb.misses 68078 # DTB misses +system.cpu0.itb.accesses 233011597 # DTB accesses +system.cpu0.numCycles 944358949 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 437915417 # Number of instructions committed -system.cpu0.committedOps 515248827 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 45685554 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4508 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93994129820 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.217923 # CPI: cycles per instruction -system.cpu0.ipc 0.450872 # IPC: instructions per cycle +system.cpu0.committedInsts 433389926 # Number of instructions committed +system.cpu0.committedOps 509312382 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 43329563 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4813 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93880363578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.179005 # CPI: cycles per instruction +system.cpu0.ipc 0.458925 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13434 # number of quiesce instructions executed -system.cpu0.tickCycles 710739035 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 260523664 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5570429 # number of replacements -system.cpu0.dcache.tags.tagsinuse 501.849943 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 152007137 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5570934 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.285754 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4974167000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.849943 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980176 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.980176 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 323765599 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 323765599 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77611950 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77611950 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69963904 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69963904 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 263445 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 263445 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 169638 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 169638 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1758419 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1758419 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721710 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1721710 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147575854 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 147575854 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147839299 # number of overall hits -system.cpu0.dcache.overall_hits::total 147839299 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3380647 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3380647 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2384184 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2384184 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670394 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 670394 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 781336 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 781336 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 154783 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 154783 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189820 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 189820 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5764831 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5764831 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6435225 # number of overall misses -system.cpu0.dcache.overall_misses::total 6435225 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 51653726500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 51653726500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46144722000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 46144722000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 52344211500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 52344211500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2307846500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2307846500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3989603000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3989603000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3214000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3214000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 97798448500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 97798448500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 97798448500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 97798448500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80992597 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 80992597 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 72348088 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 72348088 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 933839 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 933839 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 950974 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 950974 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1913202 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1913202 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1911530 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1911530 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 153340685 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 153340685 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 154274524 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 154274524 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041740 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.041740 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032954 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.032954 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.717890 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.717890 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.821617 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.821617 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080903 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080903 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099303 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099303 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037595 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.037595 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041713 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.041713 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15279.242849 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15279.242849 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19354.513746 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19354.513746 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66993.216107 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66993.216107 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14910.206547 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14910.206547 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21017.822147 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21017.822147 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13422 # number of quiesce instructions executed +system.cpu0.tickCycles 695520331 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 248838618 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5405789 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.914885 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 150600436 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5406301 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.856465 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4974406000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.914885 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978349 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.978349 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 320300004 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 320300004 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77010804 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77010804 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69515704 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69515704 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 254236 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 254236 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 165535 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 165535 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1598340 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1598340 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1577518 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1577518 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 146526508 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 146526508 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 146780744 # number of overall hits +system.cpu0.dcache.overall_hits::total 146780744 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3243116 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3243116 # 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average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16964.668782 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15197.362718 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15197.362718 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16494.842280 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16494.842280 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14830.678697 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14830.678697 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -702,161 +680,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # 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number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 821200 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113610 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113610 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 174645 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 174645 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4164201 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4164201 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4776692 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4776692 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 30167 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 30167 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29885 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29885 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60052 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60052 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38218904500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38218904500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23577025500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23577025500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13456556000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13456556000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 50843266000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 50843266000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1513106500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1513106500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3501575000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3501575000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2054500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2054500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61795930000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61795930000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75252486000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 75252486000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5426212000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5426212000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5134567500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5134567500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10560779500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10560779500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035483 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035483 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.702043 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.702043 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.832159 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.832159 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064782 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064782 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099670 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099670 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027390 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027390 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031239 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031239 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13421.373500 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13421.373500 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17907.698775 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17907.698775 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21970.210175 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21970.210175 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61913.377983 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 61913.377983 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13318.427075 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.427075 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20049.672192 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20049.672192 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15247.147095 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15247.147095 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16273.479421 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16273.479421 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179789.687367 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179789.687367 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173175.057139 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173175.057139 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176485.745163 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176485.745163 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14839.804803 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14839.804803 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15754.100537 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15754.100537 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179872.443398 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179872.443398 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171810.858290 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171810.858290 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175860.579165 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 175860.579165 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9510825 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.926606 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 228501569 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9511337 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.024127 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 29799763000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926606 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999857 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 9471710 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.926461 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 223265309 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9472222 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 23.570532 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 29829927000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926461 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999856 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999856 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 431 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 485537176 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 485537176 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 228501569 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 228501569 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 228501569 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 228501569 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 228501569 # number of overall hits -system.cpu0.icache.overall_hits::total 228501569 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9511346 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9511346 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9511346 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9511346 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9511346 # number of overall misses -system.cpu0.icache.overall_misses::total 9511346 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94734195000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 94734195000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 94734195000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 94734195000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 94734195000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 94734195000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 238012915 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 238012915 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 238012915 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 238012915 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 238012915 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 238012915 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039961 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.039961 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039961 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.039961 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039961 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.039961 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9960.124992 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9960.124992 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9960.124992 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9960.124992 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9960.124992 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9960.124992 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 474947313 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 474947313 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 223265309 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 223265309 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 223265309 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 223265309 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 223265309 # number of overall hits +system.cpu0.icache.overall_hits::total 223265309 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9472232 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9472232 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9472232 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9472232 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9472232 # number of overall misses +system.cpu0.icache.overall_misses::total 9472232 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93317915500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 93317915500 # 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miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.040699 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040699 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.040699 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040699 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.040699 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9851.734575 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9851.734575 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9851.734575 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9851.734575 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9851.734575 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9851.734575 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -865,252 +843,256 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9511346 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9511346 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9511346 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9511346 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9511346 # 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number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89978522000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 89978522000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89978522000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 89978522000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89978522000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 89978522000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88581800000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 88581800000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88581800000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 88581800000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88581800000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 88581800000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4777780500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4777780500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039961 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.039961 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039961 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.039961 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9460.124992 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9460.124992 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9460.124992 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9460.124992 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040699 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.040699 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040699 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.040699 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9351.734628 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9351.734628 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9351.734628 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9351.734628 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7512189 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7515615 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2942 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7001248 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7002240 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 870 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 975521 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2798117 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16231.650842 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 26314432 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2814109 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.350893 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 27335773000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6405.405319 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.558250 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 59.359829 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5460.175756 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3311.396146 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 928.755541 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.390955 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004062 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003623 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.333263 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.202112 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056687 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.990701 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1465 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14441 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 685 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 484 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 25 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 40 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 821 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4037 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5036 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4531 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089417 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005249 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.881409 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 507029075 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 507029075 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 480958 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155860 # 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number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12195 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8813 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 21008 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 130468 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 130468 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154478 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 154478 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 278567 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 278567 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 777554 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 777554 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1020411 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1020411 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 589182 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 589182 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12195 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8813 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 777554 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1298978 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2097540 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12195 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8813 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 777554 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1298978 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2097540 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 429581500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 328472000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 758053500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2811659500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2811659500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3201796000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3201796000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2748498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2748498 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13465224999 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 13465224999 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 23641079500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 23641079500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33953780489 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33953780489 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 49014503000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 49014503000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 429581500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 328472000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23641079500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 47419005488 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 71818138488 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 429581500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 328472000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23641079500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 47419005488 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 71818138488 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 493153 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164673 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 657826 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3773399 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3773399 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 239769 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 239769 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 189774 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 189774 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1156290 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1156290 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9511345 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 9511345 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3729138 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 3729138 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 779633 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 779633 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 493153 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164673 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 9511345 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4885428 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 15054599 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 493153 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164673 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 9511345 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4885428 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 15054599 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024729 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053518 # 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Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 27364878000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6164.786775 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 75.653187 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.660205 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5461.877118 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3523.510222 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 883.909079 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.376269 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004618 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004862 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 56 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1133 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5245 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7645 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 403 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.090576 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.888184 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 499794711 # 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number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1104644 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1104644 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9472231 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 9472231 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3573441 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 3573441 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819709 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 819709 # 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number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 217332000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17856881500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34780457489 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 24692938914 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 77812717903 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5648614500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10008059000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5436600500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5436600500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5184743000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9544187500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4910404000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4910404000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11085215000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15444659500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.031931 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10095147000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14454591500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021721 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045551 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027949 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.544140 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.544140 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.814010 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.814010 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.552666 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.552666 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.808003 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.808003 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233619 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233619 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081749 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273400 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.273400 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755630 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755630 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.138710 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024729 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.053500 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.081749 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263984 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233020 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233020 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079539 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079539 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.261370 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261370 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.712968 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.712968 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021721 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045551 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079539 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.254675 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.132553 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021721 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045551 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079539 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.254675 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187286 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30086.717448 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48894.087088 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20301.303730 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20301.303730 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15251.634537 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15251.634537 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 794166 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 794166 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39966.645809 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39966.645809 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24404.302768 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27220.014094 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27220.014094 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 77198.341917 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77198.341917 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27849.318172 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29226.035260 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31278.093076 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24404.302768 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29889.876681 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48894.087088 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33307.659423 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177598 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26111.712492 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 37010.854497 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20276.645096 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20276.645096 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15402.680134 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15402.680134 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 858000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 858000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38499.621214 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38499.621214 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23701.224158 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23701.224158 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26628.258994 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26628.258994 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 76028.640923 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 76028.640923 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23701.224158 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29193.102099 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27056.580674 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24996.039977 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27615.247776 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23701.224158 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29193.102099 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37010.854497 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29581.343345 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171784.395718 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117501.338437 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165674.249581 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165674.249581 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171868.034607 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 115744.642792 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164309.988288 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164309.988288 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168732.438315 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130899.147378 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168106.757477 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128663.671402 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 870203 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14200168 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32815 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 7469298 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 14383795 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1113522 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 480939 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348630 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 494804 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 46 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1552927 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1165328 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9511346 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6196752 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 886361 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 779633 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28635865 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18059535 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 358708 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1078688 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 48132796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 612072768 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561022439 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1317384 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3945224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1178357815 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 11561310 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 42854991 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.281176 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.449573 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 876246 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14005082 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 29885 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 6885213 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 13979886 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 878417 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 473566 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 319318 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 460407 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1465787 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1113779 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9472232 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5781099 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 926693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 819709 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28518742 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17480007 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 376075 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1070420 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 47445244 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609569408 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 544120273 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1382192 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3906208 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1158978081 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 10243316 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 41099849 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.261354 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.439372 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 30805196 71.88% 71.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 12049795 28.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 30358253 73.86% 73.86% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 10741596 26.14% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 42854991 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 19582200977 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 41099849 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 19306972981 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 188679986 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 182073987 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14347273859 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14288744572 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7985002182 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7674112954 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 194043982 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 203313475 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 585561447 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 582176435 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 137760504 # Number of BP lookups -system.cpu1.branchPred.condPredicted 98367064 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6188278 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 103396299 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 75843064 # Number of BTB hits +system.cpu1.branchPred.lookups 125904408 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89122664 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5902634 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 94266188 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 68486701 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.351817 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15930905 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1003913 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.652456 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15015861 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1004863 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1378,62 +1364,65 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 290439 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 290439 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10797 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87034 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 290439 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 290439 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 290439 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 97831 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20885.603745 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 19076.396548 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15781.781984 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 96557 98.70% 98.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.10% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 36 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 66 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 60 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 20 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 97831 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1532721648 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1532721648 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1532721648 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 87034 88.96% 88.96% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10797 11.04% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 97831 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 290439 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 261999 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 261999 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7478 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 69980 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 261999 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 261999 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 261999 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 77458 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19301.763536 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17918.383858 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 10994.886931 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 74315 95.94% 95.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2659 3.43% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 247 0.32% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 165 0.21% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 17 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 5 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 16 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 10 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 77458 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1501931648 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1501931648 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1501931648 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 69980 90.35% 90.35% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 7478 9.65% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 77458 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261999 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 290439 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97831 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261999 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77458 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97831 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 388270 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77458 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 339457 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 89204123 # DTB read hits -system.cpu1.dtb.read_misses 242859 # DTB read misses -system.cpu1.dtb.write_hits 77378465 # DTB write hits -system.cpu1.dtb.write_misses 47580 # DTB write misses +system.cpu1.dtb.read_hits 82663207 # DTB read hits +system.cpu1.dtb.read_misses 218762 # DTB read misses +system.cpu1.dtb.write_hits 71167787 # DTB write hits +system.cpu1.dtb.write_misses 43237 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 40087 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1034 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8257 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 35788 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 902 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6887 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11467 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 89446982 # DTB read accesses -system.cpu1.dtb.write_accesses 77426045 # DTB write accesses +system.cpu1.dtb.perms_faults 9904 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 82881969 # DTB read accesses +system.cpu1.dtb.write_accesses 71211024 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 166582588 # DTB hits -system.cpu1.dtb.misses 290439 # DTB misses -system.cpu1.dtb.accesses 166873027 # DTB accesses +system.cpu1.dtb.hits 153830994 # DTB hits +system.cpu1.dtb.misses 261999 # DTB misses +system.cpu1.dtb.accesses 154092993 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1463,192 +1452,191 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 66791 # Table walker walks requested -system.cpu1.itb.walker.walksLong 66791 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 712 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57147 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 66791 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 66791 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 66791 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 57859 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 23479.562384 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21074.499694 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18067.183609 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 53326 92.17% 92.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 3146 5.44% 97.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 488 0.84% 98.45% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 735 1.27% 99.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.05% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 27 0.05% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 8 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 59152 # Table walker walks requested +system.cpu1.itb.walker.walksLong 59152 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 461 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48561 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 59152 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 59152 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 59152 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 49022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21340.612378 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19735.982166 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 12453.289543 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 45897 93.63% 93.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2624 5.35% 98.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 160 0.33% 99.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 295 0.60% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 9 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 10 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 57859 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1533304148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1533304148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1533304148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 57147 98.77% 98.77% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 712 1.23% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 57859 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 49022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1502514148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1502514148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1502514148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 48561 99.06% 99.06% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 461 0.94% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 49022 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 66791 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 66791 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59152 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59152 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57859 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57859 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 124650 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 246625416 # ITB inst hits -system.cpu1.itb.inst_misses 66791 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49022 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49022 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 108174 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 225695696 # ITB inst hits +system.cpu1.itb.inst_misses 59152 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41950 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1046 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 29073 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 38178 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25916 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 217204 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 201769 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 246692207 # ITB inst accesses -system.cpu1.itb.hits 246625416 # DTB hits -system.cpu1.itb.misses 66791 # DTB misses -system.cpu1.itb.accesses 246692207 # DTB accesses -system.cpu1.numCycles 916577474 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 225754848 # ITB inst accesses +system.cpu1.itb.hits 225695696 # DTB hits +system.cpu1.itb.misses 59152 # DTB misses +system.cpu1.itb.accesses 225754848 # DTB accesses +system.cpu1.numCycles 837975509 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 453450144 # Number of instructions committed -system.cpu1.committedOps 532984432 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 47678042 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5221 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94048897478 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.021341 # CPI: cycles per instruction -system.cpu1.ipc 0.494721 # IPC: instructions per cycle +system.cpu1.committedInsts 416666374 # Number of instructions committed +system.cpu1.committedOps 490559113 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 42698463 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4659 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93986622085 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.011143 # CPI: cycles per instruction +system.cpu1.ipc 0.497230 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5293 # number of quiesce instructions executed -system.cpu1.tickCycles 728135326 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 188442148 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5347951 # number of replacements -system.cpu1.dcache.tags.tagsinuse 430.817141 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 158458993 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5348463 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.627015 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8387659413500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.817141 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.841440 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.841440 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5009 # number of quiesce instructions executed +system.cpu1.tickCycles 670350336 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 167625173 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4806043 # number of replacements +system.cpu1.dcache.tags.tagsinuse 444.186980 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 146495712 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4806555 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.478318 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8387638822500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 444.186980 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867553 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.867553 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 335833986 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 335833986 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 81837847 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 81837847 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 72225758 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 72225758 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 239509 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 239509 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 145455 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 145455 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1785819 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1785819 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1759762 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1759762 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 154063605 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 154063605 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 154303114 # number of overall hits -system.cpu1.dcache.overall_hits::total 154303114 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3469404 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3469404 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2254005 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2254005 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 641263 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 641263 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 468533 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 468533 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 172541 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 172541 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 196757 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 196757 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5723409 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5723409 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6364672 # number of overall misses -system.cpu1.dcache.overall_misses::total 6364672 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 51425230000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 51425230000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38096829500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 38096829500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16555952500 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 16555952500 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2623224000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2623224000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4131954500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4131954500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2147500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2147500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 89522059500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 89522059500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 89522059500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 89522059500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 85307251 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 85307251 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 74479763 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 74479763 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 880772 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 880772 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 613988 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 613988 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1958360 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1958360 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1956519 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1956519 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 159787014 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 159787014 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 160667786 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 160667786 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040670 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030263 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030263 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.728069 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.728069 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.763098 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.763098 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088105 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088105 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100565 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100565 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035819 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035819 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039614 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.039614 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14822.496890 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14822.496890 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16901.838949 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16901.838949 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 35335.723418 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 35335.723418 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15203.482071 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15203.482071 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21000.292239 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21000.292239 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 309963007 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 309963007 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 75874550 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 75874550 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 66435000 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 66435000 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 232604 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 232604 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 157450 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 157450 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1693988 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1693988 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1671438 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1671438 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 142309550 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 142309550 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 142542154 # number of overall hits +system.cpu1.dcache.overall_hits::total 142542154 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3161753 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3161753 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1996683 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1996683 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 552089 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 552089 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 421817 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 421817 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158395 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 158395 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 179133 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 179133 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5158436 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5158436 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5710525 # number of overall misses +system.cpu1.dcache.overall_misses::total 5710525 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43703345000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 43703345000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 33230827500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 33230827500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 13699084500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 13699084500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2222797000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2222797000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3749543500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3749543500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3215500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3215500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 76934172500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 76934172500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 76934172500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 76934172500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 79036303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 79036303 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 68431683 # 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average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15641.387764 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14065.463153 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14065.463153 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14914.243872 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14914.243872 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13472.346676 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13472.346676 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1657,161 +1645,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # 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average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3028608 # number of writebacks +system.cpu1.dcache.writebacks::total 3028608 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 352163 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 352163 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 814004 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 814004 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 37997 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 37997 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 57 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 57 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 54284447500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 65376143500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 65376143500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1096081500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1096081500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1226588000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1226588000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2322669500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2322669500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035548 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035548 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017283 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017283 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.703146 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.703146 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.728091 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.728091 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064996 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064996 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096768 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096768 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027072 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027072 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030651 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030651 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12534.516958 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12534.516958 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16122.374710 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16122.374710 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20102.610946 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20102.610946 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31472.862464 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 31472.862464 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.443147 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12577.443147 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19929.493623 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19929.493623 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14346.513863 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14346.513863 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15063.161788 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15063.161788 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110657.100261 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110657.100261 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123326.799242 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 123326.799242 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116940.775878 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116940.775878 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13597.392235 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13597.392235 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14387.282701 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14387.282701 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 132874.469633 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 132874.469633 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145675.534442 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 145675.534442 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 139340.662307 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 139340.662307 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9156821 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.982135 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 237244674 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9157333 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.907617 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8375787773000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.982135 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990199 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990199 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 8962341 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.974355 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 216525917 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8962853 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 24.158147 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8375817756000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.974355 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990184 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990184 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 501961349 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 501961349 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 237244674 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 237244674 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 237244674 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 237244674 # 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average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1820,257 +1808,254 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9157334 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9157334 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9157334 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9157334 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 9157334 # 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mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.039749 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039749 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.039749 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9259.773534 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9259.773534 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9259.773534 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9259.773534 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9259.773534 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9259.773534 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94000 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7355033 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7356454 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 1193 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6768411 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6768469 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 54 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 921370 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2420449 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13525.501015 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 25921683 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2436577 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.638565 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9890893366500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5242.566110 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 80.941753 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.247702 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3561.549924 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3753.026790 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 801.168735 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.319981 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004940 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005264 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.217380 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229067 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048899 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.825531 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14878 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 534 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 335 # Occupied blocks per task id +system.cpu1.l2cache.prefetcher.pfSpanPage 863435 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2141720 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13540.912612 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 24731326 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2157705 # 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Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004579 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.265563 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.183849 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.054126 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.826472 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1213 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14689 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 25 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 401 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 707 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 75 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1163 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5423 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4799 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3398 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 488189494 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 488189494 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 527706 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160378 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 688084 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3440434 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3440434 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 69060 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 69060 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 37815 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 37815 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 888572 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 888572 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8367748 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 8367748 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2856681 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2856681 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 194722 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 194722 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 527706 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 160378 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 8367748 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3745253 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 12801085 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 527706 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 160378 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8367748 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3745253 # number of overall hits -system.cpu1.l2cache.overall_hits::total 12801085 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11992 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8532 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 20524 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 3 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 3 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 136249 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 136249 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158895 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 158895 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 235953 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 235953 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 789586 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 789586 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 992043 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 992043 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272649 # 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number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22229315000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 22229315000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31556071491 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31556071491 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 14034162000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 14034162000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 446382000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 354037500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22229315000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 41464728988 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 64494463488 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 446382000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 354037500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22229315000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 41464728988 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 64494463488 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 539698 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 168910 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 708608 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3440437 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3440437 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205309 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 205309 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 196710 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 196710 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1124525 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1124525 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9157334 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 9157334 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3848724 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3848724 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 467371 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 467371 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 539698 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 168910 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 9157334 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4973249 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 14839191 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 539698 # 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number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2201501000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022925 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050459 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029406 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.663629 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.663629 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.807763 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.807763 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.710853 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.710853 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808226 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.808226 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.203570 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.203570 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.086224 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.257602 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257602 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.583331 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.583331 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245384 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136831 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022220 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050500 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086224 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245384 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.223033 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.223033 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081982 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081982 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255225 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255225 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.600626 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.600626 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022925 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050459 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081982 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248089 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132643 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022925 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050459 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081982 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248089 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.185012 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33000.974564 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 42844.691183 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20281.638720 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20281.638720 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15343.862293 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15343.862293 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 376499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 376499.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33349.967224 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33349.967224 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22153.141840 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25787.655901 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25787.655901 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45475.391737 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45475.391737 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25299.806196 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31223.315544 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35500.117233 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22153.141840 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27206.226770 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 42844.691183 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29868.845908 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102654.211703 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102389.906576 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 115826.041667 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 115826.041667 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87139.784946 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109186.924667 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108995.995903 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.176468 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22829.961111 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30634.755737 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20238.984356 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20238.984356 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15250.222823 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15250.222823 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 398416.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 398416.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29763.899302 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29763.899302 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 21893.896751 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 21893.896751 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 22795.864026 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22795.864026 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 39429.951241 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 39429.951241 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21893.896751 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24184.423623 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23267.710276 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 21914.295169 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24181.481998 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21893.896751 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24184.423623 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30634.755737 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25097.274457 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86000 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124871.863256 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124438.503956 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 138175.178147 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 138175.178147 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86000 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 131591.757154 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 131338.802052 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 927149 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13939785 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5280 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 7136333 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 14143122 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1073027 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 445884 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 351130 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 465721 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1873672 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1132302 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9157334 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6348630 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 574099 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 467371 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27470555 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17217135 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368278 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1176846 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 46232814 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 586075264 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 544882505 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1351280 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4317584 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1136626633 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 12009621 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 42070384 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.298426 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.457567 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 832335 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13281124 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 8420 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 6193652 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 13562835 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 802874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 426908 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 320139 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 432313 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1723284 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 998712 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8962853 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5808138 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 527324 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 420340 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26886674 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15523980 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 318688 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1026227 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 43755569 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 573628544 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 486175782 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1136136 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3690912 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1064631374 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 10738560 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 39200977 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.285389 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.451600 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 29515487 70.16% 70.16% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 12554897 29.84% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 28013450 71.46% 71.46% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 11187527 28.54% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 42070384 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 18619089977 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 39200977 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 17410316483 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 181245984 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 171564976 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13738184900 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13446378573 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7905383000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7120820957 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 199375485 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 176677986 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 637173449 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 564893937 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40322 # Transaction distribution -system.iobus.trans_dist::ReadResp 40322 # Transaction distribution -system.iobus.trans_dist::WriteReq 136608 # Transaction distribution -system.iobus.trans_dist::WriteResp 136608 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47696 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40371 # Transaction distribution +system.iobus.trans_dist::ReadResp 40371 # Transaction distribution +system.iobus.trans_dist::WriteReq 136979 # Transaction distribution +system.iobus.trans_dist::WriteResp 136979 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47802 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2318,18 +2299,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122578 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231202 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231676 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231676 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353860 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47716 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47822 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2339,18 +2320,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155708 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496618 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36211000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513101 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36314000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2370,7 +2351,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 22142000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2378,71 +2359,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 569805082 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 570865133 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92701000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92952000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147898000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148116000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115582 # number of replacements -system.iocache.tags.tagsinuse 11.293791 # Cycle average of tags in use +system.iocache.tags.replacements 115819 # number of replacements +system.iocache.tags.tagsinuse 11.287255 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115598 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115835 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9174209621000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.830929 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.462862 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239433 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466429 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705862 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9174218723000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.836610 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.450645 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239788 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465665 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705453 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040766 # Number of tag accesses -system.iocache.tags.data_accesses 1040766 # Number of data accesses +system.iocache.tags.tag_accesses 1042899 # Number of tag accesses +system.iocache.tags.data_accesses 1042899 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8873 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8910 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8854 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8891 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8873 # number of demand (read+write) misses -system.iocache.demand_misses::total 8913 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8854 # number of demand (read+write) misses +system.iocache.demand_misses::total 8894 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8873 # number of overall misses -system.iocache.overall_misses::total 8913 # number of overall misses +system.iocache.overall_misses::realview.ide 8854 # number of overall misses +system.iocache.overall_misses::total 8894 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1631093968 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1636288968 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1658968057 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1664163057 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12624582114 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12624582114 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12654105076 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12654105076 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1631093968 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1636657968 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1658968057 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1664532057 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1631093968 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1636657968 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1658968057 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1664532057 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8873 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8854 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8891 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8873 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8913 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8854 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8894 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8873 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8913 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8854 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8894 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2457,54 +2438,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183826.661558 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183646.348822 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 187369.331037 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187173.890114 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118287.442040 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118287.442040 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118280.351043 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118280.351043 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183625.936048 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 187369.331037 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 187152.243872 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 183826.661558 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183625.936048 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31363 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 187369.331037 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 187152.243872 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32802 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3550 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3449 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.834648 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.510583 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106950 # number of writebacks +system.iocache.writebacks::total 106950 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8873 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8854 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8891 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # 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mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2519,613 +2500,614 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133826.661558 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133646.348822 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137369.331037 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 137173.890114 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # 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average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 133826.661558 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 133625.936048 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 137369.331037 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 137152.243872 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1460315 # number of replacements -system.l2c.tags.tagsinuse 63815.106569 # Cycle average of tags in use -system.l2c.tags.total_refs 6243583 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1520944 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.105071 # Average number of references to valid blocks. +system.l2c.tags.replacements 1146599 # number of replacements +system.l2c.tags.tagsinuse 63894.227459 # Cycle average of tags in use +system.l2c.tags.total_refs 5787888 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1208030 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.791179 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17020.262251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 105.114677 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 114.825043 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4617.432955 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6910.402402 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7514.168760 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 272.316465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 336.862323 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3976.770964 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9922.626808 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13024.323921 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.259709 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001604 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001752 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070456 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.105444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.114657 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004155 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.005140 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.060681 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.151407 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.198735 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.973741 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9634 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 233 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50762 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 214 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 450 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8970 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2000 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4985 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 43502 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.147003 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003555 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.774567 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 74931302 # Number of tag accesses -system.l2c.tags.data_accesses 74931302 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2473005 # number of Writeback hits -system.l2c.Writeback_hits::total 2473005 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1822 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 12846 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 35586 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.163101 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.002716 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.771545 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 67839853 # Number of tag accesses +system.l2c.tags.data_accesses 67839853 # Number of data accesses +system.l2c.Writeback_hits::writebacks 2183647 # number of Writeback hits +system.l2c.Writeback_hits::total 2183647 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 31153 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 25605 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 56758 # 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average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72295.516891 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78472.966724 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72080.078821 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 76710.913302 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 90010.669529 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72295.516891 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82838.998772 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72080.078821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75193.955857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86023.056630 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77347.918437 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78365.557554 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72295.516891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82838.998772 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106241.655903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79088.014981 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79323.293173 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72080.078821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75193.955857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103867.084189 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86023.056630 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153783.741865 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84684.936614 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96859.005197 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148672.360201 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 98824.053030 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141763.341646 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153867.338482 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 106897.235358 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 96814.419762 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147308.265016 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 121174.524941 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141563.686203 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151230.657412 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66118.279570 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91698.703495 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 110147.934372 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 150603.202225 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64973.118280 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 114109.977800 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 110091.472766 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 90631 # Transaction distribution -system.membus.trans_dist::ReadResp 933772 # Transaction distribution -system.membus.trans_dist::WriteReq 38095 # Transaction distribution -system.membus.trans_dist::WriteResp 38095 # Transaction distribution -system.membus.trans_dist::Writeback 1222852 # Transaction distribution -system.membus.trans_dist::CleanEvict 259291 # Transaction distribution -system.membus.trans_dist::UpgradeReq 429274 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 300804 # Transaction distribution -system.membus.trans_dist::UpgradeResp 113465 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 664837 # Transaction distribution -system.membus.trans_dist::ReadExResp 644660 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 843141 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122578 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 90799 # Transaction distribution +system.membus.trans_dist::ReadResp 698902 # Transaction distribution +system.membus.trans_dist::WriteReq 38305 # Transaction distribution +system.membus.trans_dist::WriteResp 38305 # Transaction distribution +system.membus.trans_dist::Writeback 981364 # Transaction distribution +system.membus.trans_dist::CleanEvict 209019 # Transaction distribution +system.membus.trans_dist::UpgradeReq 434160 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 274076 # Transaction distribution +system.membus.trans_dist::UpgradeResp 111283 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 609626 # Transaction distribution +system.membus.trans_dist::ReadExResp 589528 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 608103 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106984 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122944 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5299387 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5446901 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5789694 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155708 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25274 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4403229 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4551499 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343039 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 343039 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4894538 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155959 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 169409152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 169615952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7274560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7274560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 176890512 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 639479 # Total snoops (count) -system.membus.snoop_fanout::samples 3957833 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50548 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 135367808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 135575639 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7275904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7275904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 142851543 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 619953 # Total snoops (count) +system.membus.snoop_fanout::samples 3354848 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3957833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3354848 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3957833 # Request fanout histogram -system.membus.reqLayer0.occupancy 109447997 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3354848 # Request fanout histogram +system.membus.reqLayer0.occupancy 109588500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20601500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21072500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8645644788 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6982752656 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8381282870 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6858580357 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229327995 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229669194 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3169,46 +3151,46 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 90633 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5042509 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38095 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38095 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3695900 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1651242 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 481742 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 313276 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 795018 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 104 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1145784 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1145784 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4959107 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8783138 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7404481 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16187619 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 270950615 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 216626041 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 487576656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3318184 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13892424 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.121763 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.327012 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 90801 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4609563 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38305 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38305 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3165042 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1502795 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 483481 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 285744 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 769225 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 105 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 105 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1092976 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1092976 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4526002 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8264892 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6572319 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 14837211 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254099969 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185036822 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 439136791 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2966852 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 12598332 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.109406 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.312147 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 12200843 87.82% 87.82% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1691581 12.18% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 11220005 89.06% 89.06% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1378327 10.94% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13892424 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8859040198 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 12598332 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8167142441 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2520000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2478499 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5187778836 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4888169243 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4493465928 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4052371405 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 8076f9ab6..5e0f7ea36 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.309771 # Number of seconds simulated -sim_ticks 47309771277000 # Number of ticks simulated -final_tick 47309771277000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.309827 # Number of seconds simulated +sim_ticks 47309826639000 # Number of ticks simulated +final_tick 47309826639000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108265 # Simulator instruction rate (inst/s) -host_op_rate 127309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5527040503 # Simulator tick rate (ticks/s) -host_mem_usage 775928 # Number of bytes of host memory used -host_seconds 8559.69 # Real time elapsed on the host -sim_insts 926711685 # Number of instructions simulated -sim_ops 1089722710 # Number of ops (including micro ops) simulated +host_inst_rate 99581 # Simulator instruction rate (inst/s) +host_op_rate 117105 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4980017521 # Simulator tick rate (ticks/s) +host_mem_usage 777716 # Number of bytes of host memory used +host_seconds 9499.93 # Real time elapsed on the host +sim_insts 946011818 # Number of instructions simulated +sim_ops 1112485532 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 238272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 235456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4799840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 48757000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 23433152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 111936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 80000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2674208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 14294352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12912064 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 433024 # Number of bytes read from this memory -system.physmem.bytes_read::total 107969304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4799840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2674208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7474048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 89515968 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 184448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 167936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 5084832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 44767048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 19339456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 176320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 161792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2535456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 18891728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 20722048 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 420544 # Number of bytes read from this memory +system.physmem.bytes_read::total 112451608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 5084832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2535456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7620288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 93755328 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 89536552 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3723 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3679 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 90950 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 761841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 366143 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1749 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1250 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 41828 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 223362 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 201751 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6766 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1703042 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1398687 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 93775912 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2624 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 95403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 699498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 302179 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2528 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39660 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 295196 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 323782 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6571 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1773078 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1464927 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1401261 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 5036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 4977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 101456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1030590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 495313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1691 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 302144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 272926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2282178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 101456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56525 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 157981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1892124 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1467501 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 107479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 946253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 408783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 399319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 438007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8889 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2376919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 107479 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 161072 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1981731 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1892559 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1892124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 5036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 4977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 101456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1031025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 495313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1691 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 302144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 272926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4174737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1703042 # Number of read requests accepted -system.physmem.writeReqs 1401261 # Number of write requests accepted -system.physmem.readBursts 1703042 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1401261 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 108957568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue -system.physmem.bytesWritten 89535296 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 107969304 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 89536552 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1982166 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1981731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 107479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 946688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 408783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 399319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 438007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4359084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1773078 # Number of read requests accepted +system.physmem.writeReqs 1467501 # Number of write requests accepted +system.physmem.readBursts 1773078 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1467501 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 113443520 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue +system.physmem.bytesWritten 93774528 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 112451608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 93775912 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 222271 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 104244 # Per bank write bursts -system.physmem.perBankRdBursts::1 111881 # Per bank write bursts -system.physmem.perBankRdBursts::2 106230 # Per bank write bursts -system.physmem.perBankRdBursts::3 103315 # Per bank write bursts -system.physmem.perBankRdBursts::4 101355 # Per bank write bursts -system.physmem.perBankRdBursts::5 106401 # Per bank write bursts -system.physmem.perBankRdBursts::6 102755 # Per bank write bursts -system.physmem.perBankRdBursts::7 105565 # Per bank write bursts -system.physmem.perBankRdBursts::8 101297 # Per bank write bursts -system.physmem.perBankRdBursts::9 131029 # Per bank write bursts -system.physmem.perBankRdBursts::10 105406 # Per bank write bursts -system.physmem.perBankRdBursts::11 116947 # Per bank write bursts -system.physmem.perBankRdBursts::12 96908 # Per bank write bursts -system.physmem.perBankRdBursts::13 102973 # Per bank write bursts -system.physmem.perBankRdBursts::14 100156 # Per bank write bursts -system.physmem.perBankRdBursts::15 106000 # Per bank write bursts -system.physmem.perBankWrBursts::0 86649 # Per bank write bursts -system.physmem.perBankWrBursts::1 91854 # Per bank write bursts -system.physmem.perBankWrBursts::2 85255 # Per bank write bursts -system.physmem.perBankWrBursts::3 87156 # Per bank write bursts -system.physmem.perBankWrBursts::4 84624 # Per bank write bursts -system.physmem.perBankWrBursts::5 89053 # Per bank write bursts -system.physmem.perBankWrBursts::6 87549 # Per bank write bursts -system.physmem.perBankWrBursts::7 90107 # Per bank write bursts -system.physmem.perBankWrBursts::8 85432 # Per bank write bursts -system.physmem.perBankWrBursts::9 90372 # Per bank write bursts -system.physmem.perBankWrBursts::10 86508 # Per bank write bursts -system.physmem.perBankWrBursts::11 91779 # Per bank write bursts -system.physmem.perBankWrBursts::12 81073 # Per bank write bursts -system.physmem.perBankWrBursts::13 87139 # Per bank write bursts -system.physmem.perBankWrBursts::14 84132 # Per bank write bursts -system.physmem.perBankWrBursts::15 90307 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 224875 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 113386 # Per bank write bursts +system.physmem.perBankRdBursts::1 120644 # Per bank write bursts +system.physmem.perBankRdBursts::2 108661 # Per bank write bursts +system.physmem.perBankRdBursts::3 115173 # Per bank write bursts +system.physmem.perBankRdBursts::4 103078 # Per bank write bursts +system.physmem.perBankRdBursts::5 114921 # Per bank write bursts +system.physmem.perBankRdBursts::6 108340 # Per bank write bursts +system.physmem.perBankRdBursts::7 105879 # Per bank write bursts +system.physmem.perBankRdBursts::8 98747 # Per bank write bursts +system.physmem.perBankRdBursts::9 127278 # Per bank write bursts +system.physmem.perBankRdBursts::10 99197 # Per bank write bursts +system.physmem.perBankRdBursts::11 111650 # Per bank write bursts +system.physmem.perBankRdBursts::12 107228 # Per bank write bursts +system.physmem.perBankRdBursts::13 113583 # Per bank write bursts +system.physmem.perBankRdBursts::14 112177 # Per bank write bursts +system.physmem.perBankRdBursts::15 112613 # Per bank write bursts +system.physmem.perBankWrBursts::0 94420 # Per bank write bursts +system.physmem.perBankWrBursts::1 97266 # Per bank write bursts +system.physmem.perBankWrBursts::2 90974 # Per bank write bursts +system.physmem.perBankWrBursts::3 94616 # Per bank write bursts +system.physmem.perBankWrBursts::4 87287 # Per bank write bursts +system.physmem.perBankWrBursts::5 94599 # Per bank write bursts +system.physmem.perBankWrBursts::6 89304 # Per bank write bursts +system.physmem.perBankWrBursts::7 90590 # Per bank write bursts +system.physmem.perBankWrBursts::8 84448 # Per bank write bursts +system.physmem.perBankWrBursts::9 90113 # Per bank write bursts +system.physmem.perBankWrBursts::10 85465 # Per bank write bursts +system.physmem.perBankWrBursts::11 93225 # Per bank write bursts +system.physmem.perBankWrBursts::12 88655 # Per bank write bursts +system.physmem.perBankWrBursts::13 95246 # Per bank write bursts +system.physmem.perBankWrBursts::14 93025 # Per bank write bursts +system.physmem.perBankWrBursts::15 95994 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 40 # Number of times write queue was full causing retry -system.physmem.totGap 47309769886500 # Total gap between requests +system.physmem.numWrRetry 83 # Number of times write queue was full causing retry +system.physmem.totGap 47309825190500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1681684 # Read request sizes (log2) +system.physmem.readPktSize::6 1751720 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1398687 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 611880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 417253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 192449 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 184576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 110779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 65725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 35828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29054 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 540 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1464927 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 608524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 449703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 194607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 195607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 116312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 71048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 40112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 36551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 32712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 10303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 5634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 3467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,168 +188,170 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 19662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 42991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 51483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 69980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 79960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 85124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 91378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 92978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 97068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 98211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 103646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 116678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 108732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 103454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 92841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 104 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1072258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 185.116224 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 114.248094 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 242.173437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 644445 60.10% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 212244 19.79% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 67795 6.32% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36826 3.43% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25524 2.38% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13957 1.30% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14880 1.39% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9207 0.86% 95.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 47380 4.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1072258 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 80097 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.254829 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 256.467221 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 80095 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 20153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 23447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 36691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 53186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 72210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 82749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 88726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 95528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 97547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 101638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 103246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 108748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 123417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 115282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 109625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 98032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 281 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1119709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 185.063798 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 114.156365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.940793 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 674939 60.28% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 219039 19.56% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 70659 6.31% 86.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 37987 3.39% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 28223 2.52% 92.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14545 1.30% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 15798 1.41% 94.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9595 0.86% 95.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 48924 4.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1119709 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 84177 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.057367 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 250.150754 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 84175 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::69632-73727 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 80097 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 80097 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.466185 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.028138 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.338596 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 75079 93.74% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2441 3.05% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 604 0.75% 97.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 241 0.30% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 302 0.38% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 483 0.60% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 119 0.15% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 48 0.06% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 45 0.06% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 27 0.03% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 34 0.04% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 20 0.02% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 420 0.52% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 48 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 47 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 52 0.06% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 14 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 6 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 26 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 7 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 84177 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 84177 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.406501 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.998569 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.063432 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 78913 93.75% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2654 3.15% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 594 0.71% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 256 0.30% 97.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 356 0.42% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 499 0.59% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 111 0.13% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 36 0.04% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 47 0.06% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 28 0.03% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 36 0.04% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 26 0.03% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 418 0.50% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 37 0.04% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 46 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 46 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 25 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 80097 # Writes before turning the bus around for reads -system.physmem.totQLat 88359532056 # Total ticks spent queuing -system.physmem.totMemAccLat 120280694556 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8512310000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51901.03 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 84177 # Writes before turning the bus around for reads +system.physmem.totQLat 95142418476 # Total ticks spent queuing +system.physmem.totMemAccLat 128377824726 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8862775000 # Total ticks spent in databus transfers +system.physmem.avgQLat 53675.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70651.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.89 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.89 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 72425.30 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing -system.physmem.readRowHits 1368420 # Number of row buffer hits during reads -system.physmem.writeRowHits 660769 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.23 # Row buffer hit rate for writes -system.physmem.avgGap 15240061.90 # Average gap between requests -system.physmem.pageHitRate 65.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4037576760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2203042875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6565556400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4550560560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3090044124960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1167667097760 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27361592107500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31636660066815 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.713051 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45518112024303 # Time in different power states -system.physmem_0.memoryStateTime::REF 1579777160000 # Time in different power states +system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing +system.physmem.readRowHits 1427545 # Number of row buffer hits during reads +system.physmem.writeRowHits 690525 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.13 # Row buffer hit rate for writes +system.physmem.avgGap 14599188.97 # Average gap between requests +system.physmem.pageHitRate 65.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4299372000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2345887500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6942631800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4789082880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3090047684880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1174100419575 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27355981545000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31638506623635 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.751312 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45508743621503 # Time in different power states +system.physmem_0.memoryStateTime::REF 1579778980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 211880830197 # Time in different power states +system.physmem_0.memoryStateTime::ACT 221302763997 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4068693720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2220021375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6713584800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4514888160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3090044124960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1175652112905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27354587708250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31637801134170 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.737170 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45506397156129 # Time in different power states -system.physmem_1.memoryStateTime::REF 1579777160000 # Time in different power states +system.physmem_1.actEnergy 4165628040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2272912125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6883242600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4705588080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3090047684880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1168667714520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27360747075750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31637489845995 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.729820 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45516677078545 # Time in different power states +system.physmem_1.memoryStateTime::REF 1579778980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 223594850121 # Time in different power states +system.physmem_1.memoryStateTime::ACT 213370138955 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -383,15 +385,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 148829565 # Number of BP lookups -system.cpu0.branchPred.condPredicted 98586451 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7318222 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 104779817 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 69383898 # Number of BTB hits +system.cpu0.branchPred.lookups 147637418 # Number of BP lookups +system.cpu0.branchPred.condPredicted 98315773 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7247820 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 103619610 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 67413734 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.218762 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20536581 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 208145 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.058857 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20080737 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 195189 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -422,90 +424,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 633176 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 633176 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15593 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 103829 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 293482 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 339694 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2057.107279 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 12691.149268 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-32767 334819 98.56% 98.56% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-65535 2369 0.70% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-98303 775 0.23% 99.49% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-131071 1050 0.31% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-163839 325 0.10% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::163840-196607 166 0.05% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-229375 47 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::229376-262143 24 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-294911 28 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::294912-327679 54 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-360447 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::360448-393215 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-491519 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 339694 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 334006 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 19047.289570 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 15950.264710 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 18217.957975 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 329273 98.58% 98.58% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3345 1.00% 99.58% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 501 0.15% 99.73% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 607 0.18% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 176 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 53 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 23 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 15 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 334006 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 554756829244 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.612373 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.535164 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 553440790244 99.76% 99.76% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 774310500 0.14% 99.90% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 264675000 0.05% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 116251500 0.02% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 83135500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 43553500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 14917000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 18677500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 518500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 554756829244 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 103830 86.94% 86.94% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 15593 13.06% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 119423 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 633176 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 596316 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 596316 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13005 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90766 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 267964 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 328352 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 1967.306427 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12140.663837 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 326191 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1511 0.46% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 485 0.15% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 70 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 71 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 17 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 328352 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 293288 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 18414.921511 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15494.626324 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16461.439983 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 290000 98.88% 98.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2364 0.81% 99.68% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 368 0.13% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 346 0.12% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 119 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 72 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 12 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 293288 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 554812439744 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.594659 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.537153 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 553701545244 99.80% 99.80% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 589103000 0.11% 99.91% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 238633000 0.04% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 116174000 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 85227000 0.02% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 46829500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 15433000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 19112000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 363500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 19500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 554812439744 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 90767 87.47% 87.47% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 13005 12.53% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 103772 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 596316 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 633176 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 119423 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 596316 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 103772 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 119423 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 752599 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 103772 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 700088 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 108615139 # DTB read hits -system.cpu0.dtb.read_misses 465587 # DTB read misses -system.cpu0.dtb.write_hits 88878639 # DTB write hits -system.cpu0.dtb.write_misses 167589 # DTB write misses -system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 107674804 # DTB read hits +system.cpu0.dtb.read_misses 416109 # DTB read misses +system.cpu0.dtb.write_hits 89240851 # DTB write hits +system.cpu0.dtb.write_misses 180207 # DTB write misses +system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 45077 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 45162 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 301 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7481 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37572 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 168 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7516 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 44285 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 109080726 # DTB read accesses -system.cpu0.dtb.write_accesses 89046228 # DTB write accesses +system.cpu0.dtb.perms_faults 38101 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 108090913 # DTB read accesses +system.cpu0.dtb.write_accesses 89421058 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 197493778 # DTB hits -system.cpu0.dtb.misses 633176 # DTB misses -system.cpu0.dtb.accesses 198126954 # DTB accesses +system.cpu0.dtb.hits 196915655 # DTB hits +system.cpu0.dtb.misses 596316 # DTB misses +system.cpu0.dtb.accesses 197511971 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -535,1164 +531,1160 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 92658 # Table walker walks requested -system.cpu0.itb.walker.walksLong 92658 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1215 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67279 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10404 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 82254 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1278.472779 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 8944.038924 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 81396 98.96% 98.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 425 0.52% 99.47% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 229 0.28% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 180 0.22% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 82254 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 78898 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 24333.924814 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 20592.654972 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 23297.887242 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 76185 96.56% 96.56% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 2219 2.81% 99.37% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 249 0.32% 99.69% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 140 0.18% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 58 0.07% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 30 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 78898 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 417288840772 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.850626 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.356648 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 62357623096 14.94% 14.94% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 354908424176 85.05% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 20580000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1826000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 387500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 417288840772 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 67279 98.23% 98.23% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1215 1.77% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 68494 # Table walker page sizes translated +system.cpu0.itb.walker.walks 85428 # Table walker walks requested +system.cpu0.itb.walker.walksLong 85428 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 771 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61190 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10178 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 75250 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1283.993355 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 9203.446829 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 74460 98.95% 98.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 428 0.57% 99.52% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 166 0.22% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 158 0.21% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 10 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 75250 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72139 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 23671.051720 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 20466.529400 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 20605.197168 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 70248 97.38% 97.38% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1514 2.10% 99.48% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 196 0.27% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 111 0.15% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 47 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 72139 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 421639244068 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.834946 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.371382 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 69614918048 16.51% 16.51% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 352004823020 83.48% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 17379000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 2056500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 67500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 421639244068 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 61190 98.76% 98.76% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 771 1.24% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 61961 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 92658 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 92658 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85428 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85428 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 68494 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 68494 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 161152 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 234838704 # ITB inst hits -system.cpu0.itb.inst_misses 92658 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61961 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61961 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 147389 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 231535487 # ITB inst hits +system.cpu0.itb.inst_misses 85428 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 45077 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 33056 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26943 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 232539 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 216195 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 234931362 # ITB inst accesses -system.cpu0.itb.hits 234838704 # DTB hits -system.cpu0.itb.misses 92658 # DTB misses -system.cpu0.itb.accesses 234931362 # DTB accesses -system.cpu0.numCycles 826354541 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 231620915 # ITB inst accesses +system.cpu0.itb.hits 231535487 # DTB hits +system.cpu0.itb.misses 85428 # DTB misses +system.cpu0.itb.accesses 231620915 # DTB accesses +system.cpu0.numCycles 805724204 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 96417195 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 658349874 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 148829565 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 89920479 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 686511551 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15731276 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2082372 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 301509 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6642770 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 777478 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 876995 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 234604466 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1859928 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 30773 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 801475508 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.962394 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.215680 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 95731684 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 652075833 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 147637418 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 87494471 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 667504198 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15546378 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1866411 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 305738 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6228904 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 744813 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 860245 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 231319013 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1833472 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 28917 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 781015182 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.979576 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.220669 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 432057914 53.91% 53.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 143320091 17.88% 71.79% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 50277190 6.27% 78.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 175820313 21.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 414945915 53.13% 53.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 142136658 18.20% 71.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 48870776 6.26% 77.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 175061833 22.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 801475508 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.180104 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.796692 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 115405888 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 393574581 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 246061591 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 40857295 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5576153 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 21574429 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2334934 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 682682220 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 25205347 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5576153 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 153705251 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 60022582 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 253017805 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 248013590 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 81140127 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 664288996 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6473093 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10525488 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 404111 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 973821 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 42702914 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 12474 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 634198397 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1026536806 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 783997445 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 728382 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 571881769 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 62316623 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 17028830 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14786866 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 82376276 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 108687128 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 92520441 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9956675 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8516242 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 640223835 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 17051325 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 645202743 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2940745 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 58459841 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 38213470 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 295844 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 801475508 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.805019 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.062618 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 781015182 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.183236 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.809304 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 113248081 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 377378437 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 245811555 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 39067395 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5509714 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 21219272 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2308032 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 677494422 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 25172258 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5509714 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 150635102 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 57564950 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 243777898 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 246916319 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 76611199 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 659282826 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6463914 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 10193503 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 302591 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 345572 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 40114273 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11761 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 627680154 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1013922393 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 779757811 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 794183 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 565536193 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 62143943 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16063927 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14023847 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 79290060 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 107984972 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 92881396 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9789553 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8248701 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 636103677 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16216212 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 639991449 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2906968 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 58559234 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 38038909 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 288402 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 781015182 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.819435 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.071222 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 449210773 56.05% 56.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 147559174 18.41% 74.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 124891919 15.58% 90.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 71400363 8.91% 98.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8407753 1.05% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5526 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 434056489 55.58% 55.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 142602713 18.26% 73.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 124298977 15.92% 89.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 71442121 9.15% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8609991 1.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 4891 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 801475508 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 781015182 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 66711662 45.46% 45.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 70956 0.05% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 22678 0.02% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 31 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.52% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 38740309 26.40% 71.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 41215825 28.08% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 67040735 45.54% 45.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 53703 0.04% 45.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 26002 0.02% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 14 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 38206404 25.96% 71.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 41875543 28.45% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 441248281 68.39% 68.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1607382 0.25% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 84016 0.01% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 12 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 46433 0.01% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 111952136 17.35% 86.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 90264483 13.99% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 436779538 68.25% 68.25% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1517289 0.24% 68.48% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 81855 0.01% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 23 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.50% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 47604 0.01% 68.51% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 110932479 17.33% 85.84% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 90632632 14.16% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 645202743 # Type of FU issued -system.cpu0.iq.rate 0.780782 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 146761461 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.227466 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2240404538 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 715416173 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 626754280 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1178660 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 474470 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 433754 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 791232333 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 731871 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 3009936 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 639991449 # Type of FU issued +system.cpu0.iq.rate 0.794306 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 147202401 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.230007 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2209837146 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 710527601 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 621905864 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1270303 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 504170 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 467307 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 786402566 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 791283 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2962367 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13422485 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 18059 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 156652 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6220264 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13371443 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 16751 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 153989 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6295959 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2933130 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5035754 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2934112 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4671160 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5576153 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8424043 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 6068776 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 657405938 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5509714 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7058035 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 5778589 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 652441938 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 108687128 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 92520441 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 14528017 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 62220 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5930416 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 156652 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2211475 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3142674 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5354149 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 636790575 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 108609704 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7786358 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 107984972 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 92881396 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13772451 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 68630 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5639093 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 153989 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2201982 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3098287 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5300269 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 631633854 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 107665614 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7773689 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 130778 # number of nop insts executed -system.cpu0.iew.exec_refs 197486892 # number of memory reference insts executed -system.cpu0.iew.exec_branches 120113448 # Number of branches executed -system.cpu0.iew.exec_stores 88877188 # Number of stores executed -system.cpu0.iew.exec_rate 0.770602 # Inst execution rate -system.cpu0.iew.wb_sent 628006707 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 627188034 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 305309945 # num instructions producing a value -system.cpu0.iew.wb_consumers 500537218 # num instructions consuming a value +system.cpu0.iew.exec_nop 122049 # number of nop insts executed +system.cpu0.iew.exec_refs 196907522 # number of memory reference insts executed +system.cpu0.iew.exec_branches 119104624 # Number of branches executed +system.cpu0.iew.exec_stores 89241908 # Number of stores executed +system.cpu0.iew.exec_rate 0.783933 # Inst execution rate +system.cpu0.iew.wb_sent 623170550 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 622373171 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 301982038 # num instructions producing a value +system.cpu0.iew.wb_consumers 495557723 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.758982 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609965 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.772439 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609378 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 51032011 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16755481 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 5028737 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 791775198 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.756295 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.558039 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 51133197 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15927810 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4984345 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 771348242 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.769770 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.572751 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 529474510 66.87% 66.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 135713871 17.14% 84.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 58480062 7.39% 91.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 19506672 2.46% 93.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13859320 1.75% 95.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9636766 1.22% 96.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6431343 0.81% 97.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3969096 0.50% 98.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14703558 1.86% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 513096769 66.52% 66.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 132148168 17.13% 83.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 58179832 7.54% 91.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 19360594 2.51% 93.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 14004722 1.82% 95.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9477117 1.23% 96.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6473381 0.84% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3935015 0.51% 98.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14672644 1.90% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 791775198 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 510225692 # Number of instructions committed -system.cpu0.commit.committedOps 598815315 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 771348242 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 504955538 # Number of instructions committed +system.cpu0.commit.committedOps 593760630 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 181564818 # Number of memory references committed -system.cpu0.commit.loads 95264643 # Number of loads committed -system.cpu0.commit.membars 4026241 # Number of memory barriers committed -system.cpu0.commit.branches 114090927 # Number of branches committed -system.cpu0.commit.fp_insts 424114 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 549390032 # Number of committed integer instructions. -system.cpu0.commit.function_calls 15322892 # Number of function calls committed. +system.cpu0.commit.refs 181198957 # Number of memory references committed +system.cpu0.commit.loads 94613526 # Number of loads committed +system.cpu0.commit.membars 4060839 # Number of memory barriers committed +system.cpu0.commit.branches 113014510 # Number of branches committed +system.cpu0.commit.fp_insts 458000 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 545152087 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14971844 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 415791168 69.44% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1352857 0.23% 69.66% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 66520 0.01% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 39952 0.01% 69.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.68% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 95264643 15.91% 85.59% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 86300175 14.41% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 411193864 69.25% 69.25% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1260833 0.21% 69.46% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 65173 0.01% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 41761 0.01% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 94613526 15.93% 85.42% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 86585431 14.58% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 598815315 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14703558 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1422522153 # The number of ROB reads -system.cpu0.rob.rob_writes 1309355495 # The number of ROB writes -system.cpu0.timesIdled 1107002 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24879033 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93793188049 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 510225692 # Number of Instructions Simulated -system.cpu0.committedOps 598815315 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.619586 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.619586 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.617442 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.617442 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 751256572 # number of integer regfile reads -system.cpu0.int_regfile_writes 446675945 # number of integer regfile writes -system.cpu0.fp_regfile_reads 709287 # number of floating regfile reads -system.cpu0.fp_regfile_writes 346140 # number of floating regfile writes -system.cpu0.cc_regfile_reads 138932349 # number of cc regfile reads -system.cpu0.cc_regfile_writes 139558794 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1422736351 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16846265 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6557508 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.746857 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 168230159 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6558019 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.652588 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1887096000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.746857 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993646 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.993646 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 376736198 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 376736198 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 88222232 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 88222232 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 74841943 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 74841943 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 232729 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 232729 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 258353 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 258353 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1906592 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1906592 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1977838 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1977838 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 163064175 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 163064175 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 163296904 # number of overall hits -system.cpu0.dcache.overall_hits::total 163296904 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7298679 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7298679 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 8186484 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 8186484 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 785305 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 785305 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 832077 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 832077 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 303324 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 303324 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 192936 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 192936 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 15485163 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15485163 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 16270468 # number of overall misses -system.cpu0.dcache.overall_misses::total 16270468 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 111692276000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 111692276000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 148685242611 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 148685242611 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 79029404267 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 79029404267 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4531612500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4531612500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4045324000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4045324000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3600000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3600000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 260377518611 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 260377518611 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 260377518611 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 260377518611 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 95520911 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 95520911 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 83028427 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 83028427 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1018034 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1018034 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1090430 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1090430 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2209916 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2209916 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2170774 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2170774 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 178549338 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 178549338 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 179567372 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 179567372 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076409 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.076409 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.098599 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.098599 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.771394 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.771394 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763072 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.763072 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.137256 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.137256 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088879 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088879 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086728 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.086728 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.090609 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.090609 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15303.081010 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15303.081010 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18162.283419 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18162.283419 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 94978.474669 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 94978.474669 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14939.841556 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14939.841556 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20967.180827 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20967.180827 # average StoreCondReq miss latency +system.cpu0.commit.op_class_0::total 593760630 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14672644 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1397369391 # The number of ROB reads +system.cpu0.rob.rob_writes 1299419087 # The number of ROB writes +system.cpu0.timesIdled 1071653 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24709022 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93813929115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 504955538 # Number of Instructions Simulated +system.cpu0.committedOps 593760630 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.595634 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.595634 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.626710 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.626710 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 746722296 # number of integer regfile reads +system.cpu0.int_regfile_writes 443322911 # number of integer regfile writes +system.cpu0.fp_regfile_reads 778801 # number of floating regfile reads +system.cpu0.fp_regfile_writes 335108 # number of floating regfile writes +system.cpu0.cc_regfile_reads 136612374 # number of cc regfile reads +system.cpu0.cc_regfile_writes 137527114 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1389482326 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16167899 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6374252 # number of replacements +system.cpu0.dcache.tags.tagsinuse 504.525126 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 168612051 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6374762 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.449937 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1887138000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 504.525126 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.985401 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.985401 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 375986188 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 375986188 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 87724319 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 87724319 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75477797 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75477797 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 231729 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 231729 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 266468 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 266468 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2022541 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2022541 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2052696 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2052696 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 163202116 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 163202116 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 163433845 # number of overall hits +system.cpu0.dcache.overall_hits::total 163433845 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7197565 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7197565 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7724152 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7724152 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 724383 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 724383 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 844788 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 844788 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 278463 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 278463 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 208196 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 208196 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 14921717 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 14921717 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 15646100 # number of overall misses +system.cpu0.dcache.overall_misses::total 15646100 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108620779500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 108620779500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 138974834179 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 138974834179 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 74732911806 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 74732911806 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4099802000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4099802000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4408839000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4408839000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3050500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3050500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 247595613679 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 247595613679 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 247595613679 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 247595613679 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 94921884 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 94921884 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 83201949 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 83201949 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 956112 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 956112 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1111256 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1111256 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2301004 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2301004 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2260892 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2260892 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 178123833 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 178123833 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 179079945 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 179079945 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075826 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.075826 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.092836 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.092836 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.757634 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.757634 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760210 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760210 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.121018 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.121018 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092086 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092086 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.083772 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.083772 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087369 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.087369 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15091.323177 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15091.323177 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17992.244868 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17992.244868 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88463.510142 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88463.510142 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14722.968581 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14722.968581 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21176.386674 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21176.386674 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16814.645000 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16814.645000 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16003.074934 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16003.074934 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 24592023 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 22766928 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 764014 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 809850 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 32.187922 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 28.112525 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16592.970747 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16592.970747 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15824.749534 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15824.749534 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 23148520 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 20510394 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 766944 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 746852 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 30.182803 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 27.462461 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4422416 # number of writebacks -system.cpu0.dcache.writebacks::total 4422416 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3749707 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3749707 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6590276 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6590276 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4547 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4547 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 153940 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 153940 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 10339983 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 10339983 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 10339983 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 10339983 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3548972 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3548972 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1596208 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1596208 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 778051 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 778051 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 827530 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 827530 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 149384 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 149384 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 192928 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 192928 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5145180 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5145180 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5923231 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5923231 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20289 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20289 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22269 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 22269 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 42558 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 42558 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 52135719000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 52135719000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31476098425 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 31476098425 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17784168000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17784168000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 78021331267 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 78021331267 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2035314000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2035314000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3852473000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3852473000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3523000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3523000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83611817425 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 83611817425 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 101395985425 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 101395985425 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3695888000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3695888000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3839366000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3839366000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7535254000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7535254000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037154 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037154 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019225 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019225 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.764268 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.764268 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.758902 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.758902 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.067597 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.067597 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088875 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088875 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028817 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028817 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032986 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032986 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14690.372029 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14690.372029 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.296248 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.296248 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22857.329404 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22857.329404 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94282.178612 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94282.178612 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13624.712151 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13624.712151 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19968.449370 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19968.449370 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4317679 # number of writebacks +system.cpu0.dcache.writebacks::total 4317679 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3700903 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3700903 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6185217 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6185217 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 5102 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 5102 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141775 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141775 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9886120 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9886120 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9886120 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9886120 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3496662 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3496662 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1538935 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1538935 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 717217 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 717217 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 839686 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 839686 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 136688 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136688 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 208181 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 208181 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5035597 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5035597 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5752814 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5752814 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21352 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21352 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 23308 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 23308 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 44660 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 44660 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50025996500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50025996500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29968345030 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29968345030 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17752964500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17752964500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 73677446306 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 73677446306 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1889285500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1889285500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4200723000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4200723000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2985500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2985500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 79994341530 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 79994341530 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 97747306030 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 97747306030 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3896297500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3896297500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4053651000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4053651000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7949948500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7949948500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036837 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036837 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018496 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018496 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.750139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.755619 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.755619 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059404 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059404 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092079 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092079 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028270 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032124 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14306.786444 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14306.786444 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19473.431321 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19473.431321 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24752.570700 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24752.570700 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87744.045162 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87744.045162 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.882682 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.882682 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20178.224718 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20178.224718 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16250.513573 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16250.513573 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17118.357434 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17118.357434 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182162.156834 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182162.156834 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172408.550002 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172408.550002 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177058.461394 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177058.461394 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15885.771147 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15885.771147 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16991.216130 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16991.216130 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182479.275946 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182479.275946 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173916.723872 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173916.723872 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 178010.490372 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178010.490372 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6585231 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.955630 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 227602766 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6585743 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.559922 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 17287340000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.955630 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 6538162 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.955601 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 224372588 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6538674 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.314693 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 17322639000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.955601 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999913 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999913 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 310 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 309 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 475737897 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 475737897 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 227602766 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 227602766 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 227602766 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 227602766 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 227602766 # number of overall hits -system.cpu0.icache.overall_hits::total 227602766 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6973294 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6973294 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6973294 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6973294 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6973294 # number of overall misses -system.cpu0.icache.overall_misses::total 6973294 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 74030582287 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 74030582287 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 74030582287 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 74030582287 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 74030582287 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 74030582287 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 234576060 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 234576060 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 234576060 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 234576060 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 234576060 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 234576060 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029727 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029727 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029727 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029727 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029727 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029727 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10616.300171 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10616.300171 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10616.300171 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10616.300171 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10616.300171 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10616.300171 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10890869 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 530 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 815898 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 469120906 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 469120906 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 224372588 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 224372588 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 224372588 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 224372588 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 224372588 # number of overall hits +system.cpu0.icache.overall_hits::total 224372588 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6918516 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6918516 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6918516 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6918516 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6918516 # number of overall misses +system.cpu0.icache.overall_misses::total 6918516 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 73530599413 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 73530599413 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 73530599413 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 73530599413 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 73530599413 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 73530599413 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 231291104 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 231291104 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 231291104 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 231291104 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 231291104 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 231291104 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029913 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029913 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029913 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029913 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029913 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029913 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10628.088366 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10628.088366 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10628.088366 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10628.088366 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10628.088366 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10628.088366 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10842770 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 750 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 802318 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.348322 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 53 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.514305 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 75 # 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number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6585778 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6585778 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 379817 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 379817 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 379817 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 379817 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 379817 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 379817 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6538699 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6538699 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6538699 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6538699 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6538699 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6538699 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 67014306188 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 67014306188 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 67014306188 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 67014306188 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 67014306188 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 67014306188 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 66562536735 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 66562536735 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 66562536735 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 66562536735 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 66562536735 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 66562536735 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1863746498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1863746498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028075 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028075 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028075 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028075 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028075 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028075 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10175.609653 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10175.609653 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10175.609653 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10175.609653 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10175.609653 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10175.609653 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028270 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028270 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10179.782971 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10179.782971 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10179.782971 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8598962 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8934370 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 290328 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8420678 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8427841 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 6477 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1159342 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 3030105 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16246.172494 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 22237347 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3045780 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.301035 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 15974403000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7087.125273 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 75.689704 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 100.487660 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4186.697540 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3865.106436 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 931.065881 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.432564 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004620 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.006133 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.255536 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.235907 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056828 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.991588 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1420 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14155 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 86 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 252 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 649 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 433 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 77 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 782 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4799 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4726 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3642 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.086670 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006104 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.863953 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 448543088 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 448543088 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 611768 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 192592 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 804360 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4422408 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4422408 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 116889 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 116889 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 39729 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 39729 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1062033 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 1062033 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5870980 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5870980 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3339122 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 3339122 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 194533 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 194533 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 611768 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 192592 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5870980 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4401155 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 11076495 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 611768 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 192592 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5870980 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4401155 # number of overall hits -system.cpu0.l2cache.overall_hits::total 11076495 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 14162 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 11237 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 25399 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 6 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 6 # number of Writeback misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 131236 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 131236 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 153191 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 153191 # number of SCUpgradeReq misses +system.cpu0.l2cache.prefetcher.pfSpanPage 1085415 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2879166 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16210.435264 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 21867253 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2894850 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 7.553847 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 16000650500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7399.715112 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 85.098490 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 94.687899 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4348.179928 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3389.288950 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 893.464886 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.451643 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005194 # 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average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34567.701629 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31438.523322 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38324.304280 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43613.720364 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24980.193654 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34567.701629 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65257.964947 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41125.621412 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.223576 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 36711.343140 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60164.522850 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20509.164876 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20509.164876 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15278.770448 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15278.770448 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311937.250000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311937.250000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43035.628890 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43035.628890 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25770.418735 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30857.020661 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30857.020661 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108568.802099 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108568.802099 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33277.342309 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30865.934246 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33277.342309 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38829.564388 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174158.632757 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125953.995623 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164664.824060 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164664.824060 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174473.679281 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127313.288468 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166183.497812 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166183.497812 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169190.879905 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 139454.769890 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170147.043596 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 141049.935819 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1048889 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 12194005 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 984567 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11961948 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 38264 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 22269 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 8425423 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 11622390 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1249461 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 495211 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 344893 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 512947 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 23308 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 8463420 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 11561533 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1016095 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 502894 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 380729 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 540434 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 148 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1710859 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1368930 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6585778 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6660291 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 932989 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 826261 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19798041 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21027852 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 446745 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1372185 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 42644823 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 421828960 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 663719558 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1630632 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5007440 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1092186590 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 11579815 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 39116658 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.312501 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.463513 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1691199 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1306018 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6538699 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6804200 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 945007 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 838279 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19656927 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20547872 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414026 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1295337 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 41914162 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 418816352 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 645201790 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1526168 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4749384 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1070293694 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 11878703 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 38928585 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.320254 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.466574 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 26892655 68.75% 68.75% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 12224003 31.25% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 26461563 67.97% 67.97% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 12467022 32.03% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 39116658 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 18374497429 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 38928585 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 18022605428 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 206346476 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 218178978 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9904865164 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9834328997 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9419389746 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9151913574 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 243194937 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 223594319 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 746720066 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 702320680 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 121710225 # Number of BP lookups -system.cpu1.branchPred.condPredicted 81714662 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5979961 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 85476181 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 55576245 # Number of BTB hits +system.cpu1.branchPred.lookups 127974219 # Number of BP lookups +system.cpu1.branchPred.condPredicted 85721226 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6122377 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91131353 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 60172902 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.019570 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16076930 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 165894 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 66.028760 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17085083 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 181731 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1722,83 +1714,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 527361 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 527361 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10839 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84415 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 237711 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 289650 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2083.972035 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 12311.346834 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 287768 99.35% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1260 0.44% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 464 0.16% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 78 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 55 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 289650 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 263786 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 17712.334999 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 15356.267972 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 12186.421874 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 262356 99.46% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1127 0.43% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 155 0.06% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 73 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 35 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 26 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 263786 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 425904638364 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.594204 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.544845 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 424921434364 99.77% 99.77% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 524417000 0.12% 99.89% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 206354500 0.05% 99.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 102255000 0.02% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 73118500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 43959500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 13868000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 18884000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 347500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 425904638364 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 84415 88.62% 88.62% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10839 11.38% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 95254 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 527361 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 610901 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 610901 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 15580 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 103695 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 293448 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 317453 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2113.928676 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 12461.929670 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-32767 312797 98.53% 98.53% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-65535 2424 0.76% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-98303 700 0.22% 99.52% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-131071 857 0.27% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-163839 351 0.11% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::163840-196607 153 0.05% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-229375 53 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::229376-262143 19 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-294911 21 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::294912-327679 57 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-360447 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 317453 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 338102 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 18568.539967 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 16066.889111 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14911.003076 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 335377 99.19% 99.19% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1909 0.56% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 302 0.09% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 312 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 121 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 38 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 338102 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 438848021252 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.580073 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.553130 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 437543459752 99.70% 99.70% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 782991500 0.18% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 243923500 0.06% 99.94% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 110155500 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 88476500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 41634500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 16681500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 20049000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 649500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 438848021252 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 103695 86.94% 86.94% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 15580 13.06% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 119275 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 610901 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 527361 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 95254 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 610901 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 119275 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 95254 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 622615 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 119275 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 730176 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 90076123 # DTB read hits -system.cpu1.dtb.read_misses 364024 # DTB read misses -system.cpu1.dtb.write_hits 74326349 # DTB write hits -system.cpu1.dtb.write_misses 163337 # DTB write misses -system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 94901630 # DTB read hits +system.cpu1.dtb.read_misses 438242 # DTB read misses +system.cpu1.dtb.write_hits 77470080 # DTB write hits +system.cpu1.dtb.write_misses 172659 # DTB write misses +system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 45077 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 33241 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 185 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 5418 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 42323 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 163 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7630 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 36861 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 90440147 # DTB read accesses -system.cpu1.dtb.write_accesses 74489686 # DTB write accesses +system.cpu1.dtb.perms_faults 42941 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 95339872 # DTB read accesses +system.cpu1.dtb.write_accesses 77642739 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 164402472 # DTB hits -system.cpu1.dtb.misses 527361 # DTB misses -system.cpu1.dtb.accesses 164929833 # DTB accesses +system.cpu1.dtb.hits 172371710 # DTB hits +system.cpu1.dtb.misses 610901 # DTB misses +system.cpu1.dtb.accesses 172982611 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1828,1155 +1826,1161 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 77446 # Table walker walks requested -system.cpu1.itb.walker.walksLong 77446 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 594 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55102 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9325 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 68121 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1127.809339 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8184.124599 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 67907 99.69% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 190 0.28% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 68121 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 65021 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 21947.540026 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 19801.580238 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 14876.528667 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 64283 98.86% 98.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 594 0.91% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 78 0.12% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 16 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 86285 # Table walker walks requested +system.cpu1.itb.walker.walksLong 86285 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1166 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62692 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9855 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 76430 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1337.426403 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 10105.936208 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 75617 98.94% 98.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 383 0.50% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 204 0.27% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 174 0.23% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 76430 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 73713 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 23336.867310 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 20402.005732 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 19525.264050 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 72001 97.68% 97.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1393 1.89% 99.57% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 144 0.20% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 112 0.15% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 36 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 65021 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 387249857200 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.854665 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.352569 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 56297043096 14.54% 14.54% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 330938122104 85.46% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 13360500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1244000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 37500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 50000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 387249857200 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 55102 98.93% 98.93% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 594 1.07% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55696 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 73713 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 417370190772 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.853526 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.353735 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 61155433348 14.65% 14.65% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 356194673424 85.34% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 18786000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1262500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 417370190772 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 62692 98.17% 98.17% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1166 1.83% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63858 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77446 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77446 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 86285 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 86285 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55696 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55696 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 133142 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 191622824 # ITB inst hits -system.cpu1.itb.inst_misses 77446 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63858 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63858 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 150143 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 203133106 # ITB inst hits +system.cpu1.itb.inst_misses 86285 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 45077 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 23450 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 30560 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 204512 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 224551 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 191700270 # ITB inst accesses -system.cpu1.itb.hits 191622824 # DTB hits -system.cpu1.itb.misses 77446 # DTB misses -system.cpu1.itb.accesses 191700270 # DTB accesses -system.cpu1.numCycles 652098782 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 203219391 # ITB inst accesses +system.cpu1.itb.hits 203133106 # DTB hits +system.cpu1.itb.misses 86285 # DTB misses +system.cpu1.itb.accesses 203219391 # DTB accesses +system.cpu1.numCycles 708901373 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 77581821 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 539946872 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 121710225 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 71653175 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 543040637 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 12931684 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1632229 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 244335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5898534 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 685251 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 721414 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 191398691 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1512045 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 26398 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 636270063 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.997205 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.224602 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 79210227 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 569056404 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 127974219 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 77257985 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 596249525 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13297978 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1936888 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 233747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6483042 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 760521 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 721953 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 202886748 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1527721 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28660 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 692244892 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.964370 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.215604 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 332513921 52.26% 52.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 118489139 18.62% 70.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 39798398 6.25% 77.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 145468605 22.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 371999522 53.74% 53.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 125145403 18.08% 71.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 42864856 6.19% 78.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 152235111 21.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 636270063 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.186644 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.828014 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 93717841 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 303303779 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 200797968 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 33854734 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4595741 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17115460 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1907562 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 560589350 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 20699594 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4595741 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 125431952 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 39494252 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 209485809 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 202527049 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 54735260 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 545352444 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5255771 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8923159 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 236326 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 251378 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 23064401 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 10277 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 518904030 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 842346329 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 645518990 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 772636 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 467533188 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 51370836 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14457491 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12765800 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 68374020 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 90157460 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 77360116 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8411660 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7288721 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 524903956 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 14739695 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 529653671 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2395600 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 48736249 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 31414673 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 252865 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 636270063 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.832435 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.069985 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 692244892 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.180525 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.802730 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 98103528 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 343550458 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 207545620 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 38285921 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4759365 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 18045337 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1925812 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 590182189 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 20993149 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4759365 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 132299037 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 44198902 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 235238981 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 211136719 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 64611888 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 574391592 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5359861 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9789729 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 401271 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 868513 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 28581746 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 10968 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 549201958 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 896745625 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 678703153 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 702078 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 496570478 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 52631474 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 16637084 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 14688391 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 76542594 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 94434816 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 80595349 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8923483 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7689116 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 551758554 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 16802636 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 558923093 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2479703 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 49836281 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 32327580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 272404 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 692244892 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.807407 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.056587 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 346386206 54.44% 54.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 123009687 19.33% 73.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 101156259 15.90% 89.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 58544050 9.20% 98.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7169989 1.13% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 3872 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 382813800 55.30% 55.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 135617529 19.59% 74.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 105540069 15.25% 90.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 60873310 8.79% 98.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7395424 1.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4760 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 636270063 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 692244892 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 53039712 43.72% 43.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 43863 0.04% 43.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 10928 0.01% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 13 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 32632716 26.90% 70.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 35589452 29.34% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 54751854 43.35% 43.35% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 59874 0.05% 43.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 7206 0.01% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 34635726 27.43% 70.83% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 36835867 29.17% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 360085884 67.99% 67.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1163863 0.22% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 64768 0.01% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 79405 0.01% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 92781248 17.52% 85.75% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 75478453 14.25% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 22 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 381080184 68.18% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1279374 0.23% 68.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 67457 0.01% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 77518 0.01% 68.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.44% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.44% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 97747450 17.49% 85.92% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 78671088 14.08% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 529653671 # Type of FU issued -system.cpu1.iq.rate 0.812229 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 121316684 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.229049 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1818002123 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 587994704 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 514426397 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1287564 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 520666 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 480327 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 650175074 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 795279 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2341712 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 558923093 # Type of FU issued +system.cpu1.iq.rate 0.788436 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 126290549 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.225953 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1937670345 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 618057050 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 542680096 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1190983 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 486822 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 443064 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 684478646 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 734974 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2497447 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11071583 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 15258 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 136605 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5366212 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11391566 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16442 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 147287 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5480411 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2403910 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3823950 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2518337 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4561530 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4595741 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5738657 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1529256 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 539757610 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4759365 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7377288 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1779487 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 568686865 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 90157460 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 77360116 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12526602 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 63879 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1404906 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 136605 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1813433 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2553447 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4366880 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 522753556 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 90069669 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6385743 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 94434816 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 80595349 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 14436432 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 67561 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1633321 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 147287 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1861843 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2641662 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4503505 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 551808656 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 94901612 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6513481 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 113959 # number of nop insts executed -system.cpu1.iew.exec_refs 164397082 # number of memory reference insts executed -system.cpu1.iew.exec_branches 97927466 # Number of branches executed -system.cpu1.iew.exec_stores 74327413 # Number of stores executed -system.cpu1.iew.exec_rate 0.801648 # Inst execution rate -system.cpu1.iew.wb_sent 515591253 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 514906724 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 248837648 # num instructions producing a value -system.cpu1.iew.wb_consumers 408235008 # num instructions consuming a value +system.cpu1.iew.exec_nop 125675 # number of nop insts executed +system.cpu1.iew.exec_refs 172371354 # number of memory reference insts executed +system.cpu1.iew.exec_branches 103407043 # Number of branches executed +system.cpu1.iew.exec_stores 77469742 # Number of stores executed +system.cpu1.iew.exec_rate 0.778400 # Inst execution rate +system.cpu1.iew.wb_sent 543849746 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 543123160 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 263131919 # num instructions producing a value +system.cpu1.iew.wb_consumers 431737287 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.789615 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.609545 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.766148 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.609472 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 42654937 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14486830 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4109860 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 628197112 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.781454 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.577369 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 43653536 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 16530232 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4232753 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 683948716 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.758427 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.554925 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 412381395 65.65% 65.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 112703002 17.94% 83.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 47448288 7.55% 91.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15899123 2.53% 93.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11433065 1.82% 95.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7648889 1.22% 96.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5327937 0.85% 97.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3177183 0.51% 98.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12178230 1.94% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 453202569 66.26% 66.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 123078137 18.00% 84.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 49564580 7.25% 91.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16593049 2.43% 93.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11718092 1.71% 95.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8048900 1.18% 96.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5489767 0.80% 97.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3345988 0.49% 98.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12907634 1.89% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 628197112 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 416485993 # Number of instructions committed -system.cpu1.commit.committedOps 490907395 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 683948716 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 441056280 # Number of instructions committed +system.cpu1.commit.committedOps 518724902 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 151079780 # Number of memory references committed -system.cpu1.commit.loads 79085876 # Number of loads committed -system.cpu1.commit.membars 3553216 # Number of memory barriers committed -system.cpu1.commit.branches 92889165 # Number of branches committed -system.cpu1.commit.fp_insts 468052 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 450541794 # Number of committed integer instructions. -system.cpu1.commit.function_calls 11963242 # Number of function calls committed. +system.cpu1.commit.refs 158158187 # Number of memory references committed +system.cpu1.commit.loads 83043249 # Number of loads committed +system.cpu1.commit.membars 3695786 # Number of memory barriers committed +system.cpu1.commit.branches 98284315 # Number of branches committed +system.cpu1.commit.fp_insts 431344 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 475340146 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12767541 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 338771351 69.01% 69.01% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 933774 0.19% 69.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 51484 0.01% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 70964 0.01% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 79085876 16.11% 85.33% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 71993904 14.67% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 359393863 69.28% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1051243 0.20% 69.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 53001 0.01% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.50% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 68608 0.01% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.51% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 83043249 16.01% 85.52% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 75114938 14.48% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 490907395 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12178230 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1145716069 # The number of ROB reads -system.cpu1.rob.rob_writes 1075160501 # The number of ROB writes -system.cpu1.timesIdled 888623 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 15828719 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 93967443806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 416485993 # Number of Instructions Simulated -system.cpu1.committedOps 490907395 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.565716 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.565716 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.638685 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.638685 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 618570567 # number of integer regfile reads -system.cpu1.int_regfile_writes 365658107 # number of integer regfile writes -system.cpu1.fp_regfile_reads 762313 # number of floating regfile reads -system.cpu1.fp_regfile_writes 433520 # number of floating regfile writes -system.cpu1.cc_regfile_reads 112664520 # number of cc regfile reads -system.cpu1.cc_regfile_writes 113502103 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1139246007 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14605610 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5006870 # number of replacements -system.cpu1.dcache.tags.tagsinuse 430.966811 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 140806906 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5007379 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.119882 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8489665359000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.966811 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.841732 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.841732 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 313329932 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 313329932 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 73478112 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73478112 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 62922278 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 62922278 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 161792 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 161792 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 60224 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 60224 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1740937 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1740937 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1748633 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1748633 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 136400390 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 136400390 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 136562182 # number of overall hits -system.cpu1.dcache.overall_hits::total 136562182 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 5886586 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 5886586 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6650181 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6650181 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 625497 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 625497 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 420972 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 420972 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 235563 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 235563 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 185045 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 185045 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 12536767 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 12536767 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13162264 # number of overall misses -system.cpu1.dcache.overall_misses::total 13162264 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 84434005000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 84434005000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 115550287907 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 115550287907 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14693527706 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 14693527706 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3280765000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3280765000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3888950500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3888950500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3327000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3327000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 199984292907 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 199984292907 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 199984292907 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 199984292907 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 79364698 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 79364698 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 69572459 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 69572459 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 787289 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 787289 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 481196 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 481196 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1976500 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1976500 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1933678 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1933678 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 148937157 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 148937157 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 149724446 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 149724446 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074171 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.074171 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095586 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.095586 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794495 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794495 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.874845 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.874845 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119182 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119182 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095696 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095696 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.084175 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.084175 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087910 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.087910 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14343.459010 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14343.459010 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17375.510216 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17375.510216 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 34903.812382 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 34903.812382 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13927.335787 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13927.335787 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21016.241995 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21016.241995 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 518724902 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12907634 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1229236643 # The number of ROB reads +system.cpu1.rob.rob_writes 1133012460 # The number of ROB writes +system.cpu1.timesIdled 937113 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 16656481 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 93910751930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 441056280 # Number of Instructions Simulated +system.cpu1.committedOps 518724902 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.607281 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.607281 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.622169 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.622169 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 651831389 # number of integer regfile reads +system.cpu1.int_regfile_writes 384949596 # number of integer regfile writes +system.cpu1.fp_regfile_reads 687947 # number of floating regfile reads +system.cpu1.fp_regfile_writes 437000 # number of floating regfile writes +system.cpu1.cc_regfile_reads 121245693 # number of cc regfile reads +system.cpu1.cc_regfile_writes 121813302 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1231894475 # number of misc regfile reads +system.cpu1.misc_regfile_writes 16565900 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5500590 # number of replacements +system.cpu1.dcache.tags.tagsinuse 430.004525 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 146156295 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5501102 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 26.568548 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8485200468500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.004525 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839853 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.839853 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 388 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 327866519 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 327866519 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 76697860 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76697860 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 64975008 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 64975008 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170492 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 170492 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 54492 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 54492 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1753772 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1753772 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1761808 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1761808 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 141672868 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 141672868 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 141843360 # number of overall hits +system.cpu1.dcache.overall_hits::total 141843360 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6400758 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6400758 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7699637 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7699637 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 744836 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 744836 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409878 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 409878 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 258549 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 258549 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 208576 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 208576 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 14100395 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 14100395 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 14845231 # number of overall misses +system.cpu1.dcache.overall_misses::total 14845231 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92687894000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 92687894000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138325220262 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 138325220262 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20294196326 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 20294196326 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4013433500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 4013433500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4392601500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4392601500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3408500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3408500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 231013114262 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 231013114262 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 231013114262 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 231013114262 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 83098618 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 83098618 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 72674645 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 72674645 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 915328 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 915328 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 464370 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 464370 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2012321 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2012321 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1970384 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1970384 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 155773263 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 155773263 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 156688591 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 156688591 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077026 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.077026 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.105947 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.105947 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.813737 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.813737 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.882654 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.882654 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.128483 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.128483 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105856 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105856 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.090519 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.090519 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.094744 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.094744 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14480.768371 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14480.768371 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17965.161249 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17965.161249 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 49512.772889 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 49512.772889 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15522.912485 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15522.912485 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21059.956563 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21059.956563 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15951.823377 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15951.823377 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15193.760960 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15193.760960 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 3842918 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18319630 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 344375 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 666302 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.159109 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 27.494484 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16383.449844 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16383.449844 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15561.436145 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15561.436145 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 5682783 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 23004045 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 345925 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 792691 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 16.427789 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 29.020192 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3252895 # number of writebacks -system.cpu1.dcache.writebacks::total 3252895 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3007786 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3007786 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5379273 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5379273 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3474 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3474 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 121870 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 121870 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8387059 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8387059 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8387059 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8387059 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2878800 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2878800 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1270908 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1270908 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 625447 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 625447 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 417498 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 417498 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 113693 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 113693 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 185035 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 185035 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4149708 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4149708 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4775155 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4775155 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 18068 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 18068 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 15995 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 15995 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 34063 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 34063 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38840223500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38840223500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22606708667 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22606708667 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13883914500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13883914500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14151578206 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14151578206 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1521353000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1521353000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3703986500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3703986500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3256000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3256000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 61446932167 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 61446932167 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75330846667 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 75330846667 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2814873000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2814873000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2522981000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2522981000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5337854000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5337854000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036273 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036273 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018267 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018267 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794431 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794431 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.867626 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.867626 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057522 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057522 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095691 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095691 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027862 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027862 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031893 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031893 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13491.810303 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13491.810303 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17787.840400 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17787.840400 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22198.386914 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22198.386914 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 33896.158080 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 33896.158080 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13381.237191 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13381.237191 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20017.761505 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20017.761505 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3566261 # number of writebacks +system.cpu1.dcache.writebacks::total 3566261 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3293272 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3293272 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6267237 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 6267237 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 2938 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 2938 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 130878 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 130878 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9560509 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9560509 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9560509 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9560509 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3107486 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3107486 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1432400 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1432400 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 744751 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 744751 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 406940 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 406940 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127671 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127671 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 208566 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 208566 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4539886 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4539886 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5284637 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5284637 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 16935 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 16935 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14896 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14896 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31831 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31831 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43040497000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43040497000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26400232128 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26400232128 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15655161500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15655161500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19798456326 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19798456326 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1838541000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1838541000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4184106500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4184106500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3337500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3337500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69440729128 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 69440729128 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 85095890628 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 85095890628 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2604403500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2604403500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2300537000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2300537000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4904940500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4904940500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037395 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037395 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019710 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019710 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.813644 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.813644 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.876327 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.876327 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063445 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063445 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105850 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105850 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029144 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029144 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033727 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033727 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13850.584363 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13850.584363 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18430.768031 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18430.768031 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21020.665296 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21020.665296 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 48652.028127 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 48652.028127 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14400.615645 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14400.615645 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20061.306733 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20061.306733 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14807.531558 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14807.531558 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15775.581456 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15775.581456 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155793.280939 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 155793.280939 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157735.604877 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157735.604877 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156705.340105 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156705.340105 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15295.698863 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15295.698863 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16102.504416 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16102.504416 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 153788.219663 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 153788.219663 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154439.916756 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154439.916756 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 154093.195313 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 154093.195313 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5324088 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.812989 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 185755475 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5324600 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 34.886278 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8495816906000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.812989 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980103 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980103 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5403947 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.811782 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 197154720 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5404459 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 36.480010 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8495886874000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.811782 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980101 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980101 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 388109731 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 388109731 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 185755475 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 185755475 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 185755475 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 185755475 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 185755475 # number of overall hits -system.cpu1.icache.overall_hits::total 185755475 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5637082 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5637082 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5637082 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5637082 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5637082 # number of overall misses -system.cpu1.icache.overall_misses::total 5637082 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 58647080384 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 58647080384 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 58647080384 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 58647080384 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 58647080384 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 58647080384 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 191392557 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 191392557 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 191392557 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 191392557 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 191392557 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 191392557 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029453 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029453 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029453 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029453 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029453 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029453 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10403.801184 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10403.801184 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10403.801184 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10403.801184 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10403.801184 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10403.801184 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 8439613 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 34 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 658051 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.825166 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 411165528 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 411165528 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 197154720 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 197154720 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 197154720 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 197154720 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 197154720 # number of overall hits +system.cpu1.icache.overall_hits::total 197154720 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5725810 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5725810 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5725810 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5725810 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5725810 # number of overall misses +system.cpu1.icache.overall_misses::total 5725810 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 59819230732 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 59819230732 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 59819230732 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 59819230732 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 59819230732 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 59819230732 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 202880530 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 202880530 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 202880530 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 202880530 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 202880530 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 202880530 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028223 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.028223 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028223 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.028223 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028223 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.028223 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10447.295794 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10447.295794 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10447.295794 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10447.295794 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10447.295794 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10447.295794 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 8523796 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 288 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 664103 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.835051 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 96 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 312465 # 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number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 53161463126 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 53161463126 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 53161463126 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 53161463126 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 53161463126 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 53161463126 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6100998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6100998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6100998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6100998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027820 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027820 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027820 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027820 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027820 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027820 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9984.091462 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9984.091462 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9984.091462 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9984.091462 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9984.091462 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9984.091462 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91059.671642 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91059.671642 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91059.671642 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91059.671642 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54260492010 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 54260492010 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54260492010 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 54260492010 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54260492010 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 54260492010 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5791998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5791998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5791998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5791998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026639 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.026639 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.026639 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10039.932147 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10039.932147 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10039.932147 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86447.731343 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86447.731343 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6690086 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6848412 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 136895 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7840068 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7844426 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 3981 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 833652 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2101281 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13129.737314 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 17962799 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2117240 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.484064 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10109948263500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 3719.638298 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 30.194019 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 18.354708 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4841.731410 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3496.437967 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1023.380912 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.227029 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001843 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001120 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.295516 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.213406 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.062462 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.801376 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1215 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 80 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14664 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 222 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 606 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 357 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1327 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5436 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4651 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074158 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.895020 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 353923766 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 353923766 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 516145 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 163709 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 679854 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3252875 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3252875 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 76096 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 76096 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 32991 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 32991 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 823499 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 823499 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4739467 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4739467 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2648300 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2648300 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 186015 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 186015 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 516145 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 163709 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4739467 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3471799 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8891120 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 516145 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 163709 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4739467 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3471799 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8891120 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10986 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7768 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 18754 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 19 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 19 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 135316 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 135316 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 152038 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 152038 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 244643 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 244643 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 585139 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 585139 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 965514 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 965514 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 230258 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 230258 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10986 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7768 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 585139 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1210157 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1814050 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10986 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7768 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 585139 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1210157 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1814050 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 393593000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 283804000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 677397000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2923492500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2923492500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3131932000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3131932000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3149000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3149000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10851172997 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10851172997 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16931159000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16931159000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31232900488 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31232900488 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 11958390500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 11958390500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 393593000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 283804000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16931159000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 42084073485 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 59692629485 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 393593000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 283804000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16931159000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 42084073485 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 59692629485 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 527131 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 171477 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 698608 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3252894 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3252894 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 211412 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 211412 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 185029 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 185029 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1068142 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1068142 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5324606 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 5324606 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3613814 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3613814 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 416273 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 416273 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 527131 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 171477 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5324606 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4681956 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10705170 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 527131 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 171477 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5324606 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4681956 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10705170 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020841 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.045301 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.026845 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000006 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000006 # miss rate for Writeback accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.640058 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.640058 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.821698 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.821698 # 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Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 4406.199695 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 842.278257 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.308593 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004276 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005171 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.184786 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.268933 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051409 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.823167 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1281 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 69 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14720 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 30 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 223 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 628 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 392 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 34 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1431 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5385 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4653 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3120 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078186 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 375099508 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 375099508 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 592978 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 185889 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 778867 # 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number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2601766497 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2804499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2804499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9250303496 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9250303496 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13937951500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13937951500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 28711604984 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 28711604984 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16314942498 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16314942498 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 436116500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 365754500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13937951500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 37961908480 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 52701730980 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 436116500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 365754500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13937951500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 37961908480 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 50468745441 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 103170476421 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5288500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2468909500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2474198000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2188801500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2188801500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5288500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 4657711000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 4662999500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021107 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047593 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027566 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000005 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000005 # mshr miss rate for Writeback accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.640058 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.640058 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.821698 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.821698 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.634120 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.634120 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827681 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.827681 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.218622 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.218622 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.109893 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109893 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.266538 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.266538 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.553082 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.553082 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020828 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044152 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109893 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255607 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.168183 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020828 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044152 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109893 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255607 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197282 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197282 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.115328 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.267084 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267084 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.637589 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.637589 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021107 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047593 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250766 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170837 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021107 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047593 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250766 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.230757 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30080.835580 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 49003.644062 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 49003.644062 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20075.711601 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20075.711601 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15124.639893 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15124.639893 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 453833.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 453833.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34517.028580 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34517.028580 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22935.290478 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22935.290478 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26313.248259 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26313.248259 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45935.198256 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45935.198256 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22935.290478 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27914.047244 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26318.278100 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29832.361782 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30441.157047 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22935.290478 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27914.047244 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 49003.644062 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32469.858077 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83544.776119 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147789.738765 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147552.384891 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150234.510785 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150234.510785 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83544.776119 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 148937.733024 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148809.361266 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.241473 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 36310.043470 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62702.817586 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19926.217494 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19926.217494 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15072.044681 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15072.044681 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 560899.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 560899.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 38652.446498 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 38652.446498 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22362.048081 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27036.453370 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27036.453370 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63037.326026 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63037.326026 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29172.766547 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27073.052707 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29172.766547 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37495.580260 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145787.392973 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 145523.938360 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146938.876208 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146938.876208 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 146326.254280 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 146184.698100 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 892292 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9878632 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 38264 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 15995 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 7255897 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 9976246 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 974296 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 447021 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 338151 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 459645 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 83 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 148 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1866908 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1075363 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5324617 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6289738 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 523001 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 416273 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15972735 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16223776 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 373937 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1157245 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 33727693 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 340775856 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 514151471 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1371816 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4217048 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 860516191 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 12204948 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 33927884 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.375605 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.484279 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 997626 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10426628 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 14896 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 7712009 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 10305258 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1022601 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 482744 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 380034 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 500528 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1988029 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1220428 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5404468 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6543941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 512654 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 405926 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16212466 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17789160 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 422162 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1316947 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 35740735 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 345886640 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 566771243 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1562912 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4846136 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 919066931 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 12378423 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 35388761 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.367817 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.482211 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 21184404 62.44% 62.44% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 12743480 37.56% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 22372180 63.22% 63.22% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 13016581 36.78% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 33927884 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 14269396468 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 35388761 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 15228808958 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 176820981 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 179948989 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7990923619 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8110869278 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7460231410 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8234240098 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 202704009 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 227095399 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 630714293 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 711723893 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40336 # Transaction distribution -system.iobus.trans_dist::ReadResp 40336 # Transaction distribution -system.iobus.trans_dist::WriteReq 136670 # Transaction distribution -system.iobus.trans_dist::WriteResp 136670 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47832 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40342 # Transaction distribution +system.iobus.trans_dist::ReadResp 40342 # Transaction distribution +system.iobus.trans_dist::WriteReq 136642 # Transaction distribution +system.iobus.trans_dist::WriteResp 136642 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47708 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2991,13 +2995,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122766 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231166 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231166 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122642 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231246 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231246 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354012 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47728 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3012,13 +3016,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155873 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338680 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338680 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155749 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339000 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339000 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496639 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36328000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496835 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36238000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -3046,71 +3050,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 569486466 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 569545477 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92827000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92731000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147862000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147942000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115572 # number of replacements -system.iocache.tags.tagsinuse 11.309139 # Cycle average of tags in use +system.iocache.tags.replacements 115612 # number of replacements +system.iocache.tags.tagsinuse 11.307418 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115588 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9081185715000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.844632 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.464507 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240289 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466532 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706821 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9081354759000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.848836 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.458583 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240552 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466161 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706714 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040604 # Number of tag accesses -system.iocache.tags.data_accesses 1040604 # Number of data accesses +system.iocache.tags.tag_accesses 1040964 # Number of tag accesses +system.iocache.tags.data_accesses 1040964 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8855 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8892 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8895 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8932 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8855 # number of demand (read+write) misses -system.iocache.demand_misses::total 8895 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8895 # number of demand (read+write) misses +system.iocache.demand_misses::total 8935 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8855 # number of overall misses -system.iocache.overall_misses::total 8895 # number of overall misses +system.iocache.overall_misses::realview.ide 8895 # number of overall misses +system.iocache.overall_misses::total 8935 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1639991052 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1645186052 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 373000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 373000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12624663414 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12624663414 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5568000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1639991052 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1645559052 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5568000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1639991052 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1645559052 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1662593136 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1667788136 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12635360341 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12635360341 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1662593136 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1668157136 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1662593136 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1668157136 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8855 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8892 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8895 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8932 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8855 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8895 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8895 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8935 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8855 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8895 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8895 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8935 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3125,54 +3129,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185205.087747 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185018.674314 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 124333.333333 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 124333.333333 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118288.203789 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118288.203789 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139200 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 185205.087747 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 184998.207083 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139200 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 185205.087747 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 184998.207083 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32135 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 186913.224958 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186720.570533 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118388.429850 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118388.429850 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186913.224958 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 186699.175825 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 186913.224958 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 186699.175825 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32654 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3455 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.301013 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.652380 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106702 # number of writebacks system.iocache.writebacks::total 106702 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8855 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8892 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8895 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8932 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8855 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8895 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8895 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8935 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8855 # 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number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7298960341 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1217843136 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1221407136 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1217843136 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1221407136 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3187,616 +3191,614 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135205.087747 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135018.674314 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 74333.333333 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 74333.333333 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68288.203789 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68288.203789 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 135205.087747 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 134998.207083 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 135205.087747 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 134998.207083 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136913.224958 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136720.570533 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68388.429850 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68388.429850 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136913.224958 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 136699.175825 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136913.224958 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 136699.175825 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1677022 # number of replacements -system.l2c.tags.tagsinuse 63960.007157 # Cycle average of tags in use -system.l2c.tags.total_refs 5998379 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1737036 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.453227 # Average number of references to valid blocks. +system.l2c.tags.replacements 1760747 # number of replacements +system.l2c.tags.tagsinuse 63871.601453 # Cycle average of tags in use +system.l2c.tags.total_refs 6095006 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1821172 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.346749 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 15741.839802 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 357.273948 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 484.122298 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4874.372847 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 16502.292162 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 20727.343192 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.818696 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 7.376448 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2388.813179 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1821.049873 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1043.704711 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.240201 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005452 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.007387 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074377 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.251805 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.316274 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000180 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000113 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.036450 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.027787 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.015926 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.975952 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10260 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 258 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49496 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 879 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 504 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 8874 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2439 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4866 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 41821 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.156555 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003937 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.755249 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 75068652 # Number of tag accesses -system.l2c.tags.data_accesses 75068652 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2604285 # number of Writeback hits -system.l2c.Writeback_hits::total 2604285 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 28546 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 29320 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 57866 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6394 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5412 # 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number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 279182 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3006547 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6923 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4910 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 644950 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 817196 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 305817 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5910 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4051 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 543185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 713266 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 279182 # number of demand (read+write) hits -system.l2c.demand_hits::total 3325390 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4619.393037 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9002.087865 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11374.868707 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 179.474155 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 242.215899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2745.232497 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 8268.941513 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8662.499555 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.279641 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002778 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004094 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.070486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.137361 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173567 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002739 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003696 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.041889 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.126174 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.132179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.974603 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 11384 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48804 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1357 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 826 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9193 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 233 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2623 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5288 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 40501 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.173706 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.297481 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.363939 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.107677 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.463883 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.513528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.296587 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.367763 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.063560 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.278540 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529663 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.341450 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.297481 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.363939 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.107677 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.463883 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.513528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.296587 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.367763 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.063560 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.278540 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529663 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.341450 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20800.621529 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.508332 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20796.244332 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20768.382919 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20789.283483 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20778.098350 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120935.584597 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 100900.229250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 116014.881862 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76933.592354 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 89498.558805 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76410.566438 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87864.778277 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112031.632054 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76933.592354 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 112904.774326 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76410.566438 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95311.504985 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 113609.496968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76933.592354 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 112904.774326 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76410.566438 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95311.504985 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 113609.496968 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156156.685889 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65537.313433 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 129803.636666 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114515.950499 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147660.628362 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133233.197874 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141629.718090 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156472.227426 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127801.984291 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114507.184053 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149180.347220 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 129937.567132 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141677.456104 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151711.018680 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65537.313433 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 131414.154018 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 125104.654348 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152666.603963 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 128801.438939 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 125115.391242 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 59716 # Transaction distribution -system.membus.trans_dist::ReadResp 1065238 # Transaction distribution -system.membus.trans_dist::WriteReq 38264 # Transaction distribution -system.membus.trans_dist::WriteResp 38264 # Transaction distribution -system.membus.trans_dist::Writeback 1398687 # Transaction distribution -system.membus.trans_dist::CleanEvict 273545 # Transaction distribution -system.membus.trans_dist::UpgradeReq 431435 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 293289 # Transaction distribution -system.membus.trans_dist::UpgradeResp 115559 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 699678 # Transaction distribution -system.membus.trans_dist::ReadExResp 679021 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1005522 # Transaction distribution +system.membus.trans_dist::ReadReq 59646 # Transaction distribution +system.membus.trans_dist::ReadResp 1127009 # Transaction distribution +system.membus.trans_dist::WriteReq 38204 # Transaction distribution +system.membus.trans_dist::WriteResp 38204 # Transaction distribution +system.membus.trans_dist::Writeback 1464927 # Transaction distribution +system.membus.trans_dist::CleanEvict 280718 # Transaction distribution +system.membus.trans_dist::UpgradeReq 444619 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 331926 # Transaction distribution +system.membus.trans_dist::UpgradeResp 118163 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 708914 # Transaction distribution +system.membus.trans_dist::ReadExResp 687449 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1067363 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122642 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25252 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5818316 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5966412 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342390 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342390 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6308802 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155873 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25116 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6087631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6235467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6577494 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155749 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 190243904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 190450853 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7261952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7261952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 197712805 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 632700 # Total snoops (count) -system.membus.snoop_fanout::samples 4309210 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 198978048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 199184601 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7249472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7249472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 206434073 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 682959 # Total snoops (count) +system.membus.snoop_fanout::samples 4505681 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4309210 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4505681 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4309210 # Request fanout histogram -system.membus.reqLayer0.occupancy 98315494 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4505681 # Request fanout histogram +system.membus.reqLayer0.occupancy 98301494 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21255984 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21116985 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9692600374 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10136025529 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9139212712 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9507659574 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229129958 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229108938 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3840,50 +3842,50 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 59718 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4906213 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38264 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38264 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 4003012 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1629651 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 482692 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 305095 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 787787 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 148 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 148 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1150777 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1150777 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4853770 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 59648 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5069827 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38204 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 4145743 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1638680 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 501758 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 344029 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 845787 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 136 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1170821 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1170821 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 5017419 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9404841 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6602998 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16007839 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 297836822 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 190023375 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 487860197 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3506825 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13882904 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.137454 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.344326 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9001938 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7449274 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16451212 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 278573838 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 222195147 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 500768985 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3698425 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 14333755 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.138980 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.345926 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 11974647 86.25% 86.25% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1908257 13.75% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 12341651 86.10% 86.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1992104 13.90% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13882904 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8939333587 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 14333755 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9346036195 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2427000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2541000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5448458649 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5271518855 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4022349362 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4504542320 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4812 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 4738 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13871 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 14252 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 5f37e786a..aba26f57d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.216814 # Nu sim_ticks 47216814145000 # Number of ticks simulated final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1322702 # Simulator instruction rate (inst/s) -host_op_rate 1556041 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64025133870 # Simulator tick rate (ticks/s) -host_mem_usage 730036 # Number of bytes of host memory used -host_seconds 737.47 # Real time elapsed on the host +host_inst_rate 1175010 # Simulator instruction rate (inst/s) +host_op_rate 1382295 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56876129335 # Simulator tick rate (ticks/s) +host_mem_usage 728240 # Number of bytes of host memory used +host_seconds 830.17 # Real time elapsed on the host sim_insts 975457230 # Number of instructions simulated sim_ops 1147538415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1472,7 +1472,7 @@ system.membus.trans_dist::ReadResp 560921 # Tr system.membus.trans_dist::WriteReq 38802 # Transaction distribution system.membus.trans_dist::WriteResp 38802 # Transaction distribution system.membus.trans_dist::Writeback 1578732 # Transaction distribution -system.membus.trans_dist::CleanEvict 418758 # Transaction distribution +system.membus.trans_dist::CleanEvict 418759 # Transaction distribution system.membus.trans_dist::UpgradeReq 328366 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 314759 # Transaction distribution system.membus.trans_dist::UpgradeResp 149960 # Transaction distribution @@ -1484,11 +1484,11 @@ system.membus.trans_dist::InvalidateResp 106728 # Tr system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6659521 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6809741 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6659522 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6809742 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346873 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 346873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7156614 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7156615 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) @@ -1498,17 +1498,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 system.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 217946321 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4958638 # Request fanout histogram +system.membus.snoop_fanout::samples 4958639 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4958638 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4958639 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4958638 # Request fanout histogram +system.membus.snoop_fanout::total 4958639 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 0006790d0..ba04235c3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.496387 # Number of seconds simulated -sim_ticks 47496386980500 # Number of ticks simulated -final_tick 47496386980500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.456680 # Number of seconds simulated +sim_ticks 47456679626500 # Number of ticks simulated +final_tick 47456679626500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 708538 # Simulator instruction rate (inst/s) -host_op_rate 833484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38555693115 # Simulator tick rate (ticks/s) -host_mem_usage 757988 # Number of bytes of host memory used -host_seconds 1231.89 # Real time elapsed on the host -sim_insts 872840522 # Number of instructions simulated -sim_ops 1026761155 # Number of ops (including micro ops) simulated +host_inst_rate 659863 # Simulator instruction rate (inst/s) +host_op_rate 776251 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36196220555 # Simulator tick rate (ticks/s) +host_mem_usage 759244 # Number of bytes of host memory used +host_seconds 1311.10 # Real time elapsed on the host +sim_insts 865142471 # Number of instructions simulated +sim_ops 1017738631 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 77248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 78464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2962612 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 38823816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 12701504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 109824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 113728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2837560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 15245328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12552128 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 438080 # Number of bytes read from this memory -system.physmem.bytes_read::total 85940292 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2962612 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2837560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5800172 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 72817088 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 51904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 48448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2877620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 38342664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 11776896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 153536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 163840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2826616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 16120336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11259712 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory +system.physmem.bytes_read::total 84057220 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2877620 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2826616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5704236 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70891776 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 72837672 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1207 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1226 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 86698 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 606635 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 198461 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1716 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1777 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 44425 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 238221 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 196127 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6845 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1383338 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1137767 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 70912360 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 811 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 85370 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 599117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 184014 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2560 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44254 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 251893 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 175933 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1353915 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1107684 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1140341 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 62376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 817406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 267420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 320979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 264275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1809407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 62376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59743 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 122118 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1533108 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1110258 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 60637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 807951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 248161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3235 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 339685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 237263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1771241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 60637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 120199 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493821 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1533541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1533108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 62376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 817839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 267420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 320979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 264275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3342948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1383338 # Number of read requests accepted -system.physmem.writeReqs 1140341 # Number of write requests accepted -system.physmem.readBursts 1383338 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1140341 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 88503808 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 29824 # Total number of bytes read from write queue -system.physmem.bytesWritten 72836864 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 85940292 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 72837672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 466 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1494255 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 60637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 808384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 248161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 339685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 237263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3265496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1353915 # Number of read requests accepted +system.physmem.writeReqs 1110258 # Number of write requests accepted +system.physmem.readBursts 1353915 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1110258 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 86619200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31360 # Total number of bytes read from write queue +system.physmem.bytesWritten 70911104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 84057220 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70912360 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 490 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 218501 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 80378 # Per bank write bursts -system.physmem.perBankRdBursts::1 85683 # Per bank write bursts -system.physmem.perBankRdBursts::2 84533 # Per bank write bursts -system.physmem.perBankRdBursts::3 91641 # Per bank write bursts -system.physmem.perBankRdBursts::4 87506 # Per bank write bursts -system.physmem.perBankRdBursts::5 92565 # Per bank write bursts -system.physmem.perBankRdBursts::6 85373 # Per bank write bursts -system.physmem.perBankRdBursts::7 87361 # Per bank write bursts -system.physmem.perBankRdBursts::8 80689 # Per bank write bursts -system.physmem.perBankRdBursts::9 125890 # Per bank write bursts -system.physmem.perBankRdBursts::10 79879 # Per bank write bursts -system.physmem.perBankRdBursts::11 87722 # Per bank write bursts -system.physmem.perBankRdBursts::12 73371 # Per bank write bursts -system.physmem.perBankRdBursts::13 83748 # Per bank write bursts -system.physmem.perBankRdBursts::14 77275 # Per bank write bursts -system.physmem.perBankRdBursts::15 79258 # Per bank write bursts -system.physmem.perBankWrBursts::0 66779 # Per bank write bursts -system.physmem.perBankWrBursts::1 71701 # Per bank write bursts -system.physmem.perBankWrBursts::2 72134 # Per bank write bursts -system.physmem.perBankWrBursts::3 76164 # Per bank write bursts -system.physmem.perBankWrBursts::4 73824 # Per bank write bursts -system.physmem.perBankWrBursts::5 77776 # Per bank write bursts -system.physmem.perBankWrBursts::6 71735 # Per bank write bursts -system.physmem.perBankWrBursts::7 72120 # Per bank write bursts -system.physmem.perBankWrBursts::8 69346 # Per bank write bursts -system.physmem.perBankWrBursts::9 71851 # Per bank write bursts -system.physmem.perBankWrBursts::10 68226 # Per bank write bursts -system.physmem.perBankWrBursts::11 73306 # Per bank write bursts -system.physmem.perBankWrBursts::12 64374 # Per bank write bursts -system.physmem.perBankWrBursts::13 72179 # Per bank write bursts -system.physmem.perBankWrBursts::14 67114 # Per bank write bursts -system.physmem.perBankWrBursts::15 69447 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 220771 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 83838 # Per bank write bursts +system.physmem.perBankRdBursts::1 89540 # Per bank write bursts +system.physmem.perBankRdBursts::2 77326 # Per bank write bursts +system.physmem.perBankRdBursts::3 81695 # Per bank write bursts +system.physmem.perBankRdBursts::4 84097 # Per bank write bursts +system.physmem.perBankRdBursts::5 94926 # Per bank write bursts +system.physmem.perBankRdBursts::6 83322 # Per bank write bursts +system.physmem.perBankRdBursts::7 86179 # Per bank write bursts +system.physmem.perBankRdBursts::8 76741 # Per bank write bursts +system.physmem.perBankRdBursts::9 125350 # Per bank write bursts +system.physmem.perBankRdBursts::10 75788 # Per bank write bursts +system.physmem.perBankRdBursts::11 81366 # Per bank write bursts +system.physmem.perBankRdBursts::12 76482 # Per bank write bursts +system.physmem.perBankRdBursts::13 81797 # Per bank write bursts +system.physmem.perBankRdBursts::14 77630 # Per bank write bursts +system.physmem.perBankRdBursts::15 77348 # Per bank write bursts +system.physmem.perBankWrBursts::0 68540 # Per bank write bursts +system.physmem.perBankWrBursts::1 72321 # Per bank write bursts +system.physmem.perBankWrBursts::2 65671 # Per bank write bursts +system.physmem.perBankWrBursts::3 69464 # Per bank write bursts +system.physmem.perBankWrBursts::4 70371 # Per bank write bursts +system.physmem.perBankWrBursts::5 77894 # Per bank write bursts +system.physmem.perBankWrBursts::6 70312 # Per bank write bursts +system.physmem.perBankWrBursts::7 72647 # Per bank write bursts +system.physmem.perBankWrBursts::8 65746 # Per bank write bursts +system.physmem.perBankWrBursts::9 72323 # Per bank write bursts +system.physmem.perBankWrBursts::10 65450 # Per bank write bursts +system.physmem.perBankWrBursts::11 68291 # Per bank write bursts +system.physmem.perBankWrBursts::12 65769 # Per bank write bursts +system.physmem.perBankWrBursts::13 69040 # Per bank write bursts +system.physmem.perBankWrBursts::14 66651 # Per bank write bursts +system.physmem.perBankWrBursts::15 67496 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 52 # Number of times write queue was full causing retry -system.physmem.totGap 47496383920000 # Total gap between requests +system.physmem.numWrRetry 71 # Number of times write queue was full causing retry +system.physmem.totGap 47456676566000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1340113 # Read request sizes (log2) +system.physmem.readPktSize::6 1310690 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1137767 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1131623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 75605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 35452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 23289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 20581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 14732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1107684 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1123748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 74620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 23297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 20472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 17890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 14951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 12831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,167 +188,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 19449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 57076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 65524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 69411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 70341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 73639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 73241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 74463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 72846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 73821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 77361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 71631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 68870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 66897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 16504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 19352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 63983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 68337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 71503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 71245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 72329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 70408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 71228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 74472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 69249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 64601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 857 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 158 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 866706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 186.153496 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 114.409994 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 244.608227 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 521785 60.20% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 170596 19.68% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55940 6.45% 86.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28866 3.33% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19331 2.23% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11894 1.37% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9595 1.11% 94.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9879 1.14% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 38820 4.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 866706 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 64746 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.358308 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 318.389928 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 64744 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::37 616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 238 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 850568 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 185.205557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 113.971853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.835447 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 513606 60.38% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 167161 19.65% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 54824 6.45% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28166 3.31% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18449 2.17% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11525 1.35% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9338 1.10% 94.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9545 1.12% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 37954 4.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 850568 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62842 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.536775 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 323.180031 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 62840 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 64746 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 64746 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.577549 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.073829 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.807966 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 61438 94.89% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 935 1.44% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 457 0.71% 97.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 214 0.33% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 283 0.44% 97.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 509 0.79% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 100 0.15% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.06% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 36 0.06% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 29 0.04% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 34 0.05% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 27 0.04% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 442 0.68% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 39 0.06% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 47 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 53 0.08% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 11 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 62842 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62842 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.631298 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.120021 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.777595 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 59398 94.52% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1045 1.66% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 473 0.75% 96.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 210 0.33% 97.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 336 0.53% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 469 0.75% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 106 0.17% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 34 0.05% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 31 0.05% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 28 0.04% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 37 0.06% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 34 0.05% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 449 0.71% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 44 0.07% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 47 0.07% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 32 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 9 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 64746 # Writes before turning the bus around for reads -system.physmem.totQLat 34994473123 # Total ticks spent queuing -system.physmem.totMemAccLat 60923323123 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6914360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25305.65 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::128-131 26 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62842 # Writes before turning the bus around for reads +system.physmem.totQLat 31787428314 # Total ticks spent queuing +system.physmem.totMemAccLat 57164147064 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6767125000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23486.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44055.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42236.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 1113162 # Number of row buffer hits during reads -system.physmem.writeRowHits 541079 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.54 # Row buffer hit rate for writes -system.physmem.avgGap 18820295.26 # Average gap between requests -system.physmem.pageHitRate 65.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3392073720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1850833875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5421273000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3772869840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3102232782480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1205451752805 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27440415505500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31762537091220 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.735925 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45648791331206 # Time in different power states -system.physmem_0.memoryStateTime::REF 1586008580000 # Time in different power states +system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.28 # Average write queue length when enqueuing +system.physmem.readRowHits 1086313 # Number of row buffer hits during reads +system.physmem.writeRowHits 524528 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.34 # Row buffer hit rate for writes +system.physmem.avgGap 19258662.67 # Average gap between requests +system.physmem.pageHitRate 65.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3335290560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1819851000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5311160400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3675585600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3099639126480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1204726391325 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27417225862500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31735733267865 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.730691 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45610216470982 # Time in different power states +system.physmem_0.memoryStateTime::REF 1584682580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 261586624794 # Time in different power states +system.physmem_0.memoryStateTime::ACT 261780130518 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3160223640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1724328375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5365089600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3601862640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3102232782480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1192319355510 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27451935144000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31760338786245 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.689642 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45667995849266 # Time in different power states -system.physmem_1.memoryStateTime::REF 1586008580000 # Time in different power states +system.physmem_1.actEnergy 3095003520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1688742000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5245507800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3504163680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3099639126480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1191482148060 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27428843611500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31733498303040 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.683596 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45629577337540 # Time in different power states +system.physmem_1.memoryStateTime::REF 1584682580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 242377776984 # Time in different power states +system.physmem_1.memoryStateTime::ACT 242414504460 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -412,67 +410,71 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 104839 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 104839 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10495 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79742 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 104830 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.171707 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 55.594229 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 104829 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 105954 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 105954 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10115 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80576 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 105928 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.169927 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 55.305347 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 105927 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 104830 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 90246 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 19548.112936 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18016.919113 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 12415.253011 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 89555 99.23% 99.23% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 591 0.65% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 29 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 26 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 90246 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -2134286464 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.271898 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 580308492 -27.19% -27.19% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -2714594956 127.19% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -2134286464 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 79742 88.37% 88.37% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10495 11.63% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 90237 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 104839 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 105928 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 90717 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 19602.257570 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18339.618281 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 10083.229942 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 87482 96.43% 96.43% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2786 3.07% 99.51% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 233 0.26% 99.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 145 0.16% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 15 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 6 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 19 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 7 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 11 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 90717 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 9139568088 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.172115 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -1573058396 -17.21% -17.21% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 10712626484 117.21% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 9139568088 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 80577 88.85% 88.85% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10115 11.15% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 90692 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105954 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 104839 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90237 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105954 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90692 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90237 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 195076 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90692 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 196646 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 85272873 # DTB read hits -system.cpu0.dtb.read_misses 78883 # DTB read misses -system.cpu0.dtb.write_hits 76479493 # DTB write hits -system.cpu0.dtb.write_misses 25956 # DTB write misses +system.cpu0.dtb.read_hits 80457124 # DTB read hits +system.cpu0.dtb.read_misses 79863 # DTB read misses +system.cpu0.dtb.write_hits 72637408 # DTB write hits +system.cpu0.dtb.write_misses 26091 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 39585 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 34410 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4176 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3731 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10186 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 85351756 # DTB read accesses -system.cpu0.dtb.write_accesses 76505449 # DTB write accesses +system.cpu0.dtb.perms_faults 8741 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 80536987 # DTB read accesses +system.cpu0.dtb.write_accesses 72663499 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 161752366 # DTB hits -system.cpu0.dtb.misses 104839 # DTB misses -system.cpu0.dtb.accesses 161857205 # DTB accesses +system.cpu0.dtb.hits 153094532 # DTB hits +system.cpu0.dtb.misses 105954 # DTB misses +system.cpu0.dtb.accesses 153200486 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -502,240 +504,240 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 57460 # Table walker walks requested -system.cpu0.itb.walker.walksLong 57460 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 729 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51308 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 57460 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 57460 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 57460 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52037 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 22020.322079 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 19981.613647 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 15973.969343 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 48320 92.86% 92.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 2946 5.66% 98.52% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 248 0.48% 98.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 406 0.78% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 23 0.04% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 9 0.02% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 33 0.06% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 15 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52037 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 53482 # Table walker walks requested +system.cpu0.itb.walker.walksLong 53482 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 578 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 47523 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 53482 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 53482 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 53482 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 48101 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21551.932392 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19925.788685 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 13354.053067 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 45094 93.75% 93.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2542 5.28% 99.03% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 133 0.28% 99.31% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 277 0.58% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 5 0.01% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 6 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 18 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 2 0.00% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 48101 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -326738796 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -326738796 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -326738796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 51308 98.60% 98.60% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 729 1.40% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52037 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 47523 98.80% 98.80% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 578 1.20% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 48101 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57460 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57460 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53482 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53482 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52037 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52037 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 109497 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 453477294 # ITB inst hits -system.cpu0.itb.inst_misses 57460 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48101 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48101 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 101583 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 428491503 # ITB inst hits +system.cpu0.itb.inst_misses 53482 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 27698 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24315 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 453534754 # ITB inst accesses -system.cpu0.itb.hits 453477294 # DTB hits -system.cpu0.itb.misses 57460 # DTB misses -system.cpu0.itb.accesses 453534754 # DTB accesses -system.cpu0.numCycles 94992773961 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 428544985 # ITB inst accesses +system.cpu0.itb.hits 428491503 # DTB hits +system.cpu0.itb.misses 53482 # DTB misses +system.cpu0.itb.accesses 428544985 # DTB accesses +system.cpu0.numCycles 94913359253 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 453209687 # Number of instructions committed -system.cpu0.committedOps 531499422 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 488089676 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 379595 # Number of float alu accesses -system.cpu0.num_func_calls 26785883 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 68737200 # number of instructions that are conditional controls -system.cpu0.num_int_insts 488089676 # number of integer instructions -system.cpu0.num_fp_insts 379595 # number of float instructions -system.cpu0.num_int_register_reads 710027821 # number of times the integer registers were read -system.cpu0.num_int_register_writes 387728381 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 639718 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 261592 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 118698555 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 118319526 # number of times the CC registers were written -system.cpu0.num_mem_refs 161743236 # number of memory refs -system.cpu0.num_load_insts 85268904 # Number of load instructions -system.cpu0.num_store_insts 76474332 # Number of store instructions -system.cpu0.num_idle_cycles 93849963781.964020 # Number of idle cycles -system.cpu0.num_busy_cycles 1142810179.035976 # Number of busy cycles -system.cpu0.not_idle_fraction 0.012030 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.987970 # Percentage of idle cycles -system.cpu0.Branches 100837041 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 368748107 69.34% 69.34% # Class of executed instruction -system.cpu0.op_class::IntMult 1224660 0.23% 69.57% # Class of executed instruction -system.cpu0.op_class::IntDiv 64156 0.01% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 29994 0.01% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::MemRead 85268904 16.03% 85.62% # Class of executed instruction -system.cpu0.op_class::MemWrite 76474332 14.38% 100.00% # Class of executed instruction +system.cpu0.committedInsts 428232691 # Number of instructions committed +system.cpu0.committedOps 502476550 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 461534262 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 406829 # Number of float alu accesses +system.cpu0.num_func_calls 25466680 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 64818437 # number of instructions that are conditional controls +system.cpu0.num_int_insts 461534262 # number of integer instructions +system.cpu0.num_fp_insts 406829 # number of float instructions +system.cpu0.num_int_register_reads 668961319 # number of times the integer registers were read +system.cpu0.num_int_register_writes 366250009 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 674435 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 305880 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 111832425 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 111484776 # number of times the CC registers were written +system.cpu0.num_mem_refs 153083738 # number of memory refs +system.cpu0.num_load_insts 80450777 # Number of load instructions +system.cpu0.num_store_insts 72632961 # Number of store instructions +system.cpu0.num_idle_cycles 93826651579.898026 # Number of idle cycles +system.cpu0.num_busy_cycles 1086707673.101977 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011449 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988551 # Percentage of idle cycles +system.cpu0.Branches 95423987 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 348470598 69.31% 69.31% # Class of executed instruction +system.cpu0.op_class::IntMult 1120076 0.22% 69.53% # Class of executed instruction +system.cpu0.op_class::IntDiv 60052 0.01% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 44021 0.01% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::MemRead 80450777 16.00% 85.55% # Class of executed instruction +system.cpu0.op_class::MemWrite 72632961 14.45% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 531810153 # Class of executed instruction +system.cpu0.op_class::total 502778486 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 14069 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 5594005 # number of replacements -system.cpu0.dcache.tags.tagsinuse 472.878328 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155905526 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5594517 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.867558 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3986453000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 472.878328 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.923590 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.923590 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 14022 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5233253 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.798924 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 147607157 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5233765 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.202863 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3987157000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.798924 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.939060 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.939060 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 329066714 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 329066714 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79426163 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79426163 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72239104 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72239104 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186194 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 186194 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 137014 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 137014 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1774977 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1774977 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1742409 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1742409 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 151665267 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 151665267 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 151851461 # number of overall hits -system.cpu0.dcache.overall_hits::total 151851461 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3027243 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3027243 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1374655 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1374655 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 667737 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 667737 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 757348 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 757348 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 163489 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 163489 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194173 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 194173 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4401898 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4401898 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5069635 # number of overall misses -system.cpu0.dcache.overall_misses::total 5069635 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 43551375000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 43551375000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25743175500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 25743175500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46783649000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 46783649000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2342479000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2342479000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4171693500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4171693500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2590500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2590500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 69294550500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 69294550500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 69294550500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 69294550500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 82453406 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 82453406 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73613759 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73613759 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853931 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 853931 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 894362 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 894362 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1938466 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1938466 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1936582 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1936582 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156067165 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156067165 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 156921096 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 156921096 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036715 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036715 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018674 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018674 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781957 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781957 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.846803 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.846803 # 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number of overall hits +system.cpu0.dcache.overall_hits::total 143685703 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2840159 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2840159 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1279764 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1279764 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 601589 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 601589 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 758772 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 758772 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148889 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 148889 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 188945 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 188945 # 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number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1866643 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 147628732 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 147628732 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 148407215 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 148407215 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036513 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036513 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018323 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018323 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.772771 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.772771 # 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number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -744,158 +746,157 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3814789 # number of writebacks -system.cpu0.dcache.writebacks::total 3814789 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 30828 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 30828 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21250 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21250 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41671 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41671 # 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number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26689 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 53779 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 53779 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 39330539500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 39330539500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23857005000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23857005000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13760399000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13760399000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 46026301000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 46026301000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1597973500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1597973500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3977579500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3977579500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2531500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2531500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 63187544500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 63187544500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 76947943500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 76947943500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4585847500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4585847500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4300128500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4300128500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8885976000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8885976000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036341 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036341 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018385 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018385 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775395 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775395 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.846803 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.846803 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062842 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062842 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100266 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100266 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027871 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027871 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031939 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031939 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13125.865242 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13125.865242 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17627.395347 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17627.395347 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20781.894601 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20781.894601 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60772.988111 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60772.988111 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13117.712489 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13117.712489 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20484.719812 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20484.719812 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3560219 # number of writebacks +system.cpu0.dcache.writebacks::total 3560219 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 30162 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 30162 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21215 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21215 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39917 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 39917 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 51377 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 51377 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 51377 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 51377 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2809997 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2809997 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1258549 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1258549 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 595949 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 595949 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 758772 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 758772 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 108972 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 108972 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188945 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 188945 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4068546 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4068546 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4664495 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4664495 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 26231 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 26231 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 25453 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 25453 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 51684 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 51684 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 36991828000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 36991828000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22707525500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22707525500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12844611500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12844611500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 45578894000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 45578894000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1445565000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1445565000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3885534000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3885534000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2787000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2787000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 59699353500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 59699353500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 72543965000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 72543965000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4455810500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4455810500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4073355500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4073355500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8529166000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8529166000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036126 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036126 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018019 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018019 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765526 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765526 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.848632 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.848632 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058327 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058327 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101222 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101222 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027559 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027559 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031430 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031430 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13164.365656 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13164.365656 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18042.623291 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18042.623291 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21553.205895 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21553.205895 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 60069.288271 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 60069.288271 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13265.471864 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13265.471864 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20564.365291 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20564.365291 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14526.473394 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14526.473394 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15352.883027 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15352.883027 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169281.930602 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169281.930602 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161119.880850 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 161119.880850 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165231.335651 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165231.335651 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14673.387864 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14673.387864 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15552.372765 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15552.372765 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169868.114064 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169868.114064 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160034.396731 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160034.396731 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165025.268942 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165025.268942 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 4817420 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.881006 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 448659362 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4817932 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 93.122809 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42527405000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.881006 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999768 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999768 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 4666970 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.880807 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 423824020 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4667482 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 90.803568 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42558943000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.880807 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999767 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999767 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 911772520 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 911772520 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 448659362 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 448659362 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 448659362 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 448659362 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 448659362 # number of overall hits -system.cpu0.icache.overall_hits::total 448659362 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4817932 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4817932 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4817932 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4817932 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4817932 # number of overall misses -system.cpu0.icache.overall_misses::total 4817932 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 51018469500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 51018469500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 51018469500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 51018469500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 51018469500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 51018469500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 453477294 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 453477294 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 453477294 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 453477294 # 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average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10589.287997 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10589.287997 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10589.287997 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 861650489 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 861650489 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 423824020 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 423824020 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 423824020 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 423824020 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 423824020 # number of overall hits +system.cpu0.icache.overall_hits::total 423824020 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4667483 # 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miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.622572 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.622572 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.622572 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10432.622572 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.622572 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10432.622572 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -904,251 +905,252 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # 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average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10089.287997 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10089.287997 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10089.287997 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010893 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010893 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010893 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010893 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9932.622572 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9932.622572 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9932.622572 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9932.622572 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87599.188406 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87599.188406 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87599.188406 # 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number of replacements -system.cpu0.l2cache.tags.tagsinuse 15787.482525 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 17072683 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2462926 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.931870 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 38930323500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7763.481265 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.845053 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 94.926815 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3265.491531 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3523.056672 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1075.681189 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 746 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 625 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 46 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2497 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5813 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5388 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.101440 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # 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number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 213691 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 129371 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4275985 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3741079 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8360126 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9038 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7286 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 16324 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 121358 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 121358 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 161252 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 161252 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # 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average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 42471.874070 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20602.242951 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20602.242951 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15536.343735 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15536.343735 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 298285.428571 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 298285.428571 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40531.776945 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40531.776945 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23396.083934 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23396.083934 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26434.981186 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26434.981186 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69291.038726 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69291.038726 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26968.411153 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29878.808674 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23396.083934 # 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mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23918.912033 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 42011.879855 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20310.549916 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20310.549916 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15333.020984 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15333.020984 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 584250 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 584250 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41777.875090 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41777.875090 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23928.375159 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26392.479333 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26392.479333 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 71019.576324 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 71019.576324 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29504.879855 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27789.840054 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23265.186521 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 24768.678582 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23928.375159 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29504.879855 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 42011.879855 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 31709.016783 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161281.930602 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111420.707826 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153619.880850 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153619.880850 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161868.114064 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111024.857258 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 152534.396731 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 152534.396731 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80099.188406 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157479.471541 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 123043.073557 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157271.505688 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 122168.760350 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 556196 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9235290 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 37997 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26689 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 7191964 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 8875110 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 964168 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 427001 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 350742 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 480184 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 96 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1494626 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1158048 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4817932 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5665215 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 862902 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 756174 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14539205 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18068890 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 308145 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 526057 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 33442297 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 308520148 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 566266158 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1093256 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1781832 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 877661394 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 9623929 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 31244724 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.314212 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.464201 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 548810 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 8811478 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 25453 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 6868539 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 8637410 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 769123 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 445989 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351950 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 473125 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1446257 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1069406 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4667483 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5564741 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 864337 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 757609 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14087759 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16981197 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 288818 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 540500 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 31898274 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 298891412 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 527370978 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1032672 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1867144 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 829162206 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 9613339 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 30204161 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.324614 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.468231 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 21427251 68.58% 68.58% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 9817473 31.42% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 20399459 67.54% 67.54% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 9804702 32.46% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 31244724 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14779167493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 30204161 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 14006094999 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 183875487 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 188261483 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7270023000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7044349500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8020770875 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7482254107 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 171488000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 159734000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 303329497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 307107000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1399,74 +1399,68 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 102079 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 102079 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8198 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78187 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 102062 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.078384 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 25.041362 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 102061 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 101352 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 101352 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8872 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77968 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 3 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 101349 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.078935 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 25.129292 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 101348 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 102062 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 86402 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20584.963311 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18803.464379 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14594.922091 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 82288 95.24% 95.24% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3069 3.55% 98.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 485 0.56% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 417 0.48% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 20 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 31 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 11 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 20 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 27 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 86402 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -6989065760 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.774297 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.418044 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1577450036 22.57% 22.57% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -5411615724 77.43% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -6989065760 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 78188 90.51% 90.51% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8198 9.49% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 86386 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 102079 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 101349 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 86843 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20976.923874 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.710286 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 17538.002789 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 85298 98.22% 98.22% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1315 1.51% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 45 0.05% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 84 0.10% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 70 0.08% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 86843 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -857364308 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean -0.833676 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1572128036 183.37% 183.37% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 714763728 -83.37% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -857364308 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 77968 89.78% 89.78% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8872 10.22% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 86840 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 101352 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 102079 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86386 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 101352 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86840 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86386 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 188465 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86840 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 188192 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 79156855 # DTB read hits -system.cpu1.dtb.read_misses 74074 # DTB read misses -system.cpu1.dtb.write_hits 72945567 # DTB write hits -system.cpu1.dtb.write_misses 28005 # DTB write misses +system.cpu1.dtb.read_hits 82714274 # DTB read hits +system.cpu1.dtb.read_misses 74721 # DTB read misses +system.cpu1.dtb.write_hits 75460503 # DTB write hits +system.cpu1.dtb.write_misses 26631 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 34474 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 38549 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4171 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4418 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9254 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 79230929 # DTB read accesses -system.cpu1.dtb.write_accesses 72973572 # DTB write accesses +system.cpu1.dtb.perms_faults 10567 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 82788995 # DTB read accesses +system.cpu1.dtb.write_accesses 75487134 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 152102422 # DTB hits -system.cpu1.dtb.misses 102079 # DTB misses -system.cpu1.dtb.accesses 152204501 # DTB accesses +system.cpu1.dtb.hits 158174777 # DTB hits +system.cpu1.dtb.misses 101352 # DTB misses +system.cpu1.dtb.accesses 158276129 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1496,241 +1490,242 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 60277 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60277 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 437 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54558 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60277 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60277 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60277 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 54995 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 23406.355123 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21056.017834 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18686.344458 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 50855 92.47% 92.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 2976 5.41% 97.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 347 0.63% 98.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 645 1.17% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 26 0.05% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 61 0.11% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 12 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 54995 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1687858036 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1687858036 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1687858036 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54558 99.21% 99.21% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 437 0.79% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 54995 # Table walker page sizes translated +system.cpu1.itb.walker.walks 60693 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60693 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 593 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54830 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60693 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60693 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60693 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 55423 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24648.566480 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 21393.176042 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 22659.824821 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 49924 90.08% 90.08% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 3716 6.70% 96.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 553 1.00% 97.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 965 1.74% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 32 0.06% 99.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 27 0.05% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 86 0.16% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 15 0.03% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 45 0.08% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 26 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 12 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 55423 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1656015036 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1656015036 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1656015036 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54830 98.93% 98.93% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 593 1.07% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55423 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60277 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60277 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60693 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60693 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54995 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54995 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 115272 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 419908062 # ITB inst hits -system.cpu1.itb.inst_misses 60277 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55423 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55423 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 116116 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 437193188 # ITB inst hits +system.cpu1.itb.inst_misses 60693 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 40618 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1028 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 24325 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 39897 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1024 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 27130 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 419968339 # ITB inst accesses -system.cpu1.itb.hits 419908062 # DTB hits -system.cpu1.itb.misses 60277 # DTB misses -system.cpu1.itb.accesses 419968339 # DTB accesses -system.cpu1.numCycles 94992773961 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 437253881 # ITB inst accesses +system.cpu1.itb.hits 437193188 # DTB hits +system.cpu1.itb.misses 60693 # DTB misses +system.cpu1.itb.accesses 437253881 # DTB accesses +system.cpu1.numCycles 94913359253 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 419630835 # Number of instructions committed -system.cpu1.committedOps 495261733 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 455389756 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 523939 # Number of float alu accesses -system.cpu1.num_func_calls 25402387 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 63797614 # number of instructions that are conditional controls -system.cpu1.num_int_insts 455389756 # number of integer instructions -system.cpu1.num_fp_insts 523939 # number of float instructions -system.cpu1.num_int_register_reads 660733277 # number of times the integer registers were read -system.cpu1.num_int_register_writes 360799808 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 826391 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 485612 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 108763380 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 108525865 # number of times the CC registers were written -system.cpu1.num_mem_refs 152092816 # number of memory refs -system.cpu1.num_load_insts 79152639 # Number of load instructions -system.cpu1.num_store_insts 72940177 # Number of store instructions -system.cpu1.num_idle_cycles 94000482737.518021 # Number of idle cycles -system.cpu1.num_busy_cycles 992291223.481979 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010446 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989554 # Percentage of idle cycles -system.cpu1.Branches 93826575 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 342323632 69.08% 69.08% # Class of executed instruction -system.cpu1.op_class::IntMult 986133 0.20% 69.28% # Class of executed instruction -system.cpu1.op_class::IntDiv 54444 0.01% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 82001 0.02% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::MemRead 79152639 15.97% 85.28% # Class of executed instruction -system.cpu1.op_class::MemWrite 72940177 14.72% 100.00% # Class of executed instruction +system.cpu1.committedInsts 436909780 # Number of instructions committed +system.cpu1.committedOps 515262081 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 474007520 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 488695 # Number of float alu accesses +system.cpu1.num_func_calls 26553696 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66234119 # number of instructions that are conditional controls +system.cpu1.num_int_insts 474007520 # number of integer instructions +system.cpu1.num_fp_insts 488695 # number of float instructions +system.cpu1.num_int_register_reads 687449190 # number of times the integer registers were read +system.cpu1.num_int_register_writes 375811208 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 781283 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 430208 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 112572477 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 112287439 # number of times the CC registers were written +system.cpu1.num_mem_refs 158166235 # number of memory refs +system.cpu1.num_load_insts 82712263 # Number of load instructions +system.cpu1.num_store_insts 75453972 # Number of store instructions +system.cpu1.num_idle_cycles 93876093406.586029 # Number of idle cycles +system.cpu1.num_busy_cycles 1037265846.413978 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010929 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989071 # Percentage of idle cycles +system.cpu1.Branches 97493416 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 356171607 69.09% 69.09% # Class of executed instruction +system.cpu1.op_class::IntMult 1079497 0.21% 69.30% # Class of executed instruction +system.cpu1.op_class::IntDiv 59940 0.01% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 68277 0.01% 69.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.32% # Class of executed instruction +system.cpu1.op_class::MemRead 82712263 16.04% 85.36% # Class of executed instruction +system.cpu1.op_class::MemWrite 75453972 14.64% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 495539069 # Class of executed instruction +system.cpu1.op_class::total 515545598 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5086 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 4879882 # number of replacements -system.cpu1.dcache.tags.tagsinuse 454.664905 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 147036928 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4880392 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.128098 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8391455352000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 454.664905 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888017 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.888017 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 414 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 309114667 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 309114667 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 73769374 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 73769374 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 69164773 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 69164773 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181014 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 181014 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 188653 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 188653 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1698614 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1698614 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1666903 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1666903 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 142934147 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 142934147 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 143115161 # number of overall hits -system.cpu1.dcache.overall_hits::total 143115161 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2759570 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2759570 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1240940 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1240940 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 581228 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 581228 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 477261 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 477261 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 156018 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 156018 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 186042 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 186042 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4000510 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4000510 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4581738 # number of overall misses -system.cpu1.dcache.overall_misses::total 4581738 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39233003500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 39233003500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 20835462500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 20835462500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14509055000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 14509055000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2381741000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2381741000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3985246000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3985246000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1637000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1637000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 60068466000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 60068466000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 60068466000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 60068466000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 76528944 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 76528944 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 70405713 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 70405713 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 762242 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 762242 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 665914 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 665914 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1854632 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1854632 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1852945 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1852945 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 146934657 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 146934657 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 147696899 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 147696899 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036059 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036059 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017626 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.017626 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.762524 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.762524 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.716701 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.716701 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084123 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084123 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100403 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100403 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027226 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027226 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031021 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.031021 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14217.071319 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14217.071319 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16790.064387 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16790.064387 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 30400.671750 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 30400.671750 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15265.809073 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15265.809073 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21421.216715 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21421.216715 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5256 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 5176711 # number of replacements +system.cpu1.dcache.tags.tagsinuse 457.282743 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 152806636 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5177218 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.515202 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8391490917000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.282743 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893130 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.893130 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 474 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 321544722 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 321544722 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 77092949 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 77092949 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 71608224 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 71608224 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188155 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 188155 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 187532 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 187532 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1684198 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1684198 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1657450 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1657450 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 148701173 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 148701173 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 148889328 # number of overall hits +system.cpu1.dcache.overall_hits::total 148889328 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2950342 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2950342 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1305907 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1305907 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 613815 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 613815 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 479868 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 479868 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 172330 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 172330 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 197330 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 197330 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4256249 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4256249 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4870064 # number of overall misses +system.cpu1.dcache.overall_misses::total 4870064 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42135771000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 42135771000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 22153910000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 22153910000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 15218762000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 15218762000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2580362000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2580362000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4225919000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4225919000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2953000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2953000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 64289681000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 64289681000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 64289681000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 64289681000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 80043291 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 80043291 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 72914131 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 72914131 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 801970 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 801970 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 667400 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 667400 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1856528 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1856528 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1854780 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1854780 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 152957422 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 152957422 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 153759392 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 153759392 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036859 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036859 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017910 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.017910 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765384 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.765384 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.719011 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.719011 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092824 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092824 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106390 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106390 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027826 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027826 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031673 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.031673 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14281.656499 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14281.656499 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16964.385672 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16964.385672 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 31714.475647 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 31714.475647 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14973.376661 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14973.376661 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21415.491816 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21415.491816 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15015.202062 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15015.202062 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13110.410504 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13110.410504 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15104.774415 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15104.774415 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13200.993046 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13200.993046 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1739,157 +1734,158 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3169454 # number of writebacks -system.cpu1.dcache.writebacks::total 3169454 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14967 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 14967 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 437 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 437 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44200 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44200 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 15404 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 15404 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 15404 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 15404 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2744603 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2744603 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1240503 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1240503 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 581228 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 581228 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 477261 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 477261 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111818 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111818 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 186042 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 186042 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 3985106 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 3985106 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4566334 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4566334 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11055 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11055 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11308 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11308 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22363 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22363 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35762824500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35762824500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 19580379500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 19580379500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11426394500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11426394500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14031794000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14031794000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1521108000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1521108000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3799241000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3799241000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1600000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1600000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 55343204000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 55343204000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 66769598500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 66769598500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1911574500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1911574500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2027224500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2027224500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3938799000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3938799000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035864 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035864 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017619 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017619 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762524 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762524 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.716701 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.716701 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060291 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060291 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100403 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100403 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027122 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027122 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030917 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030917 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13030.235885 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13030.235885 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15784.225834 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15784.225834 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19659.057203 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19659.057203 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 29400.671750 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 29400.671750 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13603.426997 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13603.426997 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20421.415594 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20421.415594 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3350646 # number of writebacks +system.cpu1.dcache.writebacks::total 3350646 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17552 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 17552 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 421 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 421 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45020 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45020 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 17973 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 17973 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 17973 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 17973 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2932790 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2932790 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1305486 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1305486 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 613815 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 613815 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 479868 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 479868 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127310 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127310 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 197330 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 197330 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4238276 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4238276 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4852091 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4852091 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 12503 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 12503 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 13150 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 13150 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25653 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 25653 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38342874000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38342874000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20834838000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20834838000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12333914500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12333914500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14738894000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14738894000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1690256500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1690256500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4028650000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4028650000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2892000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2892000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 59177712000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 59177712000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 71511626500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 71511626500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2070021000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2070021000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2282534000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2282534000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4352555000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4352555000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036640 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036640 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017904 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017904 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765384 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.765384 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.719011 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.719011 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068574 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068574 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106390 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106390 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027709 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027709 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031556 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031556 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13073.855953 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13073.855953 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15959.449584 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15959.449584 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20093.862972 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20093.862972 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 30714.475647 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 30714.475647 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.698610 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.698610 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20415.800943 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20415.800943 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13887.511148 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13887.511148 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14622.145139 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14622.145139 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172914.925373 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172914.925373 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179273.478953 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179273.478953 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176130.170371 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 176130.170371 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13962.684828 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13962.684828 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14738.311070 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14738.311070 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165561.945133 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165561.945133 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173576.730038 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173576.730038 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169670.408919 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169670.408919 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5061942 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.285809 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 414845603 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5062454 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 81.945555 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8391427807000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.285809 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969308 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969308 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5209177 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.272261 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 431983494 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5209689 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 82.919248 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8391463454000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.272261 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969282 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969282 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 440 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 844878583 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 844878583 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 414845603 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 414845603 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 414845603 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 414845603 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 414845603 # number of overall hits -system.cpu1.icache.overall_hits::total 414845603 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5062459 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5062459 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5062459 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5062459 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5062459 # number of overall misses -system.cpu1.icache.overall_misses::total 5062459 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51775886000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 51775886000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 51775886000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 51775886000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 51775886000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 51775886000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 419908062 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 419908062 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 419908062 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 419908062 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 419908062 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 419908062 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012056 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.012056 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012056 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.012056 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012056 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.012056 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10227.418336 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10227.418336 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10227.418336 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10227.418336 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10227.418336 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10227.418336 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 879596070 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 879596070 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 431983494 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 431983494 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 431983494 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 431983494 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 431983494 # number of overall hits +system.cpu1.icache.overall_hits::total 431983494 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5209694 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5209694 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5209694 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5209694 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5209694 # number of overall misses +system.cpu1.icache.overall_misses::total 5209694 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 53989351000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 53989351000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 53989351000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 53989351000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 53989351000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 53989351000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 437193188 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 437193188 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 437193188 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 437193188 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 437193188 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 437193188 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011916 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011916 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011916 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011916 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011916 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011916 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10363.248014 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10363.248014 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10363.248014 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10363.248014 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10363.248014 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10363.248014 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1898,256 +1894,251 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5062459 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5062459 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5062459 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5062459 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5062459 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5062459 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5209694 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5209694 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5209694 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5209694 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5209694 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5209694 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49244656500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 49244656500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49244656500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 49244656500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49244656500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 49244656500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9661500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9661500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9661500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9661500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012056 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.012056 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.012056 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.012056 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.012056 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.012056 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9727.418336 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9727.418336 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9727.418336 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9727.418336 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9727.418336 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9727.418336 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87831.818182 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 87831.818182 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87831.818182 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 87831.818182 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51384504000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 51384504000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51384504000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 51384504000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51384504000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 51384504000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9739500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9739500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9739500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9739500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011916 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011916 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011916 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011916 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9863.248014 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9863.248014 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9863.248014 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9863.248014 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88540.909091 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88540.909091 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88540.909091 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6553328 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6553344 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7168932 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7168932 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 818232 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 1797985 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13499.130791 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 17098114 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1814056 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 9.425351 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10027287971500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5261.606925 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 74.626364 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 80.602782 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3547.198081 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3740.075738 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 795.020901 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.321143 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004555 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004920 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.216504 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.228276 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048524 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.823922 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1537 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14473 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 338 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 619 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 563 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 884 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4486 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5048 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3979 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.093811 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.883362 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 335653129 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 335653129 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 217635 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 143511 # 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average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15257.662444 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15257.662444 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 264399.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 264399.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33947.956121 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33947.956121 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 24469.401986 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24469.401986 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25701.243085 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25701.243085 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 44879.650043 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 44879.650043 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24469.401986 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27292.760437 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26475.388038 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29810.112360 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33034.655861 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24469.401986 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27292.760437 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45583.901097 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31892.451076 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80331.818182 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164914.925373 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164081.594268 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171773.478953 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171773.478953 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80331.818182 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 168382.998703 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167952.009078 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.224856 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35853.894329 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37892.995609 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20762.111833 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20762.111833 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15528.106391 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15528.106391 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 221318.181818 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 221318.181818 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32673.029100 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32673.029100 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 23632.881831 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25921.997053 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25921.997053 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 42761.029854 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 42761.029854 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.643223 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26256.570645 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33937.505825 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38043.556976 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23632.881831 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.643223 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37892.995609 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29484.133120 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157561.945133 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156894.592880 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166076.730038 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166076.730038 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81040.909091 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161926.714224 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161581.356985 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 559173 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9082723 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 37997 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11308 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 6546630 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 9047745 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 872762 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 38 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 399618 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 347237 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 434764 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 96 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1786739 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1070352 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5062459 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5562594 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 582530 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 475802 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15186455 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15778247 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332058 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 524938 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 31821698 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 323997816 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 497415771 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1214224 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1819400 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 824447211 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 10229580 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 30806602 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.338828 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.473311 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 557907 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9467454 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 13150 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 6658964 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 9333240 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 797552 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 400874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 357340 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 454404 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1816504 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1125838 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5209694 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5632852 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 585123 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 478395 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15628224 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16712375 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332083 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 514043 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 33186725 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 333420856 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 527793939 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1205920 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1755584 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 864176299 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 9912470 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 31389750 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.322129 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.467292 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 20368466 66.12% 66.12% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 10438136 33.88% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 21278201 67.79% 67.79% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 10111549 32.21% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 30806602 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 13598256460 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 31389750 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 14234291993 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 189037985 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 190598993 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7593798500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7814651000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7185863072 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7637949368 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 180280000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 181343000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 297513000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 294595499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40323 # Transaction distribution -system.iobus.trans_dist::ReadResp 40323 # Transaction distribution +system.iobus.trans_dist::ReadReq 40360 # Transaction distribution +system.iobus.trans_dist::ReadResp 40360 # Transaction distribution system.iobus.trans_dist::WriteReq 136623 # Transaction distribution system.iobus.trans_dist::WriteResp 136623 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47688 # Packet count per connected master and slave (bytes) @@ -2394,11 +2378,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122622 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47708 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2415,11 +2399,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155729 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496591 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7496887 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36209000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -2448,71 +2432,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 569692377 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 569839842 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92730000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147886000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147960000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115590 # number of replacements -system.iocache.tags.tagsinuse 11.304878 # Cycle average of tags in use +system.iocache.tags.replacements 115629 # number of replacements +system.iocache.tags.tagsinuse 11.301329 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115645 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9148728954000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.397645 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.907233 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.462353 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.244202 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706555 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9148621285000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.403816 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.897512 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.462739 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.243595 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706333 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040712 # Number of tag accesses -system.iocache.tags.data_accesses 1040712 # Number of data accesses +system.iocache.tags.tag_accesses 1041045 # Number of tag accesses +system.iocache.tags.data_accesses 1041045 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8867 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8904 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8867 # number of demand (read+write) misses -system.iocache.demand_misses::total 8907 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses +system.iocache.demand_misses::total 8944 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8867 # number of overall misses -system.iocache.overall_misses::total 8907 # number of overall misses +system.iocache.overall_misses::realview.ide 8904 # number of overall misses +system.iocache.overall_misses::total 8944 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1652925028 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1658120028 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1656855076 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1662050076 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12636024349 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12636024349 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12632251766 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12632251766 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1652925028 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1658489028 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1656855076 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1662419076 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1652925028 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1658489028 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1656855076 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1662419076 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8867 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8867 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8907 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8867 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8907 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2527,54 +2511,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186413.107928 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186221.925876 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186079.860288 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185890.848451 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118394.651347 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118394.651347 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118359.303707 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118359.303707 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 186413.107928 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 186200.631863 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186079.860288 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 185869.753578 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 186413.107928 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 186200.631863 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32852 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 186079.860288 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 185869.753578 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32671 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3487 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.421279 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.525073 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106693 # number of writebacks -system.iocache.writebacks::total 106693 # number of writebacks +system.iocache.writebacks::writebacks 106695 # number of writebacks +system.iocache.writebacks::total 106695 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8867 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8867 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8907 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8867 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8907 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8904 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8944 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1209575028 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1212920028 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1211655076 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1215000076 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7299624349 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7299624349 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7295851766 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7295851766 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1209575028 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1213139028 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1211655076 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1215219076 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1209575028 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1213139028 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1211655076 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1215219076 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2589,613 +2573,612 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136413.107928 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136221.925876 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136079.860288 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 135890.848451 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68394.651347 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68394.651347 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68359.303707 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68359.303707 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136413.107928 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 136200.631863 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136079.860288 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 135869.753578 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136413.107928 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 136200.631863 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136079.860288 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 135869.753578 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1309168 # number of replacements -system.l2c.tags.tagsinuse 63754.864014 # Cycle average of tags in use -system.l2c.tags.total_refs 4916621 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1368931 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.591577 # Average number of references to valid blocks. +system.l2c.tags.replacements 1275038 # number of replacements +system.l2c.tags.tagsinuse 63572.316878 # Cycle average of tags in use +system.l2c.tags.total_refs 4892898 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1334308 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.666993 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 19091.859701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 105.912894 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 155.127533 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3615.637235 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7840.243629 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8325.501182 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 220.931545 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 308.618632 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3602.401841 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8895.404165 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11593.225658 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.291319 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001616 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002367 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.055170 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.119633 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.127037 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003371 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004709 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.054968 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.135733 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.176899 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.972822 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11100 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48385 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 212 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 379 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 10509 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 18943.726739 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 66.506889 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 88.082899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3576.388780 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7769.332592 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 6333.160086 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 237.192415 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 333.040502 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3918.032205 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9111.997525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13194.856246 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.289058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.001344 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.054571 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.118551 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.096636 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003619 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.005082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.059784 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.139038 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.201338 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.970037 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10413 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 223 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48634 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 260 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 499 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9654 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 277 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1364 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4701 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42219 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.169373 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.738297 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 62372649 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73960.340671 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 84703.646154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80056.752278 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80154.975530 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73558.828250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74610.489030 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109885.415433 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77889.860140 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78308.666292 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73811.215628 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73960.340671 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108934.888419 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 84703.646154 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.616777 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.606650 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.611427 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.642485 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.639589 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.640944 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.769654 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462230 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.667124 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.187549 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173097 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.213053 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.484032 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.270015 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.317697 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.147321 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.179725 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.087750 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.484032 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.418303 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.296979 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.342155 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.083471 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.270015 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383139 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.317697 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20755.705168 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20766.401918 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20761.312411 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20741.890782 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20758.861300 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750.902566 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 73826.680784 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71240.624019 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73229.096982 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78672.820155 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79133.822868 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 91779.376343 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74748.039673 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74604.541700 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 82802.354731 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79943.896424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79768.824306 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73601.804550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74748.039673 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 106673.311612 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78360.775323 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78814.843750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73798.584692 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74604.541700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101903.990945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 82802.354731 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143281.266150 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62331.818182 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146941.237673 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100647.773354 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136619.393758 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154772.461974 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142021.791194 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 143867.809081 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139584.273258 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 100085.406322 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 135533.787766 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149076.083650 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140146.931586 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62099.176812 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139975.166887 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62331.818182 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150901.502616 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 113817.101571 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139763.524495 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63036.363636 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 144450.255351 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 112911.939123 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 81378 # Transaction distribution -system.membus.trans_dist::ReadResp 799663 # Transaction distribution -system.membus.trans_dist::WriteReq 37997 # Transaction distribution -system.membus.trans_dist::WriteResp 37997 # Transaction distribution -system.membus.trans_dist::Writeback 1137767 # Transaction distribution -system.membus.trans_dist::CleanEvict 200903 # Transaction distribution -system.membus.trans_dist::UpgradeReq 374437 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 306668 # Transaction distribution -system.membus.trans_dist::UpgradeResp 111797 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 646745 # Transaction distribution -system.membus.trans_dist::ReadExResp 624605 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 718285 # Transaction distribution +system.membus.trans_dist::ReadReq 81967 # Transaction distribution +system.membus.trans_dist::ReadResp 767450 # Transaction distribution +system.membus.trans_dist::WriteReq 38603 # Transaction distribution +system.membus.trans_dist::WriteResp 38603 # Transaction distribution +system.membus.trans_dist::Writeback 1107684 # Transaction distribution +system.membus.trans_dist::CleanEvict 202348 # Transaction distribution +system.membus.trans_dist::UpgradeReq 391044 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 311393 # Transaction distribution +system.membus.trans_dist::UpgradeResp 114065 # Transaction distribution +system.membus.trans_dist::ReadExReq 650749 # Transaction distribution +system.membus.trans_dist::ReadExResp 628057 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 685483 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122622 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24438 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4799197 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4946349 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342551 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342551 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5288900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4735959 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4885501 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5228030 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155729 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48876 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 151511532 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 151716341 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7266432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 158982773 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 594252 # Total snoops (count) -system.membus.snoop_fanout::samples 3613210 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147705452 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 147915041 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7264128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 155179169 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 613936 # Total snoops (count) +system.membus.snoop_fanout::samples 3578377 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3613210 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3578377 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3613210 # Request fanout histogram -system.membus.reqLayer0.occupancy 101221000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3578377 # Request fanout histogram +system.membus.reqLayer0.occupancy 101272500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21240500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 23177500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7773596350 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7575699049 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7468178118 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7326536131 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229090524 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229377455 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3239,46 +3222,46 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 81380 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4075375 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 37997 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 37997 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3377178 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1228761 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 423594 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 317776 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 741370 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 96 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 96 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1071890 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1071890 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4001246 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 81969 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4074898 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38603 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38603 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 3308322 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1226405 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 439947 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 323030 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 762977 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 121 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 121 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1086983 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1086983 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4000171 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7774731 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5765311 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 13540042 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 240674354 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 168156931 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 408831285 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3034988 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 11680683 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.131880 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.338360 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7169000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6360157 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 13529157 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 219530790 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185908027 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 405438817 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3048406 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 11669556 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.129089 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.335298 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 10140239 86.81% 86.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1540444 13.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 10163148 87.09% 87.09% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1506408 12.91% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 11680683 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 7606203373 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 11669556 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 7690985653 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2481000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2550000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4538781481 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4244781764 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3532073491 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3859650249 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |