diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
| commit | e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb (patch) | |
| tree | 553bace58f742b4c98ac52d600a1103901011b8b /tests/long/fs/10.linux-boot/ref/arm | |
| parent | 0d8d6e44419e2c5464012b66abc62aaad433026b (diff) | |
| download | gem5-e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb.tar.xz | |
stats: changes due to recent changesets.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
6 files changed, 1750 insertions, 1330 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 16f8b652d..f1c3d0229 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -4,21 +4,23 @@ sim_seconds 2.845843 # Nu sim_ticks 2845842660500 # Number of ticks simulated final_tick 2845842660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164712 # Simulator instruction rate (inst/s) -host_op_rate 199442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3743328799 # Simulator tick rate (ticks/s) -host_mem_usage 646452 # Number of bytes of host memory used -host_seconds 760.24 # Real time elapsed on the host +host_inst_rate 92448 # Simulator instruction rate (inst/s) +host_op_rate 111941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2101025547 # Simulator tick rate (ticks/s) +host_mem_usage 635156 # Number of bytes of host memory used +host_seconds 1354.50 # Real time elapsed on the host sim_insts 125221621 # Number of instructions simulated sim_ops 151624712 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 10368 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3007420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1722304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1285116 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 8732480 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 774240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 153024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 621216 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 12926236 # Number of bytes read from this memory @@ -26,28 +28,32 @@ system.physmem.bytes_inst_read::cpu0.inst 1722304 # N system.physmem.bytes_inst_read::cpu1.inst 153024 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1875328 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 8977344 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory system.physmem.bytes_written::total 8995088 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 162 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 47516 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26911 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20605 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 136445 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 12121 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2391 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9730 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 202521 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 140271 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory system.physmem.num_writes::total 144707 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 3643 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 1056777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 605200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 451577 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 3068504 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 272060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 218289 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 140533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 4542147 # Total read bandwidth from this memory (bytes/s) @@ -55,16 +61,18 @@ system.physmem.bw_inst_read::cpu0.inst 605200 # In system.physmem.bw_inst_read::cpu1.inst 53771 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 658971 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 3154547 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 6221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 3160782 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 3154547 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 3643 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 1062998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 605200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 457798 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 3068504 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 272074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 218303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 140533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 7702929 # Total bandwidth to/from this memory (bytes/s) @@ -544,8 +552,8 @@ system.cpu0.dcache.tags.total_refs 40476936 # To system.cpu0.dcache.tags.sampled_refs 719053 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 56.292006 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 306903000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.305697 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965441 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.305697 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965441 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.965441 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id @@ -554,81 +562,81 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 83802985 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 83802985 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 22808347 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 22808347 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 22808347 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 16863099 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16863099 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 16863099 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381264 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 381264 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 381264 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362825 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362825 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 362825 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 39671446 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 39671446 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 39671446 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 39671446 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 39671446 # number of overall hits system.cpu0.dcache.overall_hits::total 39671446 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 540080 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 540080 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 540080 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 532227 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 532227 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 532227 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6489 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6489 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6489 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 19898 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19898 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 19898 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 1072307 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 1072307 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 1072307 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 1072307 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 1072307 # number of overall misses system.cpu0.dcache.overall_misses::total 1072307 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6648434719 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6648434719 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 6648434719 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8319872197 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8319872197 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 8319872197 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 104923750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104923750 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 104923750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 438142885 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 438142885 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 438142885 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 309000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 309000 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 309000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 14968306916 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 14968306916 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 14968306916 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 14968306916 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 14968306916 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 14968306916 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23348427 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 23348427 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 23348427 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395326 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17395326 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 17395326 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387753 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387753 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 387753 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382723 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382723 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 382723 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 40743753 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 40743753 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 40743753 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 40743753 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 40743753 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 40743753 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023131 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023131 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.023131 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030596 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030596 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.030596 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016735 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016735 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016735 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.051991 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051991 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051991 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026318 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026318 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026318 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026318 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026318 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.026318 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12310.092429 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12310.092429 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 12310.092429 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15632.187388 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15632.187388 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 15632.187388 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16169.479119 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16169.479119 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16169.479119 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 22019.443411 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22019.443411 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22019.443411 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13958.975290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 13958.975290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13958.975290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 13958.975290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -640,77 +648,77 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 523102 # number of writebacks system.cpu0.dcache.writebacks::total 523102 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42658 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42658 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 42658 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230433 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 230433 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 230433 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273091 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 273091 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 273091 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273091 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 273091 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 273091 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 497422 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 497422 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 497422 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 301794 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 301794 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 301794 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6489 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6489 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6489 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 19898 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19898 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 19898 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 799216 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 799216 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 799216 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 799216 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 799216 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 799216 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5149793898 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5149793898 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149793898 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4423706193 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4423706193 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4423706193 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 91926250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91926250 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91926250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 397751115 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 397751115 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397751115 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 291000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 291000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 291000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9573500091 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9573500091 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 9573500091 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9573500091 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9573500091 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 9573500091 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6190990749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6190990749 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6190990749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4804555500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4804555500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4804555500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995546249 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10995546249 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995546249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021304 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021304 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021304 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017349 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017349 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016735 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016735 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016735 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.051991 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051991 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051991 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019616 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.019616 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.019616 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019616 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019616 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.019616 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10352.967697 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10352.967697 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10352.967697 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14658.032277 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14658.032277 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14658.032277 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14166.474033 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14166.474033 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14166.474033 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19989.502211 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19989.502211 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19989.502211 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11978.614156 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11978.614156 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1982441 # number of replacements @@ -821,12 +829,14 @@ system.cpu0.l2cache.tags.warmup_cycle 2825848630000 # C system.cpu0.l2cache.tags.occ_blocks::writebacks 6310.295058 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.412646 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.063392 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 7791.524761 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5929.101601 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1862.423160 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1981.430976 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.385150 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003565 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.475557 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.361884 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.113673 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.120937 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.985213 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1941 # Occupied blocks per task id @@ -851,125 +861,143 @@ system.cpu0.l2cache.tags.tag_accesses 55347065 # Nu system.cpu0.l2cache.tags.data_accesses 55347065 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80493 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4332 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2344344 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1910084 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 434260 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 2429169 # number of ReadReq hits system.cpu0.l2cache.Writeback_hits::writebacks 523100 # number of Writeback hits system.cpu0.l2cache.Writeback_hits::total 523100 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4781 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 4781 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 4781 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 1890 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1890 # number of SCUpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::total 1890 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 226532 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226532 # number of ReadExReq hits system.cpu0.l2cache.ReadExReq_hits::total 226532 # number of ReadExReq hits system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80493 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4332 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 2570876 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1910084 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 660792 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::total 2655701 # number of demand (read+write) hits system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80493 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4332 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 2570876 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1910084 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 660792 # number of overall hits system.cpu0.l2cache.overall_hits::total 2655701 # number of overall hits system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 854 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 113 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 142527 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 72883 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 69644 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::total 143494 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 26406 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26406 # number of UpgradeReq misses system.cpu0.l2cache.UpgradeReq_misses::total 26406 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 18006 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18006 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::total 18006 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 44082 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44082 # number of ReadExReq misses system.cpu0.l2cache.ReadExReq_misses::total 44082 # number of ReadExReq misses system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 854 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.itb.walker 113 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 186609 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 72883 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 113726 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::total 187576 # number of demand (read+write) misses system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 854 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.itb.walker 113 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 186609 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 72883 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 113726 # number of overall misses system.cpu0.l2cache.overall_misses::total 187576 # number of overall misses system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 30085500 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2495499 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 5310554679 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3197828979 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2112725700 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::total 5343135678 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 462181513 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 462181513 # number of UpgradeReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::total 462181513 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 354964789 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 354964789 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 354964789 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 282000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 282000 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 282000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 2099231484 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2099231484 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::total 2099231484 # number of ReadExReq miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 30085500 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2495499 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 7409786163 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3197828979 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 4211957184 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::total 7442367162 # number of demand (read+write) miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 30085500 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2495499 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 7409786163 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3197828979 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 4211957184 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::total 7442367162 # number of overall miss cycles system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 81347 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4445 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2486871 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1982967 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 503904 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 2572663 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::writebacks 523100 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::total 523100 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 31187 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 31187 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 31187 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 19896 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19896 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::total 19896 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 270614 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270614 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 270614 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 81347 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4445 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 2757485 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1982967 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 774518 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::total 2843277 # number of demand (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 81347 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4445 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 2757485 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1982967 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 774518 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::total 2843277 # number of overall (read+write) accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025422 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.057312 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.036755 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.138209 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::total 0.055776 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.846699 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.846699 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.846699 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.905006 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.905006 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905006 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.162896 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.162896 # miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::total 0.162896 # miss rate for ReadExReq accesses system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025422 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.067674 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036755 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.146835 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::total 0.065972 # miss rate for demand accesses system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025422 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.067674 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036755 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.146835 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::total 0.065972 # miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22084.061947 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37259.990591 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 43876.198551 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 30336.076331 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::total 37235.951873 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17502.897561 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17502.897561 # average UpgradeReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17502.897561 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19713.694824 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19713.694824 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19713.694824 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 141000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 141000 # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 141000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 47621.058119 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47621.058119 # average ReadExReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47621.058119 # average ReadExReq miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22084.061947 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39707.549813 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 43876.198551 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37036.009215 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::total 39676.542639 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22084.061947 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39707.549813 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 43876.198551 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37036.009215 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::total 39676.542639 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -982,119 +1010,138 @@ system.cpu0.l2cache.cache_copies 0 # nu system.cpu0.l2cache.writebacks::writebacks 201133 # number of writebacks system.cpu0.l2cache.writebacks::total 201133 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 511 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 65 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 446 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3265 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3265 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::total 3265 # number of ReadExReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3776 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 65 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3711 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::total 3777 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3776 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 65 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3711 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::total 3777 # number of overall MSHR hits system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 854 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 112 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 142016 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 72818 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 69198 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::total 142982 # number of ReadReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 280772 # number of HardPFReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::total 280772 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 26406 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26406 # number of UpgradeReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26406 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 18006 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18006 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18006 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 40817 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40817 # number of ReadExReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::total 40817 # number of ReadExReq MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 854 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 112 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 182833 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 72818 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 110015 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::total 183799 # number of demand (read+write) MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 854 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 112 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 182833 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 72818 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 110015 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 280772 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::total 464571 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1685499 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 4279514975 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2677133771 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1602381204 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4305290474 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15488924735 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 449600763 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 449600763 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 449600763 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 240569359 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 240569359 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 240569359 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 219000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 219000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 219000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1467254248 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1467254248 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1467254248 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1685499 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 5746769223 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2677133771 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3069635452 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::total 5772544722 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1685499 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 5746769223 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2677133771 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3069635452 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::total 21261469457 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6177076991 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 242870500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5934206491 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6177076991 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4588309497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4588309497 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4588309497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10765386488 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 242870500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10522515988 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10765386488 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.057106 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.137324 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.055577 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.846699 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.846699 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.846699 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.905006 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905006 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905006 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.150831 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150831 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150831 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064643 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163393 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30134.034017 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23156.467008 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30110.716552 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55165.489205 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17026.462281 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17026.462281 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.462281 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13360.510885 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13360.510885 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13360.510885 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 109500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109500 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35947.135948 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 35947.135948 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35947.135948 # average ReadExReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31406.834216 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45765.812883 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.trans_dist::ReadReq 2726808 # Transaction distribution @@ -1343,8 +1390,8 @@ system.cpu1.dcache.tags.total_refs 7034054 # To system.cpu1.dcache.tags.sampled_refs 188124 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 37.390519 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 108317904000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 478.493571 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.934558 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.493571 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934558 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.934558 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id @@ -1352,81 +1399,81 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 14914460 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 14914460 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 3762812 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 3762812 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 3762812 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 3070723 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3070723 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 3070723 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 89288 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 89288 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 89288 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69262 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69262 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 69262 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 6833535 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 6833535 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 6833535 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 6833535 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 6833535 # number of overall hits system.cpu1.dcache.overall_hits::total 6833535 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 181434 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 181434 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 181434 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 139542 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 139542 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 139542 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5058 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5058 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5058 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23425 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23425 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 23425 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 320976 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 320976 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 320976 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 320976 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 320976 # number of overall misses system.cpu1.dcache.overall_misses::total 320976 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2698134351 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2698134351 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 2698134351 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3673411367 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3673411367 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 3673411367 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 91654251 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91654251 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 91654251 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540931813 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 540931813 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 540931813 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 185500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 185500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 185500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 6371545718 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6371545718 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 6371545718 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 6371545718 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6371545718 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 6371545718 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3944246 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3944246 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 3944246 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3210265 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3210265 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 3210265 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94346 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 94346 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 94346 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92687 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92687 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 92687 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 7154511 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 7154511 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 7154511 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 7154511 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7154511 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 7154511 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046000 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046000 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.046000 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043467 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.043467 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.053611 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053611 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.053611 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.252732 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.252732 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.252732 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044863 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044863 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.044863 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044863 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044863 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.044863 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.161695 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14871.161695 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.161695 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26324.772233 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26324.772233 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 26324.772233 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18120.650652 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18120.650652 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18120.650652 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23092.073127 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23092.073127 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23092.073127 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 19850.536233 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 19850.536233 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 19850.536233 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 19850.536233 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1438,77 +1485,77 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 113901 # number of writebacks system.cpu1.dcache.writebacks::total 113901 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15137 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15137 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 15137 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49794 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 49794 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 49794 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64931 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 64931 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 64931 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64931 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 64931 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 64931 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166297 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166297 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 166297 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89748 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89748 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 89748 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5058 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5058 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5058 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23425 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23425 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 23425 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256045 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 256045 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 256045 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256045 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 256045 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 256045 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2162409829 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2162409829 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2162409829 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2163633710 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2163633710 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2163633710 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 81526749 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81526749 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81526749 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492905187 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 492905187 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492905187 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 177500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 177500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 177500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4326043539 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4326043539 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 4326043539 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4326043539 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4326043539 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 4326043539 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 330271000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 330271000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 330271000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 203208500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 203208500 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 203208500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 533479500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 533479500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 533479500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042162 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042162 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042162 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027957 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027957 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027957 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.053611 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053611 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053611 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.252732 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.252732 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.252732 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.035788 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035788 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.035788 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.035788 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035788 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.035788 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13003.300294 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13003.300294 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13003.300294 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24107.876610 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24107.876610 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24107.876610 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16118.376631 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16118.376631 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16118.376631 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21041.843629 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21041.843629 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21041.843629 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16895.637638 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16895.637638 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16895.637638 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16895.637638 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 908016 # number of replacements @@ -1618,12 +1665,14 @@ system.cpu1.l2cache.tags.warmup_cycle 0 # Cy system.cpu1.l2cache.tags.occ_blocks::writebacks 8763.818423 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.824644 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.109281 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5323.780218 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3126.745417 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2197.034801 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1213.252936 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.534901 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001637 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.324938 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.190841 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.134096 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.074051 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.935534 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2056 # Occupied blocks per task id @@ -1645,119 +1694,137 @@ system.cpu1.l2cache.tags.tag_accesses 21629208 # Nu system.cpu1.l2cache.tags.data_accesses 21629208 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28145 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2626 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993919 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 889570 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 104349 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 1024690 # number of ReadReq hits system.cpu1.l2cache.Writeback_hits::writebacks 113900 # number of Writeback hits system.cpu1.l2cache.Writeback_hits::total 113900 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1602 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1602 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 1602 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 885 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 885 # number of SCUpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::total 885 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 24979 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 24979 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 24979 # number of ReadExReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28145 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2626 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1018898 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 889570 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 129328 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 1049669 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28145 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2626 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1018898 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 889570 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 129328 # number of overall hits system.cpu1.l2cache.overall_hits::total 1049669 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 614 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 219 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 85964 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 18958 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 67006 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::total 86797 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28133 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28133 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 28133 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22540 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22540 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 22540 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 35034 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35034 # number of ReadExReq misses system.cpu1.l2cache.ReadExReq_misses::total 35034 # number of ReadExReq misses system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 614 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 219 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 120998 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 18958 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 102040 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::total 121831 # number of demand (read+write) misses system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 614 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.itb.walker 219 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 120998 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 18958 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 102040 # number of overall misses system.cpu1.l2cache.overall_misses::total 121831 # number of overall misses system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13117250 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4335498 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 2028659662 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 588499240 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1440160422 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::total 2046112410 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 524558345 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 524558345 # number of UpgradeReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::total 524558345 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440871540 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 440871540 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440871540 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 173000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 173000 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 173000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1316941950 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1316941950 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::total 1316941950 # number of ReadExReq miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13117250 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4335498 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 3345601612 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 588499240 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2757102372 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::total 3363054360 # number of demand (read+write) miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13117250 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4335498 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 3345601612 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 588499240 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2757102372 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::total 3363054360 # number of overall miss cycles system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 28759 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2845 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1079883 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 908528 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 171355 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 1111487 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::writebacks 113900 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::total 113900 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29735 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29735 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 29735 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23425 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23425 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 23425 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60013 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 60013 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 60013 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 28759 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2845 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1139896 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 908528 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 231368 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::total 1171500 # number of demand (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 28759 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2845 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1139896 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 908528 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 231368 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 1171500 # number of overall (read+write) accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.076977 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.079605 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020867 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.391036 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::total 0.078091 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.946124 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.946124 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.946124 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.962220 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962220 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962220 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.583774 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.583774 # miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::total 0.583774 # miss rate for ReadExReq accesses system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.076977 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.106148 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020867 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.441029 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::total 0.103996 # miss rate for demand accesses system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.076977 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.106148 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020867 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.441029 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::total 0.103996 # miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19796.794521 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 23598.944465 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31042.263952 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21493.006925 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23573.538371 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18645.659723 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18645.659723 # average UpgradeReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18645.659723 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19559.518190 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19559.518190 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19559.518190 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 37590.396472 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37590.396472 # average ReadExReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37590.396472 # average ReadExReq miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19796.794521 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27650.057125 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31042.263952 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27019.819404 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::total 27604.258030 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19796.794521 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27650.057125 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31042.263952 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27019.819404 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::total 27604.258030 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1769,113 +1836,132 @@ system.cpu1.l2cache.fast_writes 0 # nu system.cpu1.l2cache.cache_copies 0 # number of cache copies performed system.cpu1.l2cache.writebacks::writebacks 33019 # number of writebacks system.cpu1.l2cache.writebacks::total 33019 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 106 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 18 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 88 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 284 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 284 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::total 284 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 390 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 372 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 390 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 372 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::total 390 # number of overall MSHR hits system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 614 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 219 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 85858 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 18940 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 66918 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::total 86691 # number of ReadReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25785 # number of HardPFReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::total 25785 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28133 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28133 # number of UpgradeReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28133 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22540 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22540 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22540 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 34750 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34750 # number of ReadExReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::total 34750 # number of ReadExReq MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 614 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 219 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 120608 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 18940 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 101668 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::total 121441 # number of demand (read+write) MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 614 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 219 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 120608 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 18940 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 101668 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25785 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::total 147226 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2802498 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1423893692 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 454726510 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 969167182 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1435514940 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1025770621 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 399929245 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 399929245 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 399929245 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 306606785 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306606785 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306606785 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 145000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 145000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 145000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 1042779776 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1042779776 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1042779776 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2802498 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 2466673468 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 454726510 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2011946958 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::total 2478294716 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2802498 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 2466673468 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 454726510 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2011946958 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::total 3504065337 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316947250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9029750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 307917500 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316947250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 187186000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 187186000 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 187186000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 504133250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9029750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 495103500 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 504133250 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079507 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.390523 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.077996 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.946124 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.946124 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946124 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.962220 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962220 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962220 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.579041 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.579041 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.579041 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.105806 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439421 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103663 # mshr miss rate for demand accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.105806 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439421 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125673 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 16584.286753 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14482.907170 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16558.984670 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39781.680085 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14215.662923 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14215.662923 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14215.662923 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13602.785492 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13602.785492 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13602.785492 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30008.051108 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30008.051108 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30008.051108 # average ReadExReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20451.988823 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20407.397139 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20451.988823 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23800.587783 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 1492249 # Transaction distribution @@ -2139,18 +2225,22 @@ system.l2c.tags.warmup_cycle 0 # Cy system.l2c.tags.occ_blocks::writebacks 11502.485032 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 90.401142 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038214 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 12425.194881 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 9505.348435 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2919.846446 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36413.661117 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.683124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1856.879628 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1274.245745 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 582.633884 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1880.036266 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.175514 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001379 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.189593 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.145040 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.044553 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.555628 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000117 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.028334 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.019443 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008890 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.028687 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.979254 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 31795 # Occupied blocks per task id @@ -2173,210 +2263,246 @@ system.l2c.tags.tag_accesses 5313847 # Nu system.l2c.tags.data_accesses 5313847 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 426 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 70654 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 48963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 21691 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 75814 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 118 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 32 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 24007 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 16648 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 7359 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7439 # number of ReadReq hits system.l2c.ReadReq_hits::total 178553 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 234152 # number of Writeback hits system.l2c.Writeback_hits::total 234152 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 2938 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 658 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 2938 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 658 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3596 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 142 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 176 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 142 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 176 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 3842 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 1332 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 3842 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1332 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 5174 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 426 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 74496 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 48963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 25533 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.l2cache.prefetcher 75814 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 118 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 25339 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 16648 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 8691 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.l2cache.prefetcher 7439 # number of demand (read+write) hits system.l2c.demand_hits::total 183727 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 426 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits -system.l2c.overall_hits::cpu0.inst 74496 # number of overall hits +system.l2c.overall_hits::cpu0.inst 48963 # number of overall hits +system.l2c.overall_hits::cpu0.data 25533 # number of overall hits system.l2c.overall_hits::cpu0.l2cache.prefetcher 75814 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 118 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits -system.l2c.overall_hits::cpu1.inst 25339 # number of overall hits +system.l2c.overall_hits::cpu1.inst 16648 # number of overall hits +system.l2c.overall_hits::cpu1.data 8691 # number of overall hits system.l2c.overall_hits::cpu1.l2cache.prefetcher 7439 # number of overall hits system.l2c.overall_hits::total 183727 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 162 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 32548 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 23855 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8693 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 136690 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3333 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2292 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1041 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6249 # number of ReadReq misses system.l2c.ReadReq_misses::total 178995 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 8970 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 2734 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8970 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2734 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 11704 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 618 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 1189 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 618 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1189 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1807 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 11575 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 8676 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 11575 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8676 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 20251 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 162 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 44123 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 23855 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20268 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.l2cache.prefetcher 136690 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 12009 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2292 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9717 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) misses system.l2c.demand_misses::total 199246 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 162 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 44123 # number of overall misses +system.l2c.overall_misses::cpu0.inst 23855 # number of overall misses +system.l2c.overall_misses::cpu0.data 20268 # number of overall misses system.l2c.overall_misses::cpu0.l2cache.prefetcher 136690 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu1.inst 12009 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2292 # number of overall misses +system.l2c.overall_misses::cpu1.data 9717 # number of overall misses system.l2c.overall_misses::cpu1.l2cache.prefetcher 6249 # number of overall misses system.l2c.overall_misses::total 199246 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 12996250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 2445317489 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1747991991 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 697325498 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 960250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 258262249 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 172995499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 85266750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 17612731920 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 7054791 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 1587933 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 7054791 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1587933 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 8642724 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 937466 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 512978 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 937466 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 512978 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 1450444 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 952737665 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 639334486 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 952737665 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 639334486 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 1592072151 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 12996250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 3398055154 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1747991991 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1650063163 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 960250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 897596735 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 172995499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 724601236 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 19204804071 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 12996250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 3398055154 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1747991991 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1650063163 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 960250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 897596735 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 172995499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 724601236 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of overall miss cycles system.l2c.overall_miss_latency::total 19204804071 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 64 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 103202 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 72818 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 30384 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 212504 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 130 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 32 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 27340 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 18940 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 8400 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 13688 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 357548 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 234152 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 234152 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 11908 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 3392 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 11908 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3392 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 15300 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 760 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 1365 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 760 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1365 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2125 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 15417 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 10008 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15417 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10008 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 25425 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 588 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 64 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 118619 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 72818 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 45801 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.l2cache.prefetcher 212504 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 130 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 37348 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 18940 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 18408 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13688 # number of demand (read+write) accesses system.l2c.demand_accesses::total 382973 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 588 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 64 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 118619 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 72818 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 45801 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.l2cache.prefetcher 212504 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 130 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 37348 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 18940 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 18408 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13688 # number of overall (read+write) accesses system.l2c.overall_accesses::total 382973 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.015625 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.315381 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.327598 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.286105 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.121909 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.121014 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.123929 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.500618 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.753275 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.806014 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.753275 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.806014 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.764967 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.813158 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.871062 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.813158 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.871062 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.850353 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.750795 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.866906 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.750795 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.866906 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.796500 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.015625 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.371972 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.327598 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.442523 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.321543 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.121014 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.527868 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.520261 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.015625 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.371972 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.327598 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.442523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.321543 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.121014 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.527868 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.520261 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75129.577516 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73275.707022 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 80216.898424 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77486.423342 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75477.966405 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 81908.501441 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 98397.898936 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 786.487291 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 580.809437 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 786.487291 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 580.809437 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 738.441900 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 1516.935275 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 431.436501 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1516.935275 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 431.436501 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 802.680686 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 82309.949460 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73690.005302 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82309.949460 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73690.005302 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 78616.964644 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 77013.239218 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 73275.707022 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 81412.234212 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 74743.670164 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75477.966405 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 74570.467840 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average overall miss latency system.l2c.demand_avg_miss_latency::total 96387.400856 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 77013.239218 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 73275.707022 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 81412.234212 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 74743.670164 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75477.966405 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 74570.467840 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average overall miss latency system.l2c.overall_avg_miss_latency::total 96387.400856 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -2400,153 +2526,185 @@ system.l2c.overall_mshr_hits::cpu1.inst 3 # nu system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 162 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 32540 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 23847 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8693 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3330 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 2289 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1041 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 178984 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 8970 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2734 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8970 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2734 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 11704 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 618 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1189 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 618 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1189 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1807 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 11575 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 8676 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11575 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8676 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 20251 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 162 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 44115 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 23847 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 20268 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 12006 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2289 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 9717 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 199235 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 162 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 44115 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 23847 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 20268 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 12006 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2289 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 9717 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 199235 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2034453239 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1445321741 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 589131498 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 810750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 216209999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 143882249 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 72327750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 15392098420 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91762404 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 27532715 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 91762404 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 27532715 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 119295119 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6310115 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 11917186 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6310115 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11917186 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 18227301 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 807808323 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 530171012 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 807808323 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 530171012 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 1337979335 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 2842261562 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1445321741 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1396939821 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 810750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 746381011 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 143882249 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 602498762 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 16730077755 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 2842261562 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1445321741 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1396939821 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 810750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 746381011 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 143882249 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 602498762 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 16730077755 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5519244498 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263262750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 163590000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5355654498 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6093250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 257169500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 5782507248 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4096891000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150604000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4096891000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 150604000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 4247495000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9616135498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413866750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 163590000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9452545498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6093250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 407773500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 10030002248 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.315304 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.286105 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.121800 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.123929 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.500587 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.753275 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.806014 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.753275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.806014 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813158 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.871062 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813158 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.871062 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850353 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.750795 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.866906 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.750795 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.866906 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.796500 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371905 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.442523 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.321463 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.527868 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.520232 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371905 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.442523 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.321463 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.527868 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.520232 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62521.611524 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67770.792362 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64927.927628 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69479.106628 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 85997.063536 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10229.922408 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.488296 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10229.922408 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10070.488296 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10192.679340 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.542071 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10022.864592 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10210.542071 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.864592 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10087.050913 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69789.055983 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61107.769940 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69789.055983 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61107.769940 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 66069.790875 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64428.461113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68923.417259 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62167.333916 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62004.606566 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64428.461113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68923.417259 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62167.333916 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62004.606566 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 217279 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 8068ce076..6a8c865e1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -4,47 +4,51 @@ sim_seconds 2.852858 # Nu sim_ticks 2852857543000 # Number of ticks simulated final_tick 2852857543000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169259 # Simulator instruction rate (inst/s) -host_op_rate 204656 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4303403710 # Simulator tick rate (ticks/s) -host_mem_usage 619600 # Number of bytes of host memory used -host_seconds 662.93 # Real time elapsed on the host +host_inst_rate 109881 # Simulator instruction rate (inst/s) +host_op_rate 132861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2793727953 # Simulator tick rate (ticks/s) +host_mem_usage 608784 # Number of bytes of host memory used +host_seconds 1021.17 # Real time elapsed on the host sim_insts 112207125 # Number of instructions simulated sim_ops 135672670 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 8192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10837924 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1662912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9175012 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 10847140 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1662912 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1662912 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7962752 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::total 7980276 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 128 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 169862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 25983 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143879 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 170006 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 124418 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::total 128799 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 2872 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3798971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 582893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3216078 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3802202 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 582893 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 582893 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 2791150 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 6143 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2797292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 2791150 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 2872 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3805114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 582893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3222220 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6599494 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 170006 # Number of read requests accepted @@ -534,8 +538,8 @@ system.cpu.dcache.tags.total_refs 42762284 # To system.cpu.dcache.tags.sampled_refs 842495 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 50.756721 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 281436250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953279 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.953279 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999909 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id @@ -544,77 +548,77 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 176413277 # Number of tag accesses system.cpu.dcache.tags.data_accesses 176413277 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 23536274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 23536274 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 23536274 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 18304900 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18304900 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 18304900 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457909 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457909 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 460268 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460268 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 41841174 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 41841174 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 41841174 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 41841174 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 41841174 # number of overall hits system.cpu.dcache.overall_hits::total 41841174 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 583393 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 583393 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 583393 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 541748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 541748 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 541748 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8195 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8195 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8195 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.inst 1125141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 1125141 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1125141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1125141 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 1125141 # number of overall misses system.cpu.dcache.overall_misses::total 1125141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8651014339 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8651014339 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 8651014339 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21393186307 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21393186307 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 21393186307 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 116036500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116036500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 116036500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 150500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150500 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 30044200646 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30044200646 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 30044200646 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 30044200646 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30044200646 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 30044200646 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 24119667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 24119667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 24119667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 18846648 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18846648 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 18846648 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466104 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466104 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 466104 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460270 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460270 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460270 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42966315 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42966315 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 42966315 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42966315 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42966315 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 42966315 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024187 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024187 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.024187 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028745 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028745 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.028745 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017582 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017582 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017582 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.026187 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026187 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.026187 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.026187 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026187 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026187 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14828.793522 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14828.793522 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 14828.793522 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39489.183729 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39489.183729 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 39489.183729 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14159.426480 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14159.426480 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.426480 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 75250 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26702.609403 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 26702.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26702.609403 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 26702.609403 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -626,73 +630,73 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 698310 # number of writebacks system.cpu.dcache.writebacks::total 698310 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45149 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45149 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 45149 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242834 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 242834 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 242834 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 287983 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 287983 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 287983 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 287983 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 287983 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 287983 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 538244 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 538244 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 538244 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298914 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298914 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 298914 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8195 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8195 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 8195 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 837158 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 837158 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 837158 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 837158 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 837158 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 837158 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6893184142 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6893184142 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 6893184142 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11166823654 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11166823654 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 11166823654 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 99620500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99620500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99620500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 146500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18060007796 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18060007796 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 18060007796 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18060007796 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18060007796 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 18060007796 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5790998000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790998000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790998000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439562500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4439562500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439562500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230560500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10230560500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230560500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022316 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022316 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022316 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015860 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015860 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015860 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017582 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017582 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017582 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019484 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.019484 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.019484 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019484 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019484 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.019484 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12806.801640 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12806.801640 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12806.801640 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37357.981406 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37357.981406 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37357.981406 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12156.253813 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12156.253813 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.253813 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 73250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73250 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21572.997924 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21572.997924 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21572.997924 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21572.997924 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2900110 # number of replacements @@ -797,11 +801,13 @@ system.cpu.l2cache.tags.warmup_cycle 0 # Cy system.cpu.l2cache.tags.occ_blocks::writebacks 47498.508165 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 71.489031 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000365 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 17501.014446 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12194.784847 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5306.229599 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.724770 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001091 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.267044 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186078 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.080967 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.992905 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 37 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65211 # Occupied blocks per task id @@ -817,113 +823,131 @@ system.cpu.l2cache.tags.tag_accesses 36621683 # Nu system.cpu.l2cache.tags.data_accesses 36621683 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71038 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4429 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 3409631 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 2877594 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 532037 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3485098 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 698310 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 698310 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.inst 53 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 164919 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 164919 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 164919 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 71038 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 4429 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 3574550 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2877594 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 696956 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3650017 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 71038 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 4429 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 3574550 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2877594 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 696956 # number of overall hits system.cpu.l2cache.overall_hits::total 3650017 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 128 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 37410 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 23013 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 14397 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 37539 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2779 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2779 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2779 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 131168 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131168 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 131168 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 128 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 168578 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 23013 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 145565 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 168707 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 128 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 168578 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 23013 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 145565 # number of overall misses system.cpu.l2cache.overall_misses::total 168707 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10214250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 74500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2773098000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1672158250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1100939750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 2783386750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 790966 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 790966 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 790966 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 144500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9154216683 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9154216683 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 9154216683 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10214250 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 74500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11927314683 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1672158250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10255156433 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 11937603433 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10214250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 74500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11927314683 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1672158250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10255156433 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 11937603433 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 71166 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4430 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 3447041 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 2900607 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 546434 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 3522637 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 698310 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 698310 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2832 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2832 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2832 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 296087 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296087 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 296087 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 71166 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 4430 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 3743128 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 2900607 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 842521 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 3818724 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 71166 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 4430 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3743128 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2900607 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 842521 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 3818724 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001799 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000226 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010853 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007934 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026347 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.010657 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.981285 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981285 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981285 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.443005 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443005 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.443005 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001799 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000226 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.045037 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007934 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.172773 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.044179 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001799 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000226 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.045037 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007934 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.172773 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.044179 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79798.828125 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74127.185245 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72661.463086 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76470.080572 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 74146.534271 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 284.622526 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 284.622526 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 284.622526 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 72250 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69790.014966 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69790.014966 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69790.014966 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79798.828125 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70752.498446 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72661.463086 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70450.701975 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 70759.384216 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79798.828125 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70752.498446 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72661.463086 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70450.701975 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 70759.384216 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -935,95 +959,114 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 88228 # number of writebacks system.cpu.l2cache.writebacks::total 88228 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 162 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 20 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 142 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 162 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 20 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 142 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 162 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 162 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 20 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 142 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 162 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 128 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 37248 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22993 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14255 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 37377 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2779 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2779 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2779 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 131168 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131168 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 131168 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 128 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 168416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 22993 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 145423 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 168545 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 128 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 168416 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 22993 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 145423 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 168545 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8641250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2295827000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1382505500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 913321500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2304530750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 27979779 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27979779 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27979779 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 120500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7500556317 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7500556317 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7500556317 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8641250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9796383317 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1382505500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8413877817 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 9805087067 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8641250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 62500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9796383317 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1382505500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8413877817 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 9805087067 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545301250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 159586250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385715000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545301250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4107025000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107025000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107025000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652326250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 159586250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9492740000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652326250 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010806 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026087 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010611 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.981285 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981285 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981285 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.443005 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443005 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443005 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044993 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172605 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.044136 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044993 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172605 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.044136 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61636.248926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60127.234376 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64070.256051 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61656.386280 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10068.290392 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10068.290392 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10068.290392 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57182.821397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57182.821397 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57182.821397 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58167.770978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58167.770978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 3581727 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index f860bb1f1..069845b38 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -782,9 +782,9 @@ system.cpu0.iew.iewDispNonSpecInsts 862014 # Nu system.cpu0.iew.iewIQFullEvents 26297 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 136520 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 18704 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 287591 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 287589 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 395520 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 683111 # Number of branch mispredicts detected at execute +system.cpu0.iew.branchMispredicts 683109 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 98423737 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 17803606 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1019712 # Number of squashed instructions skipped in execute diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 0523405d3..da0ad220f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -341,10 +341,10 @@ system.physmem_0.preEnergy 73012500 # En system.physmem_0.readEnergy 369306600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 291126960 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 68915344410 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 68919855390 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 1612195386000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1860850713630 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.510917 # Core power per rank (mW) +system.physmem_0.totalEnergy 1860855224610 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.510956 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 2632883157750 # Time in different power states system.physmem_0.memoryStateTime::REF 91447980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 3b8bb2577..f7aa432dd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -4,22 +4,24 @@ sim_seconds 47.355615 # Nu sim_ticks 47355615197500 # Number of ticks simulated final_tick 47355615197500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178863 # Simulator instruction rate (inst/s) -host_op_rate 210359 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9462962325 # Simulator tick rate (ticks/s) -host_mem_usage 759628 # Number of bytes of host memory used -host_seconds 5004.31 # Real time elapsed on the host +host_inst_rate 119180 # Simulator instruction rate (inst/s) +host_op_rate 140167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6305360463 # Simulator tick rate (ticks/s) +host_mem_usage 747912 # Number of bytes of host memory used +host_seconds 7510.37 # Real time elapsed on the host sim_insts 895084962 # Number of instructions simulated sim_ops 1052703090 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 106496 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 83264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 18925144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8104128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10821016 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 17557952 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 158592 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 147776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 13767904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3589696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10178208 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 16399360 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 427968 # Number of bytes read from this memory system.physmem.bytes_read::total 67574456 # Number of bytes read from this memory @@ -27,30 +29,34 @@ system.physmem.bytes_inst_read::cpu0.inst 8104128 # N system.physmem.bytes_inst_read::cpu1.inst 3589696 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 11693824 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 78266240 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory system.physmem.bytes_written::total 78287056 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 1664 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1301 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 295727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 126627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 169100 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 215138 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 159049 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory system.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 399639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 171133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 228505 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 290734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 75803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 214931 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s) @@ -58,17 +64,19 @@ system.physmem.bw_inst_read::cpu0.inst 171133 # In system.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 439 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 400078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 171133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 228945 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 370768 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 290734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 75803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 214931 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 346302 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s) @@ -354,23 +362,31 @@ system.physmem_1.memoryStateTime::REF 1581308040000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). @@ -588,8 +604,8 @@ system.cpu0.dcache.tags.total_refs 150576282 # To system.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 27.948862 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 4951668000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 501.034252 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.978583 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.034252 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978583 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.978583 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id @@ -598,93 +614,93 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 39 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 320066517 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 320066517 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 77114778 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 77114778 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 77114778 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 69351990 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69351990 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 69351990 # number of WriteReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 251432 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 251432 # number of WriteInvalidateReq hits system.cpu0.dcache.WriteInvalidateReq_hits::total 251432 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1745310 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1745310 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 1745310 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1668274 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1668274 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 1668274 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 146466768 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 146466768 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 146466768 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 146466768 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 146466768 # number of overall hits system.cpu0.dcache.overall_hits::total 146466768 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 3852692 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 3852692 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 3852692 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 2255601 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2255601 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 2255601 # number of WriteReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst 766100 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 766100 # number of WriteInvalidateReq misses system.cpu0.dcache.WriteInvalidateReq_misses::total 766100 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 104059 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 104059 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 104059 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 180014 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180014 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 180014 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 6108293 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 6108293 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 6108293 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 6108293 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 6108293 # number of overall misses system.cpu0.dcache.overall_misses::total 6108293 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54452724607 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54452724607 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 54452724607 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 41906959422 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 41906959422 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 41906959422 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 27296991314 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 27296991314 # number of WriteInvalidateReq miss cycles system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27296991314 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1502404735 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 1502404735 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 1502404735 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3769027814 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3769027814 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 3769027814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 2840500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2840500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 96359684029 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 96359684029 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 96359684029 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 96359684029 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 96359684029 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 96359684029 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 80967470 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 80967470 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 80967470 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 71607591 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 71607591 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 71607591 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 1017532 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1017532 # number of WriteInvalidateReq accesses(hits+misses) system.cpu0.dcache.WriteInvalidateReq_accesses::total 1017532 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1849369 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1849369 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 1849369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1848288 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1848288 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 1848288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 152575061 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 152575061 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 152575061 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 152575061 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 152575061 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 152575061 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.047583 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047583 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.047583 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.031499 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031499 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.031499 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.752900 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.752900 # miss rate for WriteInvalidateReq accesses system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.752900 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.056267 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056267 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056267 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.097395 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097395 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097395 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.040035 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040035 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.040035 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.040035 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040035 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.040035 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14133.682269 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14133.682269 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 18579.065811 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18579.065811 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 18579.065811 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35631.107315 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 35631.107315 # average WriteInvalidateReq miss latency system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 35631.107315 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 14438.008582 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14438.008582 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14438.008582 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20937.414946 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20937.414946 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20937.414946 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 15775.222968 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 15775.222968 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 15775.222968 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 15775.222968 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -696,91 +712,91 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 3733142 # number of writebacks system.cpu0.dcache.writebacks::total 3733142 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 361487 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 361487 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 361487 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 935411 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 935411 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 935411 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst 100 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 100 # number of WriteInvalidateReq MSHR hits system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 100 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 34 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 34 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 67 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1296898 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1296898 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 1296898 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1296898 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1296898 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 1296898 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3491205 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3491205 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 3491205 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1320190 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1320190 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 1320190 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst 766000 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 766000 # number of WriteInvalidateReq MSHR misses system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 766000 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 104025 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104025 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104025 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 179947 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 179947 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 179947 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4811395 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4811395 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 4811395 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4811395 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4811395 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 4811395 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 42113152704 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42113152704 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42113152704 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 22270249828 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22270249828 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22270249828 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 25755951436 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25755951436 # number of WriteInvalidateReq MSHR miss cycles system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 25755951436 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1293404753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1293404753 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1293404753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3399276642 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3399276642 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3399276642 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2291500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2291500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2291500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 64383402532 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 64383402532 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 64383402532 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 64383402532 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 64383402532 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 64383402532 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5824362996 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5824362996 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5824362996 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 5586865743 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5586865743 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5586865743 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 11411228739 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11411228739 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11411228739 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.043119 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043119 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043119 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018436 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.752802 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.752802 # mshr miss rate for WriteInvalidateReq accesses system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.752802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.056249 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056249 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056249 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.097359 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097359 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.031535 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031535 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.031535 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12062.641038 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12062.641038 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12062.641038 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 16868.973275 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16868.973275 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16868.973275 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 33623.957488 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33623.957488 # average WriteInvalidateReq mshr miss latency system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 33623.957488 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 12433.595318 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12433.595318 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18890.432416 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18890.432416 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 9463678 # number of replacements @@ -891,12 +907,14 @@ system.cpu0.l2cache.tags.warmup_cycle 5578143500 # Cy system.cpu0.l2cache.tags.occ_blocks::writebacks 4129.920995 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.114006 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 24.266127 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 9438.642805 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6921.151423 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2517.491382 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2562.596205 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.252070 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002570 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001481 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.576089 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.422434 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.153655 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.156408 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.988619 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 2519 # Occupied blocks per task id @@ -922,137 +940,155 @@ system.cpu0.l2cache.tags.tag_accesses 319708402 # Nu system.cpu0.l2cache.tags.data_accesses 319708402 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 463342 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 138212 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 11610557 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 8698965 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2911592 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 12212111 # number of ReadReq hits system.cpu0.l2cache.Writeback_hits::writebacks 3733141 # number of Writeback hits system.cpu0.l2cache.Writeback_hits::total 3733141 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.inst 193768 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 193768 # number of WriteInvalidateReq hits system.cpu0.l2cache.WriteInvalidateReq_hits::total 193768 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 68627 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 68627 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 68627 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 33597 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33597 # number of SCUpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::total 33597 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 855771 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 855771 # number of ReadExReq hits system.cpu0.l2cache.ReadExReq_hits::total 855771 # number of ReadExReq hits system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 463342 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.itb.walker 138212 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 12466328 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 8698965 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3767363 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::total 13067882 # number of demand (read+write) hits system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 463342 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.itb.walker 138212 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 12466328 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 8698965 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3767363 # number of overall hits system.cpu0.l2cache.overall_hits::total 13067882 # number of overall hits system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11843 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8238 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 1448613 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 765234 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 683379 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::total 1468694 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.inst 570757 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 570757 # number of WriteInvalidateReq misses system.cpu0.l2cache.WriteInvalidateReq_misses::total 570757 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 126856 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 126856 # number of UpgradeReq misses system.cpu0.l2cache.UpgradeReq_misses::total 126856 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 146340 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 146340 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::total 146340 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 10 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 270676 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 270676 # number of ReadExReq misses system.cpu0.l2cache.ReadExReq_misses::total 270676 # number of ReadExReq misses system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11843 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8238 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 1719289 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 765234 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 954055 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::total 1739370 # number of demand (read+write) misses system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11843 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8238 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 1719289 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 765234 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 954055 # number of overall misses system.cpu0.l2cache.overall_misses::total 1739370 # number of overall misses system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 383176229 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 279750987 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 44923505132 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 22688045273 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 22235459859 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::total 45586432348 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.inst 223595615 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 223595615 # number of WriteInvalidateReq miss cycles system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 223595615 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 2548596996 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2548596996 # number of UpgradeReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::total 2548596996 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 2948593769 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2948593769 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2948593769 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 2234000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2234000 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2234000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 12372799630 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12372799630 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::total 12372799630 # number of ReadExReq miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 383176229 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 279750987 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 57296304762 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22688045273 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 34608259489 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::total 57959231978 # number of demand (read+write) miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 383176229 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 279750987 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 57296304762 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22688045273 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 34608259489 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::total 57959231978 # number of overall miss cycles system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 475185 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 146450 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 13059170 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 9464199 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3594971 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 13680805 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::writebacks 3733141 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::total 3733141 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.inst 764525 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 764525 # number of WriteInvalidateReq accesses(hits+misses) system.cpu0.l2cache.WriteInvalidateReq_accesses::total 764525 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 195483 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 195483 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 195483 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 179937 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 179937 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::total 179937 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 10 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 1126447 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1126447 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 1126447 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 475185 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 146450 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 14185617 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 9464199 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4721418 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::total 14807252 # number of demand (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 475185 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 146450 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 14185617 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 9464199 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4721418 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::total 14807252 # number of overall (read+write) accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056251 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.110927 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.080856 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.190093 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::total 0.107354 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.inst 0.746551 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.746551 # miss rate for WriteInvalidateReq accesses system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.746551 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.648936 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.648936 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.648936 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.813285 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.813285 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813285 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.240292 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.240292 # miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::total 0.240292 # miss rate for ReadExReq accesses system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056251 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.121199 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.080856 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.202070 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::total 0.117467 # miss rate for demand accesses system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056251 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.121199 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.080856 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.202070 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::total 0.117467 # miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33958.604880 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31011.391677 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29648.506565 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32537.522896 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31038.754395 # average ReadReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 391.752734 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 391.752734 # average WriteInvalidateReq miss latency system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 391.752734 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 20090.472630 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20090.472630 # average UpgradeReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20090.472630 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20148.925577 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20148.925577 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20148.925577 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 223400 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 223400 # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223400 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 45710.737672 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45710.737672 # average ReadExReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45710.737672 # average ReadExReq miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33958.604880 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33325.580959 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29648.506565 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36274.910240 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::total 33321.968286 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33958.604880 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33325.580959 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29648.506565 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36274.910240 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::total 33321.968286 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 82 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1065,129 +1101,148 @@ system.cpu0.l2cache.cache_copies 0 # nu system.cpu0.l2cache.writebacks::writebacks 1399370 # number of writebacks system.cpu0.l2cache.writebacks::total 1399370 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 3403 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3395 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 3404 # number of ReadReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.inst 156 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 156 # number of WriteInvalidateReq MSHR hits system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 156 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 9658 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9658 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::total 9658 # number of ReadExReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 13061 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 13053 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::total 13062 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 13061 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 13053 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::total 13062 # number of overall MSHR hits system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11843 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8237 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 1445210 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 765226 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 679984 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::total 1465290 # number of ReadReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 1036981 # number of HardPFReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::total 1036981 # number of HardPFReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.inst 570601 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 570601 # number of WriteInvalidateReq MSHR misses system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 570601 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 126856 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 126856 # number of UpgradeReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::total 126856 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 146340 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 146340 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 146340 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 10 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 261018 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 261018 # number of ReadExReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::total 261018 # number of ReadExReq MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11843 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8237 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 1706228 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 765226 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 941002 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::total 1726308 # number of demand (read+write) MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11843 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8237 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 1706228 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 765226 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 941002 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 1036981 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::total 2763289 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 221721501 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 34355781249 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 17303340727 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 17052440522 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 34877337999 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 47311809533 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 20034543782 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 20034543782 # number of WriteInvalidateReq MSHR miss cycles system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 20034543782 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 2151275072 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2151275072 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2151275072 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 1993779824 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 1993779824 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 1993779824 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1835000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1835000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1835000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 9532664011 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9532664011 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9532664011 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 221721501 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 43888445260 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17303340727 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 26585104533 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::total 44410002010 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 221721501 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 43888445260 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17303340727 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 26585104533 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::total 91721811543 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9672004742 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4113621500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5558383242 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9672004742 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 5338553005 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5338553005 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5338553005 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15010557747 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4113621500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10896936247 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15010557747 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.110666 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.189149 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.107106 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.746347 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.746347 # mshr miss rate for WriteInvalidateReq accesses system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.746347 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.648936 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.648936 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.648936 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813285 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813285 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813285 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.231718 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231718 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231718 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.199305 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.116585 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.120279 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199305 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186617 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23772.172383 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25077.708478 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 35111.301561 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 35111.301561 # average WriteInvalidateReq mshr miss latency system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16958.402220 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16958.402220 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13624.298374 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13624.298374 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13624.298374 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 183500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 183500 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 36521.098204 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36521.098204 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36521.098204 # average ReadExReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28251.910764 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25725.422121 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25722.497380 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28251.910764 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.trans_dist::ReadReq 16482247 # Transaction distribution @@ -1441,8 +1496,8 @@ system.cpu1.dcache.tags.total_refs 161270449 # To system.cpu1.dcache.tags.sampled_refs 5624987 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 28.670368 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8377201144000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 426.107402 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.832241 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.107402 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832241 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.832241 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id @@ -1451,93 +1506,93 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2 209 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 342291215 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 342291215 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 83489779 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 83489779 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 83489779 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 73474609 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 73474609 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 73474609 # number of WriteReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 71990 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 71990 # number of WriteInvalidateReq hits system.cpu1.dcache.WriteInvalidateReq_hits::total 71990 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1908367 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1908367 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 1908367 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1854336 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1854336 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 1854336 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 156964388 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 156964388 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 156964388 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 156964388 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 156964388 # number of overall hits system.cpu1.dcache.overall_hits::total 156964388 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 4311289 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 4311289 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 4311289 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 2366929 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2366929 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 2366929 # number of WriteReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 476593 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 476593 # number of WriteInvalidateReq misses system.cpu1.dcache.WriteInvalidateReq_misses::total 476593 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 141331 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 141331 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 141331 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 193852 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193852 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 193852 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 6678218 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 6678218 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 6678218 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 6678218 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 6678218 # number of overall misses system.cpu1.dcache.overall_misses::total 6678218 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 60722587231 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 60722587231 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 60722587231 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 38093191666 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38093191666 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 38093191666 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst 11613108236 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11613108236 # number of WriteInvalidateReq miss cycles system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11613108236 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1977833980 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1977833980 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 1977833980 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3982712056 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3982712056 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 3982712056 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 2357000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2357000 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2357000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 98815778897 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 98815778897 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 98815778897 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 98815778897 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 98815778897 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 98815778897 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 87801068 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::cpu1.data 87801068 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 87801068 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 75841538 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 75841538 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 75841538 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 548583 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 548583 # number of WriteInvalidateReq accesses(hits+misses) system.cpu1.dcache.WriteInvalidateReq_accesses::total 548583 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 2049698 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2049698 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 2049698 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 2048188 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2048188 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 2048188 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 163642606 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 163642606 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 163642606 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 163642606 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 163642606 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 163642606 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.049103 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049103 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.049103 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.031209 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031209 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.031209 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst 0.868771 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.868771 # miss rate for WriteInvalidateReq accesses system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.868771 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.068952 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.068952 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.068952 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.094646 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094646 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.040810 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040810 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.040810 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.040810 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040810 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.040810 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14084.555044 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14084.555044 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 16093.930856 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16093.930856 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 24366.929930 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 24366.929930 # average WriteInvalidateReq miss latency system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 24366.929930 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13994.339388 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13994.339388 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13994.339388 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20545.117182 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20545.117182 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 14796.728543 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14796.728543 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 14796.728543 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1549,91 +1604,91 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 3711348 # number of writebacks system.cpu1.dcache.writebacks::total 3711348 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 397792 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 397792 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 397792 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 970938 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 970938 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 970938 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst 60 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 60 # number of WriteInvalidateReq MSHR hits system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 60 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 47 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 47 # number of LoadLockedReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 68 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 68 # number of StoreCondReq MSHR hits system.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 1368730 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1368730 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 1368730 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 1368730 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1368730 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 1368730 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3913497 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3913497 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 3913497 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1395991 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1395991 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 1395991 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst 476533 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 476533 # number of WriteInvalidateReq MSHR misses system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 476533 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 141284 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141284 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141284 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 193784 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193784 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 193784 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 5309488 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 5309488 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 5309488 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 5309488 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5309488 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 5309488 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 46779736993 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46779736993 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46779736993 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 20386885918 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20386885918 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20386885918 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 10653380764 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10653380764 # number of WriteInvalidateReq MSHR miss cycles system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10653380764 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1693632498 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1693632498 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1693632498 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3584420895 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3584420895 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3584420895 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 1830000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 67166622911 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 67166622911 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 67166622911 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 67166622911 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 67166622911 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 67166622911 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 548139751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 548139751 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 548139751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 613571252 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 613571252 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 613571252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 1161711003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1161711003 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1161711003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.044572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044572 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044572 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.018407 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018407 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018407 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.868662 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.868662 # mshr miss rate for WriteInvalidateReq accesses system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.868662 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.068929 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068929 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068929 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.094612 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094612 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094612 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.032446 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.032446 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.032446 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11953.436273 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11953.436273 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11953.436273 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14603.880625 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14603.880625 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14603.880625 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 22356.018920 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22356.018920 # average WriteInvalidateReq mshr miss latency system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22356.018920 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11987.433099 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11987.433099 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18496.990954 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18496.990954 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 9215030 # number of replacements @@ -1744,12 +1799,14 @@ system.cpu1.l2cache.tags.warmup_cycle 9611078525000 # C system.cpu1.l2cache.tags.occ_blocks::writebacks 5526.220513 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 77.627317 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 76.256480 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 6438.113983 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3620.154380 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2817.959604 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1415.441924 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.337294 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004738 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004654 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.392951 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.220957 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.171995 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086392 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.826029 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2491 # Occupied blocks per task id @@ -1776,141 +1833,159 @@ system.cpu1.l2cache.tags.tag_accesses 321109712 # Nu system.cpu1.l2cache.tags.data_accesses 321109712 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 544517 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158528 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 11678610 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 8400098 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 3278512 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 12381655 # number of ReadReq hits system.cpu1.l2cache.Writeback_hits::writebacks 3711345 # number of Writeback hits system.cpu1.l2cache.Writeback_hits::total 3711345 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst 202419 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 202419 # number of WriteInvalidateReq hits system.cpu1.l2cache.WriteInvalidateReq_hits::total 202419 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 77280 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 77280 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 77280 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 41809 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41809 # number of SCUpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::total 41809 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 939119 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 939119 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 939119 # number of ReadExReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 544517 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 158528 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 12617729 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 8400098 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 4217631 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 13320774 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 544517 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.itb.walker 158528 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 12617729 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 8400098 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 4217631 # number of overall hits system.cpu1.l2cache.overall_hits::total 13320774 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12561 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8870 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 1591427 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 815444 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 775983 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::total 1612858 # number of ReadReq misses system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst 272843 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 272843 # number of WriteInvalidateReq misses system.cpu1.l2cache.WriteInvalidateReq_misses::total 272843 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 137034 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 137034 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 137034 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 151974 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 151974 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 151974 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 244121 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 244121 # number of ReadExReq misses system.cpu1.l2cache.ReadExReq_misses::total 244121 # number of ReadExReq misses system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12561 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8870 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 1835548 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 815444 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1020104 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::total 1856979 # number of demand (read+write) misses system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12561 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8870 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 1835548 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 815444 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1020104 # number of overall misses system.cpu1.l2cache.overall_misses::total 1856979 # number of overall misses system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 455863233 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 358991737 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 47206598788 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 22574174788 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 24632424000 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::total 48021453758 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst 213581444 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 213581444 # number of WriteInvalidateReq miss cycles system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 213581444 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2792930491 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2792930491 # number of UpgradeReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::total 2792930491 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 3071034580 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3071034580 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3071034580 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 1783500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1783500 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1783500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9626384839 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9626384839 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::total 9626384839 # number of ReadExReq miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 455863233 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358991737 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 56832983627 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22574174788 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 34258808839 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::total 57647838597 # number of demand (read+write) miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 455863233 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358991737 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 56832983627 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22574174788 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 34258808839 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::total 57647838597 # number of overall miss cycles system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 557078 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 167398 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 13270037 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 9215542 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4054495 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 13994513 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::writebacks 3711346 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::total 3711346 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst 475262 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 475262 # number of WriteInvalidateReq accesses(hits+misses) system.cpu1.l2cache.WriteInvalidateReq_accesses::total 475262 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 214314 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 214314 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 214314 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 193783 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193783 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 193783 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1183240 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1183240 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1183240 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 557078 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 167398 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 14453277 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 9215542 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5237735 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::total 15177753 # number of demand (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 557078 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 167398 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 14453277 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 9215542 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5237735 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 15177753 # number of overall (read+write) accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052987 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.119926 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.088486 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.191388 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::total 0.115249 # miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst 0.574090 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.574090 # miss rate for WriteInvalidateReq accesses system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.574090 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.639408 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.639408 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.639408 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.784248 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.784248 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.784248 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.206316 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.206316 # miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::total 0.206316 # miss rate for ReadExReq accesses system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052987 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.126999 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.088486 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.194761 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::total 0.122349 # miss rate for demand accesses system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052987 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.126999 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.088486 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.194761 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::total 0.122349 # miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40472.574634 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29663.062640 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 27683.292523 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 31743.509845 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29774.136197 # average ReadReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 782.799793 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 782.799793 # average WriteInvalidateReq miss latency system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 782.799793 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 20381.295817 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20381.295817 # average UpgradeReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20381.295817 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20207.631437 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20207.631437 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20207.631437 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 1783500 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1783500 # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1783500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 39432.842070 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39432.842070 # average ReadExReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39432.842070 # average ReadExReq miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40472.574634 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30962.406664 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27683.292523 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33583.643275 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::total 31043.882886 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40472.574634 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30962.406664 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27683.292523 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33583.643275 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::total 31043.882886 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1923,133 +1998,152 @@ system.cpu1.l2cache.cache_copies 0 # nu system.cpu1.l2cache.writebacks::writebacks 1092301 # number of writebacks system.cpu1.l2cache.writebacks::total 1092301 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1805 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 1804 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::total 1806 # number of ReadReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.inst 45 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 45 # number of WriteInvalidateReq MSHR hits system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 45 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 7072 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7072 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::total 7072 # number of ReadExReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 8877 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 8876 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::total 8878 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 8877 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 8876 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::total 8878 # number of overall MSHR hits system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12561 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8869 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 1589622 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 815443 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 774179 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::total 1611052 # number of ReadReq MSHR misses system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 1032302 # number of HardPFReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::total 1032302 # number of HardPFReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.inst 272798 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 272798 # number of WriteInvalidateReq MSHR misses system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 272798 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 137034 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 137034 # number of UpgradeReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::total 137034 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 151974 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 151974 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 151974 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 237049 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237049 # number of ReadExReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::total 237049 # number of ReadExReq MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12561 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8869 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 1826671 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 815443 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1011228 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::total 1848101 # number of demand (read+write) MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12561 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8869 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 1826671 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 815443 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1011228 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 1032302 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::total 2880403 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 296231251 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 35897455818 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 16845762712 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 19051693106 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 36560910324 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 41289088164 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 41289088164 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 7103244766 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7103244766 # number of WriteInvalidateReq MSHR miss cycles system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7103244766 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 2312644672 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2312644672 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2312644672 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 2076231085 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2076231085 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2076231085 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 1461500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1461500 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1461500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 7288633813 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7288633813 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7288633813 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 296231251 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 43186089631 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16845762712 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 26340326919 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::total 43849544137 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 296231251 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 43186089631 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16845762712 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 26340326919 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 41289088164 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::total 85138632301 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 514241998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7364250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 506877748 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 514241998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 574249999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 574249999 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 574249999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 1088491997 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7364250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1081127747 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1088491997 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.119790 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.190943 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115120 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.573995 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.573995 # mshr miss rate for WriteInvalidateReq accesses system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.573995 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.639408 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.639408 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.639408 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.784248 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784248 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784248 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.200339 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.200339 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.200339 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::total 0.121764 # mshr miss rate for demand accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.126385 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189778 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22582.384880 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24608.899371 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 26038.478163 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26038.478163 # average WriteInvalidateReq mshr miss latency system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16876.429733 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16876.429733 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13661.751912 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13661.751912 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 1461500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1461500 # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1461500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30747.372117 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30747.372117 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117 # average ReadExReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23641.963786 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 16597851 # Transaction distribution @@ -2344,20 +2438,24 @@ system.l2c.tags.warmup_cycle 8003493500 # Cy system.l2c.tags.occ_blocks::writebacks 16627.933383 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.809416 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 10.076521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7682.914611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4159.600580 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3523.314031 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5733.726218 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 373.789781 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 460.262003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 14361.821399 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3670.846899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 10690.974499 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.253722 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000211 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.117232 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.063470 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.053762 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.087490 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005704 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.007023 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.219144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.163131 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.293209 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.983888 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 14505 # Occupied blocks per task id @@ -2379,240 +2477,276 @@ system.l2c.tags.tag_accesses 65568567 # Nu system.l2c.tags.data_accesses 65568567 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 6731 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 4742 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 1051842 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 690690 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 361152 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 521850 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 6817 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 4499 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 1187571 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 759258 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 428313 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 530462 # number of ReadReq hits system.l2c.ReadReq_hits::total 3314514 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 2491671 # number of Writeback hits system.l2c.Writeback_hits::total 2491671 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.inst 125819 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.inst 140505 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 125819 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 140505 # number of WriteInvalidateReq hits system.l2c.WriteInvalidateReq_hits::total 266324 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.inst 29765 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 32403 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 29765 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 32403 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 62168 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 5875 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 6386 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 5875 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 6386 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 12261 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 56397 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 53337 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 56397 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 53337 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 109734 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 6731 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 4742 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 1108239 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 690690 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 417549 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.l2cache.prefetcher 521850 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 6817 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 4499 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 1240908 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 759258 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 481650 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.l2cache.prefetcher 530462 # number of demand (read+write) hits system.l2c.demand_hits::total 3424248 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 6731 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 4742 # number of overall hits -system.l2c.overall_hits::cpu0.inst 1108239 # number of overall hits +system.l2c.overall_hits::cpu0.inst 690690 # number of overall hits +system.l2c.overall_hits::cpu0.data 417549 # number of overall hits system.l2c.overall_hits::cpu0.l2cache.prefetcher 521850 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 6817 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 4499 # number of overall hits -system.l2c.overall_hits::cpu1.inst 1240908 # number of overall hits +system.l2c.overall_hits::cpu1.inst 759258 # number of overall hits +system.l2c.overall_hits::cpu1.data 481650 # number of overall hits system.l2c.overall_hits::cpu1.l2cache.prefetcher 530462 # number of overall hits system.l2c.overall_hits::total 3424248 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1664 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1301 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 169093 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 74535 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 94558 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 274703 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2478 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 2309 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 162223 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 56185 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 106038 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 256515 # number of ReadReq misses system.l2c.ReadReq_misses::total 870286 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.inst 435530 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.inst 123517 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 435530 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 123517 # number of WriteInvalidateReq misses system.l2c.WriteInvalidateReq_misses::total 559047 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 44959 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 45474 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 44959 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 45474 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 90433 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 8261 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 9038 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 8261 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 9038 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 17299 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 76639 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 55158 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 76639 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 55158 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131797 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1664 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1301 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 245732 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 74535 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 171197 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.l2cache.prefetcher 274703 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2478 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 2309 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 217381 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 56185 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 161196 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.l2cache.prefetcher 256515 # number of demand (read+write) misses system.l2c.demand_misses::total 1002083 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1664 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1301 # number of overall misses -system.l2c.overall_misses::cpu0.inst 245732 # number of overall misses +system.l2c.overall_misses::cpu0.inst 74535 # number of overall misses +system.l2c.overall_misses::cpu0.data 171197 # number of overall misses system.l2c.overall_misses::cpu0.l2cache.prefetcher 274703 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2478 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 2309 # number of overall misses -system.l2c.overall_misses::cpu1.inst 217381 # number of overall misses +system.l2c.overall_misses::cpu1.inst 56185 # number of overall misses +system.l2c.overall_misses::cpu1.data 161196 # number of overall misses system.l2c.overall_misses::cpu1.l2cache.prefetcher 256515 # number of overall misses system.l2c.overall_misses::total 1002083 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 138961746 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 111055248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 13556032080 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 5745942443 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 7810089637 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 202393999 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 185177500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 12762094450 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4301130982 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 8460963468 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 95981532857 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.inst 36612963 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.inst 35758482 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 36612963 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 35758482 # number of WriteInvalidateReq miss cycles system.l2c.WriteInvalidateReq_miss_latency::total 72371445 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 213542030 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 216684315 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 213542030 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 216684315 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 430226345 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 36699987 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 41305269 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 36699987 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 41305269 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 78005256 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 6278532917 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 4207751582 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6278532917 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4207751582 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 10486284499 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 138961746 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 111055248 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 19834564997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 5745942443 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 14088622554 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 202393999 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 185177500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 16969846032 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4301130982 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 12668715050 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 106467817356 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 138961746 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 111055248 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 19834564997 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 5745942443 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 14088622554 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 202393999 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 185177500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 16969846032 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4301130982 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 12668715050 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of overall miss cycles system.l2c.overall_miss_latency::total 106467817356 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 8395 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 6043 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 1220935 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 765225 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 455710 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 796553 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 9295 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 6808 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 1349794 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 815443 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 534351 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 786977 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 4184800 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 2491671 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 2491671 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.inst 561349 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.inst 264022 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 561349 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 264022 # number of WriteInvalidateReq accesses(hits+misses) system.l2c.WriteInvalidateReq_accesses::total 825371 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 74724 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 77877 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 74724 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 77877 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 152601 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 14136 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 15424 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 14136 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 15424 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 29560 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 133036 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 108495 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 133036 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 108495 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 241531 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 8395 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 6043 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 1353971 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 765225 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 588746 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.l2cache.prefetcher 796553 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 9295 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 6808 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 1458289 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 815443 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 642846 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.l2cache.prefetcher 786977 # number of demand (read+write) accesses system.l2c.demand_accesses::total 4426331 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 8395 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 6043 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 1353971 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 765225 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 588746 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.l2cache.prefetcher 796553 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 9295 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 6808 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 1458289 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 815443 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 642846 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.l2cache.prefetcher 786977 # number of overall (read+write) accesses system.l2c.overall_accesses::total 4426331 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.215290 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.138495 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.097403 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.207496 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.339160 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.120184 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.068901 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.198443 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.207964 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.inst 0.775863 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.inst 0.467828 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.775863 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.467828 # miss rate for WriteInvalidateReq accesses system.l2c.WriteInvalidateReq_miss_rate::total 0.677328 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.601667 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.583921 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.601667 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.583921 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.592611 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.584394 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.585970 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.584394 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.585970 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.585217 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.576077 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.508392 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.576077 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.508392 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.545673 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.215290 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.181490 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.097403 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.290782 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.itb.walker 0.339160 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.149066 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.068901 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.250754 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.226391 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.215290 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.181490 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.097403 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.290782 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.itb.walker 0.339160 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.149066 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.068901 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.250754 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.226391 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85361.451191 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80169.090855 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77090.527175 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 82595.757493 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 80198.137722 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78670.068054 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76553.012049 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 79791.805466 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 110287.345605 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.inst 84.065307 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.inst 289.502514 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 84.065307 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 289.502514 # average WriteInvalidateReq miss latency system.l2c.WriteInvalidateReq_avg_miss_latency::total 129.455028 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 4749.705954 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 4765.015503 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4749.705954 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4765.015503 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 4757.404321 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 4442.559860 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 4570.178026 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4442.559860 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4570.178026 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 4509.234985 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 81923.471301 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 76285.426992 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81923.471301 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76285.426992 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 79563.908883 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85361.451191 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 80716.247770 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 77090.527175 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 82294.798121 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 80198.137722 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 78064.992028 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76553.012049 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 78591.993908 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average overall miss latency system.l2c.demand_avg_miss_latency::total 106246.505884 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85361.451191 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 80716.247770 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 77090.527175 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 82294.798121 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 80198.137722 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 78064.992028 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76553.012049 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 78591.993908 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average overall miss latency system.l2c.overall_avg_miss_latency::total 106246.505884 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 5735 # number of cycles access was blocked @@ -2625,188 +2759,226 @@ system.l2c.fast_writes 0 # nu system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 1116216 # number of writebacks system.l2c.writebacks::total 1116216 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 210 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 177 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.inst 188 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 22 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 162 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 15 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 387 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 210 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 177 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 188 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 22 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 162 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 15 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 387 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 210 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 177 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 188 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 22 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 162 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 15 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 387 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1664 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1301 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 168883 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 74347 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 94536 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2478 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2309 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 162046 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 56023 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 106023 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 869899 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.inst 435530 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.inst 123517 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 435530 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 123517 # number of WriteInvalidateReq MSHR misses system.l2c.WriteInvalidateReq_mshr_misses::total 559047 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 44959 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 45474 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 44959 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 45474 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 90433 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 8261 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 9038 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 8261 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9038 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 17299 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 76639 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 55158 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 76639 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 55158 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131797 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 1664 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1301 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 245522 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 74347 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 171175 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 2478 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 2309 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 217204 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 56023 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 161181 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 1001696 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 1664 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1301 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 245522 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 74347 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 171175 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 2478 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 2309 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 217204 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 56023 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 161181 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 1001696 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 94777748 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11415126178 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4793355973 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 6621770205 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 156241500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 10713554460 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3582053738 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 7131500722 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 85169385965 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 9786055012 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 2515639470 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 9786055012 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2515639470 # number of WriteInvalidateReq MSHR miss cycles system.l2c.WriteInvalidateReq_mshr_miss_latency::total 12301694482 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 455524094 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 460871563 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 455524094 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 460871563 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 916395657 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 84887682 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 92374949 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 84887682 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 92374949 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 177262631 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5315349505 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 3512186842 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5315349505 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3512186842 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 8827536347 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 94777748 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 16730475683 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 4793355973 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 11937119710 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 156241500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 14225741302 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3582053738 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 10643687564 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 93996922312 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 94777748 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 16730475683 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 4793355973 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 11937119710 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 156241500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 14225741302 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3582053738 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 10643687564 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 93996922312 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 7718194748 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 418305498 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2759400500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4958794248 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5045750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 413259748 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 8136500246 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4773990997 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 484709502 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4773990997 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 484709502 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 5258700499 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 12492185745 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 903015000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2759400500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9732785245 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5045750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 897969250 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 13395200745 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.138323 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.207448 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.120052 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.198415 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.207871 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.775863 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.467828 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.775863 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.467828 # mshr miss rate for WriteInvalidateReq accesses system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677328 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.601667 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.583921 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.601667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.583921 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.592611 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.584394 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.585970 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.584394 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.585970 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.585217 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.576077 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.508392 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.576077 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508392 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.545673 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290745 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.250730 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.226304 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290745 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.250730 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.226304 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67591.919720 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70044.958587 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66114.279032 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67263.713741 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22469.301798 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 20366.746845 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22469.301798 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20366.746845 # average WriteInvalidateReq mshr miss latency system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10131.989012 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10134.836676 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10131.989012 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10134.836676 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10275.715047 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10220.729033 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10275.715047 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10220.729033 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69355.674069 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63675.021611 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69355.674069 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63675.021611 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 969598 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 3ebfb1ad5..f3459bbfc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -4,47 +4,51 @@ sim_seconds 51.728175 # Nu sim_ticks 51728174627500 # Number of ticks simulated final_tick 51728174627500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184836 # Simulator instruction rate (inst/s) -host_op_rate 217188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10028441874 # Simulator tick rate (ticks/s) -host_mem_usage 718288 # Number of bytes of host memory used -host_seconds 5158.15 # Real time elapsed on the host +host_inst_rate 121986 # Simulator instruction rate (inst/s) +host_op_rate 143338 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6618487836 # Simulator tick rate (ticks/s) +host_mem_usage 708088 # Number of bytes of host memory used +host_seconds 7815.71 # Real time elapsed on the host sim_insts 953410832 # Number of instructions simulated sim_ops 1120287994 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 394816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 334912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 77628104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10241472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 67386632 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 424256 # Number of bytes read from this memory system.physmem.bytes_read::total 78782088 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 10241472 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 10241472 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 95103808 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.inst 20580 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::total 95124388 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 6169 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5233 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 1212952 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 160023 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1052929 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6629 # Number of read requests responded to by this memory system.physmem.num_reads::total 1230983 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1485997 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.inst 2573 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::total 1488570 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 7633 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 6474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 1500693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 197986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1302707 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8202 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1523002 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 197986 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 197986 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1838530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1838928 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1838530 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 7633 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 6474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1501091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1303104 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8202 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3361929 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1230983 # Number of read requests accepted @@ -311,17 +315,21 @@ system.physmem_1.memoryStateTime::REF 1727317280000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 280461298998 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 16 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). @@ -526,8 +534,8 @@ system.cpu.dcache.tags.total_refs 331084794 # To system.cpu.dcache.tags.sampled_refs 11209674 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 29.535631 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959689 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.959689 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999921 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id @@ -537,89 +545,89 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1391009936 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1391009936 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 169770938 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 169770938 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 169770938 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 152453541 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 152453541 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 152453541 # number of WriteReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst 337498 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337498 # number of WriteInvalidateReq hits system.cpu.dcache.WriteInvalidateReq_hits::total 337498 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 4114364 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4114364 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 4114364 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 4358642 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4358642 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 4358642 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 322224479 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 322224479 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 322224479 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 322224479 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 322224479 # number of overall hits system.cpu.dcache.overall_hits::total 322224479 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 8085158 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 8085158 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 8085158 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 4338895 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4338895 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 4338895 # number of WriteReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.inst 1245002 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245002 # number of WriteInvalidateReq misses system.cpu.dcache.WriteInvalidateReq_misses::total 1245002 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 246013 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 246013 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 246013 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.inst 12424053 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 12424053 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 12424053 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 12424053 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 12424053 # number of overall misses system.cpu.dcache.overall_misses::total 12424053 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128824080247 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128824080247 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 128824080247 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 144514675403 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 144514675403 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 144514675403 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.inst 29607413192 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 29607413192 # number of WriteInvalidateReq miss cycles system.cpu.dcache.WriteInvalidateReq_miss_latency::total 29607413192 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 3571422003 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3571422003 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 3571422003 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 150500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150500 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 273338755650 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 273338755650 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 273338755650 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 273338755650 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 273338755650 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 273338755650 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 177856096 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 177856096 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 177856096 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 156792436 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 156792436 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 156792436 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst 1582500 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1582500 # number of WriteInvalidateReq accesses(hits+misses) system.cpu.dcache.WriteInvalidateReq_accesses::total 1582500 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 4360377 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4360377 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 4360377 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 4358644 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4358644 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 4358644 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 334648532 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 334648532 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 334648532 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 334648532 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 334648532 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 334648532 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.045459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.045459 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.045459 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.027673 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027673 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.027673 # miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.inst 0.786731 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786731 # miss rate for WriteInvalidateReq accesses system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786731 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.056420 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056420 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056420 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.037126 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037126 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.037126 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.037126 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037126 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037126 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15933.402940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15933.402940 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 15933.402940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 33306.792490 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33306.792490 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 33306.792490 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.inst 23781.016570 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 23781.016570 # average WriteInvalidateReq miss latency system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23781.016570 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14517.208452 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14517.208452 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14517.208452 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 75250 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75250 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22000.771862 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22000.771862 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 22000.771862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22000.771862 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22000.771862 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 22000.771862 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -631,85 +639,85 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 8593512 # number of writebacks system.cpu.dcache.writebacks::total 8593512 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 755938 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 755938 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 755938 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1899458 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1899458 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1899458 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.inst 141 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 141 # number of WriteInvalidateReq MSHR hits system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 141 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 2655396 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2655396 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2655396 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 2655396 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2655396 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2655396 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7329220 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7329220 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7329220 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2439437 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2439437 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2439437 # number of WriteReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.inst 1244861 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244861 # number of WriteInvalidateReq MSHR misses system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244861 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 246009 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 246009 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 246009 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9768657 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9768657 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 9768657 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9768657 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9768657 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9768657 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102525908749 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 102525908749 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 102525908749 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 73694416463 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73694416463 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 73694416463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 27114416558 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 27114416558 # number of WriteInvalidateReq MSHR miss cycles system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 27114416558 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 3077572997 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3077572997 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3077572997 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 146500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146500 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 176220325212 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176220325212 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 176220325212 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 176220325212 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176220325212 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 176220325212 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5727815999 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5727815999 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727815999 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 5585117500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5585117500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5585117500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 11312933499 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11312933499 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 11312933499 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.041209 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041209 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041209 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015558 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015558 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015558 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.inst 0.786642 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786642 # mshr miss rate for WriteInvalidateReq accesses system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786642 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.056419 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056419 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056419 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.029191 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029191 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.029191 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.029191 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029191 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.029191 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 13988.652101 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13988.652101 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13988.652101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 30209.600192 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30209.600192 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30209.600192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 21781.079621 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21781.079621 # average WriteInvalidateReq mshr miss latency system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21781.079621 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12510.001654 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12510.001654 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12510.001654 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 73250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73250 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18039.360499 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18039.360499 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18039.360499 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18039.360499 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24725990 # number of replacements @@ -814,11 +822,13 @@ system.cpu.l2cache.tags.warmup_cycle 5745484000 # Cy system.cpu.l2cache.tags.occ_blocks::writebacks 36067.634498 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 340.939586 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 425.072148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 28524.406895 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8071.479946 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20452.926949 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.550348 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005202 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006486 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.435248 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123161 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.312087 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.997285 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 346 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 62873 # Occupied blocks per task id @@ -834,125 +844,143 @@ system.cpu.l2cache.tags.tag_accesses 371551924 # Nu system.cpu.l2cache.tags.data_accesses 371551924 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 967297 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 281175 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 31858848 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 24618722 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 7240126 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 33107320 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 8593512 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 8593512 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.inst 704117 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 704117 # number of WriteInvalidateReq hits system.cpu.l2cache.WriteInvalidateReq_hits::total 704117 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.inst 10834 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 10834 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 10834 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1670528 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1670528 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1670528 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 967297 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 281175 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 33529376 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 24618722 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 8910654 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 34777848 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 967297 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 281175 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 33529376 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 24618722 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 8910654 # number of overall hits system.cpu.l2cache.overall_hits::total 34777848 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6169 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5233 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 442678 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 107787 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 334891 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 454080 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.inst 540744 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 540744 # number of WriteInvalidateReq misses system.cpu.l2cache.WriteInvalidateReq_misses::total 540744 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.inst 38969 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 38969 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 38969 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 719318 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 719318 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 719318 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 6169 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5233 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 1161996 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 107787 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1054209 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 1173398 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 6169 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5233 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 1161996 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 107787 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1054209 # number of overall misses system.cpu.l2cache.overall_misses::total 1173398 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 490563500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 420808500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 33361514961 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 7986963739 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25374551222 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 34272886961 # number of ReadReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.inst 4498807 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 4498807 # number of WriteInvalidateReq miss cycles system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4498807 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 431949947 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 431949947 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 431949947 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 144500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 53534470118 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53534470118 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 53534470118 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 490563500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 420808500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 86895985079 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 7986963739 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 78909021340 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 87807357079 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 490563500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 420808500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 86895985079 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 7986963739 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 78909021340 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 87807357079 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 973466 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 286408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 32301526 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 24726509 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7575017 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 33561400 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 8593512 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 8593512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.inst 1244861 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1244861 # number of WriteInvalidateReq accesses(hits+misses) system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244861 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 49803 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49803 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 49803 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2389846 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2389846 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2389846 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 973466 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 286408 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 34691372 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 24726509 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9964863 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 35951246 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 973466 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 286408 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 34691372 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 24726509 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9964863 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 35951246 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006337 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018271 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.013705 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004359 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.044210 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.013530 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.inst 0.434381 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.434381 # miss rate for WriteInvalidateReq accesses system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.434381 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.782463 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782463 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782463 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.300989 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.300989 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.300989 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006337 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018271 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.033495 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004359 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.105793 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.032639 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006337 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018271 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.033495 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004359 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.105793 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.032639 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79520.748906 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80414.389452 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75362.938662 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74099.508651 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75769.582407 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 75477.640418 # average ReadReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.inst 8.319661 # average WriteInvalidateReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 8.319661 # average WriteInvalidateReq miss latency system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 8.319661 # average WriteInvalidateReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11084.450384 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11084.450384 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11084.450384 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 72250 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74423.926717 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74423.926717 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74423.926717 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79520.748906 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80414.389452 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74781.655943 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74099.508651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74851.401705 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 74831.691446 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79520.748906 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80414.389452 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74781.655943 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74099.508651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74851.401705 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 74831.691446 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -964,103 +992,122 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1379367 # number of writebacks system.cpu.l2cache.writebacks::total 1379367 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 20 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 20 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 20 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6169 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5233 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 442656 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 107785 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 334871 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 454058 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.inst 540744 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 540744 # number of WriteInvalidateReq MSHR misses system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 540744 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 38969 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38969 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 38969 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 719318 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 719318 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 719318 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6169 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5233 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1161974 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 107785 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1054189 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 1173376 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5233 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1161974 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 107785 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1054189 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1173376 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 413632000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 355518000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27784615785 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6634859761 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21149756024 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28553765785 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 12667521943 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 12667521943 # number of WriteInvalidateReq MSHR miss cycles system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 12667521943 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 390061961 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 390061961 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 390061961 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 120500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 44297743880 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44297743880 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44297743880 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 413632000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 355518000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72082359665 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6634859761 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65447499904 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 72851509665 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 413632000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 355518000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72082359665 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6634859761 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65447499904 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 72851509665 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 8006368251 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2718370250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5287998001 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8006368251 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 5177591000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5177591000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5177591000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 13183959251 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2718370250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465589001 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13183959251 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.013704 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.044207 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013529 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.inst 0.434381 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.434381 # mshr miss rate for WriteInvalidateReq accesses system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.434381 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.782463 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782463 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782463 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.300989 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.300989 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.300989 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033495 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.105791 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.032638 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033495 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.105791 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.032638 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62767.963803 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61556.429568 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.920584 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62885.723377 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 23426.098011 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 23426.098011 # average WriteInvalidateReq mshr miss latency system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23426.098011 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10009.545049 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.545049 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.545049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61582.977042 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61582.977042 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61582.977042 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61556.429568 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62083.269607 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61556.429568 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62083.269607 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 34111380 # Transaction distribution |