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authorAndreas Hansson <andreas.hansson@arm.com>2016-04-09 12:13:40 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2016-04-09 12:13:40 -0400
commitd9193d1b2039739ef4fb264c742d37f9803817e5 (patch)
tree7904829173102a8d8f654873d5cefb790e148298 /tests/long/fs/10.linux-boot/ref/arm
parent1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff)
downloadgem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes throughout.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt4857
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt1926
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt2720
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt6085
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt2664
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt4611
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt4156
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt5404
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt2211
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt2806
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt6656
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt2718
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt12
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt5236
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt4433
15 files changed, 28461 insertions, 28034 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index e45890e36..8f982bce7 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -1,162 +1,162 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.649116 # Number of seconds simulated
-sim_ticks 2649116242500 # Number of ticks simulated
-final_tick 2649116242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.848878 # Number of seconds simulated
+sim_ticks 2848878048000 # Number of ticks simulated
+final_tick 2848878048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 120147 # Simulator instruction rate (inst/s)
-host_op_rate 145490 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2497044812 # Simulator tick rate (ticks/s)
-host_mem_usage 602856 # Number of bytes of host memory used
-host_seconds 1060.90 # Real time elapsed on the host
-sim_insts 127464482 # Number of instructions simulated
-sim_ops 154350851 # Number of ops (including micro ops) simulated
+host_inst_rate 194660 # Simulator instruction rate (inst/s)
+host_op_rate 235713 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4372273286 # Simulator tick rate (ticks/s)
+host_mem_usage 620428 # Number of bytes of host memory used
+host_seconds 651.58 # Real time elapsed on the host
+sim_insts 126836472 # Number of instructions simulated
+sim_ops 153585571 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 7744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1526336 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1246188 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8224576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 394816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 723292 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 617536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1701632 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1345580 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8578560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 207872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 624532 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 336128 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12744072 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1526336 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 394816 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1921152 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8953600 # Number of bytes written to this memory
+system.physmem.bytes_read::total 12804992 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1701632 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 207872 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1909504 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8865600 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8971164 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 121 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8883164 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 140 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 23849 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 19993 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 128509 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6169 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 11324 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 9649 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 26588 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 21546 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 134040 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 3248 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 9779 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 5252 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 199670 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 139900 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 200620 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 138525 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 144291 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 576168 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 470417 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 3104649 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 966 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 149037 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 273031 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 233110 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 362 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4810688 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 576168 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 149037 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 725205 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3379844 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6615 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3386474 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3379844 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 576168 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 477032 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 3104649 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 966 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 149037 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 273047 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 233110 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 362 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 8197162 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 199670 # Number of read requests accepted
-system.physmem.writeReqs 144291 # Number of write requests accepted
-system.physmem.readBursts 199670 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 144291 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12768704 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8984192 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 12744072 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8971164 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one
+system.physmem.num_writes::total 142916 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 3145 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 597299 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 472319 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 3011206 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 247 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 72966 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 219220 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 117986 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4494749 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 597299 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 72966 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 670265 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3111962 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3118127 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3111962 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 3145 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 597299 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 478470 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 3011206 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 247 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 72966 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 219234 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 117986 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7612876 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 200620 # Number of read requests accepted
+system.physmem.writeReqs 142916 # Number of write requests accepted
+system.physmem.readBursts 200620 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 142916 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 12829952 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8896256 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 12804992 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8883164 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 12456 # Per bank write bursts
-system.physmem.perBankRdBursts::1 12907 # Per bank write bursts
-system.physmem.perBankRdBursts::2 13452 # Per bank write bursts
-system.physmem.perBankRdBursts::3 12663 # Per bank write bursts
-system.physmem.perBankRdBursts::4 15992 # Per bank write bursts
-system.physmem.perBankRdBursts::5 12602 # Per bank write bursts
-system.physmem.perBankRdBursts::6 12853 # Per bank write bursts
-system.physmem.perBankRdBursts::7 13005 # Per bank write bursts
-system.physmem.perBankRdBursts::8 12164 # Per bank write bursts
-system.physmem.perBankRdBursts::9 12306 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11290 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10778 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11668 # Per bank write bursts
-system.physmem.perBankRdBursts::13 12164 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11811 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11400 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8970 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9418 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9818 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9016 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8619 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8911 # Per bank write bursts
-system.physmem.perBankWrBursts::6 9199 # Per bank write bursts
-system.physmem.perBankWrBursts::7 9114 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8718 # Per bank write bursts
-system.physmem.perBankWrBursts::9 8852 # Per bank write bursts
-system.physmem.perBankWrBursts::10 8120 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7867 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8570 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8570 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8685 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7931 # Per bank write bursts
+system.physmem.perBankRdBursts::0 12282 # Per bank write bursts
+system.physmem.perBankRdBursts::1 12615 # Per bank write bursts
+system.physmem.perBankRdBursts::2 13546 # Per bank write bursts
+system.physmem.perBankRdBursts::3 12896 # Per bank write bursts
+system.physmem.perBankRdBursts::4 15667 # Per bank write bursts
+system.physmem.perBankRdBursts::5 12734 # Per bank write bursts
+system.physmem.perBankRdBursts::6 12682 # Per bank write bursts
+system.physmem.perBankRdBursts::7 12950 # Per bank write bursts
+system.physmem.perBankRdBursts::8 12070 # Per bank write bursts
+system.physmem.perBankRdBursts::9 12307 # Per bank write bursts
+system.physmem.perBankRdBursts::10 11595 # Per bank write bursts
+system.physmem.perBankRdBursts::11 10656 # Per bank write bursts
+system.physmem.perBankRdBursts::12 11845 # Per bank write bursts
+system.physmem.perBankRdBursts::13 12839 # Per bank write bursts
+system.physmem.perBankRdBursts::14 12069 # Per bank write bursts
+system.physmem.perBankRdBursts::15 11715 # Per bank write bursts
+system.physmem.perBankWrBursts::0 8801 # Per bank write bursts
+system.physmem.perBankWrBursts::1 9221 # Per bank write bursts
+system.physmem.perBankWrBursts::2 9816 # Per bank write bursts
+system.physmem.perBankWrBursts::3 9124 # Per bank write bursts
+system.physmem.perBankWrBursts::4 8304 # Per bank write bursts
+system.physmem.perBankWrBursts::5 8866 # Per bank write bursts
+system.physmem.perBankWrBursts::6 8953 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8983 # Per bank write bursts
+system.physmem.perBankWrBursts::8 8497 # Per bank write bursts
+system.physmem.perBankWrBursts::9 8715 # Per bank write bursts
+system.physmem.perBankWrBursts::10 8212 # Per bank write bursts
+system.physmem.perBankWrBursts::11 7775 # Per bank write bursts
+system.physmem.perBankWrBursts::12 8513 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8820 # Per bank write bursts
+system.physmem.perBankWrBursts::14 8499 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7905 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 32 # Number of times write queue was full causing retry
-system.physmem.totGap 2649115714000 # Total gap between requests
+system.physmem.numWrRetry 24 # Number of times write queue was full causing retry
+system.physmem.totGap 2848877502000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 554 # Read request sizes (log2)
+system.physmem.readPktSize::2 552 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 199088 # Read request sizes (log2)
+system.physmem.readPktSize::6 200040 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 139900 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 88665 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 60851 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 11657 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 9446 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7750 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 6278 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5185 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 4622 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3733 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 673 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 208 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 138525 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 88667 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 61660 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 11649 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 9417 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7800 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 6275 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5209 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 4659 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 3795 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 680 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 205 # What read queue length does an incoming req see
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@@ -184,162 +184,160 @@ system.physmem.wrQLenPdf::11 1 # Wh
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-system.physmem.bytesPerActivate::mean 231.501767 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 131.710526 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 295.455834 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 51656 54.97% 54.97% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::256-383 6272 6.67% 80.97% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::640-767 1465 1.56% 89.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 883 0.94% 90.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 950 1.01% 91.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8206 8.73% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 93964 # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 29.227952 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 564.671734 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6825 99.99% 99.99% # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::mean 29.782499 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6826 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6826 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.565192 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.817384 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 13.562313 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5689 83.34% 83.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 486 7.12% 90.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 93 1.36% 91.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 54 0.79% 92.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 43 0.63% 93.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 24 0.35% 93.60% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::44-47 8 0.12% 94.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 116 1.70% 96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 16 0.23% 96.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 10 0.15% 96.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 12 0.18% 96.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 73 1.07% 97.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 7 0.10% 97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 4 0.06% 98.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 20 0.29% 98.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 80 1.17% 99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 3 0.04% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.01% 99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 2 0.03% 99.60% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::108-111 1 0.01% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 9 0.13% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.01% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 1 0.01% 99.82% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::152-155 1 0.01% 99.88% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::160-163 2 0.03% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 2 0.03% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6826 # Writes before turning the bus around for reads
-system.physmem.totQLat 5414962245 # Total ticks spent queuing
-system.physmem.totMemAccLat 9155793495 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 997555000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 27141.17 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6731 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6731 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.651315 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.819444 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 13.992190 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::80-83 82 1.22% 99.45% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::total 6731 # Writes before turning the bus around for reads
+system.physmem.totQLat 5345988099 # Total ticks spent queuing
+system.physmem.totMemAccLat 9104763099 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1002340000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 26667.54 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 45891.17 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.82 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.81 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.39 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 45417.54 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.50 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.49 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.22 # Average write queue length when enqueuing
-system.physmem.readRowHits 165357 # Number of row buffer hits during reads
-system.physmem.writeRowHits 80567 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.88 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 57.39 # Row buffer hit rate for writes
-system.physmem.avgGap 7701790.94 # Average gap between requests
-system.physmem.pageHitRate 72.35 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 377130600 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 205775625 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 826254000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 473461200 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 173027368800 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 81211791960 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1518231236250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1774353018435 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.790588 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2525572951341 # Time in different power states
-system.physmem_0.memoryStateTime::REF 88459800000 # Time in different power states
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing
+system.physmem.readRowHits 166512 # Number of row buffer hits during reads
+system.physmem.writeRowHits 80458 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.06 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 57.88 # Row buffer hit rate for writes
+system.physmem.avgGap 8292806.29 # Average gap between requests
+system.physmem.pageHitRate 72.75 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 369525240 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 201625875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 821901600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 467000640 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 186074475600 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 85037796405 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1634728846500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1907701171860 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.633786 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2719381991131 # Time in different power states
+system.physmem_0.memoryStateTime::REF 95130100000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 35083346159 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 34360263869 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 333237240 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 181825875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 729924000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 436188240 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 173027368800 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 79517209320 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1519717712250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1773943465725 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.635988 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2528054644365 # Time in different power states
-system.physmem_1.memoryStateTime::REF 88459800000 # Time in different power states
+system.physmem_1.actEnergy 329782320 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 179940750 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 741741000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 433745280 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 186074475600 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 83868136740 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1635754863750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1907382685440 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.521992 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2721101495830 # Time in different power states
+system.physmem_1.memoryStateTime::REF 95130100000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 32601653135 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 32646289170 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory
@@ -350,30 +348,34 @@ system.realview.nvmem.bytes_inst_read::total 1344
system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 193 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 314 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 507 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 193 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 314 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 507 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 193 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 314 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 507 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 19632721 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 12741106 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 957809 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 12414007 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 8826841 # Number of BTB hits
+system.cpu0.branchPred.lookups 36258885 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 17779541 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1788671 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 20741460 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 11048316 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 71.103883 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 3283973 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 196273 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 53.266819 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 11219024 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 931479 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups 4153759 # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits 3951203 # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses 202556 # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted 105471 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -404,56 +406,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 67362 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 67362 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44747 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22615 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 67362 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 67362 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 67362 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 6703 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 11941.220349 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 10822.969980 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 8452.619900 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767 6653 99.25% 99.25% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535 41 0.61% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839 8 0.12% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 71829 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 71829 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46722 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25107 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 71829 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 71829 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 71829 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 7556 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12351.641080 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11368.840758 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 8528.588507 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767 7496 99.21% 99.21% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535 51 0.67% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839 5 0.07% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375 1 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 6703 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 7556 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5190 77.43% 77.43% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1513 22.57% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 6703 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67362 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 5875 77.75% 77.75% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1681 22.25% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 7556 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71829 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67362 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6703 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71829 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7556 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6703 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 74065 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7556 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 79385 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 16471465 # DTB read hits
-system.cpu0.dtb.read_misses 61259 # DTB read misses
-system.cpu0.dtb.write_hits 13861421 # DTB write hits
-system.cpu0.dtb.write_misses 6103 # DTB write misses
+system.cpu0.dtb.read_hits 24842790 # DTB read hits
+system.cpu0.dtb.read_misses 65179 # DTB read misses
+system.cpu0.dtb.write_hits 18502994 # DTB write hits
+system.cpu0.dtb.write_misses 6650 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1118 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1582 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3814 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1457 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 2027 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 565 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 16532724 # DTB read accesses
-system.cpu0.dtb.write_accesses 13867524 # DTB write accesses
+system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 24907969 # DTB read accesses
+system.cpu0.dtb.write_accesses 18509644 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 30332886 # DTB hits
-system.cpu0.dtb.misses 67362 # DTB misses
-system.cpu0.dtb.accesses 30400248 # DTB accesses
+system.cpu0.dtb.hits 43345784 # DTB hits
+system.cpu0.dtb.misses 71829 # DTB misses
+system.cpu0.dtb.accesses 43417613 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -483,37 +488,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 3870 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 3870 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 303 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3567 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 3870 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 3870 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 3870 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 2416 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12175.289735 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11303.436072 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 5287.236665 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383 2213 91.60% 91.60% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767 183 7.57% 99.17% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151 19 0.79% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 4265 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 4265 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3940 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 4265 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 4265 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 4265 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 2684 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12705.663189 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11959.550432 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 5173.129128 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383 2444 91.06% 91.06% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767 221 8.23% 99.29% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151 17 0.63% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 2416 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 2684 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2118 87.67% 87.67% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 298 12.33% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2416 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 2364 88.08% 88.08% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 320 11.92% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 2684 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3870 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3870 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4265 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4265 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2416 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2416 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 6286 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 36732226 # ITB inst hits
-system.cpu0.itb.inst_misses 3870 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2684 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2684 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 6949 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 71322502 # ITB inst hits
+system.cpu0.itb.inst_misses 4265 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
@@ -522,131 +528,166 @@ system.cpu0.itb.flush_tlb 66 # Nu
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2219 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2459 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 7242 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 7664 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 36736096 # ITB inst accesses
-system.cpu0.itb.hits 36732226 # DTB hits
-system.cpu0.itb.misses 3870 # DTB misses
-system.cpu0.itb.accesses 36736096 # DTB accesses
-system.cpu0.numCycles 162382442 # number of cpu cycles simulated
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+system.cpu0.itb.misses 4265 # DTB misses
+system.cpu0.itb.accesses 71326767 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 75583432 # Number of instructions committed
-system.cpu0.committedOps 90974289 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 5013155 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 2059 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 5135888904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.148387 # CPI: cycles per instruction
-system.cpu0.ipc 0.465466 # IPC: instructions per cycle
+system.cpu0.committedInsts 112829406 # Number of instructions committed
+system.cpu0.committedOps 136421013 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 8883957 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 1865 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 5449058541 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.204424 # CPI: cycles per instruction
+system.cpu0.ipc 0.453633 # IPC: instructions per cycle
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu0.dcache.tags.avg_refs 42.426931 # Average number of references to valid blocks.
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+system.cpu0.dcache.tags.avg_refs 55.087919 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26680.894214 # average StoreCondReq miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::total 15694.801060 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -655,149 +696,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 680701 # number of writebacks
-system.cpu0.dcache.writebacks::total 680701 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 70219 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 70219 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 244921 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 244921 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14844 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14844 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 315140 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 315140 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 315140 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 315140 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 373426 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 373426 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 313850 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 313850 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99342 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 99342 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6089 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6089 # number of LoadLockedReq MSHR misses
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-system.cpu0.dcache.StoreCondReq_mshr_misses::total 21449 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.demand_mshr_misses::total 687276 # number of demand (read+write) MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 786618 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17966 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17966 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16715 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16715 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34681 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34681 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4799499000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4799499000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6708842500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6708842500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1708183000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1708183000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97000000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97000000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 550839500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 550839500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 480000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 480000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11508341500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 11508341500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13216524500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 13216524500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3964655000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3964655000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3079216000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3079216000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7043871000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7043871000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024188 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024188 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023531 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023531 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226894 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226894 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016120 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016120 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057454 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057454 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023883 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.023883 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026926 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.026926 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12852.610691 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12852.610691 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21375.951888 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21375.951888 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17194.972922 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17194.972922 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15930.366234 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15930.366234 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25681.360436 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25681.360436 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 757698 # number of writebacks
+system.cpu0.dcache.writebacks::total 757698 # number of writebacks
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+system.cpu0.dcache.WriteReq_mshr_hits::total 266010 # number of WriteReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14891 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_misses::total 416294 # number of ReadReq MSHR misses
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+system.cpu0.dcache.StoreCondReq_mshr_misses::total 20439 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32042 # number of ReadReq MSHR uncacheable
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+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 641500 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12147316500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017541 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017541 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.229980 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.229980 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016540 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016540 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052217 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052217 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.018093 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020461 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.020461 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12705.089432 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12705.089432 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20824.058968 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20824.058968 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16646.046778 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16646.046778 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.526541 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.526541 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24959.146729 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24959.146729 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16744.861599 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16744.861599 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16801.706165 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16801.706165 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 220675.442503 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220675.442503 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 184218.725695 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184218.725695 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 203104.610594 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 203104.610594 # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16341.669816 # average overall mshr miss latency
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+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16379.909251 # average overall mshr miss latency
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+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.115224 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.115224 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189561.325024 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189561.325024 # average WriteReq mshr uncacheable latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199903.177764 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1875262 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.707229 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 34848846 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1875774 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 18.578382 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6975539000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.707229 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999428 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999428 # Average percentage of cache occupancy
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+system.cpu0.icache.tags.tagsinuse 511.725794 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 69271608 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 2042937 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 33.907853 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 6975620000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.725794 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999464 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999464 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 75325070 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 75325070 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 34848846 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 34848846 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 34848846 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 34848846 # number of demand (read+write) hits
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@@ -806,464 +847,460 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency
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+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5229022000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5229022000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 526020000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6774093500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7300113500 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010369 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11674912500 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12200932500 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009054 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162793 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162793 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.032080 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.209154 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.209154 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192971 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075242 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009588 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.023154 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.032080 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192971 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150478 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150478 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034232 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.188570 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.188570 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072306 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008562 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016410 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034232 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.175382 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.166547 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34227.272727 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 81971.291951 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 81971.291951 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25307.858808 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25307.858808 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18145.521518 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18145.521518 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 200999.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 200999.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56332.256907 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56332.256907 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 59786.314915 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27498.028017 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27498.028017 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35989.317324 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43034.348579 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35989.317324 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 81971.291951 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 64380.460217 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.161933 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 39501.170960 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79624.255077 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26001.258151 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26001.258151 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.547042 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17421.547042 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57646.697534 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57646.697534 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58632.110275 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29121.138899 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29121.138899 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44500.623571 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42141.347424 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18896.907216 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58632.110275 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37595.250453 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79624.255077 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63941.054222 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212665.896694 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198637.092720 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176687.885133 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176687.885133 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201170.042444 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193884.994021 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182043.656872 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182043.656872 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 195325.783570 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 189131.910980 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192129.027746 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188626.571124 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 5267322 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2655927 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 41328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 334158 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 329304 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4854 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 119336 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 2522924 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 16715 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 16715 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 692222 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 2091812 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 222834 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 309300 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 91686 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43805 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 115698 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 274549 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 271267 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1875793 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 569005 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 3104 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5634681 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2479031 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12447 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 171956 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 8298115 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 240318144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 94807159 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20040 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327916 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 335473259 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 1039321 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 3754204 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.107024 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.313298 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests 5755490 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900081 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44333 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 350983 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345970 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5013 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq 141142 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 2764242 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 28724 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 28724 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 743774 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 2294086 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 245615 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 332229 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 86791 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42912 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 113818 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 300259 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 296935 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2042958 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 604813 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 3110 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6136174 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2759564 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14116 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 185351 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 9095205 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261715136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104822354 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23644 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 353660 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 366914794 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 1076546 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 4066304 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.104124 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.309432 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 3357269 89.43% 89.43% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 392081 10.44% 99.87% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 4854 0.13% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 3647917 89.71% 89.71% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 413374 10.17% 99.88% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 5013 0.12% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 3754204 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 5255285493 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 4066304 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 5765624998 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 113846370 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 115477021 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 2820178266 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 3070848423 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1169961199 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1304480252 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 7446481 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 8215479 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 90008437 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 96957457 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 20449244 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 7039055 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 963225 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 10410340 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 7679577 # Number of BTB hits
+system.cpu1.branchPred.lookups 3600044 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 2023819 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 196135 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 2284720 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 1344428 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 73.768743 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 8836366 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 692168 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 58.844322 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 748131 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 53981 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups 144785 # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits 107908 # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses 36877 # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted 17103 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1293,58 +1330,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 30868 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 30868 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 23108 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7760 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 30868 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 30868 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 30868 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 2696 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11992.210682 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10915.827455 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 8355.113227 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383 2479 91.95% 91.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767 196 7.27% 99.22% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151 12 0.45% 99.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.11% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-147455 3 0.11% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::147456-163839 3 0.11% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 2696 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples -1558893032 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -1558893032 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -1558893032 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1974 73.22% 73.22% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 722 26.78% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 2696 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30868 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 22955 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 22955 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18858 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4097 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 22955 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 22955 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 22955 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 1846 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11730.498375 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11025.049339 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 6418.983235 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383 1704 92.31% 92.31% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767 130 7.04% 99.35% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151 9 0.49% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.05% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.05% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 1846 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples -1572230032 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 -1572230032 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total -1572230032 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 1316 71.29% 71.29% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 530 28.71% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 1846 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22955 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30868 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2696 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22955 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1846 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2696 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 33564 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1846 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 24801 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 12117944 # DTB read hits
-system.cpu1.dtb.read_misses 28100 # DTB read misses
-system.cpu1.dtb.write_hits 7719144 # DTB write hits
-system.cpu1.dtb.write_misses 2768 # DTB write misses
+system.cpu1.dtb.read_hits 3573471 # DTB read hits
+system.cpu1.dtb.read_misses 21372 # DTB read misses
+system.cpu1.dtb.write_hits 2968093 # DTB write hits
+system.cpu1.dtb.write_misses 1583 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 330 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 545 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 1717 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 261 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 280 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 12146044 # DTB read accesses
-system.cpu1.dtb.write_accesses 7721912 # DTB write accesses
+system.cpu1.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 3594843 # DTB read accesses
+system.cpu1.dtb.write_accesses 2969676 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 19837088 # DTB hits
-system.cpu1.dtb.misses 30868 # DTB misses
-system.cpu1.dtb.accesses 19867956 # DTB accesses
+system.cpu1.dtb.hits 6541564 # DTB hits
+system.cpu1.dtb.misses 22955 # DTB misses
+system.cpu1.dtb.accesses 6564519 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1374,44 +1411,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 2320 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 2320 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 184 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2136 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 2320 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 2320 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 2320 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12081.032947 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11456.275098 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 4603.593303 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191 188 16.74% 16.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287 645 57.44% 74.18% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383 209 18.61% 92.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.36% 97.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 97.24% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.34% 98.58% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767 3 0.27% 98.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.09% 98.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.89% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples -1559948532 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -1559948532 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total -1559948532 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 953 84.86% 84.86% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 170 15.14% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 2082 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 2082 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 151 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1931 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 2082 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 2082 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 2082 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 843 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11844.009490 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11365.721789 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 4291.658656 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191 129 15.30% 15.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287 559 66.31% 81.61% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383 106 12.57% 94.19% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479 28 3.32% 97.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 97.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671 9 1.07% 98.81% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767 1 0.12% 98.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.24% 99.17% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.59% 99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.12% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 843 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples -1573105532 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 -1573105532 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total -1573105532 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 703 83.39% 83.39% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 140 16.61% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 843 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2320 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2320 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2082 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2082 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 3443 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 41835871 # ITB inst hits
-system.cpu1.itb.inst_misses 2320 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 843 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 843 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 2925 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 6880260 # ITB inst hits
+system.cpu1.itb.inst_misses 2082 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
@@ -1420,130 +1457,165 @@ system.cpu1.itb.flush_tlb 66 # Nu
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 907 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1837 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1103 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 41838191 # ITB inst accesses
-system.cpu1.itb.hits 41835871 # DTB hits
-system.cpu1.itb.misses 2320 # DTB misses
-system.cpu1.itb.accesses 41838191 # DTB accesses
-system.cpu1.numCycles 128464441 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 6882342 # ITB inst accesses
+system.cpu1.itb.hits 6880260 # DTB hits
+system.cpu1.itb.misses 2082 # DTB misses
+system.cpu1.itb.accesses 6882342 # DTB accesses
+system.cpu1.numCycles 40344479 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
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-system.cpu1.numFetchSuspends 2726 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 5169132523 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.476134 # CPI: cycles per instruction
-system.cpu1.ipc 0.403855 # IPC: instructions per cycle
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system.cpu1.kern.inst.arm 0 # number of arm instructions executed
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23244.005715 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23244.005715 # average overall miss latency
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-system.cpu1.dcache.overall_avg_miss_latency::total 21159.247321 # average overall miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 25989.328467 # average overall miss latency
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+system.cpu1.dcache.overall_avg_miss_latency::total 23712.367863 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1552,148 +1624,149 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 234075 # number of writebacks
-system.cpu1.dcache.writebacks::total 234075 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18534 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 18534 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62653 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 62653 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12294 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12294 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 81187 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 81187 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 81187 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 81187 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 168141 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 168141 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106219 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 106219 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33570 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 33570 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5471 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5471 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23562 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23562 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 274360 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 274360 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 307930 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 307930 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17170 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17170 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14450 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14450 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31620 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31620 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2472737500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2472737500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3237291000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3237291000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 585199000 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 585199000 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 99091500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 99091500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 610069500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 610069500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 217500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 217500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5710028500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 5710028500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6295227500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 6295227500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3132437500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3132437500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2631383000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2631383000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5763820500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5763820500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014196 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014196 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014071 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014071 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331206 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331206 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051381 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051381 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226171 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226171 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014147 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.014147 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015796 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.015796 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14706.332780 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14706.332780 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30477.513439 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30477.513439 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17432.201370 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17432.201370 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18112.136721 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18112.136721 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25892.093201 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25892.093201 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 155125 # number of writebacks
+system.cpu1.dcache.writebacks::total 155125 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12753 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 12753 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42136 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 42136 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11686 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11686 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 54889 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 54889 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 54889 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 54889 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 120278 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 120278 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79623 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 79623 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23936 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 23936 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23417 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23417 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 199901 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 199901 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 223837 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 223837 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2973 # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2973 # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2311 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5284 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5284 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1843019500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1843019500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2713747500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2713747500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 448609500 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 448609500 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89247000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89247000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 612539000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 612539000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1094500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1094500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4556767000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4556767000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5005376500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 5005376500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389467000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389467000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 251809500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 251809500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641276500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641276500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035506 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035506 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027923 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027923 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.356796 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.356796 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056135 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056135 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274680 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274680 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032040 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.032040 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035495 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.035495 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15322.997556 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15322.997556 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34082.457330 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34082.457330 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18742.041277 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18742.041277 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18273.341523 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18273.341523 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26157.876756 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26157.876756 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20812.175609 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20812.175609 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20443.696619 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20443.696619 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182436.662784 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182436.662784 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182102.629758 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182102.629758 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182284.013283 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182284.013283 # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22795.118584 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22795.118584 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22361.702936 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22361.702936 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131001.345442 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131001.345442 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108961.272177 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108961.272177 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121361.941711 # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121361.941711 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 1045294 # number of replacements
-system.cpu1.icache.tags.tagsinuse 498.164820 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 40788041 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 1045806 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 39.001537 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 73317918000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.164820 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.972978 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.972978 # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements 856657 # number of replacements
+system.cpu1.icache.tags.tagsinuse 499.135889 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 6021932 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 857169 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 7.025373 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 73312939000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135889 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974875 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.974875 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 84713500 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 84713500 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 40788041 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 40788041 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 40788041 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 40788041 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 40788041 # number of overall hits
-system.cpu1.icache.overall_hits::total 40788041 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 1045806 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 1045806 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 1045806 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 1045806 # number of demand (read+write) misses
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-system.cpu1.icache.overall_misses::total 1045806 # number of overall misses
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system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1702,453 +1775,464 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
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+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14575500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 365633500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 380209000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 234344500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 234344500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14575500 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 599978000 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 614553500 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032323 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.478413 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.478413 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.025777 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.025777 # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.357845 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.357845 # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020552 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.068450 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.025777 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389774 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.100829 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020552 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068450 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.025777 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389774 # mshr miss rate for overall accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.636358 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.636358 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014999 # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.446571 # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.446571 # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.494490 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103624 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026536 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.080791 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014999 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.494490 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.129159 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20693.942614 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46108.401788 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46108.401788 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23150.202570 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23150.202570 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18325.184619 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18325.184619 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45897.697672 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45897.697672 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48734.253283 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 20354.413270 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 20354.413270 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28657.067862 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32532.103899 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28657.067862 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46108.401788 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35510.022313 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174430.984275 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174136.934383 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174593.944637 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 174593.944637 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174505.455408 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174345.046010 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.122054 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15839.048673 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48141.089849 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20158.858671 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20158.858671 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18611.232116 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18611.232116 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500499.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500499.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46505.975598 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46505.975598 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51500.038889 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18067.826079 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18067.826079 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29983.303639 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16493.212670 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14039.419087 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51500.038889 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27308.083789 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48141.089849 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32725.097946 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122984.695594 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123244.408428 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101403.937689 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101403.937689 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130138.392857 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113546.177139 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113890.567087 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 2671947 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1344357 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 22211 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 212012 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 209828 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 60366 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 1353600 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 14450 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 14450 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 179270 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 1143304 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 137947 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 47540 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 74191 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43096 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 82906 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 80697 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1045806 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295809 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 50 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3137130 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1052074 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7597 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 73953 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 4270754 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 133837568 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36094549 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12564 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 141300 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 170085981 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 473244 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1845377 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.133426 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.343498 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests 2128285 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1071677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 177050 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1430 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq 34150 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 1077374 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 2311 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 2311 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 124900 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 917333 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 97527 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 24473 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 71017 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41707 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 84949 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 57470 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 55019 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 857169 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 232907 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 41 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2571219 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 743876 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6996 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 52037 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 3374128 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 109692032 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25376564 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11932 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 99940 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 135180468 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 380471 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1449236 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.140738 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.350577 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 1601339 86.78% 86.78% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 241854 13.11% 99.88% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 2184 0.12% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 1246703 86.02% 86.02% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 201103 13.88% 99.90% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 1430 0.10% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1845377 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 2655073991 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 1449236 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 2091716493 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 86773438 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 78610365 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 1569094564 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 476141581 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 1286047248 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy 331216893 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 4456000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 4013000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 38655445 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 27068966 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 31014 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31014 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59421 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 31009 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31009 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59425 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59425 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
@@ -2161,17 +2245,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
@@ -2184,23 +2268,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2484072 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 51031501 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 48277500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 109500 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 85000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 565500 # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy 577000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 19000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
@@ -2208,13 +2292,13 @@ system.iobus.reqLayer13.occupancy 8500 # La
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 46000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
@@ -2222,54 +2306,54 @@ system.iobus.reqLayer20.occupancy 9500 # La
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6103500 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 6148000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 32838000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 33110001 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187160706 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 187086234 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 84713000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 36462 # number of replacements
-system.iocache.tags.tagsinuse 14.353695 # Cycle average of tags in use
+system.iocache.tags.replacements 36433 # number of replacements
+system.iocache.tags.tagsinuse 14.469289 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 272566004000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 14.353695 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.897106 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.897106 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 272370801000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 14.469289 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.904331 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.904331 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328320 # Number of tag accesses
-system.iocache.tags.data_accesses 328320 # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 256 # number of ReadReq misses
+system.iocache.tags.tag_accesses 328203 # Number of tag accesses
+system.iocache.tags.data_accesses 328203 # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide 256 # number of demand (read+write) misses
-system.iocache.demand_misses::total 256 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide 256 # number of overall misses
-system.iocache.overall_misses::total 256 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 33038877 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 33038877 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4577477829 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4577477829 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 33038877 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 33038877 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 33038877 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 33038877 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
+system.iocache.demand_misses::total 243 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 243 # number of overall misses
+system.iocache.overall_misses::total 243 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 31660877 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 31660877 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 4578259357 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 4578259357 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 31660877 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 31660877 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 31660877 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 31660877 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide 256 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 256 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide 256 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 256 # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
@@ -2278,40 +2362,40 @@ system.iocache.demand_miss_rate::realview.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 129058.113281 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 129058.113281 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126365.885297 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126365.885297 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 129058.113281 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 129058.113281 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 129058.113281 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 129058.113281 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 12 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 130291.674897 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 130291.674897 # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126387.460165 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126387.460165 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 130291.674897 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 130291.674897 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 130291.674897 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 36206 # number of writebacks
-system.iocache.writebacks::total 36206 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks 36190 # number of writebacks
+system.iocache.writebacks::total 36190 # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 256 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 256 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 256 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 20238877 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 20238877 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764566568 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2764566568 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 20238877 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 20238877 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 20238877 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 20238877 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses
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-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137839.784397 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129136.363636 # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126950.549250 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128328.838129 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137229.778184 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121040.090759 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133317.539645 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140684.178928 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129412.500000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122469.112521 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124118.079453 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156673.498705 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 137191.647062 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129136.363636 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133328.864550 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132978.578571 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121040.090759 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133317.539645 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140684.178928 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129412.500000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122469.112521 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124118.079453 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156673.498705 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 137191.647062 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121108.391191 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133328.864550 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140333.580665 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125863.636364 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123255.799619 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123072.534527 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 158336.875857 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 136698.978074 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194664.561616 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156457.826411 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169529.646596 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 159680.317200 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157593.287266 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158712.642484 # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.856719 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105088.889899 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170005.801849 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165038.278199 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84398.529641 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159033.494603 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 177803.408668 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 156976.769048 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 164736.154294 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174598.558569 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109133.928571 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 96034.653475 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 165146.426951 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 39162 # Transaction distribution
-system.membus.trans_dist::ReadResp 215417 # Transaction distribution
-system.membus.trans_dist::WriteReq 31165 # Transaction distribution
-system.membus.trans_dist::WriteResp 31165 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 139900 # Transaction distribution
-system.membus.trans_dist::CleanEvict 18801 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 78213 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 41798 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
-system.membus.trans_dist::ReadExReq 40189 # Transaction distribution
-system.membus.trans_dist::ReadExResp 19404 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 176255 # Transaction distribution
+system.membus.trans_dist::ReadReq 39041 # Transaction distribution
+system.membus.trans_dist::ReadResp 216336 # Transaction distribution
+system.membus.trans_dist::WriteReq 31035 # Transaction distribution
+system.membus.trans_dist::WriteResp 31035 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 138525 # Transaction distribution
+system.membus.trans_dist::CleanEvict 18214 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 73002 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 40704 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 16 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
+system.membus.trans_dist::ReadExReq 39822 # Transaction distribution
+system.membus.trans_dist::ReadExResp 19318 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 177295 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14740 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 671466 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 794158 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72957 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72957 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 867115 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14218 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664863 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 787057 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72915 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72915 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 859972 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19397092 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 19590708 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 21908852 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 125573 # Total snoops (count)
-system.membus.snoop_fanout::samples 601741 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28436 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19371036 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 19563630 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 21880750 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 120342 # Total snoops (count)
+system.membus.snoop_fanout::samples 593889 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 601741 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 593889 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 601741 # Request fanout histogram
-system.membus.reqLayer0.occupancy 91242999 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 593889 # Request fanout histogram
+system.membus.reqLayer0.occupancy 88806999 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 12732000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 12293000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1019564727 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1011120672 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1144074788 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1148583006 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 1412877 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 1341627 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
@@ -2932,52 +3015,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 1069309 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 577929 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 171835 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 21548 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 20404 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 1144 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 39165 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 514340 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 31165 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 31165 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 409596 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 144328 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 114559 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 44999 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 159558 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 51602 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 51602 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 475191 # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests 1040507 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 561217 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 153026 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 21153 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 20199 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 954 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 39044 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 500503 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 404834 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 139205 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 109172 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 43834 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 153006 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 50921 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 50921 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 461474 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1207299 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 435215 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1642514 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34510571 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7361417 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 41871988 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 461244 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 963683 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.359503 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.482323 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1330590 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 273408 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1603998 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36819910 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4347048 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 41166958 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 447482 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 940492 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.338468 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.475327 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 618380 64.17% 64.17% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 344159 35.71% 99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 1144 0.12% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 623120 66.25% 66.25% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 316418 33.64% 99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 954 0.10% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 963683 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 919452336 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 940492 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 900307645 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 640437781 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 690598933 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 288270065 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 213088139 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index 11bd5dafc..cc9440c8e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -1,120 +1,120 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.858536 # Number of seconds simulated
-sim_ticks 2858536032500 # Number of ticks simulated
-final_tick 2858536032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.858505 # Number of seconds simulated
+sim_ticks 2858505242500 # Number of ticks simulated
+final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 177299 # Simulator instruction rate (inst/s)
-host_op_rate 214372 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4522420422 # Simulator tick rate (ticks/s)
-host_mem_usage 585260 # Number of bytes of host memory used
-host_seconds 632.08 # Real time elapsed on the host
-sim_insts 112067614 # Number of instructions simulated
-sim_ops 135500271 # Number of ops (including micro ops) simulated
+host_inst_rate 194204 # Simulator instruction rate (inst/s)
+host_op_rate 234807 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4961098243 # Simulator tick rate (ticks/s)
+host_mem_usage 583728 # Number of bytes of host memory used
+host_seconds 576.18 # Real time elapsed on the host
+sim_insts 111897168 # Number of instructions simulated
+sim_ops 135292215 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 8000 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1708096 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9152172 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9156972 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10869356 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1708096 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1708096 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7939328 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10871852 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1705984 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1705984 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7955328 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7956852 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 125 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 26689 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 143524 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 7972852 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 26656 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 143599 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 170355 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 124052 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 170394 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 124302 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 128433 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 2799 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 597542 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3201699 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 128683 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 2754 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 596810 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3203413 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3802420 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 597542 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 597542 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2777411 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3803335 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 596810 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 596810 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2783038 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6130 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2783541 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2777411 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 2799 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 597542 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3207829 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2789168 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2783038 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 2754 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 596810 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3209543 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6585961 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 170355 # Number of read requests accepted
-system.physmem.writeReqs 128433 # Number of write requests accepted
-system.physmem.readBursts 170355 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 128433 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10894592 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7969344 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10869356 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7956852 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 6592503 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 170394 # Number of read requests accepted
+system.physmem.writeReqs 128683 # Number of write requests accepted
+system.physmem.readBursts 170394 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 128683 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10896320 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7985280 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10871852 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7972852 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10771 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10790 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10898 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10736 # Per bank write bursts
-system.physmem.perBankRdBursts::4 14068 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10207 # Per bank write bursts
-system.physmem.perBankRdBursts::6 11005 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10952 # Per bank write bursts
-system.physmem.perBankRdBursts::8 9928 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10232 # Per bank write bursts
-system.physmem.perBankRdBursts::10 9939 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9163 # Per bank write bursts
-system.physmem.perBankRdBursts::12 10281 # Per bank write bursts
-system.physmem.perBankRdBursts::13 11195 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10251 # Per bank write bursts
-system.physmem.perBankRdBursts::15 9812 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8074 # Per bank write bursts
-system.physmem.perBankWrBursts::1 8145 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8532 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8274 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7651 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7419 # Per bank write bursts
-system.physmem.perBankWrBursts::6 7942 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8023 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7561 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7722 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7504 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7050 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7678 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8296 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7536 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7114 # Per bank write bursts
+system.physmem.perBankRdBursts::0 10648 # Per bank write bursts
+system.physmem.perBankRdBursts::1 11113 # Per bank write bursts
+system.physmem.perBankRdBursts::2 10810 # Per bank write bursts
+system.physmem.perBankRdBursts::3 10613 # Per bank write bursts
+system.physmem.perBankRdBursts::4 13551 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10292 # Per bank write bursts
+system.physmem.perBankRdBursts::6 10857 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10932 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10292 # Per bank write bursts
+system.physmem.perBankRdBursts::9 10622 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10100 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9078 # Per bank write bursts
+system.physmem.perBankRdBursts::12 10356 # Per bank write bursts
+system.physmem.perBankRdBursts::13 10810 # Per bank write bursts
+system.physmem.perBankRdBursts::14 10110 # Per bank write bursts
+system.physmem.perBankRdBursts::15 10071 # Per bank write bursts
+system.physmem.perBankWrBursts::0 7962 # Per bank write bursts
+system.physmem.perBankWrBursts::1 8429 # Per bank write bursts
+system.physmem.perBankWrBursts::2 8465 # Per bank write bursts
+system.physmem.perBankWrBursts::3 8172 # Per bank write bursts
+system.physmem.perBankWrBursts::4 7181 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7509 # Per bank write bursts
+system.physmem.perBankWrBursts::6 7876 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8019 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7862 # Per bank write bursts
+system.physmem.perBankWrBursts::9 8101 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7665 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6948 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7780 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8006 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7432 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7363 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
-system.physmem.totGap 2858535588000 # Total gap between requests
+system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
+system.physmem.totGap 2858504798000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 543 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 169798 # Read request sizes (log2)
+system.physmem.readPktSize::6 169837 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 124052 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 163475 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 6450 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 124302 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 162916 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 7039 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
@@ -159,155 +159,158 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2999 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6966 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6332 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 7132 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6386 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6374 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6606 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7201 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6977 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 7506 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8488 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7586 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 8729 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 7393 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 7050 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 7132 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 1109 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 326 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 234 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 153 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 100 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 137 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 132 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 77 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 61427 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 307.093102 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 182.837118 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 324.066728 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22431 36.52% 36.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 14913 24.28% 60.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6673 10.86% 71.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3644 5.93% 77.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2598 4.23% 81.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2007 3.27% 85.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1018 1.66% 86.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1090 1.77% 88.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7053 11.48% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 61427 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6076 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 28.016458 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 575.560734 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6075 99.98% 99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15 1900 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2986 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 7027 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::35 275 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 145 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 130 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 122 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 109 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 116 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 80 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 103 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 96 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 71 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 61459 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 307.217495 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 182.591879 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 324.526171 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22578 36.74% 36.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 14767 24.03% 60.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6693 10.89% 71.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3646 5.93% 77.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2555 4.16% 81.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2031 3.30% 85.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1005 1.64% 86.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1119 1.82% 88.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7065 11.50% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 61459 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6091 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 27.951896 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 574.936120 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6090 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6076 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.495967 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.543257 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 14.157568 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5370 88.40% 88.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 94 1.55% 89.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 44 0.72% 90.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 49 0.81% 91.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 46 0.76% 92.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 25 0.41% 92.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 47 0.77% 93.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 10 0.16% 93.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 146 2.40% 95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 3 0.05% 96.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 8 0.13% 96.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 10 0.16% 96.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 76 1.25% 97.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 4 0.07% 97.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 5 0.08% 97.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 24 0.40% 98.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 88 1.45% 99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 2 0.03% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 1 0.02% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 8 0.13% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 1 0.02% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 8 0.13% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads
-system.physmem.totQLat 1806632250 # Total ticks spent queuing
-system.physmem.totMemAccLat 4998407250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 851140000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10613.01 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6091 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6090 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.486535 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.508732 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 14.308920 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5400 88.67% 88.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 109 1.79% 90.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 32 0.53% 90.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 43 0.71% 91.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 35 0.57% 92.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 14 0.23% 92.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 47 0.77% 93.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 15 0.25% 93.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 145 2.38% 95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 5 0.08% 95.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 5 0.08% 96.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 14 0.23% 96.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 63 1.03% 97.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 9 0.15% 97.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 5 0.08% 97.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 27 0.44% 98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 95 1.56% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.02% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.02% 99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.02% 99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.02% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 8 0.13% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.02% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 7 0.11% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.02% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 3 0.05% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6090 # Writes before turning the bus around for reads
+system.physmem.totQLat 1821948750 # Total ticks spent queuing
+system.physmem.totMemAccLat 5014230000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 851275000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10701.29 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29363.01 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 29451.29 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.23 # Average write queue length when enqueuing
-system.physmem.readRowHits 139599 # Number of row buffer hits during reads
-system.physmem.writeRowHits 93721 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.01 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes
-system.physmem.avgGap 9567103.06 # Average gap between requests
-system.physmem.pageHitRate 79.15 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 242282880 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 132198000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 697530600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 415063440 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 87013655235 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1638793270500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1913999599215 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.573595 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2726118833250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 95452760000 # Time in different power states
+system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.82 # Average write queue length when enqueuing
+system.physmem.readRowHits 139699 # Number of row buffer hits during reads
+system.physmem.writeRowHits 93863 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.21 # Row buffer hit rate for writes
+system.physmem.avgGap 9557755.35 # Average gap between requests
+system.physmem.pageHitRate 79.16 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 240408000 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 131175000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 692764800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 412173360 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 186703564320 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 86549850225 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1639181430000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1913911365705 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.550023 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2726766742000 # Time in different power states
+system.physmem_0.memoryStateTime::REF 95451720000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 36964415750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 36286757000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 630240000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 391780800 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 85155956550 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1640422830750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1913649653535 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.451174 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2728842952750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 95452760000 # Time in different power states
+system.physmem_1.actEnergy 224214480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 122339250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 635216400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 396290880 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 186703564320 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 85109194890 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1640445162750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1913635982970 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.453685 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2728879759500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 95451720000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 34240173750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 34173617000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory
@@ -327,15 +330,19 @@ system.cf0.dma_read_txs 1 # Nu
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 31018850 # Number of BP lookups
-system.cpu.branchPred.condPredicted 16837096 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2510697 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 18467994 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 13332341 # Number of BTB hits
+system.cpu.branchPred.lookups 30988279 # Number of BP lookups
+system.cpu.branchPred.condPredicted 16810499 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2467893 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 18543680 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 10372624 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 72.191603 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 7836957 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1518082 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 55.936168 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 7863209 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1506080 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 3044381 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 2857246 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 187135 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 108257 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -366,55 +373,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 66340 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 66340 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43350 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22990 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples 66340 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 66340 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 66340 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 7812 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12842.037890 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10664.293591 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 8573.106392 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767 7804 99.90% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 7812 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks 66151 # Table walker walks requested
+system.cpu.dtb.walker.walksShort 66151 # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43510 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22641 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples 66151 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 66151 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 66151 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 7866 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12681.604373 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10478.068683 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 8425.510925 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767 7859 99.91% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-163839 6 0.08% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 7866 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 517922000 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 517922000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 517922000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6422 82.21% 82.21% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1390 17.79% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7812 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66340 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K 6508 82.74% 82.74% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M 1358 17.26% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 7866 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66151 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66340 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7812 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66151 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7866 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7812 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 74152 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7866 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 74017 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 24767530 # DTB read hits
-system.cpu.dtb.read_misses 59359 # DTB read misses
-system.cpu.dtb.write_hits 19448397 # DTB write hits
-system.cpu.dtb.write_misses 6981 # DTB write misses
+system.cpu.dtb.read_hits 24710832 # DTB read hits
+system.cpu.dtb.read_misses 59358 # DTB read misses
+system.cpu.dtb.write_hits 19424403 # DTB write hits
+system.cpu.dtb.write_misses 6793 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4358 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 1306 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 1806 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 1526 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 756 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 24826889 # DTB read accesses
-system.cpu.dtb.write_accesses 19455378 # DTB write accesses
+system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 24770190 # DTB read accesses
+system.cpu.dtb.write_accesses 19431196 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 44215927 # DTB hits
-system.cpu.dtb.misses 66340 # DTB misses
-system.cpu.dtb.accesses 44282267 # DTB accesses
+system.cpu.dtb.hits 44135235 # DTB hits
+system.cpu.dtb.misses 66151 # DTB misses
+system.cpu.dtb.accesses 44201386 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -444,36 +451,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 5454 # Table walker walks requested
-system.cpu.itb.walker.walksShort 5454 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 5133 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 5454 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 5454 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 5454 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 3187 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 13010.982115 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10938.412651 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 7360.815983 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383 2457 77.09% 77.09% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767 729 22.87% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks 5761 # Table walker walks requested
+system.cpu.itb.walker.walksShort 5761 # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 327 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 5434 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples 5761 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 5761 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 5761 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 3206 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12829.694323 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10737.941546 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 7417.860411 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383 2464 76.86% 76.86% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767 741 23.11% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 3187 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 3206 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 517267500 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 517267500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 517267500 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 2877 90.27% 90.27% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 310 9.73% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3187 # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K 2896 90.33% 90.33% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M 310 9.67% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 3206 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5454 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 5454 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5761 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 5761 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3187 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3187 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 8641 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 57568551 # ITB inst hits
-system.cpu.itb.inst_misses 5454 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3206 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3206 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 8967 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 57333922 # ITB inst hits
+system.cpu.itb.inst_misses 5761 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
@@ -482,274 +489,309 @@ system.cpu.itb.flush_tlb 64 # Nu
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2975 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2992 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 8464 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 8365 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 57574005 # ITB inst accesses
-system.cpu.itb.hits 57568551 # DTB hits
-system.cpu.itb.misses 5454 # DTB misses
-system.cpu.itb.accesses 57574005 # DTB accesses
-system.cpu.numCycles 333181944 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 57339683 # ITB inst accesses
+system.cpu.itb.hits 57333922 # DTB hits
+system.cpu.itb.misses 5761 # DTB misses
+system.cpu.itb.accesses 57339683 # DTB accesses
+system.cpu.numCycles 332822103 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 112067614 # Number of instructions committed
-system.cpu.committedOps 135500271 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 7782146 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 5383950822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 2.973044 # CPI: cycles per instruction
-system.cpu.ipc 0.336356 # IPC: instructions per cycle
+system.cpu.committedInsts 111897168 # Number of instructions committed
+system.cpu.committedOps 135292215 # Number of ops (including micro ops) committed
+system.cpu.discardedOps 7734017 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles 5384249089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi 2.974357 # CPI: cycles per instruction
+system.cpu.ipc 0.336207 # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu 90691008 67.03% 67.04% # Class of committed instruction
+system.cpu.op_class_0::IntMult 113025 0.08% 67.12% # Class of committed instruction
+system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatMult 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMult 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdShift 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc 8533 0.01% 67.13% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.13% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.13% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.13% # Class of committed instruction
+system.cpu.op_class_0::MemRead 24225299 17.91% 85.03% # Class of committed instruction
+system.cpu.op_class_0::MemWrite 20252013 14.97% 100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::total 135292215 # Class of committed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
-system.cpu.tickCycles 228532556 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 104649388 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 842951 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.899807 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42615127 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 843463 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 50.524003 # Average number of references to valid blocks.
+system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
+system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 842468 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 42541757 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 842980 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 50.465915 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.899807 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 176233418 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 176233418 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 23069734 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23069734 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18281775 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18281775 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 356571 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 356571 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 443857 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 443857 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 460299 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 460299 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 41351509 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 41351509 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 41708080 # number of overall hits
-system.cpu.dcache.overall_hits::total 41708080 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 494516 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 494516 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 548690 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 548690 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 169778 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 169778 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 22259 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 22259 # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses 175934547 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 175934547 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 23016254 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 23016254 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 18262412 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 18262412 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 356302 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 356302 # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 443705 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 443705 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 460205 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 460205 # number of StoreCondReq hits
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+system.cpu.dcache.demand_hits::total 41278666 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 41634968 # number of overall hits
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+system.cpu.dcache.ReadReq_misses::total 493842 # number of ReadReq misses
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+system.cpu.dcache.WriteReq_misses::total 547981 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 169870 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 169870 # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 22311 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 22311 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 1043206 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1043206 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1212984 # number of overall misses
-system.cpu.dcache.overall_misses::total 1212984 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8031253000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8031253000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 35635370481 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 35635370481 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 293366000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 293366000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 1041823 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1041823 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1211693 # number of overall misses
+system.cpu.dcache.overall_misses::total 1211693 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 8047572500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 8047572500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 35605363979 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 35605363979 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 292635500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 292635500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 43666623481 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 43666623481 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 43666623481 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 43666623481 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23564250 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23564250 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 18830465 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 18830465 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 526349 # number of SoftPFReq accesses(hits+misses)
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@@ -978,189 +1020,189 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68029.497985 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68029.497985 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118120.405780 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118120.405780 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120379.278022 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120379.278022 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122132.052736 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122132.052736 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118139.858244 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118139.858244 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120589.285714 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120589.285714 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122700.989682 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122700.989682 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189161.612592 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181005.330582 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172794.663573 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172794.663573 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189177.171678 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181018.744089 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172855.998260 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172855.998260 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181472.374561 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177380.267939 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181509.325339 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177414.796555 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 7513127 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 3772095 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58799 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 590 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 590 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 7506242 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768367 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 134810 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3579896 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 824175 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 2897049 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 151656 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2785 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 823992 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 2894371 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 151399 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2778 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 296193 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 296193 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897573 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 547535 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2780 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 295731 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 295731 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 2894895 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 547514 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8699695 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2653154 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15282 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161550 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 11529681 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 371094976 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98987561 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18780 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288880 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 470390197 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 192578 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4075586 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.021763 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.145909 # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8691656 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2651684 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16008 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160884 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 11520232 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370751872 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98928925 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19252 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288368 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 469988417 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 192705 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4072528 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.021538 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.145168 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 3986889 97.82% 97.82% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 88697 2.18% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 3984815 97.85% 97.85% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 87713 2.15% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4075586 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 7434078000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 4072528 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 7427836500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 378877 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 4352565871 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 4348460548 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1311717177 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1310984681 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 10589994 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 11196996 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 89368907 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 88824919 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
@@ -1212,59 +1254,59 @@ system.iobus.pkt_size_system.bridge.master::total 159125
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 46502500 # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy 46452000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 104000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 331500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 85500 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 612500 # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6064500 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 6139500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 33518500 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 34107000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187144507 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 187147502 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36424 # number of replacements
-system.iocache.tags.tagsinuse 1.036750 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.037066 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 274891170000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 1.036750 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.064797 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.064797 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 274806935000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 1.037066 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.064817 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.064817 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
@@ -1278,14 +1320,14 @@ system.iocache.demand_misses::realview.ide 234 #
system.iocache.demand_misses::total 234 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 234 # number of overall misses
system.iocache.overall_misses::total 234 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 29054877 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 29054877 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4549676630 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4549676630 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 29054877 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 29054877 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 29054877 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 29054877 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 29059377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 29059377 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 4548977125 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 4548977125 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 29059377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 29059377 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 29059377 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 29059377 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
@@ -1302,14 +1344,14 @@ system.iocache.demand_miss_rate::realview.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124166.141026 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125598.405201 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125598.405201 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124166.141026 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124166.141026 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124185.371795 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124185.371795 # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125579.094661 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125579.094661 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124185.371795 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124185.371795 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1328,14 +1370,14 @@ system.iocache.demand_mshr_misses::realview.ide 234
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 17354877 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 17354877 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737053618 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2737053618 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 17354877 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 17354877 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 17354877 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 17354877 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 17359377 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 17359377 # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736351620 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 2736351620 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 17359377 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 17359377 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 17359377 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 17359377 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
@@ -1344,67 +1386,67 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75559.121522 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75559.121522 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795 # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 34893 # Transaction distribution
-system.membus.trans_dist::ReadResp 72299 # Transaction distribution
-system.membus.trans_dist::WriteReq 27584 # Transaction distribution
-system.membus.trans_dist::WriteResp 27584 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 124052 # Transaction distribution
-system.membus.trans_dist::CleanEvict 8818 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution
+system.membus.trans_dist::ReadReq 34891 # Transaction distribution
+system.membus.trans_dist::ReadResp 72400 # Transaction distribution
+system.membus.trans_dist::WriteReq 27583 # Transaction distribution
+system.membus.trans_dist::WriteResp 27583 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 124302 # Transaction distribution
+system.membus.trans_dist::CleanEvict 8612 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4581 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 129140 # Transaction distribution
-system.membus.trans_dist::ReadExResp 129140 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 37406 # Transaction distribution
+system.membus.trans_dist::ReadExReq 129077 # Transaction distribution
+system.membus.trans_dist::ReadExResp 129077 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 37509 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450778 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558346 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450878 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558440 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 631243 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 631337 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16509088 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16672873 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16527584 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16691357 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 18989993 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 505 # Total snoops (count)
-system.membus.snoop_fanout::samples 402733 # Request fanout histogram
+system.membus.pkt_size::total 19008477 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 506 # Total snoops (count)
+system.membus.snoop_fanout::samples 402790 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 402733 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 402790 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 402733 # Request fanout histogram
-system.membus.reqLayer0.occupancy 87415500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 402790 # Request fanout histogram
+system.membus.reqLayer0.occupancy 87987000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1702000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 878266116 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 879699870 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 990100000 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 990225250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 1264123 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 1263123 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 73084e9c6..c05f0ab9f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,122 +1,122 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.832923 # Number of seconds simulated
-sim_ticks 2832922792000 # Number of ticks simulated
-final_tick 2832922792000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.832863 # Number of seconds simulated
+sim_ticks 2832863135500 # Number of ticks simulated
+final_tick 2832863135500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 64859 # Simulator instruction rate (inst/s)
-host_op_rate 78668 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1624421261 # Simulator tick rate (ticks/s)
-host_mem_usage 564480 # Number of bytes of host memory used
-host_seconds 1743.96 # Real time elapsed on the host
-sim_insts 113110851 # Number of instructions simulated
-sim_ops 137193114 # Number of ops (including micro ops) simulated
+host_inst_rate 89708 # Simulator instruction rate (inst/s)
+host_op_rate 108808 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2246897924 # Simulator tick rate (ticks/s)
+host_mem_usage 584736 # Number of bytes of host memory used
+host_seconds 1260.79 # Real time elapsed on the host
+sim_insts 113102806 # Number of instructions simulated
+sim_ops 137183832 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1316352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9383208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1320448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9385192 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10702440 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1316352 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1316352 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7997632 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10708200 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1320448 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1320448 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8027392 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8015156 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 22815 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 147133 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8044916 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 22879 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 147164 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 169993 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 124963 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 170083 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 125428 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 129344 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 497 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 464662 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3312200 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 129809 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 429 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 466118 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3312971 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3777879 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 464662 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 464662 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2823103 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3779992 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 466118 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 466118 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2833667 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2829289 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2823103 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 497 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 464662 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3318386 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2839853 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2833667 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 429 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 466118 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3319156 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6607168 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 169994 # Number of read requests accepted
-system.physmem.writeReqs 129344 # Number of write requests accepted
-system.physmem.readBursts 169994 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 129344 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10868544 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8027328 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10702504 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8015156 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 6619845 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 170084 # Number of read requests accepted
+system.physmem.writeReqs 129809 # Number of write requests accepted
+system.physmem.readBursts 170084 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 129809 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10877056 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8057984 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10708264 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8044916 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11395 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10614 # Per bank write bursts
-system.physmem.perBankRdBursts::2 11056 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11362 # Per bank write bursts
-system.physmem.perBankRdBursts::4 12761 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10093 # Per bank write bursts
-system.physmem.perBankRdBursts::6 10906 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11082 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10555 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10525 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10031 # Per bank write bursts
-system.physmem.perBankRdBursts::11 8841 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9976 # Per bank write bursts
-system.physmem.perBankRdBursts::13 10659 # Per bank write bursts
-system.physmem.perBankRdBursts::14 9879 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10086 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8598 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7964 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8488 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8679 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7544 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7468 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8076 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8176 # Per bank write bursts
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@@ -159,189 +159,193 @@ system.physmem.wrQLenPdf::11 1 # Wh
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system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
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-system.physmem.totMemAccLat 5323944750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 849105000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12600.33 # Average queueing delay per DRAM burst
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+system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6159 # Writes before turning the bus around for reads
+system.physmem.totQLat 2118470000 # Total ticks spent queuing
+system.physmem.totMemAccLat 5305107500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 849770000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12464.96 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31350.33 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 31214.96 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.83 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.83 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 27.97 # Average write queue length when enqueuing
-system.physmem.readRowHits 139332 # Number of row buffer hits during reads
-system.physmem.writeRowHits 93753 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.73 # Row buffer hit rate for writes
-system.physmem.avgGap 9463959.00 # Average gap between requests
-system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 247869720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 135246375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 696290400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 421154640 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83656164285 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1626368380500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1896557542080 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.471316 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2705472781500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 94597360000 # Time in different power states
+system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing
+system.physmem.readRowHits 139692 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94186 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.19 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.80 # Row buffer hit rate for writes
+system.physmem.avgGap 9446245.51 # Average gap between requests
+system.physmem.pageHitRate 79.05 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 242388720 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 132255750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 687663600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 417033360 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 83434510665 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1626525439500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1896467659275 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.454308 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2705731371250 # Time in different power states
+system.physmem_0.memoryStateTime::REF 94595280000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 32852637000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 32529373750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 628305600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 391612320 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 81913765770 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1627896800250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1896206166975 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.347283 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2708023579500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 94597360000 # Time in different power states
+system.physmem_1.actEnergy 226187640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 123415875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 637969800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 398837520 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 82104234975 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1627692348000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1896211361490 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.363834 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2707689162500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 94595280000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30297375500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30578679500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 46900870 # Number of BP lookups
-system.cpu.branchPred.condPredicted 24033937 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1233884 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 29535620 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 21344859 # Number of BTB hits
+system.cpu.branchPred.lookups 46808005 # Number of BP lookups
+system.cpu.branchPred.condPredicted 23978413 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1175283 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 29454237 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13525326 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 72.268193 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 11734674 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 33890 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 45.919798 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 11724965 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 34889 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 7914908 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 7768670 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 146238 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 60204 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -372,45 +376,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.checker.dtb.walker.walks 9704 # Table walker walks requested
-system.cpu.checker.dtb.walker.walksShort 9704 # Table walker walks initiated with short descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples 9704 # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0 9704 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total 9704 # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walks 9709 # Table walker walks requested
+system.cpu.checker.dtb.walker.walksShort 9709 # Table walker walks initiated with short descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples 9709 # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0 9709 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total 9709 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K 6218 82.47% 82.47% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::1M 1322 17.53% 100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total 7540 # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9704 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkPageSizes::4K 6239 82.69% 82.69% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::1M 1306 17.31% 100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total 7545 # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9709 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9704 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7540 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9709 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7545 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7540 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total 17244 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7545 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total 17254 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 24578942 # DTB read hits
-system.cpu.checker.dtb.read_misses 8287 # DTB read misses
-system.cpu.checker.dtb.write_hits 19634178 # DTB write hits
-system.cpu.checker.dtb.write_misses 1417 # DTB write misses
+system.cpu.checker.dtb.read_hits 24576844 # DTB read hits
+system.cpu.checker.dtb.read_misses 8297 # DTB read misses
+system.cpu.checker.dtb.write_hits 19632942 # DTB write hits
+system.cpu.checker.dtb.write_misses 1412 # DTB write misses
system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 4283 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults 1642 # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 24587229 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 19635595 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 24585141 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 19634354 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 44213120 # DTB hits
-system.cpu.checker.dtb.misses 9704 # DTB misses
-system.cpu.checker.dtb.accesses 44222824 # DTB accesses
+system.cpu.checker.dtb.hits 44209786 # DTB hits
+system.cpu.checker.dtb.misses 9709 # DTB misses
+system.cpu.checker.dtb.accesses 44219495 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -458,7 +462,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits 115809550 # ITB inst hits
+system.cpu.checker.itb.inst_hits 115801229 # ITB inst hits
system.cpu.checker.itb.inst_misses 4825 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
@@ -475,11 +479,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 115814375 # ITB inst accesses
-system.cpu.checker.itb.hits 115809550 # DTB hits
+system.cpu.checker.itb.inst_accesses 115806054 # ITB inst accesses
+system.cpu.checker.itb.hits 115801229 # DTB hits
system.cpu.checker.itb.misses 4825 # DTB misses
-system.cpu.checker.itb.accesses 115814375 # DTB accesses
-system.cpu.checker.numCycles 139043856 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 115806054 # DTB accesses
+system.cpu.checker.numCycles 139034298 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@@ -511,84 +515,79 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 71837 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 71837 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29758 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22348 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 19731 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 52106 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 420.441024 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 2560.543879 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-4095 50336 96.60% 96.60% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::4096-8191 584 1.12% 97.72% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-12287 523 1.00% 98.73% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::12288-16383 337 0.65% 99.37% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-20479 50 0.10% 99.47% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.42% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-28671 15 0.03% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::45056-49151 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 52106 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 17457 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11531.334135 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 9171.811391 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 8140.859549 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767 17274 98.95% 98.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks 72355 # Table walker walks requested
+system.cpu.dtb.walker.walksShort 72355 # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29395 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23194 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore 19766 # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples 52589 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 463.728156 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 2807.068133 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-8191 51286 97.52% 97.52% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-16383 905 1.72% 99.24% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-24575 316 0.60% 99.84% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-32767 38 0.07% 99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-40959 15 0.03% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-49151 23 0.04% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 52589 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 17730 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12604.906937 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10089.659045 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 8394.043940 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767 17507 98.74% 98.74% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535 217 1.22% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 17457 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131387254816 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.617449 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.493362 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1 131332759316 99.96% 99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3 37388500 0.03% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5 6986000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7 6081500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9 1205000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11 646500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13 1379500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15 798500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131387254816 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6345 82.34% 82.34% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1361 17.66% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7706 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71837 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 17730 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131327621316 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean 0.619198 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev 0.492781 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1 131267451816 99.95% 99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3 41041000 0.03% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5 8807000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7 6837500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9 1021000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11 576000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13 1403500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15 474000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 131327621316 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 6380 82.61% 82.61% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M 1343 17.39% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 7723 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72355 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71837 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7706 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72355 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7723 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7706 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 79543 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7723 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 80078 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 25453240 # DTB read hits
-system.cpu.dtb.read_misses 61907 # DTB read misses
-system.cpu.dtb.write_hits 19910032 # DTB write hits
-system.cpu.dtb.write_misses 9930 # DTB write misses
+system.cpu.dtb.read_hits 25411177 # DTB read hits
+system.cpu.dtb.read_misses 62688 # DTB read misses
+system.cpu.dtb.write_hits 19865478 # DTB write hits
+system.cpu.dtb.write_misses 9667 # DTB write misses
system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 357 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch
+system.cpu.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1331 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 25515147 # DTB read accesses
-system.cpu.dtb.write_accesses 19919962 # DTB write accesses
+system.cpu.dtb.perms_faults 1317 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 25473865 # DTB read accesses
+system.cpu.dtb.write_accesses 19875145 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 45363272 # DTB hits
-system.cpu.dtb.misses 71837 # DTB misses
-system.cpu.dtb.accesses 45435109 # DTB accesses
+system.cpu.dtb.hits 45276655 # DTB hits
+system.cpu.dtb.misses 72355 # DTB misses
+system.cpu.dtb.accesses 45349010 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -618,55 +617,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 13224 # Table walker walks requested
-system.cpu.itb.walker.walksShort 13224 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 3935 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 7779 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore 1510 # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples 11714 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean 663.436913 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev 2983.675240 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095 11112 94.86% 94.86% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191 167 1.43% 96.29% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287 192 1.64% 97.93% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383 98 0.84% 98.76% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479 101 0.86% 99.62% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575 31 0.26% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks 12837 # Table walker walks requested
+system.cpu.itb.walker.walksShort 12837 # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 3369 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 7745 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore 1723 # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples 11114 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean 758.457801 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 3142.171422 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095 10521 94.66% 94.66% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191 120 1.08% 95.74% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287 234 2.11% 97.85% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383 132 1.19% 99.04% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479 45 0.40% 99.44% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.87% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 11714 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 4832 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 11551.427980 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 9033.563647 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 8305.140651 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383 3848 79.64% 79.64% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767 915 18.94% 98.57% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151 67 1.39% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::total 11114 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 5038 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12015.680826 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 9674.005789 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 7624.491394 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383 4083 81.04% 81.04% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767 936 18.58% 99.62% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-49151 16 0.32% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 4832 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 24013010416 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean 0.681227 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev 0.466165 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 7656484500 31.88% 31.88% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1 16354802916 68.11% 99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2 1665500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 24013010416 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 3004 90.43% 90.43% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 318 9.57% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated
+system.cpu.itb.walker.walkCompletionTime::total 5038 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 23953376916 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean 0.632532 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev 0.482296 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 8804085500 36.76% 36.76% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1 15147384416 63.24% 99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2 1819000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 23953376916 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 2980 89.89% 89.89% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M 335 10.11% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 3315 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 13224 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 13224 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12837 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 12837 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 16546 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 66215474 # ITB inst hits
-system.cpu.itb.inst_misses 13224 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3315 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3315 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 16152 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 65992511 # ITB inst hits
+system.cpu.itb.inst_misses 12837 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
@@ -675,98 +677,98 @@ system.cpu.itb.flush_tlb 128 # Nu
system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 3093 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 3079 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2222 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2160 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 66228698 # ITB inst accesses
-system.cpu.itb.hits 66215474 # DTB hits
-system.cpu.itb.misses 13224 # DTB misses
-system.cpu.itb.accesses 66228698 # DTB accesses
-system.cpu.numCycles 278849039 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 66005348 # ITB inst accesses
+system.cpu.itb.hits 65992511 # DTB hits
+system.cpu.itb.misses 12837 # DTB misses
+system.cpu.itb.accesses 66005348 # DTB accesses
+system.cpu.numCycles 278422079 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 104825039 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 184547548 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 46900870 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 33079533 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 161783291 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6174948 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 189837 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 10053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 357428 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 560111 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 66214357 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1060583 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6520 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 270813408 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.831546 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.217852 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 104965644 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 184047232 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 46808005 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33018961 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 161470061 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6057656 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 190492 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 8321 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 345001 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 554797 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 65991288 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1042618 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6254 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 270563337 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.829471 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.217030 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 171553183 63.35% 63.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 29255757 10.80% 74.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 14075334 5.20% 79.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 55929134 20.65% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 171642539 63.44% 63.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 29152189 10.77% 74.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 14033587 5.19% 79.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 55735022 20.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 270813408 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.168194 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.661819 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 77914241 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 121818980 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 64632452 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3838198 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2609537 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3423128 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 486335 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 157406934 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3698656 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2609537 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 83756930 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 11780773 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 76597873 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 62631659 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 33436636 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 146755972 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 956855 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 452398 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 63697 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 16353 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 30702971 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 150428298 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 678515900 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 164385434 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 141750240 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 8678055 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2842275 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2646130 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13851175 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26402053 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 21296304 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1688639 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2128632 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 143481450 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2121615 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 143268725 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 270645 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8409947 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14700028 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 125764 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 270813408 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.529031 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.865143 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 270563337 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.168119 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.661037 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 77947938 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 121878006 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 64302075 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3866348 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2568970 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3407378 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 467954 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 156978056 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3511118 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2568970 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 83705242 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 11815574 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 76555831 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 62411209 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 33506511 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 146428655 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 918489 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 467718 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 65503 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 18531 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 30749318 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 150222579 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 676982359 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 163959933 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 10887 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 141740582 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 8481991 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2839527 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2643996 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13883864 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 26339284 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 21214862 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1704584 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2138851 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 143220356 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2117775 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 143040703 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 261102 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 8154295 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14292577 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 121903 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 270563337 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.528677 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.865235 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 182463558 67.38% 67.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 45313359 16.73% 84.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 31963465 11.80% 95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 10263701 3.79% 99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 809292 0.30% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 182376042 67.41% 67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 45230245 16.72% 84.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 31877858 11.78% 95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 10262059 3.79% 99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 817100 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
@@ -774,160 +776,160 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 270813408 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 270563337 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.fu_full::IntMult 32 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5631471 25.13% 57.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 9448597 42.16% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 7341205 32.76% 32.76% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5622623 25.09% 57.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 9446888 42.15% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 95958706 66.98% 66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 113835 0.08% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 26183625 18.28% 85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21001646 14.66% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 95846012 67.01% 67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 114315 0.08% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 8579 0.01% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26129650 18.27% 85.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 20939810 14.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 143268725 # Type of FU issued
-system.cpu.iq.rate 0.513786 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 22412202 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.156435 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 579998115 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 154018366 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 140157777 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 35590 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 165655240 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 23350 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 322841 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 143040703 # Type of FU issued
+system.cpu.iq.rate 0.513755 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 22410748 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.156674 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 579280960 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 153497939 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 139990284 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 35633 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 11369 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 165425721 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 23393 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 323902 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1496212 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 510 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18521 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 704329 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1435157 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 717 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18681 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 624055 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 88213 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 6464 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 88621 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 6303 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2609537 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1244131 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 534453 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 145804019 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 2568970 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1238473 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 546153 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 145518660 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26402053 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 21296304 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1096200 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 17993 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 500261 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18521 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 317950 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 471174 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 789124 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 142326073 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25781011 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 870919 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 26339284 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 21214862 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1094251 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 17896 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 509714 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18681 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 277446 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 471378 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 748824 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 142140939 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25734314 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 827514 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 200954 # number of nop insts executed
-system.cpu.iew.exec_refs 46653702 # number of memory reference insts executed
-system.cpu.iew.exec_branches 26511824 # Number of branches executed
-system.cpu.iew.exec_stores 20872691 # Number of stores executed
-system.cpu.iew.exec_rate 0.510405 # Inst execution rate
-system.cpu.iew.wb_sent 141939572 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 140169144 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 63244057 # num instructions producing a value
-system.cpu.iew.wb_consumers 95727511 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.502670 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.660668 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 7609153 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1995851 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 755947 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 267866819 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.512747 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.116675 # Number of insts commited each cycle
+system.cpu.iew.exec_nop 180529 # number of nop insts executed
+system.cpu.iew.exec_refs 46562087 # number of memory reference insts executed
+system.cpu.iew.exec_branches 26490837 # Number of branches executed
+system.cpu.iew.exec_stores 20827773 # Number of stores executed
+system.cpu.iew.exec_rate 0.510523 # Inst execution rate
+system.cpu.iew.wb_sent 141772110 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 140001653 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 63237844 # num instructions producing a value
+system.cpu.iew.wb_consumers 95709593 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.502840 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.660726 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 7370888 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1995872 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 715425 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 267671554 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.513087 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.118264 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 194366787 72.56% 72.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 43325916 16.17% 88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 15476786 5.78% 94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 4394475 1.64% 96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 6423634 2.40% 98.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1609805 0.60% 99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 801244 0.30% 99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 411295 0.15% 99.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1056877 0.39% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 194234773 72.56% 72.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 43288369 16.17% 88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 15457266 5.77% 94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 4372596 1.63% 96.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 6412647 2.40% 98.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1623966 0.61% 99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 797879 0.30% 99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 412108 0.15% 99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1071950 0.40% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 267866819 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 113265756 # Number of instructions committed
-system.cpu.commit.committedOps 137348019 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 267671554 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 113257711 # Number of instructions committed
+system.cpu.commit.committedOps 137338737 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 45497816 # Number of memory references committed
-system.cpu.commit.loads 24905841 # Number of loads committed
-system.cpu.commit.membars 814912 # Number of memory barriers committed
-system.cpu.commit.branches 26026635 # Number of branches committed
+system.cpu.commit.refs 45494934 # Number of memory references committed
+system.cpu.commit.loads 24904127 # Number of loads committed
+system.cpu.commit.membars 814876 # Number of memory barriers committed
+system.cpu.commit.branches 26024432 # Number of branches committed
system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 120174652 # Number of committed integer instructions.
-system.cpu.commit.function_calls 4885050 # Number of function calls committed.
+system.cpu.commit.int_insts 120166310 # Number of committed integer instructions.
+system.cpu.commit.function_calls 4884393 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 91728853 66.79% 66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 112775 0.08% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 91722407 66.79% 66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 112817 0.08% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
@@ -951,507 +953,507 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% #
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 24905841 18.13% 85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 20591975 14.99% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 24904127 18.13% 85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 20590807 14.99% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 137348019 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1056877 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 389577087 # The number of ROB reads
-system.cpu.rob.rob_writes 292847921 # The number of ROB writes
-system.cpu.timesIdled 893517 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 8035631 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 5386996546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 113110851 # Number of Instructions Simulated
-system.cpu.committedOps 137193114 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.465272 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.465272 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.405635 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.405635 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 155766897 # number of integer regfile reads
-system.cpu.int_regfile_writes 88591583 # number of integer regfile writes
-system.cpu.fp_regfile_reads 9527 # number of floating regfile reads
+system.cpu.commit.op_class_0::total 137338737 # Class of committed instruction
+system.cpu.commit.bw_lim_events 1071950 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 389122780 # The number of ROB reads
+system.cpu.rob.rob_writes 292297911 # The number of ROB writes
+system.cpu.timesIdled 890833 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7858742 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 5387304193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 113102806 # Number of Instructions Simulated
+system.cpu.committedOps 137183832 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 2.461673 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.461673 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.406228 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.406228 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 155527774 # number of integer regfile reads
+system.cpu.int_regfile_writes 88490356 # number of integer regfile writes
+system.cpu.fp_regfile_reads 9528 # number of floating regfile reads
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
-system.cpu.cc_regfile_reads 502787810 # number of cc regfile reads
-system.cpu.cc_regfile_writes 53167573 # number of cc regfile writes
-system.cpu.misc_regfile_reads 348401646 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1521641 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 837383 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.925650 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 40103246 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 837895 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 47.861899 # Average number of references to valid blocks.
+system.cpu.cc_regfile_reads 502164459 # number of cc regfile reads
+system.cpu.cc_regfile_writes 53130606 # number of cc regfile writes
+system.cpu.misc_regfile_reads 347857043 # number of misc regfile reads
+system.cpu.misc_regfile_writes 1521711 # number of misc regfile writes
+system.cpu.dcache.tags.replacements 838824 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 40057266 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 839336 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 47.724947 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.925650 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 179305026 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 179305026 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 23303846 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23303846 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 15548555 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 15548555 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 345967 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 345967 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 441680 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 441680 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 460325 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 460325 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 38852401 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 38852401 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 39198368 # number of overall hits
-system.cpu.dcache.overall_hits::total 39198368 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 708722 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 708722 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3602695 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3602695 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 177881 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 177881 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 27099 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 27099 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 4311417 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4311417 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4489298 # number of overall misses
-system.cpu.dcache.overall_misses::total 4489298 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11727702000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11727702000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 232357594183 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 232357594183 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 372629000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 372629000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 302000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 302000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 244085296183 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 244085296183 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 244085296183 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 244085296183 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24012568 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24012568 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19151250 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.LoadLockedReq_accesses::total 468779 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu.dcache.overall_accesses::total 43687666 # number of overall (read+write) accesses
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-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000015 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.099885 # miss rate for demand accesses
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-system.cpu.dcache.overall_miss_rate::total 0.102759 # miss rate for overall accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.675958 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64495.494118 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64495.494118 # average WriteReq miss latency
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13750.655006 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43142.857143 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43142.857143 # average StoreCondReq miss latency
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-system.cpu.dcache.blocked_cycles::no_mshrs 871935 # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses 179127418 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 179127418 # Number of data accesses
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 695453 # number of writebacks
-system.cpu.dcache.writebacks::total 695453 # number of writebacks
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-system.cpu.dcache.ReadReq_mshr_hits::total 295641 # number of ReadReq MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses::total 413081 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
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-system.cpu.dcache.overall_mshr_uncacheable_latency::total 11351823951 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017203 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017203 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015643 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017906 # mshr miss rate for LoadLockedReq accesses
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15468.935875 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15468.935875 # average ReadReq mshr miss latency
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-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14231.290498 # average SoftPFReq mshr miss latency
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-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15061.651179 # average LoadLockedReq mshr miss latency
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-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201635.629156 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 183980.730506 # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183980.730506 # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193341.008124 # average overall mshr uncacheable latency
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-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010503 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024640 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024640 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000403 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000673 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177492 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.060383 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000403 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000673 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010503 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177492 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.060383 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132533.333333 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.760382 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.760382 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119985.985450 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119985.985450 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122650.388508 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122650.388508 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125393.240303 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125393.240303 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122650.388508 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120470.596541 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120729.053964 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136113.636364 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122687.500000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122650.388508 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120470.596541 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120729.053964 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189135.372161 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182454.281780 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172423.001631 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172423.001631 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181283.569506 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177970.778379 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61717 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2442000 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3178000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 184658000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 184658000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 211500 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 211500 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16248351500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16248351500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2434936503 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2434936503 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1655244000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1655244000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2442000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 736000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2434936503 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17903595500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 20341710003 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2442000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 736000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2434936503 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17903595500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 20341710003 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340067500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887116000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227183500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756897000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756897000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340067500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644013000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984080500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000356 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.979437 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.979437 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455860 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455860 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010540 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010540 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024422 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024422 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010540 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177221 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.060318 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010540 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177221 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.060318 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122666.666667 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127120 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.996317 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.996317 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119902.529647 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119902.529647 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122444.760284 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122444.760284 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125027.872196 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125027.872196 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122666.666667 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122444.760284 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120358.687614 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120605.645595 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122666.666667 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122444.760284 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120358.687614 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120605.645595 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.984580 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.143326 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172445.060721 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172445.060721 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181285.775113 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177974.958277 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 5483800 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47116 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 5483816 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757778 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 128080 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2556548 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2557705 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 820436 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1886845 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 149868 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 296964 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 296964 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887380 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 541203 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5667569 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2636305 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31377 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129075 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8464326 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241595648 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98327529 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47536 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218484 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 340189197 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 196985 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3053089 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.025893 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.158816 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty 822252 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 1886159 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 149793 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2772 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2777 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 297269 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 297269 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1886711 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 542312 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5665508 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2640654 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30972 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133892 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8471026 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241506672 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98506345 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48452 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 232436 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 340293905 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 194298 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3054873 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.024677 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.155138 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2974035 97.41% 97.41% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 79054 2.59% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 2979489 97.53% 97.53% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 75384 2.47% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3053089 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5400068497 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 3054873 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5401857499 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 2834904825 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 2834033066 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1303398559 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1305567557 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 19499986 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 18867982 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 74506395 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 75841383 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
+system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
@@ -1668,9 +1670,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
@@ -1691,24 +1693,24 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 43092000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks)
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system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 654000 # Layer occupancy (ticks)
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system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
@@ -1716,179 +1718,177 @@ system.iobus.reqLayer14.occupancy 9000 # La
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks)
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system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6200500 # Layer occupancy (ticks)
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system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
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system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
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system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
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system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
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system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
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+system.iocache.overall_avg_mshr_miss_latency::realview.ide 76259.538117 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76259.538117 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 34133 # Transaction distribution
-system.membus.trans_dist::ReadResp 67562 # Transaction distribution
+system.membus.trans_dist::ReadReq 34132 # Transaction distribution
+system.membus.trans_dist::ReadResp 67504 # Transaction distribution
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.trans_dist::WriteResp 27585 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 124963 # Transaction distribution
-system.membus.trans_dist::CleanEvict 7938 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 125428 # Transaction distribution
+system.membus.trans_dist::CleanEvict 7780 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4584 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 133523 # Transaction distribution
-system.membus.trans_dist::ReadExResp 133523 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 33430 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution
+system.membus.trans_dist::ReadExReq 133644 # Transaction distribution
+system.membus.trans_dist::ReadExResp 133644 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 33373 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450084 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557654 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 630522 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450558 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558126 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 631001 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16402396 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565801 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 18881001 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 513 # Total snoops (count)
-system.membus.snoop_fanout::samples 402383 # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16435996 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16599385 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 18916505 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 487 # Total snoops (count)
+system.membus.snoop_fanout::samples 402766 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 402383 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 402766 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 402383 # Request fanout histogram
-system.membus.reqLayer0.occupancy 83620000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 402766 # Request fanout histogram
+system.membus.reqLayer0.occupancy 83667000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1740000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 873794635 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 876048370 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 978214250 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 978678250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 1313623 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 3b8090468..1d7221486 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,166 +1,166 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.837475 # Number of seconds simulated
-sim_ticks 2837474672000 # Number of ticks simulated
-final_tick 2837474672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.827390 # Number of seconds simulated
+sim_ticks 2827390179000 # Number of ticks simulated
+final_tick 2827390179000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 80224 # Simulator instruction rate (inst/s)
-host_op_rate 97291 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1891605778 # Simulator tick rate (ticks/s)
-host_mem_usage 603308 # Number of bytes of host memory used
-host_seconds 1500.04 # Real time elapsed on the host
-sim_insts 120338385 # Number of instructions simulated
-sim_ops 145939190 # Number of ops (including micro ops) simulated
+host_inst_rate 115301 # Simulator instruction rate (inst/s)
+host_op_rate 139868 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2711751203 # Simulator tick rate (ticks/s)
+host_mem_usage 622004 # Number of bytes of host memory used
+host_seconds 1042.64 # Real time elapsed on the host
+sim_insts 120217407 # Number of instructions simulated
+sim_ops 145833000 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1300544 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1269544 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8448640 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1297536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1327400 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8611392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 171296 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 573268 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 376832 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 181424 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 629012 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 447552 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12143260 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1300544 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 171296 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1471840 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8572864 # Number of bytes written to this memory
+system.physmem.bytes_read::total 12497708 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1297536 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 181424 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1478960 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8852800 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8590428 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8870364 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 22568 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 20357 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 132010 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 22521 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 21261 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 134553 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2744 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8978 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 5888 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2903 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 9849 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 6993 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 192594 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 133951 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 198133 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 138325 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 138342 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 142716 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 634 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 458346 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 447420 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 2977521 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 68 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 458916 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 469479 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 3045703 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 60369 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 202035 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 132805 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4279601 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 458346 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 60369 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 518715 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3021301 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6176 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 64167 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 222471 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 158292 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4420228 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 458916 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 64167 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 523083 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3131085 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6198 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3027491 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3021301 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 3137297 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3131085 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 634 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 458346 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 453596 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 2977521 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 458916 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 475677 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 3045703 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 60369 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 202049 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 132805 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7307092 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 192595 # Number of read requests accepted
-system.physmem.writeReqs 138342 # Number of write requests accepted
-system.physmem.readBursts 192595 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 138342 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12315840 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8603136 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 12143324 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8590428 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu1.inst 64167 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 222485 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 158292 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7557525 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 198134 # Number of read requests accepted
+system.physmem.writeReqs 142716 # Number of write requests accepted
+system.physmem.readBursts 198134 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 142716 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 12670976 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8883264 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 12497772 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8870364 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11930 # Per bank write bursts
-system.physmem.perBankRdBursts::1 11054 # Per bank write bursts
-system.physmem.perBankRdBursts::2 12038 # Per bank write bursts
-system.physmem.perBankRdBursts::3 12107 # Per bank write bursts
-system.physmem.perBankRdBursts::4 14171 # Per bank write bursts
-system.physmem.perBankRdBursts::5 12096 # Per bank write bursts
-system.physmem.perBankRdBursts::6 12498 # Per bank write bursts
-system.physmem.perBankRdBursts::7 12306 # Per bank write bursts
-system.physmem.perBankRdBursts::8 12126 # Per bank write bursts
-system.physmem.perBankRdBursts::9 12003 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11820 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10972 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11787 # Per bank write bursts
-system.physmem.perBankRdBursts::13 12524 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11749 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11254 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8457 # Per bank write bursts
-system.physmem.perBankWrBursts::1 8003 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8794 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8731 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8108 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8557 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8913 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8687 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8491 # Per bank write bursts
-system.physmem.perBankWrBursts::9 8422 # Per bank write bursts
-system.physmem.perBankWrBursts::10 8472 # Per bank write bursts
-system.physmem.perBankWrBursts::11 8088 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8500 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8546 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8126 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7529 # Per bank write bursts
+system.physmem.perBankRdBursts::0 12497 # Per bank write bursts
+system.physmem.perBankRdBursts::1 12182 # Per bank write bursts
+system.physmem.perBankRdBursts::2 12917 # Per bank write bursts
+system.physmem.perBankRdBursts::3 12745 # Per bank write bursts
+system.physmem.perBankRdBursts::4 14769 # Per bank write bursts
+system.physmem.perBankRdBursts::5 12267 # Per bank write bursts
+system.physmem.perBankRdBursts::6 12449 # Per bank write bursts
+system.physmem.perBankRdBursts::7 12406 # Per bank write bursts
+system.physmem.perBankRdBursts::8 12316 # Per bank write bursts
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@@ -188,198 +188,201 @@ system.physmem.wrQLenPdf::11 1 # Wh
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+system.physmem.wrPerTurnAround::60-63 15 0.22% 96.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 76 1.13% 97.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 5 0.07% 97.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 5 0.07% 97.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 30 0.45% 98.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 72 1.07% 99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 5 0.07% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.01% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 3 0.04% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.01% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.01% 99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 1 0.01% 99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 1 0.01% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 7 0.10% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 2 0.03% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 3 0.04% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 6 0.09% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 3 0.04% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6724 # Writes before turning the bus around for reads
+system.physmem.totQLat 6642491804 # Total ticks spent queuing
+system.physmem.totMemAccLat 10354691804 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 989920000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 33550.65 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 51293.66 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.34 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.03 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.28 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.03 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 52300.65 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.14 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.14 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
+system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.64 # Average write queue length when enqueuing
-system.physmem.readRowHits 160629 # Number of row buffer hits during reads
-system.physmem.writeRowHits 79430 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 28.40 # Average write queue length when enqueuing
+system.physmem.readRowHits 165266 # Number of row buffer hits during reads
+system.physmem.writeRowHits 80705 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 59.08 # Row buffer hit rate for writes
-system.physmem.avgGap 8574062.15 # Average gap between requests
-system.physmem.pageHitRate 73.44 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 333396000 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 181912500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 765952200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 442260000 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 185329943760 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 80518312575 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1631853855750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1899425632785 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.407413 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2714633882248 # Time in different power states
-system.physmem_0.memoryStateTime::REF 94749460000 # Time in different power states
+system.physmem.writeRowHitRate 58.14 # Row buffer hit rate for writes
+system.physmem.avgGap 8295114.90 # Average gap between requests
+system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 356771520 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 194667000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 797401800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 463449600 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 184671358560 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 80516584620 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1625805455250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1892805688350 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.453328 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2704566595208 # Time in different power states
+system.physmem_0.memoryStateTime::REF 94412760000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 28091326752 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 28410820792 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 322804440 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 176133375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 735033000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 428807520 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 185329943760 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 80062823295 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1632253407750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1899308953140 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.366292 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2715300909163 # Time in different power states
-system.physmem_1.memoryStateTime::REF 94749460000 # Time in different power states
+system.physmem_1.actEnergy 329774760 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 179936625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 746865600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 435980880 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 184671358560 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 80145816435 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1626130690500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1892640423360 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.394877 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2705113148361 # Time in different power states
+system.physmem_1.memoryStateTime::REF 94412760000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 27422902087 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 27864169139 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 112 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 176 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 288 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 11 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 18 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 40 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 62 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 102 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 40 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 62 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 102 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 53970528 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 25026545 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1030924 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 32677551 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 24281541 # Number of BTB hits
+system.cpu0.branchPred.lookups 53911245 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 24947324 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 985007 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 32642222 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 14256732 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 74.306489 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 15568765 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 33847 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 43.675740 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 15584760 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 34685 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups 10159968 # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits 9991718 # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses 168250 # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted 52822 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -410,89 +413,87 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 71872 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 71872 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26693 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21064 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 24115 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 47757 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 506.909982 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 3155.228311 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191 46441 97.24% 97.24% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383 936 1.96% 99.20% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575 182 0.38% 99.59% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767 156 0.33% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-40959 14 0.03% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks 71875 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 71875 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26071 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21701 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 24103 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 47772 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 520.796701 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 3158.268863 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191 46423 97.18% 97.18% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383 981 2.05% 99.23% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575 165 0.35% 99.58% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767 156 0.33% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.04% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151 25 0.05% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 47757 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 18781 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 11082.663330 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 9588.241676 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 7811.113486 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767 18652 99.31% 99.31% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535 107 0.57% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839 11 0.06% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.05% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 18781 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 75809851172 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.731325 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.459247 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 20539595904 27.09% 27.09% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 55205651768 72.82% 99.91% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2 30292500 0.04% 99.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::3 15753500 0.02% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4 4835000 0.01% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::5 2801000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6 4041000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::7 1434000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8 1051000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::9 726000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10 722500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::11 355500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12 1232500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::13 309000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14 147500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::15 902500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 75809851172 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5808 79.13% 79.13% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1532 20.87% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 7340 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71872 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::total 47772 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 18721 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 11203.514770 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 9623.609798 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 9038.861696 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767 18593 99.32% 99.32% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535 88 0.47% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.12% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607 16 0.09% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 18721 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 87200107652 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 0.546732 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev 0.508218 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 39687331700 45.51% 45.51% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 47447148952 54.41% 99.92% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2 30000500 0.03% 99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::3 16923500 0.02% 99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4 5972000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::5 3342500 0.00% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6 3974500 0.00% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::7 1269500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8 992000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::9 652500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10 669000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::11 287500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12 887500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::13 113500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14 101000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::15 441500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 87200107652 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 5974 77.64% 77.64% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1720 22.36% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 7694 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71875 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71872 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7340 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71875 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7694 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7340 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 79212 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7694 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 79569 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 24452865 # DTB read hits
-system.cpu0.dtb.read_misses 61042 # DTB read misses
-system.cpu0.dtb.write_hits 18137868 # DTB write hits
-system.cpu0.dtb.write_misses 10830 # DTB write misses
+system.cpu0.dtb.read_hits 24391036 # DTB read hits
+system.cpu0.dtb.read_misses 61424 # DTB read misses
+system.cpu0.dtb.write_hits 18141184 # DTB write hits
+system.cpu0.dtb.write_misses 10451 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3798 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 179 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 2460 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3871 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 259 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 2351 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 1027 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 24513907 # DTB read accesses
-system.cpu0.dtb.write_accesses 18148698 # DTB write accesses
+system.cpu0.dtb.perms_faults 984 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 24452460 # DTB read accesses
+system.cpu0.dtb.write_accesses 18151635 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 42590733 # DTB hits
-system.cpu0.dtb.misses 71872 # DTB misses
-system.cpu0.dtb.accesses 42662605 # DTB accesses
+system.cpu0.dtb.hits 42532220 # DTB hits
+system.cpu0.dtb.misses 71875 # DTB misses
+system.cpu0.dtb.accesses 42604095 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -522,56 +523,55 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 11904 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 11904 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4233 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6584 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 1087 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 10817 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 600.397522 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 2698.053078 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095 10265 94.90% 94.90% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191 149 1.38% 96.27% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287 271 2.51% 98.78% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383 75 0.69% 99.47% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479 17 0.16% 99.63% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575 19 0.18% 99.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671 9 0.08% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 10817 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 3962 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12538.112065 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11491.228550 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 5924.134206 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383 3642 91.92% 91.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767 274 6.92% 98.84% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151 42 1.06% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535 3 0.08% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 3962 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 19975198824 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.751864 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.432117 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 4958102500 24.82% 24.82% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 15015628824 75.17% 99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 1397500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 19975198824 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2530 88.00% 88.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 345 12.00% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2875 # Table walker page sizes translated
+system.cpu0.itb.walker.walks 11562 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 11562 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4001 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6396 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore 1165 # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples 10397 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean 461.575454 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 2367.707906 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-4095 9981 96.00% 96.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-8191 185 1.78% 97.78% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-12287 127 1.22% 99.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-16383 59 0.57% 99.57% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-20479 11 0.11% 99.67% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-24575 23 0.22% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::28672-32767 2 0.02% 99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-36863 4 0.04% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::36864-40959 3 0.03% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 10397 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 4031 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 11997.147110 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11095.550949 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 5265.028524 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383 3778 93.72% 93.72% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767 218 5.41% 99.13% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151 33 0.82% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 4031 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 22774753212 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 0.815515 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev 0.388020 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 4202728000 18.45% 18.45% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 18570993712 81.54% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2 925000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3 106500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 22774753212 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 2507 87.47% 87.47% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 359 12.53% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 2866 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11904 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11904 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11562 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11562 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2875 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2875 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 14779 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 74216434 # ITB inst hits
-system.cpu0.itb.inst_misses 11904 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2866 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2866 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 14428 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 74050785 # ITB inst hits
+system.cpu0.itb.inst_misses 11562 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
@@ -580,1038 +580,1041 @@ system.cpu0.itb.flush_tlb 66 # Nu
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2616 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2601 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 2203 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 74228338 # ITB inst accesses
-system.cpu0.itb.hits 74216434 # DTB hits
-system.cpu0.itb.misses 11904 # DTB misses
-system.cpu0.itb.accesses 74228338 # DTB accesses
-system.cpu0.numCycles 211032659 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 74062347 # ITB inst accesses
+system.cpu0.itb.hits 74050785 # DTB hits
+system.cpu0.itb.misses 11562 # DTB misses
+system.cpu0.itb.accesses 74062347 # DTB accesses
+system.cpu0.numCycles 210807967 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 21140186 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 200489800 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 53970528 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 39850306 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 180538670 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 5902720 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 164381 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 72575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 387139 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 466386 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 108060 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 74215735 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 285684 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 6141 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 205828757 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.190746 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.306340 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 21220653 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 200130599 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 53911245 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 39833210 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 180362708 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 5820684 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 154995 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 66964 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 420974 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 452324 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 103497 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 74050081 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 272746 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 5705 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 205692457 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.188766 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.306289 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 98382336 47.80% 47.80% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 31160617 15.14% 62.94% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 14928225 7.25% 70.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 61357579 29.81% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 98524588 47.90% 47.90% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 31037557 15.09% 62.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 14908217 7.25% 70.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 61222095 29.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 205828757 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.255745 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.950042 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 26450347 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 110999505 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 60649256 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 5136264 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 2593385 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 3184080 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 362502 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 158814101 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 4185741 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 2593385 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 35368680 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 13285879 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 85120734 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 56726611 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 12733468 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 141845783 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 1133457 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1506583 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 170458 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 63498 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 8406258 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 146030033 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 654050739 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 157600072 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 10971 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 133759652 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 12270378 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 2729976 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 2583213 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 22947942 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 25466090 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 19748562 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1757357 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 2684729 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 138695125 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1764118 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 136568956 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 514251 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 11572106 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 23832263 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 127429 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 205828757 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.663508 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 0.962661 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 205692457 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.255736 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.949350 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 26429213 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 111222366 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 60319076 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 5157963 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 2563839 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 3171648 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 350947 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 158388827 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 4014782 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 2563839 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 35280795 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 13301493 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 85153816 # count of cycles rename stalled for serializing inst
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+system.cpu0.rename.UnblockCycles 12909564 # Number of cycles rename is unblocking
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+system.cpu0.rename.SquashedInsts 1085672 # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1524488 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 177088 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 62946 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 8550384 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 145816753 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 652563275 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 157207618 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 11000 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 133932927 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 11883815 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 2738789 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 2591099 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 23044959 # count of insts added to the skid buffer
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+system.cpu0.memDep0.conflictingLoads 1767343 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 2535257 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 138424520 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1769995 # Number of non-speculative instructions added to the IQ
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+system.cpu0.iq.iqSquashedInstsIssued 484040 # Number of squashed instructions issued
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+system.cpu0.iq.iqSquashedOperandsExamined 22999814 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 127035634 61.72% 61.72% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 34468527 16.75% 78.47% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 32041551 15.57% 94.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 11114901 5.40% 99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1168096 0.57% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 48 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 126945183 61.72% 61.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 34499506 16.77% 78.49% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 31998886 15.56% 94.05% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 11080832 5.39% 99.43% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
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+system.cpu0.iq.issued_per_cycle::total 205692457 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu0.iq.fu_full::IntMult 78 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 5928119 23.32% 67.05% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 8376643 32.95% 100.00% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.82% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.82% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.82% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.82% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.82% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 5937286 23.38% 67.20% # attempts to use FU when none available
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system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 92017831 67.38% 67.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 112728 0.08% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 8135 0.01% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 25188018 18.44% 85.91% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 19239929 14.09% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 91960000 67.41% 67.42% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 113905 0.08% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 8243 0.01% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.50% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 25115664 18.41% 85.92% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 19211906 14.08% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 136568956 # Type of FU issued
-system.cpu0.iq.rate 0.647146 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 25419961 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.186133 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 504862433 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 152038807 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 132856114 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 38448 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 13226 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 11442 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 161961537 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 25065 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 381033 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 136412034 # Type of FU issued
+system.cpu0.iq.rate 0.647091 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 25397576 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.186183 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 504359597 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 151322890 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 132769388 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 38543 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 13252 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 11438 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 161782111 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 25184 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 383563 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2126828 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2734 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 20764 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1086115 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2036205 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2638 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 20853 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 948035 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 121849 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 393509 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 126036 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 394781 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 2593385 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 1923862 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 225428 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 140668675 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles 2563839 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 1921080 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 231914 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 140382056 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 25466090 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 19748562 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 902405 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 28750 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 172587 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 20764 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 314258 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 420576 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 734834 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 135413166 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 24708809 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1084045 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts 25364147 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 19673316 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 906447 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 31018 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 175567 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 20853 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 275420 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 424017 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 699437 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 135325292 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 24646519 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1015002 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 209432 # number of nop insts executed
-system.cpu0.iew.exec_refs 43749631 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 26148134 # Number of branches executed
-system.cpu0.iew.exec_stores 19040822 # Number of stores executed
-system.cpu0.iew.exec_rate 0.641669 # Inst execution rate
-system.cpu0.iew.wb_sent 134807850 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 132867556 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 67789134 # num instructions producing a value
-system.cpu0.iew.wb_consumers 109636664 # num instructions consuming a value
-system.cpu0.iew.wb_rate 0.629607 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.618307 # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts 10465399 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 1636689 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 672949 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 202511851 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.637192 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.338822 # Number of insts commited each cycle
+system.cpu0.iew.exec_nop 187541 # number of nop insts executed
+system.cpu0.iew.exec_refs 43690093 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 26111417 # Number of branches executed
+system.cpu0.iew.exec_stores 19043574 # Number of stores executed
+system.cpu0.iew.exec_rate 0.641936 # Inst execution rate
+system.cpu0.iew.wb_sent 134725872 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 132780826 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 67751819 # num instructions producing a value
+system.cpu0.iew.wb_consumers 109549817 # num instructions consuming a value
+system.cpu0.iew.wb_rate 0.629866 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.618457 # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts 10037586 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 1642803 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 638504 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 202442995 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.638330 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.339217 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 140790239 69.52% 69.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 34042188 16.81% 86.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 12969775 6.40% 92.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 3421790 1.69% 94.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 4963486 2.45% 96.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 2698624 1.33% 98.21% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 1492584 0.74% 98.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 576020 0.28% 99.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1557145 0.77% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 140546392 69.43% 69.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 34245976 16.92% 86.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 12926596 6.39% 92.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 3383235 1.67% 94.40% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 4977119 2.46% 96.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 2872114 1.42% 98.28% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 1322991 0.65% 98.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 578946 0.29% 99.21% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1589626 0.79% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 202511851 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 106573853 # Number of instructions committed
-system.cpu0.commit.committedOps 129038976 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 202442995 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 106684229 # Number of instructions committed
+system.cpu0.commit.committedOps 129225495 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 42001709 # Number of memory references committed
-system.cpu0.commit.loads 23339262 # Number of loads committed
-system.cpu0.commit.membars 664486 # Number of memory barriers committed
-system.cpu0.commit.branches 25472286 # Number of branches committed
+system.cpu0.commit.refs 42053222 # Number of memory references committed
+system.cpu0.commit.loads 23327941 # Number of loads committed
+system.cpu0.commit.membars 666720 # Number of memory barriers committed
+system.cpu0.commit.branches 25467916 # Number of branches committed
system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 112576869 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 4879585 # Number of function calls committed.
+system.cpu0.commit.int_insts 112793765 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 4892953 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 86918951 67.36% 67.36% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 110181 0.09% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 8135 0.01% 67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 23339262 18.09% 85.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 18662447 14.46% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 87052485 67.36% 67.36% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 111545 0.09% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 8243 0.01% 67.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 23327941 18.05% 85.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 18725281 14.49% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 129038976 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1557145 # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads 317122360 # The number of ROB reads
-system.cpu0.rob.rob_writes 282315709 # The number of ROB writes
-system.cpu0.timesIdled 140732 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 5203902 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 5463916952 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 106422010 # Number of Instructions Simulated
-system.cpu0.committedOps 128887133 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 1.982979 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 1.982979 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.504292 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.504292 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 146824943 # number of integer regfile reads
-system.cpu0.int_regfile_writes 83833584 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 9570 # number of floating regfile reads
+system.cpu0.commit.op_class_0::total 129225495 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1589626 # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads 316721982 # The number of ROB reads
+system.cpu0.rob.rob_writes 281765642 # The number of ROB writes
+system.cpu0.timesIdled 131866 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 5115510 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 5443972636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 106532386 # Number of Instructions Simulated
+system.cpu0.committedOps 129073652 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 1.978816 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 1.978816 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.505353 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.505353 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 146797472 # number of integer regfile reads
+system.cpu0.int_regfile_writes 83857123 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 9583 # number of floating regfile reads
system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 478163179 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 51330102 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 283152527 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 1260318 # number of misc regfile writes
-system.cpu0.dcache.tags.replacements 750354 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 496.537127 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 38788721 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 750866 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 51.658646 # Average number of references to valid blocks.
+system.cpu0.cc_regfile_reads 477737826 # number of cc regfile reads
+system.cpu0.cc_regfile_writes 51222601 # number of cc regfile writes
+system.cpu0.misc_regfile_reads 282455977 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 1264842 # number of misc regfile writes
+system.cpu0.dcache.tags.replacements 752726 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 494.858519 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 38773458 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 753238 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 51.475706 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.537127 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969799 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.969799 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.858519 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966521 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.966521 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 83716112 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 83716112 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 22157554 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 22157554 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 15381796 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 15381796 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316247 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 316247 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371104 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 371104 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 369755 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 369755 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 37539350 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 37539350 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 37855597 # number of overall hits
-system.cpu0.dcache.overall_hits::total 37855597 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 688529 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 688529 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1970911 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1970911 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153379 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 153379 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 26060 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 26060 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20217 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 20217 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 2659440 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 2659440 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 2812819 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2812819 # number of overall misses
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-system.cpu0.dcache.ReadReq_miss_latency::total 9958933000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36282173869 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 36282173869 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 417298000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 417298000 # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 601500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 601500 # number of StoreCondFailReq miss cycles
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-system.cpu0.dcache.demand_miss_latency::total 46241106869 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 46241106869 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 46241106869 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 22846083 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 22846083 # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.SoftPFReq_accesses::total 469626 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397164 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 397164 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu0.dcache.StoreCondReq_accesses::total 389972 # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.demand_accesses::total 40198790 # number of demand (read+write) accesses
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-system.cpu0.dcache.overall_accesses::total 40668416 # number of overall (read+write) accesses
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-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.326598 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065615 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065615 # miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.demand_miss_rate::total 0.066157 # miss rate for demand accesses
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-system.cpu0.dcache.overall_miss_rate::total 0.069165 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14464.071956 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14464.071956 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18408.834224 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18408.834224 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16012.970069 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16012.970069 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26462.679923 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26462.679923 # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses 83704103 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 83704103 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 22086605 # number of ReadReq hits
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+system.cpu0.dcache.SoftPFReq_hits::total 316186 # number of SoftPFReq hits
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+system.cpu0.dcache.WriteReq_misses::total 1977745 # number of WriteReq misses
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+system.cpu0.dcache.SoftPFReq_misses::total 154100 # number of SoftPFReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::total 25656 # number of LoadLockedReq misses
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+system.cpu0.dcache.StoreCondReq_misses::total 20273 # number of StoreCondReq misses
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+system.cpu0.dcache.WriteReq_miss_latency::total 36928416860 # number of WriteReq miss cycles
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+system.cpu0.dcache.demand_miss_latency::total 46903054360 # number of demand (read+write) miss cycles
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+system.cpu0.dcache.SoftPFReq_accesses::total 470286 # number of SoftPFReq accesses(hits+misses)
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+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051815 # miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_miss_rate::total 0.066343 # miss rate for demand accesses
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+system.cpu0.dcache.overall_miss_rate::total 0.069366 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14487.364671 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14487.364671 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18671.980897 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18671.980897 # average WriteReq miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16267.013564 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25910.842007 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25910.842007 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17387.535297 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 17387.535297 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16439.417847 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16439.417847 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 1356 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 5556289 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 211720 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.250000 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 26.243572 # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17591.387443 # average overall miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16630.218849 # average overall miss latency
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+system.cpu0.dcache.blocked_cycles::no_mshrs 989 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 5684279 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 52 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 212555 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.019231 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 26.742627 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 750354 # number of writebacks
-system.cpu0.dcache.writebacks::total 750354 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 278216 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 278216 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1634757 # number of WriteReq MSHR hits
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-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 19327 # number of LoadLockedReq MSHR hits
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-system.cpu0.dcache.demand_mshr_hits::total 1912973 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1912973 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1912973 # number of overall MSHR hits
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-system.cpu0.dcache.ReadReq_mshr_misses::total 410313 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336154 # number of WriteReq MSHR misses
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-system.cpu0.dcache.SoftPFReq_mshr_misses::total 107278 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6733 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6733 # number of LoadLockedReq MSHR misses
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-system.cpu0.dcache.StoreCondReq_mshr_misses::total 20217 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 746467 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 746467 # number of demand (read+write) MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 853745 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31833 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31833 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28493 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60326 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60326 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5129549000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5129549000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7629793401 # number of WriteReq MSHR miss cycles
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-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1790414000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108965500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108965500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 514792000 # number of StoreCondReq MSHR miss cycles
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-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12759342401 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 12759342401 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6627988500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5396142000 # number of WriteReq MSHR uncacheable cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12024130500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017960 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017960 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019372 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019372 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228433 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228433 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016953 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016953 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051842 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051842 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018569 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.018569 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020993 # mshr miss rate for overall accesses
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12501.551255 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12501.551255 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22697.315519 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22697.315519 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16689.479670 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16689.479670 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16183.796228 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16183.796228 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25463.322946 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25463.322946 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 752726 # number of writebacks
+system.cpu0.dcache.writebacks::total 752726 # number of writebacks
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18966 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18966 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.StoreCondReq_mshr_misses::total 20273 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31816 # number of ReadReq MSHR uncacheable
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+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
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+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.018074 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.018074 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019337 # mshr miss rate for WriteReq accesses
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016799 # mshr miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12510.407430 # average ReadReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16282.884903 # average LoadLockedReq mshr miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17092.975846 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17092.975846 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17042.274217 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17042.274217 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208211.243050 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208211.243050 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189384.831362 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189384.831362 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199319.207307 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199319.207307 # average overall mshr uncacheable latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199275.942966 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1310036 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.377310 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 72844625 # Total number of references to valid blocks.
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-system.cpu0.icache.tags.avg_refs 55.583332 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 8206989500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.377310 # Average occupied blocks per requestor
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-system.cpu0.icache.tags.occ_percent::total 0.998784 # Average percentage of cache occupancy
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+system.cpu0.icache.tags.avg_refs 55.395528 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 8207383000 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 10948.513996 # average ReadReq miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 10948.513996 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.513996 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10948.513996 # average overall miss latency
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+system.cpu0.icache.ReadReq_miss_latency::total 14924586060 # number of ReadReq miss cycles
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+system.cpu0.icache.demand_miss_rate::total 0.018481 # miss rate for demand accesses
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+system.cpu0.icache.overall_miss_rate::total 0.018481 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10906.213506 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10906.213506 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10906.213506 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10906.213506 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10906.213506 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10906.213506 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 1977903 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 1805 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 120515 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 16 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.412090 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets 112.812500 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks 1310036 # number of writebacks
-system.cpu0.icache.writebacks::total 1310036 # number of writebacks
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-system.cpu0.icache.ReadReq_mshr_hits::total 56829 # number of ReadReq MSHR hits
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system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.370488 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.981842 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1389.729311 # Average occupied blocks per requestor
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-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 421 # Occupied blocks per task id
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-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 491 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4664 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7779 # Occupied blocks per task id
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-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.152067 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.152067 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042515 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042515 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184690 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184690 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.006007 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010892 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042515 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.173310 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.089320 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.006007 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010892 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042515 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.173310 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147623 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147623 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040930 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.183388 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.183388 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005801 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.008909 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.170914 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.087571 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005801 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.008909 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040930 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.170914 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207865 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24458.490566 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83211.527868 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83211.527868 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25964.367984 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25964.367984 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17902.280075 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17902.280075 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 489499 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 489499 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56486.826698 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56486.826698 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62560.707455 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62560.707455 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28542.297571 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28542.297571 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62560.707455 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37095.069291 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44308.915903 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26622.282609 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19543.209877 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62560.707455 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37095.069291 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83211.527868 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66494.954036 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200200.923570 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194365.660074 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181770.486154 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181770.486154 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191495.913238 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188698.925659 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207175 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25851.464435 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84377.313169 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25863.022966 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25863.022966 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17353.376412 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17353.376412 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60011.850907 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60011.850907 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63841.219702 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28867.833003 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28867.833003 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38249.755341 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45371.568112 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27878.186969 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20128 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63841.219702 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38249.755341 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84377.313169 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67889.929433 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200184.576942 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194351.503489 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181709.760518 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181709.760518 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132551.615052 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191455.176407 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188661.541189 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 4273775 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2158237 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33113 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 328951 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324011 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4940 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 121086 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 2004866 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 28493 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 28493 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 738565 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 1555705 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 211042 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 317280 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 85893 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42559 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 113529 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 299037 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 295734 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1310580 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595787 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 3352 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3937175 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2734284 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32274 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130084 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 6833817 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 167765632 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103829284 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59492 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 245052 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 271899460 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 1019958 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 3249040 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.119755 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.329325 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests 4281853 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2162712 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32662 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 328300 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324452 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3848 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq 121117 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 2006967 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 741466 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 1556492 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 207602 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 320187 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 85477 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42629 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 113152 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 299842 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 296502 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1312018 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 596340 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 3402 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3941483 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2739757 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 30823 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130322 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 6842385 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 167949424 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104071122 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 56120 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 243396 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 272320062 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 1018529 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 3250936 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.119239 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.327701 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 2864891 88.18% 88.18% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 379209 11.67% 99.85% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 4940 0.15% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 2867147 88.19% 88.19% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 379941 11.69% 99.88% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 3848 0.12% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 3249040 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 4275333939 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 3250936 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 4282821452 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 114905569 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 113625688 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 1969437864 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 1971630792 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1292879675 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1296047217 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 17411978 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 16802481 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 68871898 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 69515913 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 4004674 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 2314065 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 245791 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 2020541 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 1485653 # Number of BTB hits
+system.cpu1.branchPred.lookups 3871087 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 2220502 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 213805 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 1955914 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 1266404 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 73.527486 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 787487 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 5760 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 64.747428 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 774472 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 5638 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups 216728 # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits 192718 # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses 24010 # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted 5536 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1641,87 +1644,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 15918 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 15918 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8430 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3084 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 4404 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 11514 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 608.824040 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 3343.959858 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095 10992 95.47% 95.47% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::4096-8191 174 1.51% 96.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-12287 180 1.56% 98.54% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::12288-16383 59 0.51% 99.05% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.17% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.20% 99.37% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.04% 99.41% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::28672-32767 43 0.37% 99.78% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.04% 99.83% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::36864-40959 19 0.17% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 11514 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 3241 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11888.614625 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10569.570735 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 6910.032291 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383 2741 84.57% 84.57% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767 457 14.10% 98.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151 35 1.08% 99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535 7 0.22% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks 15135 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 15135 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8000 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3062 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 4073 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 11062 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 636.232146 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 3393.246458 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095 10520 95.10% 95.10% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191 182 1.65% 96.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287 208 1.88% 98.63% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383 44 0.40% 99.02% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479 10 0.09% 99.11% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575 20 0.18% 99.29% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.04% 99.33% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767 63 0.57% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.05% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::36864-40959 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::40960-45055 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 11062 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 3287 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11641.922726 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10290.587277 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 7252.269841 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383 2804 85.31% 85.31% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767 438 13.33% 98.63% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151 35 1.06% 99.70% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535 8 0.24% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 3241 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 79820713468 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.176976 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.384068 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 65723853356 82.34% 82.34% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 14081443112 17.64% 99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2 10527000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::3 1956000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4 949000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::5 421000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6 996500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::7 109000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8 31000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::9 149000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10 36500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::11 15000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12 23000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::13 37500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14 15000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::15 151500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 79820713468 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1248 73.11% 73.11% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 459 26.89% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 1707 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15918 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total 3287 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 78326908560 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.188289 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.393350 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 63608298256 81.21% 81.21% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 14703547304 18.77% 99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2 10074500 0.01% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::3 1868000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4 997000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::5 536500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6 1004000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::7 156000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8 32000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::9 91000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10 15500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::11 43500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12 105500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::13 9000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14 4500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::15 126000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 78326908560 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 1232 71.42% 71.42% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 493 28.58% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 1725 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15135 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15918 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1707 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15135 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1725 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1707 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 17625 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1725 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 16860 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 3542440 # DTB read hits
-system.cpu1.dtb.read_misses 14035 # DTB read misses
-system.cpu1.dtb.write_hits 3032103 # DTB write hits
-system.cpu1.dtb.write_misses 1883 # DTB write misses
+system.cpu1.dtb.read_hits 3481626 # DTB read hits
+system.cpu1.dtb.read_misses 13250 # DTB read misses
+system.cpu1.dtb.write_hits 2942267 # DTB write hits
+system.cpu1.dtb.write_misses 1885 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1668 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 364 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 1665 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 44 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 3556475 # DTB read accesses
-system.cpu1.dtb.write_accesses 3033986 # DTB write accesses
+system.cpu1.dtb.read_accesses 3494876 # DTB read accesses
+system.cpu1.dtb.write_accesses 2944152 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 6574543 # DTB hits
-system.cpu1.dtb.misses 15918 # DTB misses
-system.cpu1.dtb.accesses 6590461 # DTB accesses
+system.cpu1.dtb.hits 6423893 # DTB hits
+system.cpu1.dtb.misses 15135 # DTB misses
+system.cpu1.dtb.accesses 6439028 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1751,57 +1756,59 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 6720 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 6720 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4032 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2330 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 358 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 6362 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 276.642565 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 2156.603073 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-4095 6226 97.86% 97.86% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-8191 61 0.96% 98.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-12287 38 0.60% 99.42% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-16383 9 0.14% 99.56% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-20479 2 0.03% 99.59% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::20480-24575 2 0.03% 99.62% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-28671 16 0.25% 99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::28672-32767 7 0.11% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::40960-45055 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 6362 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 1209 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11358.974359 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10416.514513 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 5795.722698 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191 235 19.44% 19.44% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383 915 75.68% 95.12% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575 19 1.57% 96.69% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767 26 2.15% 98.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959 6 0.50% 99.34% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.33% 99.67% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.08% 99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.08% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::73728-81919 2 0.17% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 1209 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 15394402028 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 0.620378 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev 0.485344 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 5844439264 37.96% 37.96% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 9549582764 62.03% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 380000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 15394402028 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 707 83.08% 83.08% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 144 16.92% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 851 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 5379 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 5379 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2691 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2153 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore 535 # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples 4844 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean 218.414533 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 1692.156629 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-2047 4709 97.21% 97.21% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::2048-4095 42 0.87% 98.08% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-6143 42 0.87% 98.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::6144-8191 13 0.27% 99.22% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-10239 10 0.21% 99.42% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::10240-12287 7 0.14% 99.57% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.08% 99.65% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.10% 99.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-18431 2 0.04% 99.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.04% 99.83% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::26624-28671 6 0.12% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::28672-30719 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 4844 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 1373 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 10949.016752 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 9997.704100 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 5248.867098 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191 278 20.25% 20.25% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383 1006 73.27% 93.52% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575 56 4.08% 97.60% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767 16 1.17% 98.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959 9 0.66% 99.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151 5 0.36% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.15% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.07% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 1373 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 18192386416 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean 0.925541 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev 0.262684 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1355392264 7.45% 7.45% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1 16836194152 92.55% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2 800000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 18192386416 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 695 82.94% 82.94% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 143 17.06% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 838 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6720 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6720 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5379 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5379 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 851 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 851 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 7571 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 7202560 # ITB inst hits
-system.cpu1.itb.inst_misses 6720 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 838 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 838 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 6217 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 6965528 # ITB inst hits
+system.cpu1.itb.inst_misses 5379 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
@@ -1810,1025 +1817,1019 @@ system.cpu1.itb.flush_tlb 66 # Nu
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 915 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 902 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 341 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 384 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 7209280 # ITB inst accesses
-system.cpu1.itb.hits 7202560 # DTB hits
-system.cpu1.itb.misses 6720 # DTB misses
-system.cpu1.itb.accesses 7209280 # DTB accesses
-system.cpu1.numCycles 32401432 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 6970907 # ITB inst accesses
+system.cpu1.itb.hits 6965528 # DTB hits
+system.cpu1.itb.misses 5379 # DTB misses
+system.cpu1.itb.accesses 6970907 # DTB accesses
+system.cpu1.numCycles 32092744 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 8088351 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 21358444 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 4004674 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 2273140 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 22559668 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 709698 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 89320 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 30191 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 187953 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 272100 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 17466 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 7201931 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 106041 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2579 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 31599898 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.827450 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.197285 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 7782299 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 20640770 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 3871087 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 2233594 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 22614955 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 645830 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 74008 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 29636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 160010 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 275842 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 16624 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 6964682 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 92359 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 1934 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 31276289 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.805380 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.188121 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 19506083 61.73% 61.73% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 4380023 13.86% 75.59% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 1374078 4.35% 79.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 6339714 20.06% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 19613481 62.71% 62.71% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 4233968 13.54% 76.25% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 1331194 4.26% 80.50% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 6097646 19.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 31599898 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.123596 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.659182 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 6634182 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 16202869 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 7616699 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 910855 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 235293 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 619161 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 122169 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 20057728 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 931915 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 235293 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 7874159 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 2260152 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 11399374 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 7269011 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 2561909 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 19031053 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 153065 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 202989 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 28113 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 12734 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 1710748 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 18778237 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 89017572 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 21965763 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 3 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 16813455 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1964782 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 364894 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 300103 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 2457661 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 3778976 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 3342332 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 554105 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 450807 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 18329749 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 508607 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 18175118 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 83980 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1786298 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 4127648 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 40965 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 31599898 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.575164 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 0.924804 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 31276289 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.120622 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.643160 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 6336736 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 16565133 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 7246187 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 914830 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 213403 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 597831 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 111765 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 19357447 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 835377 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 213403 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 7521212 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 2374588 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 11566982 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 6962571 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 2637533 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 18397316 # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts 130089 # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents 214163 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 27812 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 12950 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 1772414 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 18194678 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 86130501 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 21182613 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 5 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 16531195 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1663483 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 369349 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 301926 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 2462039 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 3681622 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 3198899 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 554263 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 453752 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 17730825 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 507077 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 17704327 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 59995 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1478553 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 3387139 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 37397 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 31276289 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.566062 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 0.918538 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 20823460 65.90% 65.90% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 5404189 17.10% 83.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3573075 11.31% 94.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 1571925 4.97% 99.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 227241 0.72% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 20752127 66.35% 66.35% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 5297030 16.94% 83.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3493708 11.17% 94.46% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 1513821 4.84% 99.30% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 219597 0.70% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 6 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 31599898 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 31276289 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 1136230 27.62% 27.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 665 0.02% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.64% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 1332872 32.40% 60.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 1643603 39.96% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 1110256 27.87% 27.87% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 673 0.02% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 1321373 33.17% 61.07% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 1550767 38.93% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 11198655 61.62% 61.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 26151 0.14% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 3134 0.02% 61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 3723841 20.49% 82.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 3223313 17.73% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 10922763 61.70% 61.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 25931 0.15% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 3184 0.02% 61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 3652522 20.63% 82.49% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 3099903 17.51% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 18175118 # Type of FU issued
-system.cpu1.iq.rate 0.560936 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 4113370 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.226319 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 72147484 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 20632628 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 17784107 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 17704327 # Type of FU issued
+system.cpu1.iq.rate 0.551661 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 3983069 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.224977 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 70728007 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 19724904 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 17354196 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 22288464 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 21687372 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 72358 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 71019 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 345916 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 595 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 8007 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 274863 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 284912 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 435 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 8471 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 200526 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 35609 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 53341 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 36020 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 53245 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 235293 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 517337 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 146372 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 18855001 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles 213403 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 522979 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 149253 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 18243784 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 3778976 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 3342332 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 266125 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 6620 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 133975 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 8007 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 29726 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 104216 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 133942 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 17973018 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 3647924 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 186185 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts 3681622 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 3198899 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 268198 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 4775 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 139704 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 8471 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 19696 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 91512 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 111208 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 17534609 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 3585774 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 154586 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 16645 # number of nop insts executed
-system.cpu1.iew.exec_refs 6817035 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 2587014 # Number of branches executed
-system.cpu1.iew.exec_stores 3169111 # Number of stores executed
-system.cpu1.iew.exec_rate 0.554698 # Inst execution rate
-system.cpu1.iew.wb_sent 17871186 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 17784107 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 8844810 # num instructions producing a value
-system.cpu1.iew.wb_consumers 13737258 # num instructions consuming a value
-system.cpu1.iew.wb_rate 0.548868 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.643856 # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts 1617174 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 467642 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 126235 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 31232048 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.546078 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.299760 # Number of insts commited each cycle
+system.cpu1.iew.exec_nop 5882 # number of nop insts executed
+system.cpu1.iew.exec_refs 6645326 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 2522938 # Number of branches executed
+system.cpu1.iew.exec_stores 3059552 # Number of stores executed
+system.cpu1.iew.exec_rate 0.546373 # Inst execution rate
+system.cpu1.iew.wb_sent 17440127 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 17354196 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 8664228 # num instructions producing a value
+system.cpu1.iew.wb_consumers 13427268 # num instructions consuming a value
+system.cpu1.iew.wb_rate 0.540751 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.645271 # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts 1321053 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 469680 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 104293 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 30960244 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.541417 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.301399 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 22985371 73.60% 73.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 4918403 15.75% 89.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1437568 4.60% 93.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 538908 1.73% 95.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 452299 1.45% 97.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 299028 0.96% 98.08% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 181643 0.58% 98.66% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 99960 0.32% 98.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 318868 1.02% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 22892252 73.94% 73.94% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 4806577 15.52% 89.47% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1404802 4.54% 94.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 524965 1.70% 95.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 440442 1.42% 97.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 285091 0.92% 98.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 183452 0.59% 98.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 97903 0.32% 98.95% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 324760 1.05% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 31232048 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 13919439 # Number of instructions committed
-system.cpu1.commit.committedOps 17055121 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 30960244 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 13688085 # Number of instructions committed
+system.cpu1.commit.committedOps 16762412 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 6500529 # Number of memory references committed
-system.cpu1.commit.loads 3433060 # Number of loads committed
-system.cpu1.commit.membars 191637 # Number of memory barriers committed
-system.cpu1.commit.branches 2464934 # Number of branches committed
+system.cpu1.commit.refs 6395083 # Number of memory references committed
+system.cpu1.commit.loads 3396710 # Number of loads committed
+system.cpu1.commit.membars 189727 # Number of memory barriers committed
+system.cpu1.commit.branches 2413565 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 15221061 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 413171 # Number of function calls committed.
+system.cpu1.commit.int_insts 14968527 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 408976 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 10526100 61.72% 61.72% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 25358 0.15% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 3134 0.02% 61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 3433060 20.13% 82.01% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 3067469 17.99% 100.00% # Class of committed instruction
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+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.83% # Class of committed instruction
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+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.83% # Class of committed instruction
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+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.83% # Class of committed instruction
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+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.83% # Class of committed instruction
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system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 17055121 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 318868 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 48693377 # The number of ROB reads
-system.cpu1.rob.rob_writes 37704462 # The number of ROB writes
-system.cpu1.timesIdled 54449 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 801534 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 5641978926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 13916375 # Number of Instructions Simulated
-system.cpu1.committedOps 17052057 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 2.328295 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 2.328295 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.429499 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.429499 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 20171144 # number of integer regfile reads
-system.cpu1.int_regfile_writes 11610273 # number of integer regfile writes
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-system.cpu1.cc_regfile_writes 5511942 # number of cc regfile writes
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-system.cpu1.misc_regfile_writes 345736 # number of misc regfile writes
-system.cpu1.dcache.tags.replacements 150581 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 478.131368 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 5834465 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 150940 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 38.654200 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 89605225500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.131368 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.933850 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.933850 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 12862288 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 12862288 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 3070880 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 3070880 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 2527415 # number of WriteReq hits
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-system.cpu1.dcache.LoadLockedReq_hits::total 70538 # number of LoadLockedReq hits
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-system.cpu1.dcache.StoreCondReq_hits::total 61948 # number of StoreCondReq hits
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-system.cpu1.dcache.overall_hits::total 5641192 # number of overall hits
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-system.cpu1.dcache.ReadReq_misses::total 179007 # number of ReadReq misses
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-system.cpu1.dcache.SoftPFReq_misses::total 23941 # number of SoftPFReq misses
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-system.cpu1.dcache.LoadLockedReq_misses::total 17385 # number of LoadLockedReq misses
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-system.cpu1.dcache.ReadReq_miss_latency::total 3308418500 # number of ReadReq miss cycles
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-system.cpu1.dcache.overall_accesses::total 6160730 # number of overall (read+write) accesses
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-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.197730 # miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274104 # miss rate for StoreCondReq accesses
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-system.cpu1.dcache.overall_miss_rate::total 0.084331 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18482.062154 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 18482.062154 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34861.560510 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 34861.560510 # average WriteReq miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20569.168824 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27212.358926 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27212.358926 # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total 16762412 # Class of committed instruction
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+system.cpu1.idleCycles 816455 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu1.committedOps 16759348 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 2.345100 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 2.345100 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.426421 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.426421 # IPC: Total IPC of All Threads
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+system.cpu1.dcache.tags.warmup_cycle 104643213000 # Cycle when the warmup percentage was hit.
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+system.cpu1.dcache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 334 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.658203 # Percentage of cache occupancy per task id
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+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1848000 # number of StoreCondFailReq miss cycles
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+system.cpu1.dcache.LoadLockedReq_accesses::total 86791 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu1.dcache.overall_accesses::total 6052746 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054585 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.054585 # miss rate for ReadReq accesses
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+system.cpu1.dcache.WriteReq_miss_rate::total 0.111806 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358080 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358080 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.204699 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.204699 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274923 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274923 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081300 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.081300 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084288 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.084288 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19106.141997 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 19106.141997 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37445.819435 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 37445.819435 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20593.999775 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20593.999775 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26950.505312 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26950.505312 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28945.372837 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 28945.372837 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27611.531672 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 27611.531672 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 640 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 1636825 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 27 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 30227 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 23.703704 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 54.151090 # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30881.033763 # average overall miss latency
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+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29464.735252 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 29464.735252 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 465 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 1794947 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 35 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 29761 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.285714 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 60.312053 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 150582 # number of writebacks
-system.cpu1.dcache.writebacks::total 150582 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62660 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 62660 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 238202 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 238202 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12477 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12477 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 300862 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 300862 # number of demand (read+write) MSHR hits
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-system.cpu1.dcache.overall_mshr_hits::total 300862 # number of overall MSHR hits
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-system.cpu1.dcache.ReadReq_mshr_misses::total 116347 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78388 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 78388 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23063 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 23063 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4908 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4908 # number of LoadLockedReq MSHR misses
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-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23392 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 194735 # number of demand (read+write) MSHR misses
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-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3053 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2411 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5464 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5464 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1737573500 # number of ReadReq MSHR miss cycles
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-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 402982000 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95410500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95410500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035800 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027563 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027563 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.345058 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.345058 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055822 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055822 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274104 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274104 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031956 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.031956 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035353 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.035353 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14934.407419 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14934.407419 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35348.585893 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35348.585893 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17473.095434 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17473.095434 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19439.792176 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19439.792176 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26212.658174 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26212.658174 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 147018 # number of writebacks
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+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14946.296883 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14946.296883 # average ReadReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23151.865104 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23151.865104 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22550.530542 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22550.530542 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142221.094006 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142221.094006 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124728.535877 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124728.535877 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134502.470717 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134502.470717 # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23908.499350 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23908.499350 # average overall mshr miss latency
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 4811835313 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4811835313 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 4811835313 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4811835313 # number of overall MSHR miss cycles
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-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8603.917157 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 8603.917157 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8603.917157 # average overall mshr miss latency
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-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132539.215686 # average overall mshr uncacheable latency
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system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 50212 # number of prefetches not generated due to page crossing
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-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 426.745588 # Average occupied blocks per requestor
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-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14157 # Occupied blocks per task id
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system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 1522873 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 769340 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12387 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 172724 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169892 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2832 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 26445 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 767980 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 2411 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 2411 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 120637 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 616293 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 90499 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 23834 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 71062 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41585 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 84984 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 57226 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 54414 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 559261 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 224052 # Transaction distribution
+system.cpu1.toL2Bus.snoop_filter.tot_requests 1463686 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 739552 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11057 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 170999 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169235 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1764 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq 24298 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 736701 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 2419 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 2419 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 121677 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 588534 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 90826 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 26224 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 69999 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41335 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 85194 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 56383 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 54101 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 533160 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 217797 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1677474 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 729934 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16099 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27235 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2450742 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 71554208 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24804884 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29628 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50548 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 96439268 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 367369 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1124026 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.173917 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.385628 # Request fanout histogram
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1599162 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 719912 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12717 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 26238 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 2358029 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 68212704 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24362994 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 22880 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48456 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 92647034 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 368307 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1093026 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.175061 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.384243 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 931371 82.86% 82.86% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 189823 16.89% 99.75% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 2832 0.25% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 903444 82.66% 82.66% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 187818 17.18% 99.84% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 1764 0.16% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1124026 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 1482640983 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 1093026 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 1422321490 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 79919843 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 79991516 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 839140704 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 799908367 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 323172006 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 318043852 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 8701980 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 6997998 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 14614966 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 14133980 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31018 # Transaction distribution
system.iobus.trans_dist::ReadResp 31018 # Transaction distribution
@@ -2880,59 +2881,59 @@ system.iobus.pkt_size_system.bridge.master::total 162812
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 40406500 # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy 40405500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 111000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 89000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 580500 # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6147500 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 6085500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 34101000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 34122000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187141705 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 187170938 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36458 # number of replacements
-system.iocache.tags.tagsinuse 14.554769 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 14.550737 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 256290748000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 14.554769 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.909673 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.909673 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 256092273000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 14.550737 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.909421 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.909421 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
@@ -2946,14 +2947,14 @@ system.iocache.demand_misses::realview.ide 252 #
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 252 # number of overall misses
system.iocache.overall_misses::total 252 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 32655877 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 32655877 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4577690828 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4577690828 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 32655877 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 32655877 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 32655877 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 32655877 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 32570877 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 32570877 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 4577184061 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 4577184061 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 32570877 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 32570877 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 32570877 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 32570877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
@@ -2970,19 +2971,19 @@ system.iocache.demand_miss_rate::realview.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 129586.813492 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 129586.813492 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126371.765349 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 126371.765349 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 129586.813492 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 129586.813492 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 129586.813492 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 129586.813492 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 129249.511905 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 129249.511905 # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126357.775536 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 126357.775536 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 129249.511905 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 129249.511905 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 129249.511905 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 129249.511905 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -2996,14 +2997,14 @@ system.iocache.demand_mshr_misses::realview.ide 252
system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 20055877 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 20055877 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764790800 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2764790800 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 20055877 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 20055877 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 20055877 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 20055877 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 19970877 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 19970877 # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764245413 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 2764245413 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 19970877 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 19970877 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 19970877 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 19970877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
@@ -3012,602 +3013,604 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1
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+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.071429 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.266743 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.610394 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.654837 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.563466 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.130841 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030303 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.363650 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.285952 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743486 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.071429 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.266743 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.610394 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.654837 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.563466 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72697.972196 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72196.525271 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72603.666299 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74620.056497 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73853.274050 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.390746 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141449.018360 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124290.790391 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 134095.252867 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122876.579413 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128593.047792 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124151.666918 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131187.312693 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143712.467270 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127333.333333 # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129515.337633 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133709.634561 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144844.415396 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122876.579413 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135452.910156 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124151.666918 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123902.924389 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 142686.940483 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127333.333333 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136190.127532 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125304.258789 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 143713.943682 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 136071.428571 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122876.579413 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135452.910156 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147071.644934 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 123333.333333 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124151.666918 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123902.924389 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171823.960768 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 142686.940483 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182200.405366 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107029.411765 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116233.444262 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171351.246650 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164765.891307 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100120.492742 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159722.529414 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173965.786643 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107029.411765 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109119.669108 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 166134.840376 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122626.563959 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136190.127532 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148202.778405 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129666.666667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124367.545164 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125304.258789 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 172400.467610 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 143713.943682 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182183.869845 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116675.945312 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171343.181823 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164706.920769 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100167.840430 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159657.433890 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114551.448551 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173925.964321 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108362.745098 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109403.480240 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 166100.187895 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 37989 # Transaction distribution
-system.membus.trans_dist::ReadResp 208587 # Transaction distribution
-system.membus.trans_dist::WriteReq 30904 # Transaction distribution
-system.membus.trans_dist::WriteResp 30904 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 133951 # Transaction distribution
-system.membus.trans_dist::CleanEvict 15326 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 74253 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 40479 # Transaction distribution
+system.membus.trans_dist::ReadReq 37993 # Transaction distribution
+system.membus.trans_dist::ReadResp 212610 # Transaction distribution
+system.membus.trans_dist::WriteReq 30918 # Transaction distribution
+system.membus.trans_dist::WriteResp 30918 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 138325 # Transaction distribution
+system.membus.trans_dist::CleanEvict 16163 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 72828 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 40466 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
-system.membus.trans_dist::ReadExReq 38529 # Transaction distribution
-system.membus.trans_dist::ReadExResp 18901 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 170599 # Transaction distribution
+system.membus.trans_dist::ReadExReq 40267 # Transaction distribution
+system.membus.trans_dist::ReadExResp 20420 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 174618 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13702 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 641454 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 763128 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13740 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656523 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 778231 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 836077 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 851180 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27404 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18415544 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18606080 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19049928 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 19240508 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 20924224 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 120501 # Total snoops (count)
-system.membus.snoop_fanout::samples 578275 # Request fanout histogram
+system.membus.pkt_size::total 21558652 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 119912 # Total snoops (count)
+system.membus.snoop_fanout::samples 587818 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 578275 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 587818 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 578275 # Request fanout histogram
-system.membus.reqLayer0.occupancy 81956500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 587818 # Request fanout histogram
+system.membus.reqLayer0.occupancy 81915500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 11341491 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 11626486 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 978727928 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1006913072 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1093472967 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1122228815 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 1338381 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 1359881 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
@@ -3650,56 +3653,56 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 990338 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 533884 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 147185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 20219 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 19375 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 844 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 37992 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 475955 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 393750 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 117353 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 108673 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 43588 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 152261 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 50171 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 50171 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 437979 # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests 988623 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 533441 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 142864 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 21333 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 20424 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 909 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 37996 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 474339 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30918 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30918 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 400884 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 117322 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 107373 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 43404 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 150777 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 50440 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 50440 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 436359 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1264500 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 260756 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1525256 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35008152 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3970344 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 38978496 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 440946 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 906523 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.342627 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.476546 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256848 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 266902 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1523750 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34918134 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4292486 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 39210620 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 443927 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 909712 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.336026 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.474459 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 596768 65.83% 65.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 308911 34.08% 99.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 844 0.09% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 604934 66.50% 66.50% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 303869 33.40% 99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 909 0.10% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 906523 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 872587716 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 909712 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 874582688 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 657818310 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 652718656 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 206175111 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 208359113 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1860 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 1876 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2731 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 2727 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index f27d56388..9195b9140 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,122 +1,122 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.832923 # Number of seconds simulated
-sim_ticks 2832922792000 # Number of ticks simulated
-final_tick 2832922792000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.832863 # Number of seconds simulated
+sim_ticks 2832863135500 # Number of ticks simulated
+final_tick 2832863135500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 79525 # Simulator instruction rate (inst/s)
-host_op_rate 96457 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1991756148 # Simulator tick rate (ticks/s)
-host_mem_usage 563904 # Number of bytes of host memory used
-host_seconds 1422.32 # Real time elapsed on the host
-sim_insts 113110851 # Number of instructions simulated
-sim_ops 137193114 # Number of ops (including micro ops) simulated
+host_inst_rate 115587 # Simulator instruction rate (inst/s)
+host_op_rate 140197 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2895087258 # Simulator tick rate (ticks/s)
+host_mem_usage 586016 # Number of bytes of host memory used
+host_seconds 978.51 # Real time elapsed on the host
+sim_insts 113102806 # Number of instructions simulated
+sim_ops 137183832 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 1408 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1316352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9383208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1320448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9385192 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10702440 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1316352 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1316352 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7997632 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10708200 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1320448 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1320448 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8027392 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8015156 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 22 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 22815 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 147133 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8044916 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 22879 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 147164 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 169993 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 124963 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 170083 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 125428 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 129344 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 497 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 464662 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3312200 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 129809 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 429 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 466118 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3312971 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3777879 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 464662 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 464662 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2823103 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3779992 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 466118 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 466118 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2833667 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2829289 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2823103 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 497 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 464662 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3318386 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2839853 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2833667 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 429 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 466118 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3319156 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6607168 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 169994 # Number of read requests accepted
-system.physmem.writeReqs 129344 # Number of write requests accepted
-system.physmem.readBursts 169994 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 129344 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10868544 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8027328 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10702504 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8015156 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 6619845 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 170084 # Number of read requests accepted
+system.physmem.writeReqs 129809 # Number of write requests accepted
+system.physmem.readBursts 170084 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 129809 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10877056 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8057984 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10708264 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8044916 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11395 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10614 # Per bank write bursts
-system.physmem.perBankRdBursts::2 11056 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11362 # Per bank write bursts
-system.physmem.perBankRdBursts::4 12761 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10093 # Per bank write bursts
-system.physmem.perBankRdBursts::6 10906 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11082 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10555 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10525 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10031 # Per bank write bursts
-system.physmem.perBankRdBursts::11 8841 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9976 # Per bank write bursts
-system.physmem.perBankRdBursts::13 10659 # Per bank write bursts
-system.physmem.perBankRdBursts::14 9879 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10086 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8598 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7964 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8488 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8679 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7544 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7468 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8076 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8176 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8056 # Per bank write bursts
-system.physmem.perBankWrBursts::9 7912 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7497 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6567 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7556 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8041 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7358 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7447 # Per bank write bursts
+system.physmem.perBankRdBursts::0 11273 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10590 # Per bank write bursts
+system.physmem.perBankRdBursts::2 10987 # Per bank write bursts
+system.physmem.perBankRdBursts::3 11172 # Per bank write bursts
+system.physmem.perBankRdBursts::4 12956 # Per bank write bursts
+system.physmem.perBankRdBursts::5 9956 # Per bank write bursts
+system.physmem.perBankRdBursts::6 10483 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10745 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10596 # Per bank write bursts
+system.physmem.perBankRdBursts::9 10173 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10343 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9301 # Per bank write bursts
+system.physmem.perBankRdBursts::12 10027 # Per bank write bursts
+system.physmem.perBankRdBursts::13 11029 # Per bank write bursts
+system.physmem.perBankRdBursts::14 10190 # Per bank write bursts
+system.physmem.perBankRdBursts::15 10133 # Per bank write bursts
+system.physmem.perBankWrBursts::0 8501 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7944 # Per bank write bursts
+system.physmem.perBankWrBursts::2 8565 # Per bank write bursts
+system.physmem.perBankWrBursts::3 8669 # Per bank write bursts
+system.physmem.perBankWrBursts::4 7612 # Per bank write bursts
+system.physmem.perBankWrBursts::5 7365 # Per bank write bursts
+system.physmem.perBankWrBursts::6 7701 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8000 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7958 # Per bank write bursts
+system.physmem.perBankWrBursts::9 7673 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7751 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6981 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7673 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8385 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7646 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7482 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
-system.physmem.totGap 2832922560000 # Total gap between requests
+system.physmem.numWrRetry 13 # Number of times write queue was full causing retry
+system.physmem.totGap 2832862903500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 2996 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 166442 # Read request sizes (log2)
+system.physmem.readPktSize::6 166532 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 124963 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 150475 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 16443 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2160 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 726 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 125428 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 150650 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 16386 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2178 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 724 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
@@ -159,189 +159,193 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1876 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2935 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6553 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6085 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 7044 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6552 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6402 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6670 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7193 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 7575 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8576 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7511 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7909 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 9031 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 7522 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 7223 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 7208 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 1227 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 325 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 226 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 112 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 97 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 78 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 88 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 81 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 133 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 76 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 59 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 120 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 70 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 62162 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 303.976835 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 179.556802 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 324.609366 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 23353 37.57% 37.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 15037 24.19% 61.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6420 10.33% 72.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3598 5.79% 77.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2572 4.14% 82.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1554 2.50% 84.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1555 2.50% 87.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1056 1.70% 88.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7017 11.29% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 62162 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6134 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 27.682426 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 569.995454 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6133 99.98% 99.98% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::46 90 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 95 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 71 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 92 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 50 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 49 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 61981 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 305.496459 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 180.645422 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 324.944153 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 23140 37.33% 37.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 14875 24.00% 61.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6518 10.52% 71.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3622 5.84% 77.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2531 4.08% 81.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1654 2.67% 84.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1506 2.43% 86.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1111 1.79% 88.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7024 11.33% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 61981 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6159 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 27.593765 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 568.835471 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6158 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6134 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6134 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.447832 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.494220 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 14.258033 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5448 88.82% 88.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 109 1.78% 90.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 26 0.42% 91.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 55 0.90% 91.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 22 0.36% 92.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 18 0.29% 92.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 54 0.88% 93.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 11 0.18% 93.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 137 2.23% 95.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 15 0.24% 96.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 11 0.18% 96.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 9 0.15% 96.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 67 1.09% 97.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 4 0.07% 97.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 9 0.15% 97.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 29 0.47% 98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 82 1.34% 99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 6159 # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::mean 20.442604 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::96-99 1 0.02% 99.58% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 5 0.08% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 3 0.05% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6134 # Writes before turning the bus around for reads
-system.physmem.totQLat 2139801000 # Total ticks spent queuing
-system.physmem.totMemAccLat 5323944750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 849105000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12600.33 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::100-103 1 0.02% 99.59% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::172-175 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6159 # Writes before turning the bus around for reads
+system.physmem.totQLat 2118470000 # Total ticks spent queuing
+system.physmem.totMemAccLat 5305107500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 849770000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12464.96 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31350.33 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 31214.96 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.83 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.83 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 27.97 # Average write queue length when enqueuing
-system.physmem.readRowHits 139332 # Number of row buffer hits during reads
-system.physmem.writeRowHits 93753 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.73 # Row buffer hit rate for writes
-system.physmem.avgGap 9463959.00 # Average gap between requests
-system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 247869720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 135246375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 696290400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 421154640 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83656164285 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1626368380500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1896557542080 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.471316 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2705472781500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 94597360000 # Time in different power states
+system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing
+system.physmem.readRowHits 139692 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94186 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.19 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.80 # Row buffer hit rate for writes
+system.physmem.avgGap 9446245.51 # Average gap between requests
+system.physmem.pageHitRate 79.05 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 242388720 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 132255750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 687663600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 417033360 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 83434510665 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1626525439500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1896467659275 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.454308 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2705731371250 # Time in different power states
+system.physmem_0.memoryStateTime::REF 94595280000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 32852637000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 32529373750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 628305600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 391612320 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 185032436160 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 81913765770 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1627896800250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1896206166975 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.347283 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2708023579500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 94597360000 # Time in different power states
+system.physmem_1.actEnergy 226187640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 123415875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 637969800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 398837520 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 82104234975 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1627692348000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1896211361490 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.363834 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2707689162500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 94595280000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30297375500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30578679500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 46900870 # Number of BP lookups
-system.cpu.branchPred.condPredicted 24033937 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1233884 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 29535620 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 21344859 # Number of BTB hits
+system.cpu.branchPred.lookups 46808005 # Number of BP lookups
+system.cpu.branchPred.condPredicted 23978413 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1175283 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 29454237 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13525326 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 72.268193 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 11734674 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 33890 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 45.919798 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 11724965 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 34889 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 7914908 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 7768670 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 146238 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 60204 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -372,84 +376,79 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 71837 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 71837 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29758 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22348 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 19731 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 52106 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 420.441024 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 2560.543879 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-4095 50336 96.60% 96.60% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::4096-8191 584 1.12% 97.72% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-12287 523 1.00% 98.73% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::12288-16383 337 0.65% 99.37% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-20479 50 0.10% 99.47% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.42% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-28671 15 0.03% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::45056-49151 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 52106 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 17457 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11531.334135 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 9171.811391 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 8140.859549 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767 17274 98.95% 98.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks 72355 # Table walker walks requested
+system.cpu.dtb.walker.walksShort 72355 # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29395 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23194 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore 19766 # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples 52589 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 463.728156 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 2807.068133 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-8191 51286 97.52% 97.52% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-16383 905 1.72% 99.24% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-24575 316 0.60% 99.84% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-32767 38 0.07% 99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-40959 15 0.03% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-49151 23 0.04% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 52589 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 17730 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12604.906937 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10089.659045 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 8394.043940 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767 17507 98.74% 98.74% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535 217 1.22% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 17457 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131387254816 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.617449 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.493362 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1 131332759316 99.96% 99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3 37388500 0.03% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5 6986000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7 6081500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9 1205000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11 646500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13 1379500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15 798500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131387254816 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6345 82.34% 82.34% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1361 17.66% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7706 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71837 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 17730 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131327621316 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean 0.619198 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev 0.492781 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1 131267451816 99.95% 99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3 41041000 0.03% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5 8807000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7 6837500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9 1021000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11 576000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13 1403500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15 474000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 131327621316 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 6380 82.61% 82.61% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M 1343 17.39% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 7723 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72355 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71837 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7706 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72355 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7723 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7706 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 79543 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7723 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 80078 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 25453240 # DTB read hits
-system.cpu.dtb.read_misses 61907 # DTB read misses
-system.cpu.dtb.write_hits 19910032 # DTB write hits
-system.cpu.dtb.write_misses 9930 # DTB write misses
+system.cpu.dtb.read_hits 25411177 # DTB read hits
+system.cpu.dtb.read_misses 62688 # DTB read misses
+system.cpu.dtb.write_hits 19865478 # DTB write hits
+system.cpu.dtb.write_misses 9667 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 357 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch
+system.cpu.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1331 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 25515147 # DTB read accesses
-system.cpu.dtb.write_accesses 19919962 # DTB write accesses
+system.cpu.dtb.perms_faults 1317 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 25473865 # DTB read accesses
+system.cpu.dtb.write_accesses 19875145 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 45363272 # DTB hits
-system.cpu.dtb.misses 71837 # DTB misses
-system.cpu.dtb.accesses 45435109 # DTB accesses
+system.cpu.dtb.hits 45276655 # DTB hits
+system.cpu.dtb.misses 72355 # DTB misses
+system.cpu.dtb.accesses 45349010 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -479,55 +478,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 13224 # Table walker walks requested
-system.cpu.itb.walker.walksShort 13224 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 3935 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 7779 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore 1510 # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples 11714 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean 663.436913 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev 2983.675240 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095 11112 94.86% 94.86% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191 167 1.43% 96.29% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287 192 1.64% 97.93% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383 98 0.84% 98.76% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479 101 0.86% 99.62% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575 31 0.26% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks 12837 # Table walker walks requested
+system.cpu.itb.walker.walksShort 12837 # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 3369 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 7745 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore 1723 # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples 11114 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean 758.457801 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 3142.171422 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095 10521 94.66% 94.66% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191 120 1.08% 95.74% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287 234 2.11% 97.85% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383 132 1.19% 99.04% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479 45 0.40% 99.44% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.87% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 11714 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 4832 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 11551.427980 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 9033.563647 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 8305.140651 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383 3848 79.64% 79.64% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767 915 18.94% 98.57% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151 67 1.39% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::total 11114 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 5038 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12015.680826 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 9674.005789 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 7624.491394 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383 4083 81.04% 81.04% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767 936 18.58% 99.62% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-49151 16 0.32% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 4832 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 24013010416 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean 0.681227 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev 0.466165 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 7656484500 31.88% 31.88% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1 16354802916 68.11% 99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2 1665500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 24013010416 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 3004 90.43% 90.43% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 318 9.57% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated
+system.cpu.itb.walker.walkCompletionTime::total 5038 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 23953376916 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean 0.632532 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev 0.482296 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 8804085500 36.76% 36.76% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1 15147384416 63.24% 99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2 1819000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 23953376916 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 2980 89.89% 89.89% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M 335 10.11% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 3315 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 13224 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 13224 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12837 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 12837 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 16546 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 66215474 # ITB inst hits
-system.cpu.itb.inst_misses 13224 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3315 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3315 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 16152 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 65992511 # ITB inst hits
+system.cpu.itb.inst_misses 12837 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
@@ -536,98 +538,98 @@ system.cpu.itb.flush_tlb 64 # Nu
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 3093 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 3079 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2222 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2160 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 66228698 # ITB inst accesses
-system.cpu.itb.hits 66215474 # DTB hits
-system.cpu.itb.misses 13224 # DTB misses
-system.cpu.itb.accesses 66228698 # DTB accesses
-system.cpu.numCycles 278849039 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 66005348 # ITB inst accesses
+system.cpu.itb.hits 65992511 # DTB hits
+system.cpu.itb.misses 12837 # DTB misses
+system.cpu.itb.accesses 66005348 # DTB accesses
+system.cpu.numCycles 278422079 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 104825039 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 184547548 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 46900870 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 33079533 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 161783291 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6174948 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 189837 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 10053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 357428 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 560111 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 66214357 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1060583 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6520 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 270813408 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.831546 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.217852 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 104965644 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 184047232 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 46808005 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33018961 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 161470061 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6057656 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 190492 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 8321 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 345001 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 554797 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 65991288 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1042618 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6254 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 270563337 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.829471 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.217030 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 171553183 63.35% 63.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 29255757 10.80% 74.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 14075334 5.20% 79.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 55929134 20.65% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 171642539 63.44% 63.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 29152189 10.77% 74.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 14033587 5.19% 79.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 55735022 20.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 270813408 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.168194 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.661819 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 77914241 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 121818980 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 64632452 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3838198 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2609537 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3423128 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 486335 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 157406934 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3698656 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2609537 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 83756930 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 11780773 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 76597873 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 62631659 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 33436636 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 146755972 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 956855 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 452398 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 63697 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 16353 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 30702971 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 150428298 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 678515900 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 164385434 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 141750240 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 8678055 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2842275 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2646130 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13851175 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26402053 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 21296304 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1688639 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2128632 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 143481450 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2121615 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 143268725 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 270645 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8409947 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14700028 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 125764 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 270813408 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.529031 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.865143 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 270563337 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.168119 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.661037 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 77947938 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 121878006 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 64302075 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3866348 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2568970 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3407378 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 467954 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 156978056 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3511118 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2568970 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 83705242 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 11815574 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 76555831 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 62411209 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 33506511 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 146428655 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 918489 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 467718 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 65503 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 18531 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 30749318 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 150222579 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 676982359 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 163959933 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 10887 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 141740582 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 8481991 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2839527 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2643996 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13883864 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 26339284 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 21214862 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1704584 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2138851 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 143220356 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2117775 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 143040703 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 261102 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 8154295 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14292577 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 121903 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 270563337 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.528677 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.865235 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 182463558 67.38% 67.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 45313359 16.73% 84.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 31963465 11.80% 95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 10263701 3.79% 99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 809292 0.30% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 182376042 67.41% 67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 45230245 16.72% 84.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 31877858 11.78% 95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 10262059 3.79% 99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 817100 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
@@ -635,160 +637,160 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 270813408 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 270563337 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 7332102 32.71% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 32 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5631471 25.13% 57.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 9448597 42.16% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 7341205 32.76% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 32 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5622623 25.09% 57.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 9446888 42.15% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 95958706 66.98% 66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 113835 0.08% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 26183625 18.28% 85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21001646 14.66% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 95846012 67.01% 67.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 114315 0.08% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 8579 0.01% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26129650 18.27% 85.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 20939810 14.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 143268725 # Type of FU issued
-system.cpu.iq.rate 0.513786 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 22412202 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.156435 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 579998115 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 154018366 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 140157777 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 35590 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 165655240 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 23350 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 322841 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 143040703 # Type of FU issued
+system.cpu.iq.rate 0.513755 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 22410748 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.156674 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 579280960 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 153497939 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 139990284 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 35633 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 11369 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 165425721 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 23393 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 323902 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1496212 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 510 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18521 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 704329 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1435157 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 717 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18681 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 624055 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 88213 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 6464 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 88621 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 6303 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2609537 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1244131 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 534453 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 145804019 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 2568970 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1238473 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 546153 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 145518660 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26402053 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 21296304 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1096200 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 17993 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 500261 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18521 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 317950 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 471174 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 789124 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 142326073 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25781011 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 870919 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 26339284 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 21214862 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1094251 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 17896 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 509714 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18681 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 277446 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 471378 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 748824 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 142140939 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25734314 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 827514 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 200954 # number of nop insts executed
-system.cpu.iew.exec_refs 46653702 # number of memory reference insts executed
-system.cpu.iew.exec_branches 26511824 # Number of branches executed
-system.cpu.iew.exec_stores 20872691 # Number of stores executed
-system.cpu.iew.exec_rate 0.510405 # Inst execution rate
-system.cpu.iew.wb_sent 141939572 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 140169144 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 63244057 # num instructions producing a value
-system.cpu.iew.wb_consumers 95727511 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.502670 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.660668 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 7609153 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1995851 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 755947 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 267866819 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.512747 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.116675 # Number of insts commited each cycle
+system.cpu.iew.exec_nop 180529 # number of nop insts executed
+system.cpu.iew.exec_refs 46562087 # number of memory reference insts executed
+system.cpu.iew.exec_branches 26490837 # Number of branches executed
+system.cpu.iew.exec_stores 20827773 # Number of stores executed
+system.cpu.iew.exec_rate 0.510523 # Inst execution rate
+system.cpu.iew.wb_sent 141772110 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 140001653 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 63237844 # num instructions producing a value
+system.cpu.iew.wb_consumers 95709593 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.502840 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.660726 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 7370888 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1995872 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 715425 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 267671554 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.513087 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.118264 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 194366787 72.56% 72.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 43325916 16.17% 88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 15476786 5.78% 94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 4394475 1.64% 96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 6423634 2.40% 98.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1609805 0.60% 99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 801244 0.30% 99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 411295 0.15% 99.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1056877 0.39% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 194234773 72.56% 72.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 43288369 16.17% 88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 15457266 5.77% 94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 4372596 1.63% 96.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 6412647 2.40% 98.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1623966 0.61% 99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 797879 0.30% 99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 412108 0.15% 99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1071950 0.40% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 267866819 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 113265756 # Number of instructions committed
-system.cpu.commit.committedOps 137348019 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 267671554 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 113257711 # Number of instructions committed
+system.cpu.commit.committedOps 137338737 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 45497816 # Number of memory references committed
-system.cpu.commit.loads 24905841 # Number of loads committed
-system.cpu.commit.membars 814912 # Number of memory barriers committed
-system.cpu.commit.branches 26026635 # Number of branches committed
+system.cpu.commit.refs 45494934 # Number of memory references committed
+system.cpu.commit.loads 24904127 # Number of loads committed
+system.cpu.commit.membars 814876 # Number of memory barriers committed
+system.cpu.commit.branches 26024432 # Number of branches committed
system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 120174652 # Number of committed integer instructions.
-system.cpu.commit.function_calls 4885050 # Number of function calls committed.
+system.cpu.commit.int_insts 120166310 # Number of committed integer instructions.
+system.cpu.commit.function_calls 4884393 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 91728853 66.79% 66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 112775 0.08% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 91722407 66.79% 66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 112817 0.08% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
@@ -812,507 +814,507 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% #
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 24905841 18.13% 85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 20591975 14.99% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 24904127 18.13% 85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 20590807 14.99% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 137348019 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1056877 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 389577087 # The number of ROB reads
-system.cpu.rob.rob_writes 292847921 # The number of ROB writes
-system.cpu.timesIdled 893517 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 8035631 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 5386996546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 113110851 # Number of Instructions Simulated
-system.cpu.committedOps 137193114 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.465272 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.465272 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.405635 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.405635 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 155766897 # number of integer regfile reads
-system.cpu.int_regfile_writes 88591582 # number of integer regfile writes
-system.cpu.fp_regfile_reads 9527 # number of floating regfile reads
+system.cpu.commit.op_class_0::total 137338737 # Class of committed instruction
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+system.cpu.committedOps 137183832 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 2.461673 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.461673 # CPI: Total CPI of All Threads
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system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
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system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
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system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
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system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses
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-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126427500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 295000 # number of StoreCondReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 28052474984 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276715500 # number of ReadReq MSHR uncacheable cycles
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15468.935875 # average ReadReq mshr miss latency
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-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15061.651179 # average LoadLockedReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36973.957880 # average overall mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33705.654822 # average overall mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193341.008124 # average overall mshr uncacheable latency
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-system.cpu.icache.tags.tagsinuse 511.154178 # Cycle average of tags in use
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-system.cpu.icache.tags.avg_refs 34.032224 # Average number of references to valid blocks.
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 160 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 5483800 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47116 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 5483816 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757778 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 128080 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2556548 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2557705 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 820436 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1886845 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 149868 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 296964 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 296964 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887380 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 541203 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5667569 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2636305 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31377 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129075 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8464326 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241595648 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98327529 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47536 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218484 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 340189197 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 196985 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3053089 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.025893 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.158816 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty 822252 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 1886159 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 149793 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2772 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2777 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 297269 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 297269 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1886711 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 542312 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5665508 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2640654 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30972 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133892 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8471026 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241506672 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98506345 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48452 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 232436 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 340293905 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 194298 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3054873 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.024677 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.155138 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2974035 97.41% 97.41% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 79054 2.59% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 2979489 97.53% 97.53% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 75384 2.47% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3053089 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5400068497 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 3054873 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5401857499 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 2834904825 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 2834033066 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1303398559 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1305567557 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 19499986 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 18867982 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 74506395 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 75841383 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
+system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
@@ -1529,9 +1531,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
@@ -1552,24 +1554,24 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 43092000 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 43093000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 654000 # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy 649500 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
@@ -1577,179 +1579,177 @@ system.iobus.reqLayer14.occupancy 9000 # La
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6200500 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 6154500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 32980000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 33075500 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 187207462 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 187134993 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 36409 # number of replacements
-system.iocache.tags.tagsinuse 1.005413 # Cycle average of tags in use
-system.iocache.tags.total_refs 30 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 256609976000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 1.005413 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.062838 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.062838 # Average percentage of cache occupancy
+system.iocache.tags.replacements 36413 # number of replacements
+system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 256498269000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 1.005739 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.062859 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.062859 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328227 # Number of tag accesses
-system.iocache.tags.data_accesses 328227 # Number of data accesses
-system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits
-system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits
-system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 249 # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses
-system.iocache.demand_misses::total 249 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide 249 # number of overall misses
-system.iocache.overall_misses::total 249 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 31311877 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 31311877 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 4548827585 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 4548827585 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 31311877 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 31311877 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 31311877 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 31311877 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
+system.iocache.tags.tag_accesses 328023 # Number of tag accesses
+system.iocache.tags.data_accesses 328023 # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 223 # number of ReadReq misses
+system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
+system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses
+system.iocache.demand_misses::total 223 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 223 # number of overall misses
+system.iocache.overall_misses::total 223 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 28155877 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 28155877 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 4550151116 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 4550151116 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 28155877 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 28155877 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 28155877 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 28155877 # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.510040 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125750.510040 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125675.579086 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125675.579086 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125750.510040 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125750.510040 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125750.510040 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125750.510040 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 126259.538117 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126259.538117 # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125611.503865 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125611.503865 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 126259.538117 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126259.538117 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 126259.538117 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126259.538117 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 36160 # number of writebacks
-system.iocache.writebacks::total 36160 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 36195 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 36195 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 18861877 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 18861877 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737619112 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 2737619112 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 18861877 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 18861877 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 18861877 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 18861877 # number of overall MSHR miss cycles
+system.iocache.writebacks::writebacks 36190 # number of writebacks
+system.iocache.writebacks::total 36190 # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 223 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 223 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 17005877 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 17005877 # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737535612 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 2737535612 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 17005877 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 17005877 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 17005877 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 17005877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.510040 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.510040 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75635.284211 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75635.284211 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.510040 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75750.510040 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.510040 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75750.510040 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76259.538117 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76259.538117 # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75572.427451 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75572.427451 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 76259.538117 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76259.538117 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 76259.538117 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76259.538117 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 34133 # Transaction distribution
-system.membus.trans_dist::ReadResp 67562 # Transaction distribution
+system.membus.trans_dist::ReadReq 34132 # Transaction distribution
+system.membus.trans_dist::ReadResp 67504 # Transaction distribution
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.trans_dist::WriteResp 27585 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 124963 # Transaction distribution
-system.membus.trans_dist::CleanEvict 7938 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 125428 # Transaction distribution
+system.membus.trans_dist::CleanEvict 7780 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4584 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 133523 # Transaction distribution
-system.membus.trans_dist::ReadExResp 133523 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 33430 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution
+system.membus.trans_dist::ReadExReq 133644 # Transaction distribution
+system.membus.trans_dist::ReadExResp 133644 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 33373 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450084 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557654 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 630522 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450558 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558126 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 631001 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16402396 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565801 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 18881001 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 513 # Total snoops (count)
-system.membus.snoop_fanout::samples 402383 # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16435996 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16599385 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 18916505 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 487 # Total snoops (count)
+system.membus.snoop_fanout::samples 402766 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 402383 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 402766 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 402383 # Request fanout histogram
-system.membus.reqLayer0.occupancy 83620000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 402766 # Request fanout histogram
+system.membus.reqLayer0.occupancy 83667000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1740000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 873794635 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 876048370 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 978214250 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 978678250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 1313623 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 932631673..a5289b78c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1,160 +1,164 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.824888 # Number of seconds simulated
-sim_ticks 2824887572500 # Number of ticks simulated
-final_tick 2824887572500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.824845 # Number of seconds simulated
+sim_ticks 2824844934500 # Number of ticks simulated
+final_tick 2824844934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 216723 # Simulator instruction rate (inst/s)
-host_op_rate 262904 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4977623525 # Simulator tick rate (ticks/s)
-host_mem_usage 565980 # Number of bytes of host memory used
-host_seconds 567.52 # Real time elapsed on the host
-sim_insts 122993828 # Number of instructions simulated
-sim_ops 149202488 # Number of ops (including micro ops) simulated
+host_inst_rate 301884 # Simulator instruction rate (inst/s)
+host_op_rate 366207 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6935241973 # Simulator tick rate (ticks/s)
+host_mem_usage 588164 # Number of bytes of host memory used
+host_seconds 407.32 # Real time elapsed on the host
+sim_insts 122962642 # Number of instructions simulated
+sim_ops 149162643 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 541924 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4139684 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 101376 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 929664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 333376 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 1678720 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker 4352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 417152 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 3014592 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 540004 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4201700 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 117312 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 902784 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 1664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 307648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 1658880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker 4224 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 418176 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 2992192 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11164040 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 541924 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 101376 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 333376 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 417152 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1393828 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8400768 # Number of bytes written to this memory
+system.physmem.bytes_read::total 11145864 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 540004 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 117312 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 307648 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 418176 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1383140 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8393280 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8418292 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8410804 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 16921 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 65202 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1584 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 14526 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 5209 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 26230 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker 68 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 6518 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 47103 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 16891 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 66171 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1833 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 14106 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 26 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 4807 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 25920 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker 66 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 6534 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 46753 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 183411 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 131262 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 183127 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 131145 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 135643 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 135526 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 68 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 191839 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1465433 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35887 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 329098 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 702 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 118014 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 594261 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker 1541 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 147670 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 1067155 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 191162 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1487409 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6932075 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bytesWritten 4461760 # Total number of bytes written to DRAM
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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-system.physmem.totGap 2823321303500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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@@ -182,172 +186,170 @@ system.physmem.rdQLenPdf::28 0 # Wh
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+system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 32 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 39182 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 275.494666 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 163.171776 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 307.907235 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 16210 41.37% 41.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 9497 24.24% 65.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 3855 9.84% 75.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2019 5.15% 80.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1646 4.20% 84.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1042 2.66% 87.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 570 1.45% 88.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 566 1.44% 90.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 3777 9.64% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 39182 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 3537 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 28.251343 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 474.824507 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 3535 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 3587 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 3587 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.435461 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.049607 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 11.402559 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3 5 0.14% 0.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7 1 0.03% 0.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11 2 0.06% 0.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 3 0.08% 0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 3190 88.93% 89.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 86 2.40% 91.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 46 1.28% 92.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 29 0.81% 93.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 24 0.67% 94.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 7 0.20% 94.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 31 0.86% 95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 8 0.22% 95.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 55 1.53% 97.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 9 0.25% 97.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 4 0.11% 97.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 7 0.20% 97.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 27 0.75% 98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 2 0.06% 98.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 3 0.08% 98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 13 0.36% 99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 26 0.72% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.03% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 1 0.03% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 4 0.11% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 1 0.03% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 1 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 3587 # Writes before turning the bus around for reads
-system.physmem.totQLat 1320327750 # Total ticks spent queuing
-system.physmem.totMemAccLat 3217284000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 505855000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13050.46 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 3537 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 3537 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.426915 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.022626 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 11.137247 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 7 0.20% 0.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 2 0.06% 0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 2 0.06% 0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 5 0.14% 0.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 3142 88.83% 89.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 84 2.37% 91.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 38 1.07% 92.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 37 1.05% 93.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 22 0.62% 94.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 9 0.25% 94.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 25 0.71% 95.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 6 0.17% 95.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 52 1.47% 97.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 8 0.23% 97.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 5 0.14% 97.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 10 0.28% 97.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 31 0.88% 98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 1 0.03% 98.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 1 0.03% 98.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 15 0.42% 99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 29 0.82% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.03% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.03% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 1 0.03% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 3 0.08% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 3537 # Writes before turning the bus around for reads
+system.physmem.totQLat 1310108250 # Total ticks spent queuing
+system.physmem.totMemAccLat 3184227000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 499765000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13107.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31800.46 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 31857.24 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.26 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.27 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 20.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 81754 # Number of row buffer hits during reads
-system.physmem.writeRowHits 49701 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 71.27 # Row buffer hit rate for writes
-system.physmem.avgGap 16510554.34 # Average gap between requests
-system.physmem.pageHitRate 76.92 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 156287880 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 85131750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 404929200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 229929840 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 179785114080 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 73278235845 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1622828751000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1876768379595 # Total energy per rank (pJ)
-system.physmem_0.averagePower 667.450508 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2640406091750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 91914680000 # Time in different power states
+system.physmem.avgWrQLen 28.41 # Average write queue length when enqueuing
+system.physmem.readRowHits 80619 # Number of row buffer hits during reads
+system.physmem.writeRowHits 48864 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 80.66 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 71.09 # Row buffer hit rate for writes
+system.physmem.avgGap 16727764.68 # Average gap between requests
+system.physmem.pageHitRate 76.76 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 156212280 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 85094625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 402051000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 227525760 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 179782062720 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 73198076175 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1622869382250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1876720404810 # Total energy per rank (pJ)
+system.physmem_0.averagePower 667.445189 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2640467902750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 91913120000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 20314514250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 20211500000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 141802920 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 77215875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 384181200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 221823360 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 179785114080 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 72833545215 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1617851985750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1871295668400 # Total energy per rank (pJ)
-system.physmem_1.averagePower 667.627988 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2641096901750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 91914680000 # Time in different power states
+system.physmem_1.actEnergy 140003640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 76213500 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 377559000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 217734480 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 179782062720 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 72424788525 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1619952843000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1872971204865 # Total energy per rank (pJ)
+system.physmem_1.averagePower 667.534203 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2641599878750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 91913120000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 19627144250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 19067953250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
@@ -397,47 +399,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 4962 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 4962 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 4962 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 4962 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 4962 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 53085003580 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 1.356186 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -18908123670 -35.62% -35.62% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 71993127250 135.62% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 53085003580 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 2699 66.41% 66.41% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1365 33.59% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 4064 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4962 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 4956 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 4956 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 4956 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 4956 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 4956 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 57378110626 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.254713 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -14614977624 -25.47% -25.47% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 71993088250 125.47% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 57378110626 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 2714 66.86% 66.86% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1345 33.14% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 4059 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4956 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4962 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4064 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4956 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4059 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4064 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 9026 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4059 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 9015 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 11954908 # DTB read hits
-system.cpu0.dtb.read_misses 4164 # DTB read misses
-system.cpu0.dtb.write_hits 9290329 # DTB write hits
-system.cpu0.dtb.write_misses 798 # DTB write misses
-system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits 12035285 # DTB read hits
+system.cpu0.dtb.read_misses 4159 # DTB read misses
+system.cpu0.dtb.write_hits 9387276 # DTB write hits
+system.cpu0.dtb.write_misses 797 # DTB write misses
+system.cpu0.dtb.flush_tlb 170 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 344 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2862 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 2853 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 723 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 725 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 165 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 11959072 # DTB read accesses
-system.cpu0.dtb.write_accesses 9291127 # DTB write accesses
+system.cpu0.dtb.read_accesses 12039444 # DTB read accesses
+system.cpu0.dtb.write_accesses 9388073 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 21245237 # DTB hits
-system.cpu0.dtb.misses 4962 # DTB misses
-system.cpu0.dtb.accesses 21250199 # DTB accesses
+system.cpu0.dtb.hits 21422561 # DTB hits
+system.cpu0.dtb.misses 4956 # DTB misses
+system.cpu0.dtb.accesses 21427517 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -467,649 +469,652 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 2303 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 2303 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 2303 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 2303 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 2303 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 53085003580 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 1.356188 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -18908264170 -35.62% -35.62% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 71993267750 135.62% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 53085003580 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 1258 73.83% 73.83% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 446 26.17% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 1704 # Table walker page sizes translated
+system.cpu0.itb.walker.walks 2296 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 2296 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 2296 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 2296 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 2296 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 57378110626 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 1.254717 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -14615152624 -25.47% -25.47% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 71993263250 125.47% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 57378110626 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 1260 74.03% 74.03% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 442 25.97% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 1702 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2303 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2303 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2296 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2296 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1704 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1704 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 4007 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 57101564 # ITB inst hits
-system.cpu0.itb.inst_misses 2303 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1702 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1702 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 3998 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 57357207 # ITB inst hits
+system.cpu0.itb.inst_misses 2296 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb 170 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 344 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1710 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1708 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 57103867 # ITB inst accesses
-system.cpu0.itb.hits 57101564 # DTB hits
-system.cpu0.itb.misses 2303 # DTB misses
-system.cpu0.itb.accesses 57103867 # DTB accesses
-system.cpu0.numCycles 69056557 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 57359503 # ITB inst accesses
+system.cpu0.itb.hits 57357207 # DTB hits
+system.cpu0.itb.misses 2296 # DTB misses
+system.cpu0.itb.accesses 57359503 # DTB accesses
+system.cpu0.numCycles 69413199 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 3089 # number of quiesce instructions executed
-system.cpu0.committedInsts 55689685 # Number of instructions committed
-system.cpu0.committedOps 67533645 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 59242517 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 4477 # Number of float alu accesses
-system.cpu0.num_func_calls 5745226 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 7381576 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 59242517 # number of integer instructions
-system.cpu0.num_fp_insts 4477 # number of float instructions
-system.cpu0.num_int_register_reads 109364432 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 41082844 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3371 # number of times the floating registers were read
+system.cpu0.kern.inst.quiesce 3088 # number of quiesce instructions executed
+system.cpu0.committedInsts 55950811 # Number of instructions committed
+system.cpu0.committedOps 67895775 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 59559074 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 4429 # Number of float alu accesses
+system.cpu0.num_func_calls 5748533 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 7418510 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 59559074 # number of integer instructions
+system.cpu0.num_fp_insts 4429 # number of float instructions
+system.cpu0.num_int_register_reads 109971244 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 41296090 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 3323 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1108 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 205589269 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 25204829 # number of times the CC registers were written
-system.cpu0.num_mem_refs 21807623 # number of memory refs
-system.cpu0.num_load_insts 12096876 # Number of load instructions
-system.cpu0.num_store_insts 9710747 # Number of store instructions
-system.cpu0.num_idle_cycles 65266459.651417 # Number of idle cycles
-system.cpu0.num_busy_cycles 3790097.348583 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.054884 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.945116 # Percentage of idle cycles
-system.cpu0.Branches 13519232 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 2179 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 46765026 68.14% 68.15% # Class of executed instruction
-system.cpu0.op_class::IntMult 50017 0.07% 68.22% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 3786 0.01% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.22% # Class of executed instruction
-system.cpu0.op_class::MemRead 12096876 17.63% 85.85% # Class of executed instruction
-system.cpu0.op_class::MemWrite 9710747 14.15% 100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads 206667111 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 25287842 # number of times the CC registers were written
+system.cpu0.num_mem_refs 21990124 # number of memory refs
+system.cpu0.num_load_insts 12179885 # Number of load instructions
+system.cpu0.num_store_insts 9810239 # Number of store instructions
+system.cpu0.num_idle_cycles 65532351.821320 # Number of idle cycles
+system.cpu0.num_busy_cycles 3880847.178680 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.055909 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.944091 # Percentage of idle cycles
+system.cpu0.Branches 13556627 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 2177 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 46939683 68.04% 68.05% # Class of executed instruction
+system.cpu0.op_class::IntMult 49866 0.07% 68.12% # Class of executed instruction
+system.cpu0.op_class::IntDiv 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 3817 0.01% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.12% # Class of executed instruction
+system.cpu0.op_class::MemRead 12179885 17.66% 85.78% # Class of executed instruction
+system.cpu0.op_class::MemWrite 9810239 14.22% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 68628631 # Class of executed instruction
-system.cpu0.dcache.tags.replacements 834080 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.996936 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 46068701 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 834592 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 55.199069 # Average number of references to valid blocks.
+system.cpu0.op_class::total 68985667 # Class of executed instruction
+system.cpu0.dcache.tags.replacements 833417 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.996599 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 46053699 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 833929 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 55.224964 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.869099 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 12.090258 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.459372 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data 17.578207 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929432 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.023614 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012616 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data 0.034332 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.718134 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.522877 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.743087 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data 15.012501 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.936949 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022506 # Average percentage of cache occupancy
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+system.cpu0.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 193256162 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 193256162 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 11356893 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 3664656 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 4328434 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data 6496122 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 25846105 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 8947209 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 2625670 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 3368119 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data 3982538 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 18923536 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 168512 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data 54432 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data 75016 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu3.data 87845 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 385805 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 206942 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74426 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 78729 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 90116 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 450213 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 207891 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76401 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data 81635 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu3.data 94165 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 460092 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 20304102 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 6290326 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 7696553 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data 10478660 # number of demand (read+write) hits
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-system.cpu0.dcache.overall_hits::cpu2.data 7771569 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data 10566505 # number of overall hits
-system.cpu0.dcache.overall_hits::total 45155446 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 160217 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 56728 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 95563 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data 209826 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 522334 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 126244 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 30952 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data 98555 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data 1104293 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1360044 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 49130 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data 18052 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data 32658 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu3.data 39211 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 139051 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3529 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2613 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3858 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8177 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 18177 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu3.data 29 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 286461 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 87680 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data 194118 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data 1314119 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1882378 # number of demand (read+write) misses
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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 39310.344828 # average StoreCondReq miss latency
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-system.cpu0.dcache.avg_blocked_cycles::no_targets 62.912656 # average number of cycles each access was blocked
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+system.cpu0.dcache.overall_accesses::total 47152619 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014066 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.015194 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.021522 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031007 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.019740 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013971 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011332 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.028355 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.218156 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.066740 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.228899 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.247525 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.300778 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.306138 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.264544 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018231 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.033759 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.044189 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.082806 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038487 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000009 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000273 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000059 # miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013587 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.024519 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data 0.111670 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.040182 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016275 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.016220 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.028257 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data 0.113722 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.042675 # miss rate for overall accesses
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14930.048166 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 18005.736249 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11816.788977 # average ReadReq miss latency
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+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67046.784317 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70750.347147 # average WriteReq miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13810.878661 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14281.250000 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.003551 # average LoadLockedReq miss latency
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+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 32703.703704 # average StoreCondReq miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 49193.272799 # average overall miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::total 45804.041517 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 501932 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 35431 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 12377 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 549 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.553607 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 64.537341 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 691847 # number of writebacks
-system.cpu0.dcache.writebacks::total 691847 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 79 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 15182 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 96539 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 111800 # number of ReadReq MSHR hits
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-system.cpu0.dcache.WriteReq_mshr_hits::total 1060489 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1591 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2377 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5420 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9388 # number of LoadLockedReq MSHR hits
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-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 28713 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 69423 # number of SoftPFReq MSHR misses
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-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2757 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5260 # number of LoadLockedReq MSHR misses
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-system.cpu0.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 5504 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 8482 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17415 # number of ReadReq MSHR uncacheable
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-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4256 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6706 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13744 # number of WriteReq MSHR uncacheable
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-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 9760 # number of overall MSHR uncacheable misses
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-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31159 # number of overall MSHR uncacheable misses
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-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3885775500 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 25499000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 42983000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 83849000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 1111000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1111000 # number of StoreCondReq MSHR miss cycles
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-system.cpu0.dcache.demand_mshr_miss_latency::total 15738138942 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3047931000 # number of overall MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_miss_latency::total 16787422942 # number of overall MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3530288000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 493653500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 837467000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1430846952 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2761967452 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1098106500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1930026500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 3264122452 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6292255452 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015223 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018169 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016894 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009493 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011651 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015490 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017429 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008544 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.245213 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.213013 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.225987 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.132271 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.013266 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.017933 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.028049 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.011230 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000308 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000063 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013735 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016992 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017125 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.009081 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016336 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019631 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019351 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.010451 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16905.744144 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14522.076113 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15542.674799 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15523.418306 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59996.042259 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66493.547366 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72464.797451 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68387.831367 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13122.538539 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13899.568364 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17317.713231 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15114.356913 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15036.203523 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17217.420662 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15590.496917 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15940.874525 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 38310.344828 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 38310.344828 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 32130.809009 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35336.634845 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40532.971235 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37150.846833 # average overall mshr miss latency
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-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201940.224397 # average overall mshr uncacheable latency
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+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31407 # number of overall MSHR uncacheable misses
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+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 488593000 # number of SoftPFReq MSHR miss cycles
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 21022000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 38674500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 858000 # number of StoreCondReq MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6342099452 # number of overall MSHR uncacheable cycles
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+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018086 # mshr miss rate for ReadReq accesses
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+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015450 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017507 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008439 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.243899 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.209461 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.225402 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.130193 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.013171 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.015432 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.025271 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010015 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000273 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000054 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013576 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016930 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017099 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.008977 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016168 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019535 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019297 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.010324 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17131.119965 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14546.692533 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15573.979638 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15599.814496 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59235.825815 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66654.455352 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72468.578376 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68346.367667 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13247.159573 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13908.850109 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17403.134461 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15175.116153 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16223.800196 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 16790.734824 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16001.034340 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16260.341151 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 34320 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 34320 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31749.890189 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35401.451444 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40680.604485 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37165.479930 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28608.600520 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32282.945987 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37811.529763 # average overall mshr miss latency
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+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177764.764058 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199615.453248 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215261.811258 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202701.441924 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179304.958391 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 197907.271054 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 212378.140854 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200959.523267 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178456.328818 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 198869.346734 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 213989.919649 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201932.672716 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1989175 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.436154 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 93885937 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1989687 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 47.186285 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 12780860000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 432.324798 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.897610 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 29.477932 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst 38.735813 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.844384 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.021284 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst 0.057574 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst 0.075656 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.998899 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 1977299 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.446080 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 94017526 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 1977811 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 47.536153 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 12783647500 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 433.555546 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.959606 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst 24.981249 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst 41.949679 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.846788 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.021405 # Average percentage of cache occupancy
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+system.cpu0.icache.tags.occ_percent::cpu3.inst 0.081933 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.998918 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 227 # Occupied blocks per task id
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-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13570.497436 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13356.068530 # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks 1977299 # number of writebacks
+system.cpu0.icache.writebacks::total 1977299 # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 43224 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 43224 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst 43224 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 43224 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst 43224 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 43224 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 205937 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 497244 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 544816 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 1247997 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 205937 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 497244 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst 544816 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 1247997 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 205937 # number of overall MSHR misses
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+system.cpu0.icache.overall_mshr_misses::cpu3.inst 544816 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 1247997 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2700747000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6566263500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7404631489 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 16671641989 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2700747000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6566263500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7404631489 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 16671641989 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2700747000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6566263500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7404631489 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 16671641989 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011382 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045949 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.055790 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012995 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011382 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045949 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.055790 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.012995 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011382 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045949 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.055790 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.012995 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13114.433055 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13205.314695 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13591.068341 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13358.719603 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13114.433055 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13205.314695 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13591.068341 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13358.719603 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13114.433055 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13205.314695 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13591.068341 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13358.719603 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -1140,60 +1145,55 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 1864 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 1864 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 484 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1380 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 1864 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 1864 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 1864 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 1576 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 14376.903553 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 12683.026885 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 6626.503749 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::4096-6143 273 17.32% 17.32% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::6144-8191 48 3.05% 20.37% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::10240-12287 463 29.38% 49.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::12288-14335 60 3.81% 53.55% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::14336-16383 242 15.36% 68.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-18431 70 4.44% 73.35% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::22528-24575 399 25.32% 98.67% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-26623 21 1.33% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 1576 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks 1898 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 1898 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 494 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1404 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 1898 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 1898 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 1898 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 1607 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 13317.672682 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11568.146418 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 7309.305815 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383 1216 75.67% 75.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767 390 24.27% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 1607 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1094 69.42% 69.42% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 482 30.58% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 1576 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1864 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K 1115 69.38% 69.38% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 492 30.62% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 1607 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1898 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1864 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1576 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1898 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1607 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1576 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 3440 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1607 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 3505 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 3874336 # DTB read hits
-system.cpu1.dtb.read_misses 1644 # DTB read misses
-system.cpu1.dtb.write_hits 2735867 # DTB write hits
-system.cpu1.dtb.write_misses 220 # DTB write misses
-system.cpu1.dtb.flush_tlb 150 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 124 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits 3875526 # DTB read hits
+system.cpu1.dtb.read_misses 1673 # DTB read misses
+system.cpu1.dtb.write_hits 2730535 # DTB write hits
+system.cpu1.dtb.write_misses 225 # DTB write misses
+system.cpu1.dtb.flush_tlb 151 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 137 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1077 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1104 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 240 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 62 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 3875980 # DTB read accesses
-system.cpu1.dtb.write_accesses 2736087 # DTB write accesses
+system.cpu1.dtb.perms_faults 65 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 3877199 # DTB read accesses
+system.cpu1.dtb.write_accesses 2730760 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 6610203 # DTB hits
-system.cpu1.dtb.misses 1864 # DTB misses
-system.cpu1.dtb.accesses 6612067 # DTB accesses
+system.cpu1.dtb.hits 6606061 # DTB hits
+system.cpu1.dtb.misses 1898 # DTB misses
+system.cpu1.dtb.accesses 6607959 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1223,89 +1223,89 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 917 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 917 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 740 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 917 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 917 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 917 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 666 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 13797.297297 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 12192.351828 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 6305.163791 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-6143 141 21.17% 21.17% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.15% 21.32% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::10240-12287 171 25.68% 47.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-14335 40 6.01% 53.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::14336-16383 171 25.68% 78.68% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::22528-24575 137 20.57% 99.25% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-26623 5 0.75% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 666 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks 937 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 937 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 756 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 937 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 937 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 937 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 679 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 12754.050074 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11061.595827 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 6405.303661 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143 193 28.42% 28.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::6144-8191 2 0.29% 28.72% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287 178 26.22% 54.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335 59 8.69% 63.62% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::14336-16383 121 17.82% 81.44% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575 122 17.97% 99.41% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-26623 4 0.59% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 679 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 489 73.42% 73.42% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 177 26.58% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 666 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 498 73.34% 73.34% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 181 26.66% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 679 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 917 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 917 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 937 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 937 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 666 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 666 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 1583 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 18092232 # ITB inst hits
-system.cpu1.itb.inst_misses 917 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 679 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 679 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 1616 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 18092512 # ITB inst hits
+system.cpu1.itb.inst_misses 937 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 150 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 124 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb 151 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 137 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 697 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 710 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 18093149 # ITB inst accesses
-system.cpu1.itb.hits 18092232 # DTB hits
-system.cpu1.itb.misses 917 # DTB misses
-system.cpu1.itb.accesses 18093149 # DTB accesses
-system.cpu1.numCycles 144011117 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 18093449 # ITB inst accesses
+system.cpu1.itb.hits 18092512 # DTB hits
+system.cpu1.itb.misses 937 # DTB misses
+system.cpu1.itb.accesses 18093449 # DTB accesses
+system.cpu1.numCycles 144009903 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.committedInsts 17422083 # Number of instructions committed
-system.cpu1.committedOps 20907241 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 18575942 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 1372 # Number of float alu accesses
-system.cpu1.num_func_calls 1991871 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 2240039 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 18575942 # number of integer instructions
-system.cpu1.num_fp_insts 1372 # number of float instructions
-system.cpu1.num_int_register_reads 34372457 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 13029259 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 1112 # number of times the floating registers were read
+system.cpu1.committedInsts 17421496 # Number of instructions committed
+system.cpu1.committedOps 20899704 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 18577797 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 1420 # Number of float alu accesses
+system.cpu1.num_func_calls 1993621 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 2230861 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 18577797 # number of integer instructions
+system.cpu1.num_fp_insts 1420 # number of float instructions
+system.cpu1.num_int_register_reads 34369600 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 13035963 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 1160 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 260 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 76102433 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 7596638 # number of times the CC registers were written
-system.cpu1.num_mem_refs 6802434 # number of memory refs
-system.cpu1.num_load_insts 3915999 # Number of load instructions
-system.cpu1.num_store_insts 2886435 # Number of store instructions
-system.cpu1.num_idle_cycles 136776220.801950 # Number of idle cycles
-system.cpu1.num_busy_cycles 7234896.198050 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.050238 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.949762 # Percentage of idle cycles
-system.cpu1.Branches 4344241 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 21 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 14689053 68.29% 68.29% # Class of executed instruction
-system.cpu1.op_class::IntMult 16409 0.08% 68.37% # Class of executed instruction
+system.cpu1.num_cc_register_reads 76091586 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 7577345 # number of times the CC registers were written
+system.cpu1.num_mem_refs 6800182 # number of memory refs
+system.cpu1.num_load_insts 3918123 # Number of load instructions
+system.cpu1.num_store_insts 2882059 # Number of store instructions
+system.cpu1.num_idle_cycles 136636530.852378 # Number of idle cycles
+system.cpu1.num_busy_cycles 7373372.147622 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.051200 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.948800 # Percentage of idle cycles
+system.cpu1.Branches 4337148 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 23 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 14686036 68.30% 68.30% # Class of executed instruction
+system.cpu1.op_class::IntMult 16352 0.08% 68.37% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 68.37% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 68.37% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 68.37% # Class of executed instruction
@@ -1329,24 +1329,28 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.37% # Cl
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.37% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.37% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 960 0.00% 68.37% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 68.37% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.37% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.37% # Class of executed instruction
-system.cpu1.op_class::MemRead 3915999 18.21% 86.58% # Class of executed instruction
-system.cpu1.op_class::MemWrite 2886435 13.42% 100.00% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 955 0.00% 68.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 68.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.38% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.38% # Class of executed instruction
+system.cpu1.op_class::MemRead 3918123 18.22% 86.60% # Class of executed instruction
+system.cpu1.op_class::MemWrite 2882059 13.40% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 21508877 # Class of executed instruction
-system.cpu2.branchPred.lookups 5793612 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 2980826 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 510173 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 3341090 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 2404622 # Number of BTB hits
+system.cpu1.op_class::total 21503548 # Class of executed instruction
+system.cpu2.branchPred.lookups 5770264 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 2970192 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 504477 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 3340147 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 1745677 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 71.971183 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 1623448 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 331512 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 52.263478 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 1611184 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 331954 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.indirectLookups 670735 # Number of indirect predictor lookups.
+system.cpu2.branchPred.indirectHits 637081 # Number of indirect target hits.
+system.cpu2.branchPred.indirectMisses 33654 # Number of indirect misses.
+system.cpu2.branchPredindirectMispredicted 21230 # Number of mispredicted indirect branches.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1376,54 +1380,60 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.dtb.walker.walks 13179 # Table walker walks requested
-system.cpu2.dtb.walker.walksShort 13179 # Table walker walks initiated with short descriptors
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8247 # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4932 # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples 13179 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0 13179 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total 13179 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples 2214 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 13311.653117 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 11619.348750 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 8511.573667 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-32767 2213 99.95% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-294911 1 0.05% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total 2214 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walks 12712 # Table walker walks requested
+system.cpu2.dtb.walker.walksShort 12712 # Table walker walks initiated with short descriptors
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8004 # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4708 # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples 12712 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0 12712 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total 12712 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples 2182 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 12059.578368 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 10400.362655 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 6359.555797 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::2048-4095 13 0.60% 0.60% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::4096-6143 665 30.48% 31.07% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::6144-8191 1 0.05% 31.12% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::10240-12287 773 35.43% 66.54% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::12288-14335 182 8.34% 74.89% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::14336-16383 171 7.84% 82.72% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::22528-24575 366 16.77% 99.50% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::24576-26623 11 0.50% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total 2182 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 2000052000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000052000 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000052000 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K 1376 62.15% 62.15% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::1M 838 37.85% 100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total 2214 # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 13179 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K 1365 62.56% 62.56% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::1M 817 37.44% 100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total 2182 # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12712 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 13179 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2214 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12712 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2182 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2214 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total 15393 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2182 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total 14894 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 4658745 # DTB read hits
-system.cpu2.dtb.read_misses 11783 # DTB read misses
-system.cpu2.dtb.write_hits 3577519 # DTB write hits
-system.cpu2.dtb.write_misses 1396 # DTB write misses
-system.cpu2.dtb.flush_tlb 154 # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva 176 # Number of times TLB was flushed by MVA
+system.cpu2.dtb.read_hits 4621518 # DTB read hits
+system.cpu2.dtb.read_misses 11435 # DTB read misses
+system.cpu2.dtb.write_hits 3537262 # DTB write hits
+system.cpu2.dtb.write_misses 1277 # DTB write misses
+system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed
+system.cpu2.dtb.flush_tlb_mva 162 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 1514 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 206 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 331 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries 1476 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 227 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 324 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 4670528 # DTB read accesses
-system.cpu2.dtb.write_accesses 3578915 # DTB write accesses
+system.cpu2.dtb.perms_faults 121 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 4632953 # DTB read accesses
+system.cpu2.dtb.write_accesses 3538539 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 8236264 # DTB hits
-system.cpu2.dtb.misses 13179 # DTB misses
-system.cpu2.dtb.accesses 8249443 # DTB accesses
+system.cpu2.dtb.hits 8158780 # DTB hits
+system.cpu2.dtb.misses 12712 # DTB misses
+system.cpu2.dtb.accesses 8171492 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1453,82 +1463,122 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.walker.walks 1381 # Table walker walks requested
-system.cpu2.itb.walker.walksShort 1381 # Table walker walks initiated with short descriptors
-system.cpu2.itb.walker.walksShortTerminationLevel::Level1 251 # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1130 # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples 1381 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0 1381 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total 1381 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples 875 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 13237.714286 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 11667.376673 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 6208.114147 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::4096-6143 218 24.91% 24.91% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::6144-8191 1 0.11% 25.03% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::10240-12287 241 27.54% 52.57% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::12288-14335 34 3.89% 56.46% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::14336-16383 216 24.69% 81.14% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::22528-24575 162 18.51% 99.66% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::24576-26623 3 0.34% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total 875 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walks 1416 # Table walker walks requested
+system.cpu2.itb.walker.walksShort 1416 # Table walker walks initiated with short descriptors
+system.cpu2.itb.walker.walksShortTerminationLevel::Level1 256 # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1160 # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples 1416 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0 1416 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total 1416 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples 870 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 12294.252874 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 10677.468386 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 6303.110021 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::4096-6143 282 32.41% 32.41% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::6144-8191 1 0.11% 32.53% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::10240-12287 251 28.85% 61.38% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::12288-14335 36 4.14% 65.52% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::14336-16383 152 17.47% 82.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::16384-18431 1 0.11% 83.10% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::22528-24575 145 16.67% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::24576-26623 2 0.23% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total 870 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 2000037500 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000037500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000037500 # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K 624 71.31% 71.31% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::1M 251 28.69% 100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total 875 # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K 614 70.57% 70.57% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::1M 256 29.43% 100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total 870 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1381 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1381 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1416 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1416 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 875 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total 875 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total 2256 # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits 10914034 # ITB inst hits
-system.cpu2.itb.inst_misses 1381 # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 870 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total 870 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total 2286 # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits 10823576 # ITB inst hits
+system.cpu2.itb.inst_misses 1416 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.flush_tlb 154 # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva 176 # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb_mva 162 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 885 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries 879 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 1797 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 1762 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 10915415 # ITB inst accesses
-system.cpu2.itb.hits 10914034 # DTB hits
-system.cpu2.itb.misses 1381 # DTB misses
-system.cpu2.itb.accesses 10915415 # DTB accesses
-system.cpu2.numCycles 1393570543 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 10824992 # ITB inst accesses
+system.cpu2.itb.hits 10823576 # DTB hits
+system.cpu2.itb.misses 1416 # DTB misses
+system.cpu2.itb.accesses 10824992 # DTB accesses
+system.cpu2.numCycles 1395003779 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 20500176 # Number of instructions committed
-system.cpu2.committedOps 24831062 # Number of ops (including micro ops) committed
-system.cpu2.discardedOps 1467933 # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends 564 # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles 4256215364 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi 67.978467 # CPI: cycles per instruction
-system.cpu2.ipc 0.014711 # IPC: instructions per cycle
+system.cpu2.committedInsts 20361751 # Number of instructions committed
+system.cpu2.committedOps 24653563 # Number of ops (including micro ops) committed
+system.cpu2.discardedOps 1458677 # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends 555 # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles 4254696736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi 68.510993 # CPI: cycles per instruction
+system.cpu2.ipc 0.014596 # IPC: instructions per cycle
+system.cpu2.op_class_0::No_OpClass 53 0.00% 0.00% # Class of committed instruction
+system.cpu2.op_class_0::IntAlu 16404326 66.54% 66.54% # Class of committed instruction
+system.cpu2.op_class_0::IntMult 20837 0.08% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::IntDiv 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatAdd 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatCmp 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatCvt 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatMult 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatDiv 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdAdd 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdAlu 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdCmp 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdCvt 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdMisc 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdMult 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdShift 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.62% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMisc 1376 0.01% 66.63% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.63% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.63% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.63% # Class of committed instruction
+system.cpu2.op_class_0::MemRead 4532751 18.39% 85.02% # Class of committed instruction
+system.cpu2.op_class_0::MemWrite 3694220 14.98% 100.00% # Class of committed instruction
+system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu2.op_class_0::total 24653563 # Class of committed instruction
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.tickCycles 42639934 # Number of cycles that the object actually ticked
-system.cpu2.idleCycles 1350930609 # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups 13289019 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 7253126 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 312439 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 8263558 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 6253160 # Number of BTB hits
+system.cpu2.tickCycles 42378112 # Number of cycles that the object actually ticked
+system.cpu2.idleCycles 1352625667 # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups 13251998 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 7208175 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 300007 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 8273745 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 4241517 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 75.671521 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 3098416 # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect 16246 # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct 51.264778 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 3096619 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect 16788 # Number of incorrect RAS predictions.
+system.cpu3.branchPred.indirectLookups 2038227 # Number of indirect predictor lookups.
+system.cpu3.branchPred.indirectHits 1978271 # Number of indirect target hits.
+system.cpu3.branchPred.indirectMisses 59956 # Number of indirect misses.
+system.cpu3.branchPredindirectMispredicted 18256 # Number of mispredicted indirect branches.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1558,87 +1608,84 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.dtb.walker.walks 32928 # Table walker walks requested
-system.cpu3.dtb.walker.walksShort 32928 # Table walker walks initiated with short descriptors
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11539 # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7550 # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore 13839 # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples 19089 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean 453.769186 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 3060.650979 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-8191 18684 97.88% 97.88% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::8192-16383 255 1.34% 99.21% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::16384-24575 92 0.48% 99.70% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::24576-32767 26 0.14% 99.83% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::32768-40959 12 0.06% 99.90% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::40960-49151 11 0.06% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::49152-57343 5 0.03% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-73727 3 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total 19089 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples 6197 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 13294.578022 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 10885.248950 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 8635.189295 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-16383 4539 73.25% 73.25% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1528 24.66% 97.90% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::32768-49151 104 1.68% 99.58% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::49152-65535 10 0.16% 99.74% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-81919 13 0.21% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total 6197 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -8048051564 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean 0.976034 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-1 -8093653564 100.57% 100.57% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::2-3 33199000 -0.41% 100.15% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-5 6574500 -0.08% 100.07% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::6-7 2215500 -0.03% 100.04% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-9 1246000 -0.02% 100.03% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::10-11 692500 -0.01% 100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-13 364000 -0.00% 100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::14-15 852000 -0.01% 100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-17 153000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::18-19 182500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-21 65500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::22-23 10500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-25 20000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::26-27 4500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-29 3500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::30-31 19000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -8048051564 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K 1804 69.07% 69.07% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::1M 808 30.93% 100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total 2612 # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 32928 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walks 33988 # Table walker walks requested
+system.cpu3.dtb.walker.walksShort 33988 # Table walker walks initiated with short descriptors
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11189 # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8109 # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore 14690 # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples 19298 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean 517.203855 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 3689.785170 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-16383 19110 99.03% 99.03% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::16384-32767 146 0.76% 99.78% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::32768-49151 30 0.16% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::49152-65535 4 0.02% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-81919 3 0.02% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::81920-98303 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::147456-163839 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total 19298 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples 6381 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 13105.939508 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 10791.784480 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 9136.863267 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-32767 6254 98.01% 98.01% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::32768-65535 124 1.94% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-163839 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::360448-393215 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total 6381 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -8047267064 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean 0.135073 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-1 -8095966564 100.61% 100.61% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::2-3 33943000 -0.42% 100.18% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-5 7702500 -0.10% 100.09% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::6-7 2846000 -0.04% 100.05% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-9 1530000 -0.02% 100.03% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::10-11 743500 -0.01% 100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-13 398000 -0.00% 100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::14-15 810000 -0.01% 100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-17 216000 -0.00% 100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::18-19 164500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-21 85000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::22-23 84500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-25 64500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::26-27 35000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-29 17500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::30-31 59500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -8047267064 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K 1874 70.21% 70.21% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::1M 795 29.79% 100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total 2669 # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33988 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 32928 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2612 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33988 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2669 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2612 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total 35540 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2669 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total 36657 # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
-system.cpu3.dtb.read_hits 7260437 # DTB read hits
-system.cpu3.dtb.read_misses 28509 # DTB read misses
-system.cpu3.dtb.write_hits 5425830 # DTB write hits
-system.cpu3.dtb.write_misses 4419 # DTB write misses
-system.cpu3.dtb.flush_tlb 161 # Number of times complete TLB was flushed
-system.cpu3.dtb.flush_tlb_mva 272 # Number of times TLB was flushed by MVA
+system.cpu3.dtb.read_hits 7187515 # DTB read hits
+system.cpu3.dtb.read_misses 29422 # DTB read misses
+system.cpu3.dtb.write_hits 5346412 # DTB write hits
+system.cpu3.dtb.write_misses 4566 # DTB write misses
+system.cpu3.dtb.flush_tlb 162 # Number of times complete TLB was flushed
+system.cpu3.dtb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries 1914 # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults 485 # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults 810 # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_entries 1921 # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults 451 # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults 735 # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses 7288946 # DTB read accesses
-system.cpu3.dtb.write_accesses 5430249 # DTB write accesses
+system.cpu3.dtb.perms_faults 408 # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses 7216937 # DTB read accesses
+system.cpu3.dtb.write_accesses 5350978 # DTB write accesses
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu3.dtb.hits 12686267 # DTB hits
-system.cpu3.dtb.misses 32928 # DTB misses
-system.cpu3.dtb.accesses 12719195 # DTB accesses
+system.cpu3.dtb.hits 12533927 # DTB hits
+system.cpu3.dtb.misses 33988 # DTB misses
+system.cpu3.dtb.accesses 12567915 # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1668,386 +1715,388 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.itb.walker.walks 4959 # Table walker walks requested
-system.cpu3.itb.walker.walksShort 4959 # Table walker walks initiated with short descriptors
-system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1575 # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2956 # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore 428 # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples 4531 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean 1378.172589 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev 5474.247381 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-8191 4267 94.17% 94.17% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::8192-16383 125 2.76% 96.93% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::16384-24575 86 1.90% 98.83% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::24576-32767 32 0.71% 99.54% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-40959 9 0.20% 99.74% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::40960-49151 4 0.09% 99.82% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::49152-57343 1 0.02% 99.85% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::57344-65535 2 0.04% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-73727 2 0.04% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::73728-81919 2 0.04% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total 4531 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples 1743 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 12810.097533 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 10341.257314 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 8222.199176 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-4095 24 1.38% 1.38% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::4096-8191 622 35.69% 37.06% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::8192-12287 348 19.97% 57.03% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::12288-16383 324 18.59% 75.62% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::16384-20479 26 1.49% 77.11% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::20480-24575 315 18.07% 95.18% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::24576-28671 50 2.87% 98.05% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::28672-32767 6 0.34% 98.39% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-36863 6 0.34% 98.74% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::36864-40959 6 0.34% 99.08% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::40960-45055 8 0.46% 99.54% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::45056-49151 4 0.23% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.06% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::57344-61439 2 0.11% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::61440-65535 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total 1743 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -4005171768 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean -0.325586 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0 -5306419980 132.49% 132.49% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1 1298923212 -32.43% 100.06% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2 1978000 -0.05% 100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3 238000 -0.01% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4 109000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -4005171768 # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K 967 73.54% 73.54% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::1M 348 26.46% 100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total 1315 # Table walker page sizes translated
+system.cpu3.itb.walker.walks 4586 # Table walker walks requested
+system.cpu3.itb.walker.walksShort 4586 # Table walker walks initiated with short descriptors
+system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1476 # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2630 # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore 480 # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples 4106 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean 1386.751096 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev 5919.935544 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-8191 3869 94.23% 94.23% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::8192-16383 140 3.41% 97.64% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::16384-24575 51 1.24% 98.88% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::24576-32767 18 0.44% 99.32% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-40959 9 0.22% 99.54% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::40960-49151 8 0.19% 99.73% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::49152-57343 3 0.07% 99.81% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::57344-65535 2 0.05% 99.85% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-73727 1 0.02% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.02% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::81920-90111 2 0.05% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::106496-114687 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total 4106 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples 1793 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 12167.875070 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 9929.586957 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 7490.636626 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-4095 25 1.39% 1.39% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::4096-8191 685 38.20% 39.60% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::8192-12287 343 19.13% 58.73% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::12288-16383 337 18.80% 77.52% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::16384-20479 34 1.90% 79.42% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::20480-24575 327 18.24% 97.66% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::24576-28671 25 1.39% 99.05% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::28672-32767 2 0.11% 99.16% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-36863 8 0.45% 99.61% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::36864-40959 3 0.17% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::40960-45055 1 0.06% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::45056-49151 1 0.06% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::49152-53247 2 0.11% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total 1793 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -8048536564 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean 0.273748 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev 0.444975 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0 -5842963052 72.60% 72.60% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1 -2207207512 27.42% 100.02% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2 1197000 -0.01% 100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3 240000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4 159500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5 37500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -8048536564 # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K 959 73.04% 73.04% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::1M 354 26.96% 100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total 1313 # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4959 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4959 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4586 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4586 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1315 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1315 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total 6274 # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits 9813721 # ITB inst hits
-system.cpu3.itb.inst_misses 4959 # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1313 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1313 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total 5899 # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits 9766961 # ITB inst hits
+system.cpu3.itb.inst_misses 4586 # ITB inst misses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.itb.flush_tlb 161 # Number of times complete TLB was flushed
-system.cpu3.itb.flush_tlb_mva 272 # Number of times TLB was flushed by MVA
+system.cpu3.itb.flush_tlb 162 # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries 1311 # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_entries 1310 # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults 728 # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults 793 # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.inst_accesses 9818680 # ITB inst accesses
-system.cpu3.itb.hits 9813721 # DTB hits
-system.cpu3.itb.misses 4959 # DTB misses
-system.cpu3.itb.accesses 9818680 # DTB accesses
-system.cpu3.numCycles 58198977 # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses 9771547 # ITB inst accesses
+system.cpu3.itb.hits 9766961 # DTB hits
+system.cpu3.itb.misses 4586 # DTB misses
+system.cpu3.itb.accesses 9771547 # DTB accesses
+system.cpu3.numCycles 57688008 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 20997510 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 52319874 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 13289019 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 9351576 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 34146869 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 1603241 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles 75601 # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles 830 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles 252 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles 167692 # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles 75270 # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles 481 # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines 9812317 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 215159 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes 2588 # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples 56266104 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.124866 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.272811 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles 20811667 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 52032939 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 13251998 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 9316407 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 33930226 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 1581195 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles 68181 # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles 837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles 231 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles 120341 # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles 80383 # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles 479 # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines 9765461 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 207701 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes 2399 # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples 55802921 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.126478 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.271735 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 42091874 74.81% 74.81% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 1838725 3.27% 78.08% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 1172268 2.08% 80.16% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3680170 6.54% 86.70% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 919176 1.63% 88.33% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 559542 0.99% 89.33% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 2920436 5.19% 94.52% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 600253 1.07% 95.59% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 2483660 4.41% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 41696635 74.72% 74.72% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 1836227 3.29% 78.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 1165179 2.09% 80.10% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3688200 6.61% 86.71% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 906119 1.62% 88.33% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 549240 0.98% 89.32% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 2914414 5.22% 94.54% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 602851 1.08% 95.62% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 2444056 4.38% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 56266104 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.228338 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 0.898983 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 14691998 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 32127735 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 7847757 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 886811 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 711602 # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved 982939 # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred 91189 # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts 45025985 # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts 297573 # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles 711602 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 15176381 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 3842485 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 22070368 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 8242497 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 6222544 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 43140081 # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents 802 # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents 912982 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents 87651 # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents 4846837 # Number of times rename has blocked due to SQ full
-system.cpu3.rename.RenamedOperands 44765157 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 198174110 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 48152546 # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups 3891 # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps 37263168 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 7501989 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 722657 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 671168 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 5019030 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 7753962 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 6001781 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 1096461 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 1526920 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 41470903 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 516515 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 39452509 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 52405 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 6056878 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 13877375 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 54814 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 56266104 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 0.701177 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.409085 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 55802921 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.229718 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 0.901971 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 14568500 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 31866419 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 7772530 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 890722 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 704491 # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved 971896 # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred 87220 # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts 44589995 # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts 289462 # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles 704491 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 15048240 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 3770694 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 21829138 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 8174722 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 6275353 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 42740341 # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents 1149 # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents 970338 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents 89122 # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents 4852694 # Number of times rename has blocked due to SQ full
+system.cpu3.rename.RenamedOperands 44469906 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 196241867 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 47658111 # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups 4195 # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps 37088315 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 7381591 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 715058 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 665415 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 5054904 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 7671721 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 5900836 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 1096117 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 1546300 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 41143792 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 502169 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 39136227 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 53751 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 5932360 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 13678384 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 53132 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 55802921 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 0.701329 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.406591 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 40628428 72.21% 72.21% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 5180351 9.21% 81.41% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 3993172 7.10% 88.51% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 3216769 5.72% 94.23% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 1270144 2.26% 96.49% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 778707 1.38% 97.87% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 841867 1.50% 99.37% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 243134 0.43% 99.80% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 113532 0.20% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 40242426 72.12% 72.12% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 5178735 9.28% 81.40% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 3976743 7.13% 88.52% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 3203415 5.74% 94.26% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 1255788 2.25% 96.51% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 764372 1.37% 97.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 832267 1.49% 99.37% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 238253 0.43% 99.80% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 110922 0.20% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 56266104 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 55802921 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 56907 9.43% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 285269 47.26% 56.69% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 261388 43.31% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 55579 9.37% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 279420 47.11% 56.48% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 258160 43.52% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass 82 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 26244378 66.52% 66.52% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 29732 0.08% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 2423 0.01% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.60% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 7478738 18.96% 85.56% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 5697150 14.44% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 26095739 66.68% 66.68% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 29921 0.08% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 2385 0.01% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 7397588 18.90% 85.66% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 5610508 14.34% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 39452509 # Type of FU issued
-system.cpu3.iq.rate 0.677890 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 603564 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.015298 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 135818664 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 48068982 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 38286246 # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads 8427 # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes 4554 # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses 3686 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 40051464 # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses 4527 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 171911 # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total 39136227 # Type of FU issued
+system.cpu3.iq.rate 0.678412 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 593159 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.015156 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 134713506 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 47601839 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 37987745 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads 8779 # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes 5136 # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses 39724596 # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses 4706 # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads 167565 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 1183804 # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses 1366 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 29886 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 609084 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 1160512 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 1106 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 29283 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 565980 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads 109633 # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked 44383 # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads 108566 # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked 42617 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 711602 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 3194648 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 528279 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 42035264 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 85063 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 7753962 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 6001781 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 267022 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 22471 # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents 499621 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 29886 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 141382 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 125809 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 267191 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 39120156 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 7345638 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 299518 # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles 704491 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 3164370 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 480380 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 41688366 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 67674 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 7671721 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 5900836 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 259515 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 22770 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents 451545 # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents 29283 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 127479 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 130166 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 257645 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 38819065 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 7269277 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 283258 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 47846 # number of nop insts executed
-system.cpu3.iew.exec_refs 12983277 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 7265357 # Number of branches executed
-system.cpu3.iew.exec_stores 5637639 # Number of stores executed
-system.cpu3.iew.exec_rate 0.672179 # Inst execution rate
-system.cpu3.iew.wb_sent 38830479 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 38289932 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 20020734 # num instructions producing a value
-system.cpu3.iew.wb_consumers 34859038 # num instructions consuming a value
-system.cpu3.iew.wb_rate 0.657914 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.574334 # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts 6072535 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 461701 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 222399 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 54967240 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 0.654139 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 1.550137 # Number of insts commited each cycle
+system.cpu3.iew.exec_nop 42405 # number of nop insts executed
+system.cpu3.iew.exec_refs 12824699 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 7229147 # Number of branches executed
+system.cpu3.iew.exec_stores 5555422 # Number of stores executed
+system.cpu3.iew.exec_rate 0.672914 # Inst execution rate
+system.cpu3.iew.wb_sent 38534574 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 37991618 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 19895902 # num instructions producing a value
+system.cpu3.iew.wb_consumers 34654427 # num instructions consuming a value
+system.cpu3.iew.wb_rate 0.658570 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.574123 # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts 5941681 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 449037 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 213879 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 54520381 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 0.655520 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.547792 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 41117767 74.80% 74.80% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 6171974 11.23% 86.03% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 3094219 5.63% 91.66% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 1318133 2.40% 94.06% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 709863 1.29% 95.35% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 496595 0.90% 96.25% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 959944 1.75% 98.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 230664 0.42% 98.42% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 868081 1.58% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 40723522 74.69% 74.69% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 6130634 11.24% 85.94% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 3105134 5.70% 91.63% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 1318169 2.42% 94.05% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 725183 1.33% 95.38% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 499193 0.92% 96.30% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 937316 1.72% 98.02% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 226626 0.42% 98.43% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 854604 1.57% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 54967240 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 29407542 # Number of instructions committed
-system.cpu3.commit.committedOps 35956198 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 54520381 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 29254199 # Number of instructions committed
+system.cpu3.commit.committedOps 35739216 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 11962855 # Number of memory references committed
-system.cpu3.commit.loads 6570158 # Number of loads committed
-system.cpu3.commit.membars 179658 # Number of memory barriers committed
-system.cpu3.commit.branches 6851927 # Number of branches committed
-system.cpu3.commit.fp_insts 3664 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 31411124 # Number of committed integer instructions.
-system.cpu3.commit.function_calls 1242322 # Number of function calls committed.
+system.cpu3.commit.refs 11846065 # Number of memory references committed
+system.cpu3.commit.loads 6511209 # Number of loads committed
+system.cpu3.commit.membars 174051 # Number of memory barriers committed
+system.cpu3.commit.branches 6823805 # Number of branches committed
+system.cpu3.commit.fp_insts 3728 # Number of committed floating point instructions.
+system.cpu3.commit.int_insts 31222090 # Number of committed integer instructions.
+system.cpu3.commit.function_calls 1239495 # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu 23962177 66.64% 66.64% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult 28743 0.08% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.72% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc 2423 0.01% 66.73% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.73% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.73% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.73% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead 6570158 18.27% 85.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite 5392697 15.00% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu 23861802 66.77% 66.77% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult 28964 0.08% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc 2385 0.01% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead 6511209 18.22% 85.07% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite 5334856 14.93% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total 35956198 # Class of committed instruction
-system.cpu3.commit.bw_lim_events 868081 # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads 90502636 # The number of ROB reads
-system.cpu3.rob.rob_writes 85356048 # The number of ROB writes
-system.cpu3.timesIdled 229941 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 1932873 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 5160445886 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 29381884 # Number of Instructions Simulated
-system.cpu3.committedOps 35930540 # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi 1.980778 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 1.980778 # CPI: Total CPI of All Threads
-system.cpu3.ipc 0.504852 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 0.504852 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 42608417 # number of integer regfile reads
-system.cpu3.int_regfile_writes 24235283 # number of integer regfile writes
-system.cpu3.fp_regfile_reads 14369 # number of floating regfile reads
-system.cpu3.fp_regfile_writes 12266 # number of floating regfile writes
-system.cpu3.cc_regfile_reads 138322316 # number of cc regfile reads
-system.cpu3.cc_regfile_writes 14832721 # number of cc regfile writes
-system.cpu3.misc_regfile_reads 76348373 # number of misc regfile reads
-system.cpu3.misc_regfile_writes 345208 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 30184 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30184 # Transaction distribution
+system.cpu3.commit.op_class_0::total 35739216 # Class of committed instruction
+system.cpu3.commit.bw_lim_events 854604 # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads 89694984 # The number of ROB reads
+system.cpu3.rob.rob_writes 84644228 # The number of ROB writes
+system.cpu3.timesIdled 227110 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 1885087 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 5160958859 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 29228584 # Number of Instructions Simulated
+system.cpu3.committedOps 35713601 # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi 1.973685 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 1.973685 # CPI: Total CPI of All Threads
+system.cpu3.ipc 0.506667 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 0.506667 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 42269804 # number of integer regfile reads
+system.cpu3.int_regfile_writes 24060507 # number of integer regfile writes
+system.cpu3.fp_regfile_reads 14520 # number of floating regfile reads
+system.cpu3.fp_regfile_writes 12259 # number of floating regfile writes
+system.cpu3.cc_regfile_reads 137213750 # number of cc regfile reads
+system.cpu3.cc_regfile_writes 14769664 # number of cc regfile writes
+system.cpu3.misc_regfile_reads 75722045 # number of misc regfile reads
+system.cpu3.misc_regfile_writes 336113 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
system.iobus.trans_dist::WriteResp 59010 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes)
@@ -2070,9 +2119,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178388 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
@@ -2093,91 +2142,93 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480341 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 27681500 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480317 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 27737500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 101500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 206500 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 203000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
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@@ -2186,408 +2237,424 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
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@@ -2596,268 +2663,280 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000580 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.001938 # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::total 0.001911 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.994667 # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006663 # mshr miss rate for ReadCleanReq accesses
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+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.029283 # mshr miss rate for ReadSharedReq accesses
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+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008901 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.137216 # mshr miss rate for demand accesses
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68011.304348 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 67991.022099 # average UpgradeReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190198.506782 # average ReadReq mshr uncacheable latency
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+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200867.139195 # average WriteReq mshr uncacheable latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 40114 # Transaction distribution
-system.membus.trans_dist::ReadResp 76465 # Transaction distribution
+system.membus.trans_dist::ReadResp 76256 # Transaction distribution
system.membus.trans_dist::WriteReq 27565 # Transaction distribution
system.membus.trans_dist::WriteResp 27565 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 131262 # Transaction distribution
-system.membus.trans_dist::CleanEvict 9255 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4560 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 11 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1783 # Transaction distribution
-system.membus.trans_dist::ReadExReq 138008 # Transaction distribution
-system.membus.trans_dist::ReadExResp 138008 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 36351 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 131145 # Transaction distribution
+system.membus.trans_dist::CleanEvict 8918 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4561 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1773 # Transaction distribution
+system.membus.trans_dist::ReadExReq 137930 # Transaction distribution
+system.membus.trans_dist::ReadExResp 137930 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 36142 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution
system.membus.trans_dist::InvalidateResp 21008 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 486392 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 593844 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94027 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 94027 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 687871 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 485390 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 592842 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 93962 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 93962 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 686804 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17273404 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 17436529 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2322624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2322624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19759153 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 308 # Total snoops (count)
-system.membus.snoop_fanout::samples 423355 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17249660 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 17412785 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2320704 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2320704 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19733489 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 305 # Total snoops (count)
+system.membus.snoop_fanout::samples 422579 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 423355 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 422579 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 423355 # Request fanout histogram
-system.membus.reqLayer0.occupancy 54051500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 422579 # Request fanout histogram
+system.membus.reqLayer0.occupancy 54357000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 682000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 681000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 487313006 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 480576517 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 582602000 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 576477250 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 785081 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 796581 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
@@ -2900,60 +2979,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 5677345 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 2853013 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 45306 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 358 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 358 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests 5652845 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 2841067 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 44935 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 620 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 112463 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2640157 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 111946 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2627538 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 761584 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 1989175 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 147491 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2813 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2842 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 296749 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 296749 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 1989735 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 538020 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 15216 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5986563 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2626405 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26917 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102214 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 8742099 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 254678264 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97882489 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 44408 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 182720 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 352787881 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 192824 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 4204353 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.021421 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.144784 # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty 760858 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 1977299 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 146343 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2855 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2881 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 296356 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 296356 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 1977848 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 537746 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 15186 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5950911 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2624548 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25489 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 101523 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 8702471 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 253157304 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97861305 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41336 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 179384 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 351239329 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 193521 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 4203870 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.021594 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.145354 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 4114290 97.86% 97.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 90063 2.14% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 4113091 97.84% 97.84% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 90779 2.16% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4204353 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 3491124499 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 4203870 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 3441050999 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 176919 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 260919 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1900767119 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1872616750 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 770214712 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 760136706 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 11666477 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 11021467 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 48138206 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 48272206 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index 9e6069cc9..653375199 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,140 +1,140 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.823493 # Number of seconds simulated
-sim_ticks 2823493079000 # Number of ticks simulated
-final_tick 2823493079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.822600 # Number of seconds simulated
+sim_ticks 2822599892000 # Number of ticks simulated
+final_tick 2822599892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 90172 # Simulator instruction rate (inst/s)
-host_op_rate 109444 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2177949659 # Simulator tick rate (ticks/s)
-host_mem_usage 568424 # Number of bytes of host memory used
-host_seconds 1296.40 # Real time elapsed on the host
-sim_insts 116899487 # Number of instructions simulated
-sim_ops 141883778 # Number of ops (including micro ops) simulated
+host_inst_rate 133046 # Simulator instruction rate (inst/s)
+host_op_rate 161483 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3211959283 # Simulator tick rate (ticks/s)
+host_mem_usage 588416 # Number of bytes of host memory used
+host_seconds 878.78 # Real time elapsed on the host
+sim_insts 116918246 # Number of instructions simulated
+sim_ops 141908177 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 3648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 3520 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 661248 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5289056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 5312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 712448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4516488 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 680320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5169248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 4928 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 692096 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4617224 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11189224 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 661248 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 712448 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1373696 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8440896 # Number of bytes written to this memory
+system.physmem.bytes_read::total 11168360 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 680320 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 692096 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1372416 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8444928 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8458420 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 57 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8462452 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 55 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 10332 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 83160 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 83 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 11132 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 70572 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 10630 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 81288 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 77 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 10814 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 72146 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 175352 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 131889 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 175026 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 131952 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 136270 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 1292 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 136333 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 1247 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 234195 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1873231 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 1881 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 252329 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1599610 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 241026 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1831378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 1746 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 245198 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1635805 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3962901 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 234195 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 252329 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 486524 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2989522 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3956763 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 241026 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 245198 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 486224 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2991897 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6206 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2995729 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2989522 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 1292 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2998105 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2991897 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 1247 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 234195 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1879435 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 1881 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 252329 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 1599613 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 241026 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1837584 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 1746 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 245198 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1635808 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6958630 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 175353 # Number of read requests accepted
-system.physmem.writeReqs 136270 # Number of write requests accepted
-system.physmem.readBursts 175353 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 136270 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 11214528 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8470656 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11189288 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8458420 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 6954869 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 175027 # Number of read requests accepted
+system.physmem.writeReqs 136333 # Number of write requests accepted
+system.physmem.readBursts 175027 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 136333 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11191872 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8475200 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11168424 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8462452 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11394 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10988 # Per bank write bursts
-system.physmem.perBankRdBursts::2 11451 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11269 # Per bank write bursts
-system.physmem.perBankRdBursts::4 11015 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10539 # Per bank write bursts
-system.physmem.perBankRdBursts::6 11408 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11336 # Per bank write bursts
-system.physmem.perBankRdBursts::8 11237 # Per bank write bursts
-system.physmem.perBankRdBursts::9 11286 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10494 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10073 # Per bank write bursts
-system.physmem.perBankRdBursts::12 10670 # Per bank write bursts
-system.physmem.perBankRdBursts::13 11521 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10545 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10001 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8622 # Per bank write bursts
-system.physmem.perBankWrBursts::1 8285 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8892 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8784 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7852 # Per bank write bursts
-system.physmem.perBankWrBursts::5 7876 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8452 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8530 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8484 # Per bank write bursts
-system.physmem.perBankWrBursts::9 8682 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7871 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7713 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8237 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8870 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7879 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7325 # Per bank write bursts
+system.physmem.perBankRdBursts::0 12029 # Per bank write bursts
+system.physmem.perBankRdBursts::1 11047 # Per bank write bursts
+system.physmem.perBankRdBursts::2 10999 # Per bank write bursts
+system.physmem.perBankRdBursts::3 11203 # Per bank write bursts
+system.physmem.perBankRdBursts::4 11530 # Per bank write bursts
+system.physmem.perBankRdBursts::5 11229 # Per bank write bursts
+system.physmem.perBankRdBursts::6 11724 # Per bank write bursts
+system.physmem.perBankRdBursts::7 11678 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10819 # Per bank write bursts
+system.physmem.perBankRdBursts::9 11281 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10383 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9840 # Per bank write bursts
+system.physmem.perBankRdBursts::12 10191 # Per bank write bursts
+system.physmem.perBankRdBursts::13 10806 # Per bank write bursts
+system.physmem.perBankRdBursts::14 10203 # Per bank write bursts
+system.physmem.perBankRdBursts::15 9911 # Per bank write bursts
+system.physmem.perBankWrBursts::0 8929 # Per bank write bursts
+system.physmem.perBankWrBursts::1 8449 # Per bank write bursts
+system.physmem.perBankWrBursts::2 8574 # Per bank write bursts
+system.physmem.perBankWrBursts::3 8748 # Per bank write bursts
+system.physmem.perBankWrBursts::4 8391 # Per bank write bursts
+system.physmem.perBankWrBursts::5 8421 # Per bank write bursts
+system.physmem.perBankWrBursts::6 8483 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8696 # Per bank write bursts
+system.physmem.perBankWrBursts::8 8251 # Per bank write bursts
+system.physmem.perBankWrBursts::9 8705 # Per bank write bursts
+system.physmem.perBankWrBursts::10 8031 # Per bank write bursts
+system.physmem.perBankWrBursts::11 7697 # Per bank write bursts
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+system.physmem.wrPerTurnAround::176-179 3 0.05% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6529 # Writes before turning the bus around for reads
+system.physmem.totQLat 2732692250 # Total ticks spent queuing
+system.physmem.totMemAccLat 6011561000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 874365000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 15626.72 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 34441.87 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 34376.72 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.97 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.96 # Average system read bandwidth in MiByte/s
@@ -298,69 +298,73 @@ system.physmem.peakBW 12800.00 # Th
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.46 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 13.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 144282 # Number of row buffer hits during reads
-system.physmem.writeRowHits 97631 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.75 # Row buffer hit rate for writes
-system.physmem.avgGap 9060604.96 # Average gap between requests
-system.physmem.pageHitRate 78.64 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 255898440 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 139627125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 697320000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 436058640 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 184416570000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 80131577265 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1623802634250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1889879685720 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.341932 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2701224800750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 94282500000 # Time in different power states
+system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 12.39 # Average write queue length when enqueuing
+system.physmem.readRowHits 143838 # Number of row buffer hits during reads
+system.physmem.writeRowHits 97566 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.66 # Row buffer hit rate for writes
+system.physmem.avgGap 9065389.63 # Average gap between requests
+system.physmem.pageHitRate 78.55 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 262589040 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 143277750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 713224200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 445117680 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 184358085600 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 80173196100 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1623228875250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1889324365620 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.357529 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2700270963250 # Time in different power states
+system.physmem_0.memoryStateTime::REF 94252600000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 27981865500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 28070184250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 240544080 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 131249250 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 669442800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 421595280 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 184416570000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 79215076260 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1624606582500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1889701060170 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.278668 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2702572917000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 94282500000 # Time in different power states
+system.physmem_1.actEnergy 235562040 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 128530875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 650777400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 412996320 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 184358085600 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 79158702690 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1624118781750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1889063436675 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.265086 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2701767276500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 94252600000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 26637651500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 26580005000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 249 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 249 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 249 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 249 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 249 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 249 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 768 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 768 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 12 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 272 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 272 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 272 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 272 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 272 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 272 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 26562225 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 13713319 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 500857 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 15697125 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 12422609 # Number of BTB hits
+system.cpu0.branchPred.lookups 26616996 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 13742017 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 493041 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 15603811 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 8045769 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 79.139390 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 6635585 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 27692 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 51.562846 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 6633595 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 28274 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups 4499378 # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits 4391333 # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses 108045 # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted 31802 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -391,90 +395,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 56581 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 56581 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17171 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 13789 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 25621 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 30960 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 892.441860 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 5515.724394 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-16383 30478 98.44% 98.44% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-32767 319 1.03% 99.47% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-49151 90 0.29% 99.76% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-65535 32 0.10% 99.87% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-81919 19 0.06% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-114687 6 0.02% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::114688-131071 6 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-147455 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 30960 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 12756 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 13625.744748 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11059.152446 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 9336.432793 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383 9266 72.64% 72.64% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3226 25.29% 97.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151 240 1.88% 99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.03% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-81919 2 0.02% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-147455 13 0.10% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::147456-163839 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 12756 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 91893354244 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.629728 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.506061 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 91810040244 99.91% 99.91% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3 56305000 0.06% 99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5 12880500 0.01% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7 5151500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9 2494500 0.00% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11 1674000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13 953500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15 2585000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17 396500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19 403500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-21 80000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::22-23 39000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-25 135500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::26-27 32000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-29 29000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::30-31 154500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 91893354244 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 3474 69.45% 69.45% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1528 30.55% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 5002 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 56581 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 58233 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 58233 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17222 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14806 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 26205 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 32028 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 716.310728 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 4455.738407 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-16383 31643 98.80% 98.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-32767 285 0.89% 99.69% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-49151 60 0.19% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-65535 17 0.05% 99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-81919 11 0.03% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::81920-98303 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-114687 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::114688-131071 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::147456-163839 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 32028 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 12683 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 13005.479776 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 10522.110524 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 9554.054292 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767 12456 98.21% 98.21% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535 198 1.56% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303 4 0.03% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071 15 0.12% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839 9 0.07% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 12683 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 95295475040 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 0.626262 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev 0.503838 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 95214863040 99.92% 99.92% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3 54562500 0.06% 99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5 11789500 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7 5218000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9 3107500 0.00% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11 1725500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13 925000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15 2340500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17 429500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19 156000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-21 103500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::22-23 23000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-25 167000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::26-27 8500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-29 11000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::30-31 45000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 95295475040 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 3556 69.39% 69.39% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1569 30.61% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 5125 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58233 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 56581 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5002 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58233 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5125 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5002 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 61583 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5125 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 63358 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 13951355 # DTB read hits
-system.cpu0.dtb.read_misses 47293 # DTB read misses
-system.cpu0.dtb.write_hits 10502243 # DTB write hits
-system.cpu0.dtb.write_misses 9288 # DTB write misses
-system.cpu0.dtb.flush_tlb 177 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 479 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits 14003627 # DTB read hits
+system.cpu0.dtb.read_misses 49308 # DTB read misses
+system.cpu0.dtb.write_hits 10435159 # DTB write hits
+system.cpu0.dtb.write_misses 8925 # DTB write misses
+system.cpu0.dtb.flush_tlb 179 # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva 465 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3270 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 756 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1257 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3323 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 748 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 1266 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 577 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 13998648 # DTB read accesses
-system.cpu0.dtb.write_accesses 10511531 # DTB write accesses
+system.cpu0.dtb.perms_faults 726 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 14052935 # DTB read accesses
+system.cpu0.dtb.write_accesses 10444084 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 24453598 # DTB hits
-system.cpu0.dtb.misses 56581 # DTB misses
-system.cpu0.dtb.accesses 24510179 # DTB accesses
+system.cpu0.dtb.hits 24438786 # DTB hits
+system.cpu0.dtb.misses 58233 # DTB misses
+system.cpu0.dtb.accesses 24497019 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -504,803 +504,807 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 8148 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 8148 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2287 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5071 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 790 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 7358 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 1843.571623 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 7891.595546 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-16383 7065 96.02% 96.02% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-32767 220 2.99% 99.01% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-49151 36 0.49% 99.50% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::49152-65535 18 0.24% 99.74% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-81919 7 0.10% 99.84% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::81920-98303 3 0.04% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-114687 4 0.05% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::114688-131071 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-147455 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::147456-163839 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 7358 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 3026 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 13026.107072 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 10729.463375 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 8131.043208 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383 2342 77.40% 77.40% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767 631 20.85% 98.25% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151 50 1.65% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.03% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 7841 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 7841 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2269 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4662 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore 910 # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples 6931 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean 1597.099986 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 6530.842043 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-8191 6483 93.54% 93.54% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-16383 245 3.53% 97.07% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-24575 100 1.44% 98.51% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-32767 38 0.55% 99.06% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-40959 21 0.30% 99.37% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-49151 16 0.23% 99.60% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::49152-57343 8 0.12% 99.71% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::57344-65535 6 0.09% 99.80% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-73727 6 0.09% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::73728-81919 3 0.04% 99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::81920-90111 3 0.04% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-106495 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 6931 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 3149 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12098.126389 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 9906.288908 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 7800.353471 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383 2504 79.52% 79.52% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767 621 19.72% 99.24% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151 19 0.60% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535 3 0.10% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-114687 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 3026 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 23173609508 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.733481 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.443211 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 6183538408 26.68% 26.68% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 16984817600 73.29% 99.98% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 4062000 0.02% 99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3 741500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4 212000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5 115000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6 49000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::7 74000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 23173609508 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 1678 75.04% 75.04% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 558 24.96% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2236 # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total 3149 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 35165227396 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 0.607117 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev 0.488806 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 13821063428 39.30% 39.30% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 21340361468 60.69% 99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2 2726000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3 763000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4 254500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5 59000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 35165227396 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 1680 75.03% 75.03% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 559 24.97% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 2239 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 8148 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 8148 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7841 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7841 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2236 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2236 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 10384 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 20133708 # ITB inst hits
-system.cpu0.itb.inst_misses 8148 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2239 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2239 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 10080 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 20129466 # ITB inst hits
+system.cpu0.itb.inst_misses 7841 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 177 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 479 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb 179 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva 465 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2157 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1247 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1367 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 20141856 # ITB inst accesses
-system.cpu0.itb.hits 20133708 # DTB hits
-system.cpu0.itb.misses 8148 # DTB misses
-system.cpu0.itb.accesses 20141856 # DTB accesses
-system.cpu0.numCycles 111776852 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 20137307 # ITB inst accesses
+system.cpu0.itb.hits 20129466 # DTB hits
+system.cpu0.itb.misses 7841 # DTB misses
+system.cpu0.itb.accesses 20137307 # DTB accesses
+system.cpu0.numCycles 111772551 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 39403190 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 103921497 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 26562225 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 19058194 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 67156695 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 3114917 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 123726 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 4268 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 480 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 186283 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 122357 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 649 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 20132007 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 351323 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 4252 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 108555069 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.151171 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.270996 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 39602252 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 104018130 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 26616996 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 19070697 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 66981465 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3101347 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 109391 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 4554 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 495 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 137372 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 131975 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 607 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 20127570 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 345492 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 4051 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 108518747 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.151083 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.270431 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 79990801 73.69% 73.69% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 3808874 3.51% 77.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 2395058 2.21% 79.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 7998029 7.37% 86.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1538152 1.42% 88.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 1084902 1.00% 89.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 6043071 5.57% 94.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 1032645 0.95% 95.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4663537 4.30% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 79947267 73.67% 73.67% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 3818944 3.52% 77.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 2390633 2.20% 79.39% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 8016162 7.39% 86.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1540680 1.42% 88.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 1082847 1.00% 89.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 6027122 5.55% 94.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 1035069 0.95% 95.71% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4660023 4.29% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 108555069 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.237636 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.929723 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 26882807 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 63335776 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 15412280 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 1509994 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1413858 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1870073 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 145529 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 86268020 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 470270 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1413858 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 27733992 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 6692590 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 45841615 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 16067408 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 10805241 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 82544618 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 2042 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 1112195 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 256310 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 8681649 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 84728075 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 381395863 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 92554269 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 5536 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 72228631 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 12499436 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1563164 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 1465809 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 8810200 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 14722968 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 11667187 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 2112375 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 2825425 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 79486771 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1117550 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 76500149 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 87453 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10367122 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 23085587 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 102592 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 108555069 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.704713 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.405532 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 108518747 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.238135 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.930623 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 27080846 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 63086875 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 15439246 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 1499474 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1411975 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 1879709 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 140548 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 86265439 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 466335 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1411975 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 27919581 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 6708694 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 45822380 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 16094749 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 10561036 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 82571629 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1978 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 1083684 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 247104 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 8473675 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 84960464 # Number of destination operands rename has renamed
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+system.cpu0.rename.fp_rename_lookups 6511 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 72285025 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 12675423 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1561908 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 1463600 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 8728047 # count of insts added to the skid buffer
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+system.cpu0.memDep0.insertedStores 11575214 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 2006179 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 2797578 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 79563534 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1113915 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 76525093 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 91014 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10394891 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 23261666 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 100529 # Number of squashed non-spec instructions that were removed
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 77869372 71.73% 71.73% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 10452853 9.63% 81.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 7709491 7.10% 88.46% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 6441479 5.93% 94.40% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2337672 2.15% 96.55% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1520744 1.40% 97.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 1474811 1.36% 99.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 488573 0.45% 99.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 260074 0.24% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 77980499 71.86% 71.86% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 10237558 9.43% 81.29% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 7702853 7.10% 88.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 6507672 6.00% 94.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2342197 2.16% 96.55% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1521714 1.40% 97.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 1465392 1.35% 99.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 497793 0.46% 99.76% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 108555069 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 108518747 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 112277 9.78% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 1 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 527304 45.92% 55.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 508852 44.31% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 115286 10.03% 10.03% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.03% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.03% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.03% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.03% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.03% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 533290 46.39% 56.42% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 501036 43.58% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 223 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 50954579 66.61% 66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 56909 0.07% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 4066 0.01% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 14340871 18.75% 85.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 11143495 14.57% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 257 0.00% 0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 51005106 66.65% 66.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 57020 0.07% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 4013 0.01% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.73% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 14388531 18.80% 85.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 11070162 14.47% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 76500149 # Type of FU issued
-system.cpu0.iq.rate 0.684401 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1148434 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.015012 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 262779006 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 91017673 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 74252791 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 12248 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 6548 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 5441 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 77641803 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 6557 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 356027 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 76525093 # Type of FU issued
+system.cpu0.iq.rate 0.684650 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1149614 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.015023 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 262795692 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 91116693 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 74267630 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 13869 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 8272 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 6120 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 77667016 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 7434 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 356348 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1992322 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2344 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 53958 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1074198 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2003014 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2146 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 53724 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1008418 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 201819 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 121524 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 205247 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 123541 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1413858 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 5274994 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 1203442 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 80734208 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 135083 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 14722968 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 11667187 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 571297 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 46146 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 1145124 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 53958 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 220662 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 202640 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 423302 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 75944815 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 14120955 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 498889 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1411975 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 5317808 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 1170288 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 80797143 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 102579 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 14766139 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 11575214 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 569653 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 44979 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 1113707 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 53724 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 203717 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 217691 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 421408 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 75980075 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 14169520 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 486959 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 129887 # number of nop insts executed
-system.cpu0.iew.exec_refs 25162401 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 14058004 # Number of branches executed
-system.cpu0.iew.exec_stores 11041446 # Number of stores executed
-system.cpu0.iew.exec_rate 0.679432 # Inst execution rate
-system.cpu0.iew.wb_sent 75389517 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 74258232 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 38914565 # num instructions producing a value
-system.cpu0.iew.wb_consumers 68266536 # num instructions consuming a value
-system.cpu0.iew.wb_rate 0.664344 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.570039 # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts 10404302 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 1014958 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 357219 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 106153750 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.662378 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.559927 # Number of insts commited each cycle
+system.cpu0.iew.exec_nop 119694 # number of nop insts executed
+system.cpu0.iew.exec_refs 25144307 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 14085484 # Number of branches executed
+system.cpu0.iew.exec_stores 10974787 # Number of stores executed
+system.cpu0.iew.exec_rate 0.679774 # Inst execution rate
+system.cpu0.iew.wb_sent 75414321 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 74273750 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 38951887 # num instructions producing a value
+system.cpu0.iew.wb_consumers 68092338 # num instructions consuming a value
+system.cpu0.iew.wb_rate 0.664508 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.572045 # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts 10417951 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 1013386 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 354305 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 106111246 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.663072 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.565077 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 78810789 74.24% 74.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 12397271 11.68% 85.92% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 6093008 5.74% 91.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2657069 2.50% 94.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1361434 1.28% 95.45% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 829942 0.78% 96.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 1724502 1.62% 97.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 420914 0.40% 98.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1858821 1.75% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 78913412 74.37% 74.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 12236512 11.53% 85.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 6105044 5.75% 91.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2654450 2.50% 94.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1291559 1.22% 95.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 838114 0.79% 96.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 1777849 1.68% 97.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 428900 0.40% 98.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1865406 1.76% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 106153750 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 57962859 # Number of instructions committed
-system.cpu0.commit.committedOps 70313918 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 106111246 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 58013653 # Number of instructions committed
+system.cpu0.commit.committedOps 70359398 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 23323635 # Number of memory references committed
-system.cpu0.commit.loads 12730646 # Number of loads committed
-system.cpu0.commit.membars 416255 # Number of memory barriers committed
-system.cpu0.commit.branches 13367689 # Number of branches committed
-system.cpu0.commit.fp_insts 5418 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 61732949 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 2627340 # Number of function calls committed.
+system.cpu0.commit.refs 23329921 # Number of memory references committed
+system.cpu0.commit.loads 12763125 # Number of loads committed
+system.cpu0.commit.membars 416120 # Number of memory barriers committed
+system.cpu0.commit.branches 13382810 # Number of branches committed
+system.cpu0.commit.fp_insts 5642 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 61776783 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 2631243 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 46930865 66.74% 66.74% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 55353 0.08% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 4065 0.01% 66.83% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 12730646 18.11% 84.93% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 10592989 15.07% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 46969916 66.76% 66.76% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 55548 0.08% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 4013 0.01% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.84% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 12763125 18.14% 84.98% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 10566796 15.02% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 70313918 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1858821 # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads 172659175 # The number of ROB reads
-system.cpu0.rob.rob_writes 163836244 # The number of ROB writes
-system.cpu0.timesIdled 382209 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 3221783 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2095451919 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 57886136 # Number of Instructions Simulated
-system.cpu0.committedOps 70237195 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 1.930978 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 1.930978 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.517872 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.517872 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 82912613 # number of integer regfile reads
-system.cpu0.int_regfile_writes 47294039 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 16301 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 13368 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 268256269 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 27711258 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 150058010 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 778660 # number of misc regfile writes
-system.cpu0.dcache.tags.replacements 855157 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.968827 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 42356538 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 855669 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 49.501078 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 186702500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 253.928302 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 258.040525 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.495954 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.503985 # Average percentage of cache occupancy
+system.cpu0.commit.op_class_0::total 70359398 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1865406 # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads 172653686 # The number of ROB reads
+system.cpu0.rob.rob_writes 163961445 # The number of ROB writes
+system.cpu0.timesIdled 387576 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 3253804 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 2105668651 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 57936809 # Number of Instructions Simulated
+system.cpu0.committedOps 70282554 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 1.929215 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 1.929215 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.518346 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.518346 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 82848883 # number of integer regfile reads
+system.cpu0.int_regfile_writes 47347730 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 16917 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 13431 # number of floating regfile writes
+system.cpu0.cc_regfile_reads 268451571 # number of cc regfile reads
+system.cpu0.cc_regfile_writes 27744432 # number of cc regfile writes
+system.cpu0.misc_regfile_reads 149385288 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 777097 # number of misc regfile writes
+system.cpu0.dcache.tags.replacements 854224 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.968814 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 42339027 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 854736 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 49.534625 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 186719500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 247.066049 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 264.902765 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.482551 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.517388 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999939 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 189260797 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 189260797 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 12293541 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 12887736 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 25181277 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 7941758 # number of WriteReq hits
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-system.cpu0.dcache.WriteReq_hits::total 15902591 # number of WriteReq hits
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-system.cpu0.icache.demand_mshr_miss_latency::total 26047394473 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12547401986 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 13499992487 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 26047394473 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 86506500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 86506500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 86506500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total 86506500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.046516 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.048117 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047330 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.046516 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.048117 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.047330 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.046516 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.048117 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.047330 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13399.059614 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13490.158162 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13446.120560 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13399.059614 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13490.158162 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13446.120560 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13399.059614 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13490.158162 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13446.120560 # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129500.748503 # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129500.748503 # average overall mshr uncacheable latency
+system.cpu0.icache.writebacks::writebacks 1939563 # number of writebacks
+system.cpu0.icache.writebacks::total 1939563 # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71879 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 76450 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 148329 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 71879 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst 76450 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 148329 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 71879 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst 76450 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 148329 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 939619 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1000599 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 1940218 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 939619 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 1000599 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 1940218 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 939619 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 1000599 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 1940218 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 667 # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total 667 # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 667 # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total 667 # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12628351483 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 13458642491 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 26086993974 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12628351483 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 13458642491 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 26086993974 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12628351483 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 13458642491 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 26086993974 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 86307500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 86307500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 86307500 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total 86307500 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.046685 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.048376 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047542 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.046685 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.048376 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.047542 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.046685 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.048376 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.047542 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13439.863905 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13450.585590 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13445.393236 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13439.863905 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13450.585590 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13445.393236 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13439.863905 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13450.585590 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13445.393236 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129396.551724 # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129396.551724 # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129396.551724 # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129396.551724 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 27851239 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 14560281 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 547901 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 17369720 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 13131935 # Number of BTB hits
+system.cpu1.branchPred.lookups 27771206 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 14500509 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 522402 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 17226329 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 8535757 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 75.602456 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 6845775 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 28937 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 49.550644 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 6833635 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 30645 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups 4632770 # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits 4521609 # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses 111161 # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted 32231 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1330,86 +1334,85 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 58134 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 58134 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19184 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13709 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 25241 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 32893 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 754.218223 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 5187.950869 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-16383 32437 98.61% 98.61% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-32767 325 0.99% 99.60% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-49151 66 0.20% 99.80% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-65535 27 0.08% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-81919 14 0.04% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::98304-114687 6 0.02% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::114688-131071 7 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-147455 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 32893 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 13323 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 14712.226976 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 12353.172902 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 8523.936722 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767 13006 97.62% 97.62% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535 308 2.31% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303 7 0.05% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 13323 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 91468552244 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.754474 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.453530 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 91381383244 99.90% 99.90% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3 60460000 0.07% 99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5 14228500 0.02% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7 4319000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9 2420500 0.00% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11 1621000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13 756000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15 2345500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17 509500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19 194000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-21 44500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::22-23 92500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-25 69000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::26-27 14000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-29 16500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::30-31 78500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 91468552244 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 3728 68.30% 68.30% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 1730 31.70% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 5458 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58134 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 59668 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 59668 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19466 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14180 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 26022 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 33646 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 657.210367 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 4292.478693 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-16383 33233 98.77% 98.77% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-32767 307 0.91% 99.68% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-49151 64 0.19% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-65535 23 0.07% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-81919 10 0.03% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::81920-98303 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-114687 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::114688-131071 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::147456-163839 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 33646 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 13510 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 14754.441155 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 12483.879781 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 8047.547321 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383 9092 67.30% 67.30% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767 4121 30.50% 97.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151 269 1.99% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535 27 0.20% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 13510 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 94672983040 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.774011 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.442469 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 94586502540 99.91% 99.91% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3 59948000 0.06% 99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5 13676000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7 4818000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9 2374500 0.00% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11 1378000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13 809000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15 2250500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17 491500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19 205500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-21 133000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::22-23 51500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-25 144500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::26-27 33000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-29 26000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::30-31 141500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 94672983040 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 3789 68.70% 68.70% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 1726 31.30% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 5515 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 59668 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58134 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5458 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 59668 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5515 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5458 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 63592 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5515 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 65183 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 14422090 # DTB read hits
-system.cpu1.dtb.read_misses 50182 # DTB read misses
-system.cpu1.dtb.write_hits 10473943 # DTB write hits
-system.cpu1.dtb.write_misses 7952 # DTB write misses
-system.cpu1.dtb.flush_tlb 187 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 438 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits 14351950 # DTB read hits
+system.cpu1.dtb.read_misses 51492 # DTB read misses
+system.cpu1.dtb.write_hits 10462781 # DTB write hits
+system.cpu1.dtb.write_misses 8176 # DTB write misses
+system.cpu1.dtb.flush_tlb 185 # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva 452 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 3617 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 774 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 1261 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 3688 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 817 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 1295 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 668 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 14472272 # DTB read accesses
-system.cpu1.dtb.write_accesses 10481895 # DTB write accesses
+system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 14403442 # DTB read accesses
+system.cpu1.dtb.write_accesses 10470957 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 24896033 # DTB hits
-system.cpu1.dtb.misses 58134 # DTB misses
-system.cpu1.dtb.accesses 24954167 # DTB accesses
+system.cpu1.dtb.hits 24814731 # DTB hits
+system.cpu1.dtb.misses 59668 # DTB misses
+system.cpu1.dtb.accesses 24874399 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1439,381 +1442,384 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 8670 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 8670 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2733 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 5073 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 864 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 7806 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 1475.083269 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 5979.271301 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-8191 7339 94.02% 94.02% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-16383 201 2.57% 96.59% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-24575 162 2.08% 98.67% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-32767 41 0.53% 99.19% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-40959 20 0.26% 99.45% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::40960-49151 18 0.23% 99.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::49152-57343 11 0.14% 99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::57344-65535 7 0.09% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-73727 6 0.08% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 7806 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 3293 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 13788.642575 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11489.093660 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 8040.901956 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191 943 28.64% 28.64% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383 1544 46.89% 75.52% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575 636 19.31% 94.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767 109 3.31% 98.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959 26 0.79% 98.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151 30 0.91% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.06% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 3293 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 39929935692 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 0.810654 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev 0.392199 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 7566087000 18.95% 18.95% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 32359225692 81.04% 99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 3801500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3 739500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4 82000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 39929935692 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 1840 75.75% 75.75% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 589 24.25% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 2429 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 8103 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 8103 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2668 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4534 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore 901 # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples 7202 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean 1511.663427 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 6714.706424 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-8191 6781 94.15% 94.15% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-16383 223 3.10% 97.25% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-24575 95 1.32% 98.57% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-32767 31 0.43% 99.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-40959 22 0.31% 99.31% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::40960-49151 21 0.29% 99.60% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::49152-57343 6 0.08% 99.68% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::57344-65535 5 0.07% 99.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-73727 5 0.07% 99.82% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::73728-81919 4 0.06% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::81920-90111 3 0.04% 99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::90112-98303 3 0.04% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-106495 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::106496-114687 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 7202 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 3356 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 13427.145411 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11321.856073 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 7351.367505 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191 969 28.87% 28.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383 1595 47.53% 76.40% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575 704 20.98% 97.38% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767 60 1.79% 99.17% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959 15 0.45% 99.61% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151 10 0.30% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.06% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 3356 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 30238902600 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean 0.763443 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev 0.425547 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 7158457500 23.67% 23.67% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1 23076737600 76.31% 99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2 2728500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3 531500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4 338000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5 109500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 30238902600 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 1852 75.44% 75.44% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 603 24.56% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 2455 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 8670 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 8670 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 8103 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 8103 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2429 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2429 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 11099 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 20800432 # ITB inst hits
-system.cpu1.itb.inst_misses 8670 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2455 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2455 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 10558 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 20686520 # ITB inst hits
+system.cpu1.itb.inst_misses 8103 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 187 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 438 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb 185 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva 452 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2396 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 2423 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1452 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1387 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 20809102 # ITB inst accesses
-system.cpu1.itb.hits 20800432 # DTB hits
-system.cpu1.itb.misses 8670 # DTB misses
-system.cpu1.itb.accesses 20809102 # DTB accesses
-system.cpu1.numCycles 114311171 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 20694623 # ITB inst accesses
+system.cpu1.itb.hits 20686520 # DTB hits
+system.cpu1.itb.misses 8103 # DTB misses
+system.cpu1.itb.accesses 20694623 # DTB accesses
+system.cpu1.numCycles 114249642 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 41255732 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 107366172 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 27851239 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 19977710 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 67431456 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3269763 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 132240 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 6802 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 490 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 244886 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 129624 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 516 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 20797736 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 380485 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 4341 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 110836590 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.165245 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.275623 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 41315815 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 106868458 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 27771206 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 19891001 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 67522618 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3218365 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 120489 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 7203 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 373 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 155077 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 135282 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 428 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 20683839 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 366531 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 4147 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 110866430 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.159053 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.270352 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 81231588 73.29% 73.29% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 3970288 3.58% 76.87% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 2467097 2.23% 79.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 8234974 7.43% 86.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1686085 1.52% 88.05% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 1118021 1.01% 89.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 6327387 5.71% 94.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 1165631 1.05% 95.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 4635519 4.18% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 81385669 73.41% 73.41% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 3966024 3.58% 76.99% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 2458990 2.22% 79.20% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 8216379 7.41% 86.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1659206 1.50% 88.11% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 1099479 0.99% 89.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 6321498 5.70% 94.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 1169763 1.06% 95.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4589422 4.14% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 110836590 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.243644 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.939245 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 28312223 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 63485769 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 15857940 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 1699967 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1480365 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1967991 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 156560 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 89109002 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 506529 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1480365 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 29245196 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 7030025 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 46679858 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 16613031 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 9787785 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 85253260 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 3942 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 1676107 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 305456 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 7062303 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 88411129 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 392062369 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 94760881 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 6288 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 74434583 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 13976546 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1569925 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1472475 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 9793304 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 15295862 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 11556895 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 2150664 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 2742502 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 82043962 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1094941 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 78552222 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 91402 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 11492320 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 25159173 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 115830 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 110836590 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.708721 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.399471 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 110866430 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.243075 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.935394 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 28349810 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 63611088 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 15737668 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 1707179 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1460344 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1943796 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 150726 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 88547543 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 497407 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1460344 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 29270752 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 6941234 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 46643920 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 16512645 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 10037169 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 84769560 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 3293 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 1700452 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 295960 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 7294084 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 88006736 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 389941348 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 94160116 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 6639 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 74402972 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 13603764 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1570437 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1473591 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 9835455 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 15202584 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 11508546 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 2153155 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 2847808 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 81703406 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1095595 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 78289936 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 93469 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 11173378 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 24596663 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 114922 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 110866430 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.706164 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.396793 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 79260307 71.51% 71.51% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 10548653 9.52% 81.03% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 8143333 7.35% 88.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 6690324 6.04% 94.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 2458107 2.22% 96.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1498250 1.35% 97.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1549439 1.40% 99.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 479797 0.43% 99.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 208380 0.19% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 79351505 71.57% 71.57% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 10562137 9.53% 81.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 8130695 7.33% 88.43% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 6659293 6.01% 94.44% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 2446771 2.21% 96.65% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1483581 1.34% 97.99% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1548529 1.40% 99.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 478985 0.43% 99.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 204934 0.18% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 110836590 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 110866430 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 101010 9.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 6 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 525539 46.85% 55.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 495241 44.15% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 95398 8.54% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 6 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 529553 47.39% 55.93% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 492367 44.07% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 2114 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 52641439 67.01% 67.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 59500 0.08% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 4515 0.01% 67.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 67.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 14821785 18.87% 85.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 11022863 14.03% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 2080 0.00% 0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 52483936 67.04% 67.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 59147 0.08% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 3 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 4561 0.01% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 14738514 18.83% 85.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 11001690 14.05% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 78552222 # Type of FU issued
-system.cpu1.iq.rate 0.687179 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 1121796 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.014281 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 269139975 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 94675085 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 76216531 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 14257 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 7438 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6100 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 79664197 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7707 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 356033 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 78289936 # Type of FU issued
+system.cpu1.iq.rate 0.685253 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 1117324 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.014272 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 268642821 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 94014634 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 76000311 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 14274 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8222 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6128 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 79397497 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7683 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 354386 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2227814 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 2318 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 52493 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1114040 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2162238 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 2091 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 51645 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1037860 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 209025 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 78912 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 208157 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 79710 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1480365 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 5648229 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 1078467 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 83272482 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 147374 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 15295862 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 11556895 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 563425 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 44942 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 1020454 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 52493 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 252230 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 220958 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 473188 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 77949376 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 14581691 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 544828 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1460344 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 5576526 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 1063680 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 82916416 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 111836 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 15202584 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 11508546 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 564987 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 44159 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 1006496 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 51645 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 224871 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 227319 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 452190 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 77723399 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 14509905 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 506997 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 133579 # number of nop insts executed
-system.cpu1.iew.exec_refs 25499167 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 14792050 # Number of branches executed
-system.cpu1.iew.exec_stores 10917476 # Number of stores executed
-system.cpu1.iew.exec_rate 0.681905 # Inst execution rate
-system.cpu1.iew.wb_sent 77406308 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 76222631 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 39922690 # num instructions producing a value
-system.cpu1.iew.wb_consumers 69416540 # num instructions consuming a value
-system.cpu1.iew.wb_rate 0.666799 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.575118 # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts 11468538 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 979111 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 393347 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 108253443 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.662563 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.545359 # Number of insts commited each cycle
+system.cpu1.iew.exec_nop 117415 # number of nop insts executed
+system.cpu1.iew.exec_refs 25415143 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 14757344 # Number of branches executed
+system.cpu1.iew.exec_stores 10905238 # Number of stores executed
+system.cpu1.iew.exec_rate 0.680294 # Inst execution rate
+system.cpu1.iew.wb_sent 77189704 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 76006439 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 39824876 # num instructions producing a value
+system.cpu1.iew.wb_consumers 69384097 # num instructions consuming a value
+system.cpu1.iew.wb_rate 0.665266 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.573977 # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts 11134037 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 980673 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 373526 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 108332250 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.661887 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.544752 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 80221800 74.11% 74.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 12496129 11.54% 85.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6526093 6.03% 91.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 2656879 2.45% 94.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1402571 1.30% 95.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 920713 0.85% 96.28% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 1916865 1.77% 98.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 408370 0.38% 98.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1704023 1.57% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 80307491 74.13% 74.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 12497635 11.54% 85.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6520784 6.02% 91.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 2657688 2.45% 94.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1393058 1.29% 95.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 929919 0.86% 96.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 1912801 1.77% 98.05% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 410208 0.38% 98.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1702666 1.57% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 108253443 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 59091533 # Number of instructions committed
-system.cpu1.commit.committedOps 71724765 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 108332250 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 59059498 # Number of instructions committed
+system.cpu1.commit.committedOps 71703684 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 23510903 # Number of memory references committed
-system.cpu1.commit.loads 13068048 # Number of loads committed
-system.cpu1.commit.membars 397789 # Number of memory barriers committed
-system.cpu1.commit.branches 14004784 # Number of branches committed
-system.cpu1.commit.fp_insts 6010 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 62686547 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 2707347 # Number of function calls committed.
+system.cpu1.commit.refs 23511032 # Number of memory references committed
+system.cpu1.commit.loads 13040346 # Number of loads committed
+system.cpu1.commit.membars 397932 # Number of memory barriers committed
+system.cpu1.commit.branches 13998335 # Number of branches committed
+system.cpu1.commit.fp_insts 5786 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 62664719 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 2706612 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 48151619 67.13% 67.13% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 57729 0.08% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 4514 0.01% 67.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 13068048 18.22% 85.44% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 10442855 14.56% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 48130630 67.12% 67.12% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 57462 0.08% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 4560 0.01% 67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 13040346 18.19% 85.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 10470686 14.60% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 71724765 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 1704023 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 176984123 # The number of ROB reads
-system.cpu1.rob.rob_writes 168968777 # The number of ROB writes
-system.cpu1.timesIdled 412637 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 3474581 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 3325416664 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 59013351 # Number of Instructions Simulated
-system.cpu1.committedOps 71646583 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 1.937039 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.937039 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.516252 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.516252 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 84580836 # number of integer regfile reads
-system.cpu1.int_regfile_writes 48527680 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 17118 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 13376 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 275597104 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 29295940 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 152598843 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 741284 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
+system.cpu1.commit.op_class_0::total 71703684 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 1702666 # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads 176703276 # The number of ROB reads
+system.cpu1.rob.rob_writes 168209083 # The number of ROB writes
+system.cpu1.timesIdled 415823 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 3383212 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 3313474839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 58981437 # Number of Instructions Simulated
+system.cpu1.committedOps 71625623 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 1.937044 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.937044 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.516251 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.516251 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 84346535 # number of integer regfile reads
+system.cpu1.int_regfile_writes 48387599 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 17183 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 13302 # number of floating regfile writes
+system.cpu1.cc_regfile_reads 274779775 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 29204766 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 152559581 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 742832 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 30182 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30182 # Transaction distribution
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
@@ -1836,9 +1842,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
@@ -1859,36 +1865,36 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 334000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
@@ -1896,54 +1902,54 @@ system.iobus.reqLayer20.occupancy 9000 # La
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
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system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
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-system.iocache.ReadReq_misses::total 223 # number of ReadReq misses
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system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
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system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
@@ -1952,14 +1958,14 @@ system.iocache.demand_miss_rate::realview.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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-system.iocache.WriteLineReq_avg_miss_latency::total 125654.042099 # average WriteLineReq miss latency
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system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1970,22 +1976,22 @@ system.iocache.fast_writes 0 # nu
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
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-system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
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system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
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system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
@@ -1994,274 +2000,274 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
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system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.010810 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010719 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.028632 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.025771 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027255 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001596 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000151 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010621 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.186127 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.002035 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010810 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.176181 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.061048 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001596 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000151 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010621 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.186127 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.002035 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010810 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.176181 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.061048 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 132736.363636 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 129865.248227 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68022.503516 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68022.831050 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68022.660819 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68500 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68444.444444 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68468.750000 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123588.533668 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123625.407695 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 123605.560123 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123537.508060 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 123103.934783 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123305.574483 # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125187.234772 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127916.809402 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126444.146146 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129271.929825 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126461.038961 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 129026.315789 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68039.735099 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67994.841562 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68018.486223 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68055.555556 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68406.250000 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68280 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123180.606630 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123781.955397 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 123465.997810 # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123955.903488 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122830.035232 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123370.335033 # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126433.920174 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127968.372039 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127132.122495 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132736.363636 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123537.508060 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123745.752562 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123103.934783 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124045.493871 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 123820.613689 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129271.929825 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123955.903488 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123510.775255 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126461.038961 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122830.035232 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124177.716751 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 123776.078495 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132736.363636 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123537.508060 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123745.752562 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130361.445783 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123103.934783 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124045.493871 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 123820.613689 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188336.146130 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191333.801527 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188313.693021 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158608.534262 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190068.852592 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172711.396259 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173240.767306 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190789.524041 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 181065.462608 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123955.903488 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123510.775255 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126461.038961 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122830.035232 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124177.716751 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 123776.078495 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113679.905547 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188657.262946 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191062.303955 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188314.253271 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 159027.717853 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189801.073957 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172737.857039 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113679.905547 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173632.794113 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190519.334501 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 181077.933400 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 31797 # Transaction distribution
-system.membus.trans_dist::ReadResp 68215 # Transaction distribution
+system.membus.trans_dist::ReadReq 31796 # Transaction distribution
+system.membus.trans_dist::ReadResp 68170 # Transaction distribution
system.membus.trans_dist::WriteReq 27588 # Transaction distribution
system.membus.trans_dist::WriteResp 27588 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 131889 # Transaction distribution
-system.membus.trans_dist::CleanEvict 8934 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4627 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 16 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 131952 # Transaction distribution
+system.membus.trans_dist::CleanEvict 8761 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4667 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 25 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 138214 # Transaction distribution
-system.membus.trans_dist::ReadExResp 138214 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 36419 # Transaction distribution
+system.membus.trans_dist::ReadExReq 137941 # Transaction distribution
+system.membus.trans_dist::ReadExResp 137941 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 36375 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2082 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 468775 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 576357 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 649232 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 468049 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 575633 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72895 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72895 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 648528 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 768 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4164 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17330524 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 17494517 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17313692 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 17477749 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19811637 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 495 # Total snoops (count)
-system.membus.snoop_fanout::samples 415722 # Request fanout histogram
+system.membus.pkt_size::total 19794869 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 502 # Total snoops (count)
+system.membus.snoop_fanout::samples 415341 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 415722 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 415341 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 415722 # Request fanout histogram
-system.membus.reqLayer0.occupancy 95416500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 415341 # Request fanout histogram
+system.membus.reqLayer0.occupancy 95676000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 17812 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 18156 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1712500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1708000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 923381363 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 923138375 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1008957748 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1006417999 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 1266123 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
@@ -2556,60 +2562,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 5624778 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 2831936 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 48182 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 419 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 419 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests 5630525 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 2835578 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 46774 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 561 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 561 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 148456 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2644699 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 149785 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2648524 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27588 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27588 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 836907 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 1936583 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 159084 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2829 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 72 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2901 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 296764 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 296764 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 1937168 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 559160 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 836080 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 1939563 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 158867 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 3009 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 79 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 3088 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 296443 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 296443 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 1940218 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 558543 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5811959 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2689934 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41086 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 162624 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 8705603 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247943872 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 100077301 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 63112 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 285092 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 348369377 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 207323 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3149099 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.027296 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.162945 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5820932 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2687552 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37507 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 166977 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 8712968 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 248323008 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99964405 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56712 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 289268 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 348633393 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 209286 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3152616 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.027333 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.163051 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 3063141 97.27% 97.27% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 85958 2.73% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 3066446 97.27% 97.27% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 86170 2.73% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3149099 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 5537165495 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 3152616 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 5542088496 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 269377 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 378877 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2908738015 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2913039562 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1330413513 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1329029128 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 25349416 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 23370914 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 91789111 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 95118571 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 3037 # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index e615eccd3..3367a33d1 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -1,168 +1,168 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 47.454492 # Number of seconds simulated
-sim_ticks 47454492026000 # Number of ticks simulated
-final_tick 47454492026000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.535940 # Number of seconds simulated
+sim_ticks 47535940136000 # Number of ticks simulated
+final_tick 47535940136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 326065 # Simulator instruction rate (inst/s)
-host_op_rate 383423 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16260643539 # Simulator tick rate (ticks/s)
-host_mem_usage 772552 # Number of bytes of host memory used
-host_seconds 2918.37 # Real time elapsed on the host
-sim_insts 951575519 # Number of instructions simulated
-sim_ops 1118968402 # Number of ops (including micro ops) simulated
+host_inst_rate 225035 # Simulator instruction rate (inst/s)
+host_op_rate 264677 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11911388135 # Simulator tick rate (ticks/s)
+host_mem_usage 769700 # Number of bytes of host memory used
+host_seconds 3990.80 # Real time elapsed on the host
+sim_insts 898069628 # Number of instructions simulated
+sim_ops 1056270581 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 233088 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 210624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 7916672 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 17537736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 18153728 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 166400 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 132160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3894272 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 12497872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 21171968 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 432064 # Number of bytes read from this memory
-system.physmem.bytes_read::total 82346584 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 7916672 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3894272 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 11810944 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 92922304 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 89728 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 8161024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 14243656 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 14782784 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 150400 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 127744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 3048640 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 9523856 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 12507584 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 413056 # Number of bytes read from this memory
+system.physmem.bytes_read::total 63147416 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 8161024 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 3048640 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 11209664 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 75703424 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 92942888 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 3642 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 3291 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 123698 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 274040 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 283652 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2600 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 2065 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 60848 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 195292 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 330812 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6751 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1286691 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1451911 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 75724008 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1402 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 127516 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 222570 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 230981 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 2350 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1996 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 47635 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 148823 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 195431 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6454 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 986704 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1182866 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1454485 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 4912 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 4438 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 166827 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 369570 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 382550 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 3507 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 2785 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 82063 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 263365 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 446153 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 9105 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1735275 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 166827 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 82063 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 248890 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1958135 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1185440 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 2081 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 1888 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 171681 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 299640 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 310981 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 3164 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 2687 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 64133 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 200351 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 263118 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8689 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1328414 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 171681 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 64133 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 235815 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1592551 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1958569 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1958135 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 4912 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 4438 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 166827 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 370003 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 382550 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 3507 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 2785 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 82063 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 263365 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 446153 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 9105 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3693844 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1286691 # Number of read requests accepted
-system.physmem.writeReqs 1454485 # Number of write requests accepted
-system.physmem.readBursts 1286691 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1454485 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 82317440 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 30784 # Total number of bytes read from write queue
-system.physmem.bytesWritten 92941888 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 82346584 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 92942888 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 481 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total 1592984 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1592551 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 2081 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 1888 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 171681 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 300073 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 310981 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 3164 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 2687 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 64133 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 200351 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 263118 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8689 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2921398 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 986704 # Number of read requests accepted
+system.physmem.writeReqs 1185440 # Number of write requests accepted
+system.physmem.readBursts 986704 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1185440 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 63115328 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 33728 # Total number of bytes read from write queue
+system.physmem.bytesWritten 75722560 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 63147416 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 75724008 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 527 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 68545 # Per bank write bursts
-system.physmem.perBankRdBursts::1 77862 # Per bank write bursts
-system.physmem.perBankRdBursts::2 76461 # Per bank write bursts
-system.physmem.perBankRdBursts::3 81936 # Per bank write bursts
-system.physmem.perBankRdBursts::4 74664 # Per bank write bursts
-system.physmem.perBankRdBursts::5 81822 # Per bank write bursts
-system.physmem.perBankRdBursts::6 81067 # Per bank write bursts
-system.physmem.perBankRdBursts::7 83827 # Per bank write bursts
-system.physmem.perBankRdBursts::8 73756 # Per bank write bursts
-system.physmem.perBankRdBursts::9 133954 # Per bank write bursts
-system.physmem.perBankRdBursts::10 75964 # Per bank write bursts
-system.physmem.perBankRdBursts::11 77586 # Per bank write bursts
-system.physmem.perBankRdBursts::12 69247 # Per bank write bursts
-system.physmem.perBankRdBursts::13 78127 # Per bank write bursts
-system.physmem.perBankRdBursts::14 73347 # Per bank write bursts
-system.physmem.perBankRdBursts::15 78045 # Per bank write bursts
-system.physmem.perBankWrBursts::0 83788 # Per bank write bursts
-system.physmem.perBankWrBursts::1 90226 # Per bank write bursts
-system.physmem.perBankWrBursts::2 90168 # Per bank write bursts
-system.physmem.perBankWrBursts::3 95983 # Per bank write bursts
-system.physmem.perBankWrBursts::4 89513 # Per bank write bursts
-system.physmem.perBankWrBursts::5 93413 # Per bank write bursts
-system.physmem.perBankWrBursts::6 92742 # Per bank write bursts
-system.physmem.perBankWrBursts::7 93553 # Per bank write bursts
-system.physmem.perBankWrBursts::8 87937 # Per bank write bursts
-system.physmem.perBankWrBursts::9 94416 # Per bank write bursts
-system.physmem.perBankWrBursts::10 91588 # Per bank write bursts
-system.physmem.perBankWrBursts::11 94818 # Per bank write bursts
-system.physmem.perBankWrBursts::12 85405 # Per bank write bursts
-system.physmem.perBankWrBursts::13 92349 # Per bank write bursts
-system.physmem.perBankWrBursts::14 86484 # Per bank write bursts
-system.physmem.perBankWrBursts::15 89834 # Per bank write bursts
+system.physmem.perBankRdBursts::0 63842 # Per bank write bursts
+system.physmem.perBankRdBursts::1 66317 # Per bank write bursts
+system.physmem.perBankRdBursts::2 58522 # Per bank write bursts
+system.physmem.perBankRdBursts::3 64863 # Per bank write bursts
+system.physmem.perBankRdBursts::4 59095 # Per bank write bursts
+system.physmem.perBankRdBursts::5 67998 # Per bank write bursts
+system.physmem.perBankRdBursts::6 58322 # Per bank write bursts
+system.physmem.perBankRdBursts::7 56006 # Per bank write bursts
+system.physmem.perBankRdBursts::8 52486 # Per bank write bursts
+system.physmem.perBankRdBursts::9 111449 # Per bank write bursts
+system.physmem.perBankRdBursts::10 50777 # Per bank write bursts
+system.physmem.perBankRdBursts::11 58061 # Per bank write bursts
+system.physmem.perBankRdBursts::12 51458 # Per bank write bursts
+system.physmem.perBankRdBursts::13 52890 # Per bank write bursts
+system.physmem.perBankRdBursts::14 54883 # Per bank write bursts
+system.physmem.perBankRdBursts::15 59208 # Per bank write bursts
+system.physmem.perBankWrBursts::0 77123 # Per bank write bursts
+system.physmem.perBankWrBursts::1 81948 # Per bank write bursts
+system.physmem.perBankWrBursts::2 74623 # Per bank write bursts
+system.physmem.perBankWrBursts::3 80009 # Per bank write bursts
+system.physmem.perBankWrBursts::4 75007 # Per bank write bursts
+system.physmem.perBankWrBursts::5 80611 # Per bank write bursts
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+system.physmem.wrPerTurnAround::76-79 108 0.18% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 156 0.25% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 24 0.04% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 11 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 61315 # Writes before turning the bus around for reads
+system.physmem.totQLat 31916274746 # Total ticks spent queuing
+system.physmem.totMemAccLat 50407093496 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4930885000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 32363.64 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 55329.37 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.74 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.96 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 51113.64 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.33 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.33 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing
-system.physmem.readRowHits 962295 # Number of row buffer hits during reads
-system.physmem.writeRowHits 551527 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.82 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 37.98 # Row buffer hit rate for writes
-system.physmem.avgGap 17311726.76 # Average gap between requests
-system.physmem.pageHitRate 55.28 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 4656869280 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2540950500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4884235200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 4726421280 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1219171959180 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27403246221750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31738723386870 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.824424 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45587152483743 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1584609520000 # Time in different power states
+system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing
+system.physmem.readRowHits 734466 # Number of row buffer hits during reads
+system.physmem.writeRowHits 450279 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.48 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 38.06 # Row buffer hit rate for writes
+system.physmem.avgGap 21884340.09 # Average gap between requests
+system.physmem.pageHitRate 54.61 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3920933520 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2139398250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3860672400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3974430240 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1203845511330 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27465556979250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31788114192270 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.717535 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45690953287273 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1587329380000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 282729931257 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 257656491727 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 4601144520 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2510545125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 5148202800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4683944880 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3099496729680 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1221460881390 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27401238395250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31739139843645 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.833200 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45583769039323 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1584609520000 # Time in different power states
+system.physmem_1.actEnergy 3522604680 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1922056125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3831445800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3692478960 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1196085851100 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27472363698750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31786234402695 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.677991 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45702273449121 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1587329380000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 286113375677 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 246336261879 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
@@ -382,15 +381,19 @@ system.cf0.dma_read_txs 122 # Nu
system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 147959066 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 105493690 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 6448516 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 111296242 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 81329533 # Number of BTB hits
+system.cpu0.branchPred.lookups 146462396 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 102364881 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 6839955 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 108739004 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 75372629 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 73.074824 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 17161750 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 1109253 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 69.315173 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 17612403 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 1195732 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups 3915449 # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits 2665463 # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses 1249986 # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted 447212 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -421,64 +424,62 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 300034 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 300034 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11904 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91094 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 300034 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 300034 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 300034 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 102998 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 24703.863182 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21663.255890 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 26203.116698 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 100872 97.94% 97.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 180 0.17% 98.11% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1639 1.59% 99.70% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 73 0.07% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 76 0.07% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 46 0.04% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 69 0.07% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 28 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 102998 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 302048 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 302048 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10564 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84260 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 302048 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 302048 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 302048 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 94824 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22896.634818 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 21259.302446 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 17613.215135 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 93928 99.06% 99.06% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.18% 99.23% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 600 0.63% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 32 0.03% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 34 0.04% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 94824 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 91094 88.44% 88.44% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 11904 11.56% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 102998 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 300034 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 84260 88.86% 88.86% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 10564 11.14% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 94824 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302048 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 300034 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 102998 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302048 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94824 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 102998 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 403032 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94824 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 396872 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 94891169 # DTB read hits
-system.cpu0.dtb.read_misses 247198 # DTB read misses
-system.cpu0.dtb.write_hits 84318368 # DTB write hits
-system.cpu0.dtb.write_misses 52836 # DTB write misses
-system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 94909868 # DTB read hits
+system.cpu0.dtb.read_misses 253021 # DTB read misses
+system.cpu0.dtb.write_hits 83284387 # DTB write hits
+system.cpu0.dtb.write_misses 49027 # DTB write misses
+system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 40307 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1747 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 9392 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 38313 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 2113 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 10577 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 12141 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 95138367 # DTB read accesses
-system.cpu0.dtb.write_accesses 84371204 # DTB write accesses
+system.cpu0.dtb.perms_faults 10792 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 95162889 # DTB read accesses
+system.cpu0.dtb.write_accesses 83333414 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 179209537 # DTB hits
-system.cpu0.dtb.misses 300034 # DTB misses
-system.cpu0.dtb.accesses 179509571 # DTB accesses
+system.cpu0.dtb.hits 178194255 # DTB hits
+system.cpu0.dtb.misses 302048 # DTB misses
+system.cpu0.dtb.accesses 178496303 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -508,187 +509,228 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 71231 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 71231 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 667 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60897 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 71231 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 71231 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 71231 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 61564 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 29116.975830 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24576.932577 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 30900.488305 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 59287 96.30% 96.30% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 14 0.02% 96.32% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 2011 3.27% 99.59% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 94 0.15% 99.74% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 85 0.14% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 46 0.07% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 61564 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 66529 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 66529 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 603 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54822 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 66529 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 66529 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 66529 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 55425 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25786.567433 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23469.117152 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 20785.804114 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767 51379 92.70% 92.70% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535 3140 5.67% 98.37% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303 12 0.02% 98.39% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.39% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839 536 0.97% 99.36% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607 270 0.49% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375 8 0.01% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911 15 0.03% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 55425 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 60897 98.92% 98.92% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 667 1.08% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 61564 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 54822 98.91% 98.91% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 603 1.09% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 55425 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 71231 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 71231 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66529 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66529 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61564 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61564 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 132795 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 264582301 # ITB inst hits
-system.cpu0.itb.inst_misses 71231 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55425 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55425 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 121954 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 260612167 # ITB inst hits
+system.cpu0.itb.inst_misses 66529 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 28772 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 27578 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 223649 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 178681 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 264653532 # ITB inst accesses
-system.cpu0.itb.hits 264582301 # DTB hits
-system.cpu0.itb.misses 71231 # DTB misses
-system.cpu0.itb.accesses 264653532 # DTB accesses
-system.cpu0.numCycles 1106984671 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 260678696 # ITB inst accesses
+system.cpu0.itb.hits 260612167 # DTB hits
+system.cpu0.itb.misses 66529 # DTB misses
+system.cpu0.itb.accesses 260678696 # DTB accesses
+system.cpu0.numCycles 1099930824 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 488099503 # Number of instructions committed
-system.cpu0.committedOps 574418730 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 50785821 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 5453 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 93802885102 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.267949 # CPI: cycles per instruction
-system.cpu0.ipc 0.440927 # IPC: instructions per cycle
+system.cpu0.committedInsts 487305462 # Number of instructions committed
+system.cpu0.committedOps 572197777 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 47186623 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 4440 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 93972724601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.257169 # CPI: cycles per instruction
+system.cpu0.ipc 0.443033 # IPC: instructions per cycle
+system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
+system.cpu0.op_class_0::IntAlu 396450876 69.29% 69.29% # Class of committed instruction
+system.cpu0.op_class_0::IntMult 1302433 0.23% 69.51% # Class of committed instruction
+system.cpu0.op_class_0::IntDiv 64217 0.01% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMisc 76920 0.01% 69.54% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction
+system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction
+system.cpu0.op_class_0::MemRead 91382938 15.97% 85.51% # Class of committed instruction
+system.cpu0.op_class_0::MemWrite 82920392 14.49% 100.00% # Class of committed instruction
+system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu0.op_class_0::total 572197777 # Class of committed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 5643 # number of quiesce instructions executed
-system.cpu0.tickCycles 789747765 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 317236906 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements 6140209 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 501.783411 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 169967706 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 6140721 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 27.678787 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 13277 # number of quiesce instructions executed
+system.cpu0.tickCycles 780613530 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 319317294 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements 5972011 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 508.033077 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 169168179 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 5972523 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 28.324408 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.783411 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980046 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.980046 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.033077 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992252 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.992252 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 388 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 361643482 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 361643482 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 86800691 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 86800691 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 78258675 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 78258675 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268918 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 268918 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 127943 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 127943 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1971519 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1971519 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1943002 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1943002 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 165059366 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 165059366 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 165328284 # number of overall hits
-system.cpu0.dcache.overall_hits::total 165328284 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 3776237 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 3776237 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 2642039 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 2642039 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 748095 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 748095 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 774634 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 774634 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 182353 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 182353 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 209431 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 209431 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 6418276 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 6418276 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 7166371 # number of overall misses
-system.cpu0.dcache.overall_misses::total 7166371 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 71342778500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 71342778500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67996340500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 67996340500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 46419090000 # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total 46419090000 # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3111811500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 3111811500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5902963500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 5902963500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7077000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7077000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 139339119000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 139339119000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 139339119000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 139339119000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 90576928 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 90576928 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 80900714 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 80900714 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1017013 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 1017013 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 902577 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total 902577 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2153872 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 2153872 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2152433 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 2152433 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 171477642 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 171477642 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 172494655 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 172494655 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041691 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.041691 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032658 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.032658 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.735581 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.735581 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.858247 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total 0.858247 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084663 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084663 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097300 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097300 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037429 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041545 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.041545 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18892.558518 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 18892.558518 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25736.312182 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 25736.312182 # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59923.899545 # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59923.899545 # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17064.767237 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17064.767237 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28185.719879 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28185.719879 # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses 359361260 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 359361260 # Number of data accesses
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+system.cpu0.dcache.ReadReq_misses::total 3693348 # number of ReadReq misses
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+system.cpu0.dcache.SoftPFReq_misses::total 661742 # number of SoftPFReq misses
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+system.cpu0.dcache.demand_misses::total 6153573 # number of demand (read+write) misses
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+system.cpu0.dcache.ReadReq_miss_latency::total 64125292500 # number of ReadReq miss cycles
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+system.cpu0.dcache.WriteReq_miss_latency::total 62047058000 # number of WriteReq miss cycles
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+system.cpu0.dcache.WriteLineReq_miss_latency::total 51167444000 # number of WriteLineReq miss cycles
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+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5746000 # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5746000 # number of StoreCondFailReq miss cycles
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+system.cpu0.dcache.demand_miss_latency::total 126172350500 # number of demand (read+write) miss cycles
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+system.cpu0.dcache.overall_miss_latency::total 126172350500 # number of overall miss cycles
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+system.cpu0.dcache.SoftPFReq_accesses::total 966772 # number of SoftPFReq accesses(hits+misses)
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+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.684486 # miss rate for SoftPFReq accesses
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+system.cpu0.dcache.demand_miss_rate::total 0.036104 # miss rate for demand accesses
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+system.cpu0.dcache.overall_miss_rate::total 0.039761 # miss rate for overall accesses
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+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17362.374870 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25220.074587 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 25220.074587 # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60346.652640 # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60346.652640 # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16484.243098 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16484.243098 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28412.814058 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21709.742460 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 21709.742460 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19443.469924 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 19443.469924 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20503.917074 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 20503.917074 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18513.062199 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 18513.062199 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -697,161 +739,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.writebacks::total 6140232 # number of writebacks
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-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 78 # number of WriteLineReq MSHR hits
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-system.cpu0.dcache.SoftPFReq_mshr_misses::total 746538 # number of SoftPFReq MSHR misses
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-system.cpu0.dcache.StoreCondReq_mshr_misses::total 209378 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15086 # number of ReadReq MSHR uncacheable
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16949.253530 # average ReadReq mshr miss latency
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-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58921.065746 # average WriteLineReq mshr miss latency
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -860,258 +902,256 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1120,242 +1160,251 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236376 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236376 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078301 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270406 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270406 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.746562 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.746562 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.138559 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024128 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052279 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078301 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.262462 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224517 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224517 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071267 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254730 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254730 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728290 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728290 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.125137 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.053996 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61741.289726 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29925.451776 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29925.451776 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19653.868363 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19653.868363 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 557499.727273 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 557499.727273 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57548.640546 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57548.640546 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32489.756980 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39651.911728 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39651.911728 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 68676.397845 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 68676.397845 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39758.098096 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51149.320787 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 59453.022795 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32489.756980 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43414.679931 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61741.289726 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46034.137306 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174585 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35899.796364 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56710.263890 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29958.038116 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29958.038116 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19875.340328 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19875.340328 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 994400 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 994400 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58388.867967 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58388.867967 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33267.758218 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35913.269977 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35913.269977 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70950.838813 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70950.838813 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37874.691491 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167006.529232 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141191.713035 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164452.679019 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164452.679019 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179904.022730 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179904.022730 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165693.017191 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145649.104605 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181697.727273 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159888.378301 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 32897508 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16815136 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 2403341 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2402836 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 505 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 933618 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 15066373 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 15977 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 15976 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 5804347 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 11960956 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 3276888 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 1153411 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 478642 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 376774 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 550943 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1307095 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1283776 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9846192 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5335526 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 825564 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 772295 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29642681 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19817496 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 405752 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1239273 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 51105202 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1263627520 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 749575419 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1544024 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4686408 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 2019433371 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 8071764 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 25329170 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.108588 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.311185 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests 33857668 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 17264460 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3128 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 2263959 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2263472 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 487 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq 924227 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 15578589 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 31149 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 31148 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 5528357 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 12594701 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 3060195 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 1058289 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 483217 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361321 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 533499 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1230571 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1205955 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10516550 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5115631 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 898497 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 845557 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 31653744 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19358528 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 379556 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1223236 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 52615064 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1349432640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 724409976 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1445984 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4653440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 2079942040 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 7567377 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 25314697 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.102016 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.302732 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 22579237 89.14% 89.14% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 2749428 10.85% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 505 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 22732690 89.80% 89.80% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 2581520 10.20% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 487 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 25329170 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 32745453976 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 25314697 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 33752723480 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 192728655 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 205163062 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 14851397186 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 15856801952 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 8851946898 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 8551593856 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 212824349 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 198848419 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 653582276 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 641675758 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 143060728 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 103431257 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 6108949 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 108043566 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 80039888 # Number of BTB hits
+system.cpu1.branchPred.lookups 127453033 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 91217282 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 5663830 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 96224557 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 67852361 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 74.081124 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 15973583 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 1078136 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 70.514600 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 14431851 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 916644 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups 3338859 # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits 2197659 # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses 1141200 # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted 412569 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1385,63 +1434,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 316205 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 316205 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13111 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 102055 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 316205 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 316205 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 316205 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 115166 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23006.933470 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21361.362420 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 17841.956140 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 114056 99.04% 99.04% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 145 0.13% 99.16% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 815 0.71% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.03% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 115166 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 1788277352 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1788277352 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1788277352 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 102056 88.62% 88.62% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 13111 11.38% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 115167 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 316205 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 261031 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 261031 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9619 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80662 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 261031 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 261031 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 261031 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 90281 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23808.564371 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21471.713865 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 22312.583155 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 88920 98.49% 98.49% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 187 0.21% 98.70% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 992 1.10% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 26 0.03% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 90281 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 1786242352 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1786242352 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1786242352 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 80662 89.35% 89.35% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 9619 10.65% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 90281 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261031 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 316205 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 115167 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261031 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90281 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 115167 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 431372 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90281 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 351312 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 90416501 # DTB read hits
-system.cpu1.dtb.read_misses 263668 # DTB read misses
-system.cpu1.dtb.write_hits 78865175 # DTB write hits
-system.cpu1.dtb.write_misses 52537 # DTB write misses
-system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 80497438 # DTB read hits
+system.cpu1.dtb.read_misses 213464 # DTB read misses
+system.cpu1.dtb.write_hits 70911031 # DTB write hits
+system.cpu1.dtb.write_misses 47567 # DTB write misses
+system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 39779 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1900 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 9673 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 37751 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1110 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 7072 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 11862 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 90680169 # DTB read accesses
-system.cpu1.dtb.write_accesses 78917712 # DTB write accesses
+system.cpu1.dtb.perms_faults 11967 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 80710902 # DTB read accesses
+system.cpu1.dtb.write_accesses 70958598 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 169281676 # DTB hits
-system.cpu1.dtb.misses 316205 # DTB misses
-system.cpu1.dtb.accesses 169597881 # DTB accesses
+system.cpu1.dtb.hits 151408469 # DTB hits
+system.cpu1.dtb.misses 261031 # DTB misses
+system.cpu1.dtb.accesses 151669500 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1471,187 +1521,222 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 61623 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 61623 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 682 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 51951 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 61623 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 61623 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 61623 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 52633 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26809.463644 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23734.871548 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 24762.364644 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 51446 97.74% 97.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 1035 1.97% 99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 44 0.08% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 33 0.06% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 52633 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1787261852 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1787261852 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1787261852 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 51951 98.70% 98.70% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 682 1.30% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 52633 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 64962 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 64962 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 549 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55482 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 64962 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 64962 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 64962 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 56031 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 27185.022577 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24059.100661 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 24848.225124 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 54737 97.69% 97.69% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.71% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 1140 2.03% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 63 0.11% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 56031 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 1785244852 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1785244852 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1785244852 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 55482 99.02% 99.02% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 549 0.98% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 56031 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61623 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61623 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64962 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64962 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52633 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 52633 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 114256 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 255703249 # ITB inst hits
-system.cpu1.itb.inst_misses 61623 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56031 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56031 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 120993 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 225980528 # ITB inst hits
+system.cpu1.itb.inst_misses 64962 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 47226 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1094 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 28254 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 26783 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 225386 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 166792 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 255764872 # ITB inst accesses
-system.cpu1.itb.hits 255703249 # DTB hits
-system.cpu1.itb.misses 61623 # DTB misses
-system.cpu1.itb.accesses 255764872 # DTB accesses
-system.cpu1.numCycles 1013399126 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 226045490 # ITB inst accesses
+system.cpu1.itb.hits 225980528 # DTB hits
+system.cpu1.itb.misses 64962 # DTB misses
+system.cpu1.itb.accesses 226045490 # DTB accesses
+system.cpu1.numCycles 884296043 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 463476016 # Number of instructions committed
-system.cpu1.committedOps 544549672 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 51973590 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 4681 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 93896343891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.186519 # CPI: cycles per instruction
-system.cpu1.ipc 0.457348 # IPC: instructions per cycle
+system.cpu1.committedInsts 410764166 # Number of instructions committed
+system.cpu1.committedOps 484072804 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 46607969 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 5245 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 94188329171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.152807 # CPI: cycles per instruction
+system.cpu1.ipc 0.464510 # IPC: instructions per cycle
+system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu1.op_class_0::IntAlu 334821764 69.17% 69.17% # Class of committed instruction
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+system.cpu1.op_class_0::FloatAdd 0 0.00% 69.38% # Class of committed instruction
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+system.cpu1.op_class_0::SimdFloatMisc 37353 0.01% 69.38% # Class of committed instruction
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+system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.38% # Class of committed instruction
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+system.cpu1.op_class_0::MemRead 77588616 16.03% 85.41% # Class of committed instruction
+system.cpu1.op_class_0::MemWrite 70613457 14.59% 100.00% # Class of committed instruction
+system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
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+system.cpu1.op_class_0::total 484072804 # Class of committed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 13591 # number of quiesce instructions executed
-system.cpu1.tickCycles 759435347 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 253963779 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements 5640902 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 433.747661 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 160682361 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5641413 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 28.482645 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8381463375500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 433.747661 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.847163 # Average percentage of cache occupancy
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-system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 341448433 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 341448433 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 82699161 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 82699161 # number of ReadReq hits
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-system.cpu1.dcache.SoftPFReq_hits::total 257576 # number of SoftPFReq hits
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-system.cpu1.dcache.WriteLineReq_hits::total 197387 # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1901357 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1901357 # number of LoadLockedReq hits
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-system.cpu1.dcache.StoreCondReq_hits::total 1855769 # number of StoreCondReq hits
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-system.cpu1.dcache.demand_hits::total 155939863 # number of demand (read+write) hits
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-system.cpu1.dcache.overall_hits::total 156197439 # number of overall hits
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-system.cpu1.dcache.ReadReq_misses::total 3585243 # number of ReadReq misses
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-system.cpu1.dcache.WriteReq_misses::total 2523734 # number of WriteReq misses
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-system.cpu1.dcache.SoftPFReq_misses::total 738365 # number of SoftPFReq misses
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-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162310 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 162310 # number of LoadLockedReq misses
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-system.cpu1.dcache.overall_misses::total 6847342 # number of overall misses
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-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7112000 # number of StoreCondFailReq miss cycles
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-system.cpu1.dcache.demand_miss_rate::total 0.037698 # miss rate for demand accesses
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-system.cpu1.dcache.overall_miss_rate::total 0.041997 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16883.295079 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16883.295079 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23244.765692 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 23244.765692 # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45191.877418 # average WriteLineReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27814.215406 # average StoreCondReq miss latency
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+system.cpu1.dcache.ReadReq_miss_rate::total 0.041548 # miss rate for ReadReq accesses
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+system.cpu1.dcache.WriteReq_miss_rate::total 0.033342 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763649 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763649 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.923520 # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total 0.923520 # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086981 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086981 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108553 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108553 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037686 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.037686 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041911 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.041911 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22487.926017 # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36344.643463 # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36344.643463 # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.816343 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.816343 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19511.338969 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19511.338969 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17407.385377 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17407.385377 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18905.380849 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 18905.380849 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16900.590550 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16900.590550 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1660,161 +1745,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 5640935 # number of writebacks
-system.cpu1.dcache.writebacks::total 5640935 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 429416 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 429416 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1043359 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 1043359 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42170 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42170 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 72 # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total 72 # number of StoreCondReq MSHR hits
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-system.cpu1.dcache.demand_mshr_hits::total 1472775 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1472775 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1472775 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3155827 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 3155827 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1480375 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 1480375 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 738082 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 738082 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 486914 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total 486914 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120140 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120140 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206366 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 206366 # number of StoreCondReq MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 5374284 # number of overall MSHR misses
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-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23242 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22236 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22236 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 45478 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 45478 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 47412877500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 47412877500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34746994000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 34746994000 # number of WriteReq MSHR miss cycles
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-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 19660408500 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 21514132500 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 21514132500 # number of WriteLineReq MSHR miss cycles
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1774236500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5529988500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6729000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6729000 # number of StoreCondFailReq MSHR miss cycles
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-system.cpu1.dcache.demand_mshr_miss_latency::total 82159871500 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.dcache.overall_mshr_miss_latency::total 101820280000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4292810500 # number of ReadReq MSHR uncacheable cycles
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-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4172773000 # number of WriteReq MSHR uncacheable cycles
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-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8465583500 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036575 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036575 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019539 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019539 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741090 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.741090 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.711473 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.711473 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058217 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058217 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100070 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100070 # mshr miss rate for StoreCondReq accesses
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-system.cpu1.dcache.demand_mshr_miss_rate::total 0.028610 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032962 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.032962 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.915284 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15023.915284 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23471.751414 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23471.751414 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 26637.160234 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 26637.160234 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44184.666081 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44184.666081 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14768.074746 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14768.074746 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26796.994175 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26796.994175 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 5011891 # number of writebacks
+system.cpu1.dcache.writebacks::total 5011891 # number of writebacks
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+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4914500 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.763222 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.763222 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.923389 # mshr miss rate for WriteLineReq accesses
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065139 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065139 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108506 # mshr miss rate for StoreCondReq accesses
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+system.cpu1.dcache.demand_mshr_miss_rate::total 0.028659 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032934 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.032934 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22503.329682 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24536.042946 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24536.042946 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35336.230388 # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35336.230388 # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14316.258975 # average LoadLockedReq mshr miss latency
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@@ -1823,498 +1908,494 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
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-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34082.743167 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34082.743167 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55618.562661 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55618.562661 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35508.934910 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43550.507380 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 49426.938192 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31302.166565 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37697.368599 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 73136.413477 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 46603.070327 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176697.508820 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176521.984144 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 180156.075733 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180156.075733 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178388.539514 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178295.209673 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.194834 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42980.473047 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50482.920781 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30794.884700 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30794.884700 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19197.135951 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19197.135951 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 897199.600000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 897199.600000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44069.998428 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44069.998428 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29828.373467 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31486.407700 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31486.407700 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45586.717224 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45586.717224 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32740.287687 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 135772.411988 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 135772.411988 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126743.790893 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126776.093159 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 30687781 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15695228 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2622 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 2305562 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2305078 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 484 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 905031 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 14265709 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 22236 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 22236 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 4974934 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 11314728 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 3212624 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 1143576 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 456570 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 371810 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 515155 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 96 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1270102 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1247161 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9254432 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5086529 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 540215 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 484636 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27762958 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18273152 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 349398 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1329953 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 47715461 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1184539712 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 703787179 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1323840 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5057400 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1894708131 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 7537959 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 23658040 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.112405 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.315929 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests 27757324 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14199775 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1809 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096264 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095922 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 342 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq 778911 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 12918528 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 7641 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 7641 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342023 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 10300458 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 2852323 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 992320 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 439929 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 359269 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 498097 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1135001 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1111432 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8450384 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4652967 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 462443 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp 408042 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25350826 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16287327 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370687 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1094902 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 43103742 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1081622336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 628052039 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1412064 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4140800 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1715227239 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 6782222 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 21311973 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.112849 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.316459 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 20999234 88.76% 88.76% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 2658322 11.24% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 484 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 18907277 88.72% 88.72% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 2404354 11.28% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 342 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 23658040 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 30538190977 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 21311973 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 27584218481 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 182787124 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 185839513 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 13885672200 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 12678955503 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 8385983653 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 7484332893 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 183975884 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 194250357 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 697921212 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 577391819 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40434 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40434 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136979 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136979 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47874 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 40390 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40390 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136973 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136973 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
@@ -2325,15 +2406,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122964 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122924 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231722 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231722 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354826 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47894 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 354726 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
@@ -2344,103 +2425,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
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+system.iocache.overall_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.l2c.tags.tagsinuse 63595.107970 # Cycle average of tags in use
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+system.l2c.tags.tagsinuse 63551.257518 # Cycle average of tags in use
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system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit.
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-system.l2c.tags.occ_blocks::cpu0.itb.walker 216.352807 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 5273.180907 # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10592.541457 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.822853 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 191.052659 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 3264.316466 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 6229.486316 # Average occupied blocks per requestor
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-system.l2c.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2651 # Occupied blocks per task id
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency
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system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency
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+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164187.760622 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109250.104434 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 137138.398922 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 90728 # Transaction distribution
-system.membus.trans_dist::ReadResp 1177835 # Transaction distribution
-system.membus.trans_dist::WriteReq 38212 # Transaction distribution
-system.membus.trans_dist::WriteResp 38212 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1451911 # Transaction distribution
-system.membus.trans_dist::CleanEvict 312799 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 438732 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 328709 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
-system.membus.trans_dist::ReadExReq 166722 # Transaction distribution
-system.membus.trans_dist::ReadExResp 150087 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1087107 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 695373 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122964 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 91289 # Transaction distribution
+system.membus.trans_dist::ReadResp 902614 # Transaction distribution
+system.membus.trans_dist::WriteReq 38789 # Transaction distribution
+system.membus.trans_dist::WriteResp 38789 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1182866 # Transaction distribution
+system.membus.trans_dist::CleanEvict 259673 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 445486 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 315870 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 22 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
+system.membus.trans_dist::ReadExReq 143483 # Transaction distribution
+system.membus.trans_dist::ReadExResp 126149 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 811325 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 668729 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122924 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24892 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5587054 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 5734962 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238554 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 238554 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5973516 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156002 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27208 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4633500 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4783684 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238198 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 238198 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5021882 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155939 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49784 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168012608 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 168219718 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276864 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7276864 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 175496582 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 622390 # Total snoops (count)
-system.membus.snoop_fanout::samples 4610336 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54416 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 131613504 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 131825183 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257920 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7257920 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 139083103 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 621301 # Total snoops (count)
+system.membus.snoop_fanout::samples 3957559 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 4610336 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3957559 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 4610336 # Request fanout histogram
-system.membus.reqLayer0.occupancy 110366494 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3957559 # Request fanout histogram
+system.membus.reqLayer0.occupancy 105148497 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 20951999 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 22946496 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 10147074149 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 8356686345 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 6858565377 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 5285705581 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 45617493 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 45456154 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
@@ -3217,53 +3291,53 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 13817515 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 7477037 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 2215935 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 187202 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 169247 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 17955 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 90730 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 5393978 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38212 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38212 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 4613586 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 3368394 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 769711 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 415575 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1185286 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 166 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 166 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 331620 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 331620 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 5310492 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 975909 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 868925 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10817825 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9492092 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 20309917 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 274107435 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 237950875 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 512058310 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 3424368 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 9784683 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.340448 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.477717 # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests 12610950 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 6824430 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 2134576 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 142334 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 128133 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 14201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 91291 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 4901304 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38789 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38789 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 3987141 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 3034318 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 743952 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 399827 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1143779 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 302895 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 302895 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 4817262 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 944420 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 837436 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10209362 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8295779 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 18505141 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250153960 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 205145975 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 455299935 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 3080857 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 8841930 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.362342 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.484007 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 6471464 66.14% 66.14% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 3295264 33.68% 99.82% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 17955 0.18% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 5652330 63.93% 63.93% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 3175399 35.91% 99.84% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 14201 0.16% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 9784683 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 10614903907 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 8841930 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 9598709952 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2624417 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2569910 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 5004390482 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4696248682 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4630478453 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4118726891 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
index 6b3e79c96..d628e39f4 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
@@ -1,139 +1,139 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 51.660643 # Number of seconds simulated
-sim_ticks 51660642512000 # Number of ticks simulated
-final_tick 51660642512000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.660653 # Number of seconds simulated
+sim_ticks 51660652947000 # Number of ticks simulated
+final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 304990 # Simulator instruction rate (inst/s)
-host_op_rate 358371 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16937149026 # Simulator tick rate (ticks/s)
-host_mem_usage 683404 # Number of bytes of host memory used
-host_seconds 3050.14 # Real time elapsed on the host
-sim_insts 930261902 # Number of instructions simulated
-sim_ops 1093080704 # Number of ops (including micro ops) simulated
+host_inst_rate 204210 # Simulator instruction rate (inst/s)
+host_op_rate 239956 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11350998190 # Simulator tick rate (ticks/s)
+host_mem_usage 682908 # Number of bytes of host memory used
+host_seconds 4551.20 # Real time elapsed on the host
+sim_insts 929398934 # Number of instructions simulated
+sim_ops 1092086880 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 377280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 320000 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 10274880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 61682056 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 384384 # Number of bytes read from this memory
-system.physmem.bytes_read::total 73038600 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 10274880 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 10274880 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 89590976 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 61721352 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 394752 # Number of bytes read from this memory
+system.physmem.bytes_read::total 73038088 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 10229888 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 10229888 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 89631104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 89611556 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 5895 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5000 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 160545 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 963795 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6006 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1141241 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1399859 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 89651684 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 5915 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 4899 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 159842 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 964409 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6168 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1141233 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1400486 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1402432 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 7303 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 6194 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 198892 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1193985 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 7441 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1413815 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 198892 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 198892 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1734221 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1403059 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 7328 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 6069 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 198021 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1194746 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 7641 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1413805 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 198021 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 198021 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1734998 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1734619 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1734221 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 7303 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 6194 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 198892 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1194384 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 7441 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3148435 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1141241 # Number of read requests accepted
-system.physmem.writeReqs 1402432 # Number of write requests accepted
-system.physmem.readBursts 1141241 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1402432 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 72981760 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 57664 # Total number of bytes read from write queue
-system.physmem.bytesWritten 89610624 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 73038600 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 89611556 # Total written bytes from the system interface side
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-system.physmem.wrPerTurnAround::28-31 326 0.42% 97.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 60 0.08% 97.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 114 0.15% 98.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 230 0.30% 98.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 35 0.05% 98.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 294 0.38% 98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 75 0.10% 98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 27 0.04% 98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 50 0.07% 99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 318 0.41% 99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 35 0.05% 99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 31 0.04% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 111 0.14% 99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 179 0.23% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 5 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 5 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 2 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 6 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 16 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 76825 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 76825 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 18.233622 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.685886 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 7.065993 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 64901 84.48% 84.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 9488 12.35% 96.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 481 0.63% 97.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 307 0.40% 97.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 57 0.07% 97.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 121 0.16% 98.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 251 0.33% 98.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 28 0.04% 98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 303 0.39% 98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 81 0.11% 98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 29 0.04% 98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 51 0.07% 99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 317 0.41% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 31 0.04% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 113 0.15% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 181 0.24% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 5 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 10 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 7 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 76765 # Writes before turning the bus around for reads
-system.physmem.totQLat 16541565713 # Total ticks spent queuing
-system.physmem.totMemAccLat 37922940713 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5701700000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 14505.82 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 76825 # Writes before turning the bus around for reads
+system.physmem.totQLat 16555348236 # Total ticks spent queuing
+system.physmem.totMemAccLat 37939329486 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 5702395000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 14516.14 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 33255.82 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 33266.14 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.73 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW 1.74 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.41 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.73 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.74 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing
-system.physmem.readRowHits 872320 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1020096 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.50 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 72.85 # Row buffer hit rate for writes
-system.physmem.avgGap 20309466.12 # Average gap between requests
-system.physmem.pageHitRate 74.49 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2456674920 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1340447625 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4274961600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 4509756000 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3374221858800 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1317434781870 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29840739448500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34544977929315 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.690476 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49641970693393 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1725062300000 # Time in different power states
+system.physmem.avgWrQLen 24.25 # Average write queue length when enqueuing
+system.physmem.readRowHits 872195 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1020290 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 76.48 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 72.84 # Row buffer hit rate for writes
+system.physmem.avgGap 20304529.14 # Average gap between requests
+system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 2468362680 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1346824875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 4283830200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 4532753520 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1318333461255 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29839955813250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34545143413140 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.693578 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49640663734133 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1725062560000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 293608746107 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 294925880867 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2442877920 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1332919500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4619643600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4563319680 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3374221858800 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1319027164650 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29839342629750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34545550413900 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.701557 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49639611346782 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1725062300000 # Time in different power states
+system.physmem_1.actEnergy 2436497280 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1329438000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 4611859200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 4544417520 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3374222367360 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1316960739945 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29841159946500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34545265265805 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.695937 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49642646529009 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1725062560000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 295966370718 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 292938700991 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
@@ -340,15 +342,19 @@ system.cf0.dma_read_txs 122 # Nu
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 254908438 # Number of BP lookups
-system.cpu.branchPred.condPredicted 178242351 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 12005241 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 187385958 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 132827814 # Number of BTB hits
+system.cpu.branchPred.lookups 256209592 # Number of BP lookups
+system.cpu.branchPred.condPredicted 178352168 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 12215343 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 188533609 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 127068742 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 70.884615 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 31213174 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2144347 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 67.398456 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 31319231 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 2132154 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 7072039 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 5016643 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 2055396 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 841768 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -379,64 +385,63 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 567320 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 567320 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20723 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 182198 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples 567320 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 567320 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 567320 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 202921 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 27429.733739 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 23186.871186 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 21494.309968 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535 200464 98.79% 98.79% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071 14 0.01% 98.80% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607 2073 1.02% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143 61 0.03% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679 133 0.07% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215 52 0.03% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751 92 0.05% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287 15 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks 561578 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 561578 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20867 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181761 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples 561578 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 561578 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 561578 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 202628 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 27245.592909 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 23033.802603 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 21444.921579 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535 200160 98.78% 98.78% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.78% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607 2084 1.03% 99.81% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143 75 0.04% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679 137 0.07% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215 55 0.03% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751 85 0.04% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359 10 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 202921 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 202628 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 182199 89.79% 89.79% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 20723 10.21% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 202922 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 567320 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K 181762 89.70% 89.70% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 20867 10.30% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 202629 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 561578 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 567320 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202922 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 561578 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 202629 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202922 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 770242 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 202629 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 764207 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 179769202 # DTB read hits
-system.cpu.dtb.read_misses 468572 # DTB read misses
-system.cpu.dtb.write_hits 159383411 # DTB write hits
-system.cpu.dtb.write_misses 98748 # DTB write misses
+system.cpu.dtb.read_hits 179568747 # DTB read hits
+system.cpu.dtb.read_misses 462708 # DTB read misses
+system.cpu.dtb.write_hits 159223685 # DTB write hits
+system.cpu.dtb.write_misses 98870 # DTB write misses
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 45817 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 78846 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 1354 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 15815 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 78994 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 14910 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 23199 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 180237774 # DTB read accesses
-system.cpu.dtb.write_accesses 159482159 # DTB write accesses
+system.cpu.dtb.perms_faults 23300 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 180031455 # DTB read accesses
+system.cpu.dtb.write_accesses 159322555 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 339152613 # DTB hits
-system.cpu.dtb.misses 567320 # DTB misses
-system.cpu.dtb.accesses 339719933 # DTB accesses
+system.cpu.dtb.hits 338792432 # DTB hits
+system.cpu.dtb.misses 561578 # DTB misses
+system.cpu.dtb.accesses 339354010 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -466,184 +471,219 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 135719 # Table walker walks requested
-system.cpu.itb.walker.walksLong 135719 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1067 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 118398 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 135719 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 135719 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 135719 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 119465 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 30823.412715 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 26220.565528 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 24055.511247 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 116639 97.63% 97.63% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 7 0.01% 97.64% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607 2565 2.15% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143 80 0.07% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679 132 0.11% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215 26 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751 13 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks 133823 # Table walker walks requested
+system.cpu.itb.walker.walksLong 133823 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2 1057 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3 116932 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples 133823 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 133823 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 133823 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 117989 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 30581.308427 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 25983.502451 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 24251.357512 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535 115208 97.64% 97.64% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 97.65% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607 2538 2.15% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143 65 0.06% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679 122 0.10% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751 18 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 119465 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 117989 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 118398 99.11% 99.11% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1067 0.89% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 119465 # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K 116932 99.10% 99.10% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1057 0.90% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 117989 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135719 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 135719 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 133823 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 133823 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119465 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 119465 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 255184 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 443155891 # ITB inst hits
-system.cpu.itb.inst_misses 135719 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 117989 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 117989 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 251812 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 442793055 # ITB inst hits
+system.cpu.itb.inst_misses 133823 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 45817 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_mva_asid 45818 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1095 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 56716 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 56590 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 363456 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 313131 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 443291610 # ITB inst accesses
-system.cpu.itb.hits 443155891 # DTB hits
-system.cpu.itb.misses 135719 # DTB misses
-system.cpu.itb.accesses 443291610 # DTB accesses
-system.cpu.numCycles 2560430377 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 442926878 # ITB inst accesses
+system.cpu.itb.hits 442793055 # DTB hits
+system.cpu.itb.misses 133823 # DTB misses
+system.cpu.itb.accesses 442926878 # DTB accesses
+system.cpu.numCycles 2561963341 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 930261902 # Number of instructions committed
-system.cpu.committedOps 1093080704 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 94082781 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 7654 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 100762000477 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 2.752376 # CPI: cycles per instruction
-system.cpu.ipc 0.363322 # IPC: instructions per cycle
+system.cpu.committedInsts 929398934 # Number of instructions committed
+system.cpu.committedOps 1092086880 # Number of ops (including micro ops) committed
+system.cpu.discardedOps 94664249 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends 7656 # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles 100760459460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi 2.756581 # CPI: cycles per instruction
+system.cpu.ipc 0.362768 # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu 756821893 69.30% 69.30% # Class of committed instruction
+system.cpu.op_class_0::IntMult 2277263 0.21% 69.51% # Class of committed instruction
+system.cpu.op_class_0::IntDiv 98455 0.01% 69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc 109444 0.01% 69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction
+system.cpu.op_class_0::MemRead 174118935 15.94% 85.47% # Class of committed instruction
+system.cpu.op_class_0::MemWrite 158660847 14.53% 100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu.op_class_0::total 1092086880 # Class of committed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 16514 # number of quiesce instructions executed
-system.cpu.tickCycles 1756892100 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 803538277 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 10835760 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.930073 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 323161698 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 10836272 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 29.822221 # Average number of references to valid blocks.
+system.cpu.kern.inst.quiesce 16516 # number of quiesce instructions executed
+system.cpu.tickCycles 1757425284 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 804538057 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 10826762 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.930071 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 322795140 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 10827274 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 29.813150 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.930073 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.930071 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1357625936 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1357625936 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 165326360 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 165326360 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148822242 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148822242 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 515783 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 515783 # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data 336254 # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total 336254 # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3901835 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3901835 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 4210707 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 4210707 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 314148602 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 314148602 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 314664385 # number of overall hits
-system.cpu.dcache.overall_hits::total 314664385 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 6435963 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 6435963 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 4178110 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 4178110 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 1419320 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 1419320 # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data 1240241 # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total 1240241 # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 310588 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 310588 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 10614073 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 10614073 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 12033393 # number of overall misses
-system.cpu.dcache.overall_misses::total 12033393 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 119289543000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 119289543000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 206542043000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 206542043000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53400604000 # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total 53400604000 # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5170357500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 5170357500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245500 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 245500 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 325831586000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 325831586000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 325831586000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 325831586000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 171762323 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 171762323 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.WriteReq_accesses::total 153000352 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 1935103 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 1935103 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data 1576495 # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total 1576495 # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4212423 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 4212423 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 4210710 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 4210710 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 324762675 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 324762675 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 326697778 # number of overall (read+write) accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 18534.839775 # average ReadReq miss latency
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-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43056.634960 # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43056.634960 # average WriteLineReq miss latency
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-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 81833.333333 # average StoreCondReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::total 27077.282858 # average overall miss latency
+system.cpu.dcache.tags.tag_accesses 1356106386 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1356106386 # Number of data accesses
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+system.cpu.dcache.ReadReq_hits::total 165131668 # number of ReadReq hits
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 49391.098209 # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 43118.922264 # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 43118.922264 # average WriteLineReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency::total 27077.325157 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -652,155 +692,155 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.writebacks::total 8326510 # number of writebacks
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-system.cpu.dcache.ReadReq_mshr_hits::total 781266 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses
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@@ -809,230 +849,231 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2582673500 # number of UpgradeReq MSHR miss cycles
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+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 37418286000 # number of InvalidateReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936074000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5776092000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11712166000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5819357000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5819357000 # number of WriteReq MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936074000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11595449000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17531523000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006266 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017228 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008851 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11579839500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17515913500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008952 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.781855 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781855 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782932 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782932 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.281746 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.281746 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004458 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043831 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043831 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.432301 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.432301 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006266 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017228 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.100566 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.030880 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006266 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017228 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004458 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.100566 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.030880 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127133.868747 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68015.362686 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68015.362686 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69333.333333 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69333.333333 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122751.847678 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122751.847678 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122519.268728 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122519.268728 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125017.660953 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125017.660953 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.957429 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.957429 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127309.414758 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122519.268728 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123503.885757 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123442.045334 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126926.900000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122519.268728 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123503.885757 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123442.045334 # average overall mshr miss latency
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+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.433198 # mshr miss rate for InvalidateReq accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for demand accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::total 0.030853 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006391 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017341 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004419 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.100722 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.030853 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127272.008692 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68013.417428 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68013.417428 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122748.217880 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122748.217880 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122464.475999 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122464.475999 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125035.706823 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125035.706823 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69662.462277 # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69662.462277 # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127245.224345 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127304.347826 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122464.475999 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123510.470995 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171412.648010 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136178.475920 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.477660 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.477660 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171419.592249 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136181.196661 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172180.427817 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172180.427817 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172031.645476 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146447.498998 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 171800.060828 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146317.106890 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 70987580 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 35868028 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4400 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 2259 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2259 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 71082854 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 35915919 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 1747427 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 33339280 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 1731601 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 33371848 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 9726418 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 24282731 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 2753122 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 48457 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 48460 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2288395 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2288395 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 24283253 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 7316706 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 1346757 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 1240093 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72953851 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32740884 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 695726 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2196697 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 108587158 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3111570496 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1147294802 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2321736 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7526280 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 4268713314 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 2190531 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 38708484 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.018284 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.133976 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty 9712830 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 24339101 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 2759131 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 48504 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 48506 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2287534 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2287534 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 24339623 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 7308730 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq 1346598 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp 1239934 # Transaction distribution
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+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 682590 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2171018 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 108690560 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3118785792 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1145820498 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2260056 # Cumulative packet size per connected master and slave (bytes)
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+system.cpu.toL2Bus.pkt_size::total 4274270394 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 2199102 # Total snoops (count)
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+system.cpu.toL2Bus.snoop_fanout::mean 0.018274 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.133941 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 38000745 98.17% 98.17% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 707739 1.83% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 38033532 98.17% 98.17% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 707965 1.83% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 38708484 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 68659919994 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 38741497 # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1469394 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 1462889 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 36510728693 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 36594790182 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 15090009225 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 15076717704 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 405546924 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 400149367 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 1255965393 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 1245546930 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40330 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40330 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40324 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40324 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
@@ -1256,11 +1297,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231018 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231018 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353802 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
@@ -1275,100 +1316,100 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334504 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334504 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492424 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 42214500 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 333500 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
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+system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
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+system.iobus.reqLayer23.occupancy 25573000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 34147500 # Layer occupancy (ticks)
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system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 566993946 # Layer occupancy (ticks)
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system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115490 # number of replacements
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system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115506 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13153331095000 # Cycle when the warmup percentage was hit.
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-system.iocache.tags.occ_blocks::realview.ide 6.919950 # Average occupied blocks per requestor
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system.iocache.tags.occ_percent::realview.ide 0.432497 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.652578 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039938 # Number of tag accesses
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system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
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system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
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system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
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-system.iocache.WriteLineReq_miss_latency::total 13412464756 # number of WriteLineReq miss cycles
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-system.iocache.overall_miss_latency::total 1630233190 # number of overall miss cycles
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system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
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system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8845 # number of demand (read+write) accesses
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+system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8845 # number of overall (read+write) accesses
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system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
@@ -1382,55 +1423,55 @@ system.iocache.demand_miss_rate::total 1 # mi
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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-system.iocache.ReadReq_avg_miss_latency::realview.ide 183696.573205 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 183503.961946 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 186008.157144 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 185803.977129 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125745.000713 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125745.000713 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 183696.573205 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183481.507034 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 183696.573205 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183481.507034 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 31904 # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.640422 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125739.640422 # average WriteLineReq miss latency
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+system.iocache.overall_avg_miss_latency::realview.ide 186008.157144 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 185780.729925 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 32855 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3290 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 9.697264 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 9.711794 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8845 # number of ReadReq MSHR misses
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system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
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system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 8845 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 8885 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1182546190 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1185782190 # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 1202176101 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 1205396101 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8074127324 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 8074127324 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 1182546190 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 1185983190 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 1182546190 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 1185983190 # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073547861 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 8073547861 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 1202176101 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 1205597101 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 1202176101 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1205597101 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
@@ -1444,72 +1485,72 @@ system.iocache.demand_mshr_miss_rate::total 1 #
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133696.573205 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 133503.961946 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136008.157144 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 135803.977129 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75696.836083 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75696.836083 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 133696.573205 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 133481.507034 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 133696.573205 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 133481.507034 # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.403482 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.403482 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 136008.157144 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 135780.729925 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 86006 # Transaction distribution
-system.membus.trans_dist::ReadResp 534352 # Transaction distribution
+system.membus.trans_dist::ReadResp 535040 # Transaction distribution
system.membus.trans_dist::WriteReq 33706 # Transaction distribution
system.membus.trans_dist::WriteResp 33706 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1399859 # Transaction distribution
-system.membus.trans_dist::CleanEvict 242769 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 38707 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1400486 # Transaction distribution
+system.membus.trans_dist::CleanEvict 243574 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 38729 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
-system.membus.trans_dist::ReadExReq 644117 # Transaction distribution
-system.membus.trans_dist::ReadExResp 644117 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 448346 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 642566 # Transaction distribution
+system.membus.trans_dist::ReadExReq 643252 # Transaction distribution
+system.membus.trans_dist::ReadExResp 643252 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 449034 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 643674 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4378022 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4507674 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237045 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 237045 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4744719 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4380248 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4509900 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237195 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 237195 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4747095 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155441452 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 155611858 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7208704 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7208704 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 162820562 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 3543 # Total snoops (count)
-system.membus.snoop_fanout::samples 3536130 # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155470700 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 155641106 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7219072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7219072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 162860178 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 3374 # Total snoops (count)
+system.membus.snoop_fanout::samples 3538498 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3536130 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3538498 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3536130 # Request fanout histogram
-system.membus.reqLayer0.occupancy 102490000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3538498 # Request fanout histogram
+system.membus.reqLayer0.occupancy 97241000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5501500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 5639000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 9311720798 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 9317752261 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 6129482304 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 6128850630 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 44955070 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 44857615 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
index 4faaeac69..43d314d14 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
@@ -1,139 +1,139 @@
---------- Begin Simulation Statistics ----------
sim_seconds 51.327140 # Number of seconds simulated
-sim_ticks 51327140089000 # Number of ticks simulated
-final_tick 51327140089000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 51327139864000 # Number of ticks simulated
+final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 155840 # Simulator instruction rate (inst/s)
-host_op_rate 183117 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9430836418 # Simulator tick rate (ticks/s)
-host_mem_usage 687516 # Number of bytes of host memory used
-host_seconds 5442.48 # Real time elapsed on the host
-sim_insts 848158120 # Number of instructions simulated
-sim_ops 996609834 # Number of ops (including micro ops) simulated
+host_inst_rate 122613 # Simulator instruction rate (inst/s)
+host_op_rate 144072 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7419967145 # Simulator tick rate (ticks/s)
+host_mem_usage 687012 # Number of bytes of host memory used
+host_seconds 6917.44 # Real time elapsed on the host
+sim_insts 848164321 # Number of instructions simulated
+sim_ops 996610207 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 211968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 207872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5637664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 41611720 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 447104 # Number of bytes read from this memory
-system.physmem.bytes_read::total 48116328 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 5637664 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5637664 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 68318336 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 41583048 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 443008 # Number of bytes read from this memory
+system.physmem.bytes_read::total 48132008 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5661728 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5661728 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 68386496 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 68338916 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 3312 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3248 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 104041 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 650196 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6986 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 767783 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1067474 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 68407076 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 3558 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 3383 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 104417 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 649748 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6922 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 768028 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1068539 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1070047 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 4130 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 4050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 109838 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 810716 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8711 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 937444 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 109838 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 109838 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1331037 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1071112 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 4436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 4218 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 110307 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 810157 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8631 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 937750 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 110307 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 110307 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1332365 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1331438 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1331037 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 4130 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 4050 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 109838 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 811117 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8711 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2268882 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 767783 # Number of read requests accepted
-system.physmem.writeReqs 1070047 # Number of write requests accepted
-system.physmem.readBursts 767783 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1070047 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 49097152 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 40960 # Total number of bytes read from write queue
-system.physmem.bytesWritten 68336896 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 48116328 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 68338916 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 640 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_write::total 1332766 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1332365 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 4436 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 4218 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 110307 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 810558 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8631 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2270516 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 768028 # Number of read requests accepted
+system.physmem.writeReqs 1071112 # Number of write requests accepted
+system.physmem.readBursts 768028 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1071112 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 49106944 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 46848 # Total number of bytes read from write queue
+system.physmem.bytesWritten 68406272 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 48132008 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 68407076 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 732 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 44980 # Per bank write bursts
-system.physmem.perBankRdBursts::1 51602 # Per bank write bursts
-system.physmem.perBankRdBursts::2 47368 # Per bank write bursts
-system.physmem.perBankRdBursts::3 43602 # Per bank write bursts
-system.physmem.perBankRdBursts::4 45132 # Per bank write bursts
-system.physmem.perBankRdBursts::5 50541 # Per bank write bursts
-system.physmem.perBankRdBursts::6 45264 # Per bank write bursts
-system.physmem.perBankRdBursts::7 48215 # Per bank write bursts
-system.physmem.perBankRdBursts::8 45181 # Per bank write bursts
-system.physmem.perBankRdBursts::9 71916 # Per bank write bursts
-system.physmem.perBankRdBursts::10 43746 # Per bank write bursts
-system.physmem.perBankRdBursts::11 51986 # Per bank write bursts
-system.physmem.perBankRdBursts::12 43936 # Per bank write bursts
-system.physmem.perBankRdBursts::13 46943 # Per bank write bursts
-system.physmem.perBankRdBursts::14 42923 # Per bank write bursts
-system.physmem.perBankRdBursts::15 43808 # Per bank write bursts
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@@ -159,125 +159,126 @@ system.physmem.wrQLenPdf::11 1 # Wh
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+system.physmem.wrPerTurnAround::36-39 248 0.46% 96.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 301 0.56% 97.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 130 0.24% 97.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 393 0.73% 98.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 142 0.26% 98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 38 0.07% 98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 61 0.11% 98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 323 0.60% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 40 0.07% 99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 24 0.04% 99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 111 0.20% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 181 0.33% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 3 0.01% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 3 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 2 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 11 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 5 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 17 0.03% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 54136 # Writes before turning the bus around for reads
-system.physmem.totQLat 15242803686 # Total ticks spent queuing
-system.physmem.totMemAccLat 29626734936 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 3835715000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 19869.57 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 14 0.03% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 3 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 9 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 6 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 54191 # Writes before turning the bus around for reads
+system.physmem.totQLat 15195806089 # Total ticks spent queuing
+system.physmem.totMemAccLat 29582606089 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 3836480000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 19804.36 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 38619.57 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 38554.36 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s
@@ -286,41 +287,41 @@ system.physmem.peakBW 12800.00 # Th
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing
-system.physmem.readRowHits 579803 # Number of row buffer hits during reads
-system.physmem.writeRowHits 783916 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.42 # Row buffer hit rate for writes
-system.physmem.avgGap 27928121.03 # Average gap between requests
+system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing
+system.physmem.readRowHits 579763 # Number of row buffer hits during reads
+system.physmem.writeRowHits 784939 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.44 # Row buffer hit rate for writes
+system.physmem.avgGap 27908228.00 # Average gap between requests
system.physmem.pageHitRate 74.32 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1791077400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 977274375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2938244400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3468841200 # Energy for write commands per rank (pJ)
+system.physmem_0.actEnergy 1800088920 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 982191375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2947417200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3479286960 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1235175473835 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29712796340250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34309586468340 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.449224 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49429866192554 # Time in different power states
+system.physmem_0.actBackEnergy 1235810088180 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29712239669250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34309697958765 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.451396 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49428932348966 # Time in different power states
system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 183347171196 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 184281028534 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 1771020720 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 966330750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3045424200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3450165840 # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy 1763997480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 962498625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3037452600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3446848080 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1235608843410 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29712416191500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34309697193300 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.451381 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49429214230967 # Time in different power states
+system.physmem_1.actBackEnergy 1235330422065 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29712660420750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34309640856480 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.450284 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49429628001327 # Time in different power states
system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 183999255033 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
@@ -344,15 +345,19 @@ system.cf0.dma_read_txs 122 # Nu
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 224297572 # Number of BP lookups
-system.cpu.branchPred.condPredicted 149902957 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 12193787 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 158452721 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 103491021 # Number of BTB hits
+system.cpu.branchPred.lookups 225024609 # Number of BP lookups
+system.cpu.branchPred.condPredicted 149819801 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 12305268 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 158924221 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 98148969 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 65.313502 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 30817326 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 343319 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 61.758345 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 30872234 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 343569 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 6729545 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 4744517 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -383,45 +388,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.checker.dtb.walker.walks 197812 # Table walker walks requested
-system.cpu.checker.dtb.walker.walksLong 197812 # Table walker walks initiated with long descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples 197812 # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0 197812 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total 197812 # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walks 197728 # Table walker walks requested
+system.cpu.checker.dtb.walker.walksLong 197728 # Table walker walks initiated with long descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples 197728 # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0 197728 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total 197728 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walksPending::samples -1584953796 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 -1584953796 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total -1584953796 # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K 154082 91.53% 91.53% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::2M 14256 8.47% 100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total 168338 # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 197812 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkPageSizes::4K 154026 91.54% 91.54% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::2M 14228 8.46% 100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total 168254 # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 197728 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 197812 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 168338 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 197728 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 168254 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 168338 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total 366150 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 168254 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total 365982 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 159555068 # DTB read hits
-system.cpu.checker.dtb.read_misses 147115 # DTB read misses
-system.cpu.checker.dtb.write_hits 144752666 # DTB write hits
-system.cpu.checker.dtb.write_misses 50697 # DTB write misses
+system.cpu.checker.dtb.read_hits 159555012 # DTB read hits
+system.cpu.checker.dtb.read_misses 147105 # DTB read misses
+system.cpu.checker.dtb.write_hits 144753445 # DTB write hits
+system.cpu.checker.dtb.write_misses 50623 # DTB write misses
system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 71773 # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries 71788 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults 6971 # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults 6683 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 19053 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 159702183 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 144803363 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 159702117 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 144804068 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 304307734 # DTB hits
-system.cpu.checker.dtb.misses 197812 # DTB misses
-system.cpu.checker.dtb.accesses 304505546 # DTB accesses
+system.cpu.checker.dtb.hits 304308457 # DTB hits
+system.cpu.checker.dtb.misses 197728 # DTB misses
+system.cpu.checker.dtb.accesses 304506185 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -451,26 +456,26 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.checker.itb.walker.walks 119797 # Table walker walks requested
-system.cpu.checker.itb.walker.walksLong 119797 # Table walker walks initiated with long descriptors
-system.cpu.checker.itb.walker.walkWaitTime::samples 119797 # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::0 119797 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::total 119797 # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walks 119805 # Table walker walks requested
+system.cpu.checker.itb.walker.walksLong 119805 # Table walker walks initiated with long descriptors
+system.cpu.checker.itb.walker.walkWaitTime::samples 119805 # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::0 119805 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::total 119805 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walksPending::samples -1586149296 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 -1586149296 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total -1586149296 # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walkPageSizes::4K 107938 98.83% 98.83% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::4K 107946 98.83% 98.83% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::2M 1280 1.17% 100.00% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::total 109218 # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::total 109226 # Table walker page sizes translated
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119797 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119797 # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119805 # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119805 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109218 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109218 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin::total 229015 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits 848564500 # ITB inst hits
-system.cpu.checker.itb.inst_misses 119797 # ITB inst misses
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109226 # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109226 # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total 229031 # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.inst_hits 848570685 # ITB inst hits
+system.cpu.checker.itb.inst_misses 119805 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
@@ -479,18 +484,18 @@ system.cpu.checker.itb.flush_tlb 20 # Nu
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries 51743 # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries 51713 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 848684297 # ITB inst accesses
-system.cpu.checker.itb.hits 848564500 # DTB hits
-system.cpu.checker.itb.misses 119797 # DTB misses
-system.cpu.checker.itb.accesses 848684297 # DTB accesses
-system.cpu.checker.numCycles 997179136 # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses 848690490 # ITB inst accesses
+system.cpu.checker.itb.hits 848570685 # DTB hits
+system.cpu.checker.itb.misses 119805 # DTB misses
+system.cpu.checker.itb.accesses 848690490 # DTB accesses
+system.cpu.checker.numCycles 997179501 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@@ -522,85 +527,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 949838 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 949838 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15818 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155419 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 436827 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 513011 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 2225.817770 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 14567.134273 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535 509618 99.34% 99.34% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071 1930 0.38% 99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607 987 0.19% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143 197 0.04% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679 149 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751 53 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks 947007 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155482 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore 435407 # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples 511600 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 2285.571736 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 14838.819778 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535 508020 99.30% 99.30% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071 2030 0.40% 99.70% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607 1046 0.20% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143 222 0.04% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679 147 0.03% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751 54 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::458752-524287 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 513011 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 485512 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23036.801356 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 18084.539614 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20755.830536 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535 474265 97.68% 97.68% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071 7843 1.62% 99.30% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607 2427 0.50% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143 166 0.03% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679 551 0.11% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215 105 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751 109 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 485512 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 779669132376 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.722626 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.523315 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1 777439658376 99.71% 99.71% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3 1176099000 0.15% 99.86% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5 488850000 0.06% 99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7 205535000 0.03% 99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9 152105500 0.02% 99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11 121751500 0.02% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13 29187500 0.00% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15 53249500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17 2696000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 779669132376 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 155420 90.76% 90.76% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 15818 9.24% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 171238 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 949838 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 511600 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 486864 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 22927.774491 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 17879.583197 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20925.745088 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535 475438 97.65% 97.65% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071 7837 1.61% 99.26% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607 2530 0.52% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143 265 0.05% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679 545 0.11% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215 113 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751 104 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287 16 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 486864 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 779668807876 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean 0.725507 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev 0.522451 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1 777433889876 99.71% 99.71% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3 1160253500 0.15% 99.86% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5 513477500 0.07% 99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7 201866500 0.03% 99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9 152233500 0.02% 99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11 119773500 0.02% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13 32296000 0.00% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15 52448000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17 2569500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 779668807876 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 155483 90.77% 90.77% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 15816 9.23% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 171299 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 947007 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 949838 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171238 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 947007 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171299 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171238 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 1121076 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171299 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 1118306 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 169331819 # DTB read hits
-system.cpu.dtb.read_misses 674131 # DTB read misses
-system.cpu.dtb.write_hits 147501461 # DTB write hits
-system.cpu.dtb.write_misses 275707 # DTB write misses
+system.cpu.dtb.read_hits 169398877 # DTB read hits
+system.cpu.dtb.read_misses 674798 # DTB read misses
+system.cpu.dtb.write_hits 147332912 # DTB write hits
+system.cpu.dtb.write_misses 272209 # DTB write misses
system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 72020 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 10130 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 72102 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 69829 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 170005950 # DTB read accesses
-system.cpu.dtb.write_accesses 147777168 # DTB write accesses
+system.cpu.dtb.perms_faults 69070 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 170073675 # DTB read accesses
+system.cpu.dtb.write_accesses 147605121 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 316833280 # DTB hits
-system.cpu.dtb.misses 949838 # DTB misses
-system.cpu.dtb.accesses 317783118 # DTB accesses
+system.cpu.dtb.hits 316731789 # DTB hits
+system.cpu.dtb.misses 947007 # DTB misses
+system.cpu.dtb.accesses 317678796 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -630,62 +637,65 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 161333 # Table walker walks requested
-system.cpu.itb.walker.walksLong 161333 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 121604 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore 17607 # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples 143726 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean 1329.870726 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev 9693.373994 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767 142645 99.25% 99.25% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535 592 0.41% 99.66% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303 67 0.05% 99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071 93 0.06% 99.77% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607 24 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks 162102 # Table walker walks requested
+system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3 120022 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore 17916 # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples 144186 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean 1142.128917 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 9607.655205 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767 143046 99.21% 99.21% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535 588 0.41% 99.62% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303 94 0.07% 99.68% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071 159 0.11% 99.79% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839 224 0.16% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607 44 0.03% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 143726 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 140644 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 29101.756918 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24236.740283 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 22905.442201 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 137486 97.75% 97.75% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 886 0.63% 98.38% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607 1961 1.39% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143 124 0.09% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679 124 0.09% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215 33 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 140644 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 672291747976 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean 0.944017 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev 0.230261 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 37693655356 5.61% 5.61% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1 634541752620 94.38% 99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2 55651000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3 688000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 672291747976 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 121604 98.84% 98.84% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 123037 # Table walker page sizes translated
+system.cpu.itb.walker.walkWaitTime::229376-262143 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 144186 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 139421 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28788.855337 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23782.658152 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 24182.866310 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535 136254 97.73% 97.73% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071 690 0.49% 98.22% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607 2101 1.51% 99.73% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143 136 0.10% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679 151 0.11% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215 47 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751 30 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 139421 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 680881393568 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean 0.947864 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev 0.222600 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 35543211356 5.22% 5.22% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1 645294358712 94.77% 99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2 43207500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3 580000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4 36000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 680881393568 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 120022 98.78% 98.78% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1483 1.22% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 121505 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161333 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 161333 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162102 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 162102 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123037 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 123037 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 284370 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 356599136 # ITB inst hits
-system.cpu.itb.inst_misses 161333 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121505 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 121505 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 283607 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 357007788 # ITB inst hits
+system.cpu.itb.inst_misses 162102 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
@@ -694,261 +704,261 @@ system.cpu.itb.flush_tlb 20 # Nu
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 53042 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 52913 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 369633 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 357575 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 356760469 # ITB inst accesses
-system.cpu.itb.hits 356599136 # DTB hits
-system.cpu.itb.misses 161333 # DTB misses
-system.cpu.itb.accesses 356760469 # DTB accesses
-system.cpu.numCycles 1628081885 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 357169890 # ITB inst accesses
+system.cpu.itb.hits 357007788 # DTB hits
+system.cpu.itb.misses 162102 # DTB misses
+system.cpu.itb.accesses 357169890 # DTB accesses
+system.cpu.numCycles 1631144067 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 644023121 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1000825975 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 224297572 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 134308347 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 897356081 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 26042356 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 3815311 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 27434 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 9297529 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1037208 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 977 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 356212596 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 6096332 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 48851 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 1568578839 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.747604 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.149571 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 646909214 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 898024303 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 26265536 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 3811072 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 29306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 8704800 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1028212 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 873 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 356634442 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 6247312 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 47880 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 1571640548 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.747058 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.149321 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 1011708684 64.50% 64.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 213717515 13.62% 78.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 70499052 4.49% 82.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 272653588 17.38% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 1013991405 64.52% 64.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 214266060 13.63% 78.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 70309362 4.47% 82.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 273073721 17.38% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1568578839 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.137768 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.614727 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 523834599 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 552751170 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 433009950 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 49764409 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 9218711 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 33629126 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 3862659 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 1084582874 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 28977480 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 9218711 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 568372766 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 66217937 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 371830406 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 438295981 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 114643038 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1064838864 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 6775021 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 5115924 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 336846 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 638712 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 63601510 # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents 20546 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1012729668 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1640391275 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1259385666 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1476745 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 947192806 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 65536859 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 26910765 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 23247835 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 101832167 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 173436334 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 151069277 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 9864131 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8951241 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1029826470 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 27204925 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1045231227 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3279121 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 60421557 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33664917 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 313528 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1568578839 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.666356 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.920348 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 1571640548 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.137955 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.614702 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 526349627 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 552086440 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 434104674 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 49724049 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 9375758 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 33560071 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 3814526 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 1085977369 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 29430616 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 9375758 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 571292055 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 65924513 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 371563835 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 438965882 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 114518505 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1065686030 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 6908876 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 5086020 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 334343 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 634469 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 63514971 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 20439 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1013378726 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1640198292 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1259502846 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1473679 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 947186300 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 66192423 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 26900223 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 23242764 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 101754926 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 173828486 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 150818351 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 9879664 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 8976205 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1030662331 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 27200654 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1045735608 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3378731 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 61252774 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 34075299 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 309098 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1571640548 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.665378 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.919633 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 921654762 58.76% 58.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 333747896 21.28% 80.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 234544221 14.95% 94.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 72152324 4.60% 99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 6460263 0.41% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 19373 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 924076981 58.80% 58.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 334351644 21.27% 80.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 234725096 14.94% 95.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 72033056 4.58% 99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 6434251 0.41% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 19520 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1568578839 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1571640548 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 57742950 35.03% 35.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 99825 0.06% 35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 625 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 44231739 26.83% 61.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 62727458 38.06% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 57663018 35.01% 35.01% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available
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+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available
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+system.cpu.iq.fu_full::MemRead 44277065 26.88% 61.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 62625013 38.03% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
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-system.cpu.iq.FU_type_0::FloatAdd 380 0.00% 69.12% # Type of FU issued
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-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued
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+system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 173211987 16.57% 85.71% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1045231227 # Type of FU issued
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-system.cpu.iq.fu_busy_rate 0.157697 # FU busy rate (busy events/executed inst)
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-system.cpu.iq.int_inst_queue_writes 1116644145 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1027372601 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 2483800 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 950168 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 912054 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1208499896 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1560667 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 4304106 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1045735608 # Type of FU issued
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+system.cpu.iq.fu_busy_rate 0.157490 # FU busy rate (busy events/executed inst)
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+system.cpu.iq.int_inst_queue_writes 1118319185 # Number of integer instruction queue writes
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+system.cpu.iq.fp_inst_queue_reads 2472282 # Number of floating instruction queue reads
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+system.cpu.iq.fp_alu_accesses 1555013 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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-system.cpu.iew.lsq.thread0.ignoredResponses 14456 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 142604 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 6312817 # Number of stores squashed
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+system.cpu.iew.lsq.thread0.squashedStores 6061186 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2532139 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1442341 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2527357 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1438792 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 9218711 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 7060342 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 6923682 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1057253447 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 9375758 # Number of cycles IEW is squashing
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+system.cpu.iew.iewUnblockCycles 6913711 # Number of cycles IEW is unblocking
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system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
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-system.cpu.iew.iewLSQFullEvents 6792645 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 142604 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3655399 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 5100784 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 222052 # number of nop insts executed
-system.cpu.iew.exec_refs 316816486 # number of memory reference insts executed
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-system.cpu.iew.exec_rate 0.635143 # Inst execution rate
-system.cpu.iew.wb_sent 1029092840 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1028284655 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 437786008 # num instructions producing a value
-system.cpu.iew.wb_consumers 708231099 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.631593 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.618140 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 51332329 # The number of squashed insts skipped by commit
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-system.cpu.commit.branchMispredicts 8391320 # The number of times a branch was mispredicted
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-system.cpu.commit.committed_per_cycle::mean 0.640242 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.274821 # Number of insts commited each cycle
+system.cpu.iew.exec_nop 235018 # number of nop insts executed
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+system.cpu.iew.exec_rate 0.634049 # Inst execution rate
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+system.cpu.iew.wb_count 1028301148 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 437817967 # num instructions producing a value
+system.cpu.iew.wb_consumers 708345311 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.630417 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.618086 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 51892888 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 26891556 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 1044975044 67.13% 67.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 287768132 18.49% 85.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 120346121 7.73% 93.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 36551788 2.35% 95.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 28453995 1.83% 97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 14010396 0.90% 98.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 8635881 0.55% 98.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 4170150 0.27% 99.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 11702475 0.75% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 1047836838 67.19% 67.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 288037345 18.47% 85.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 120098323 7.70% 93.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 36644408 2.35% 95.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 28496008 1.83% 97.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 13936779 0.89% 98.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 8648827 0.55% 98.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 4175441 0.27% 99.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 11706752 0.75% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1556613982 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 848158120 # Number of instructions committed
-system.cpu.commit.committedOps 996609834 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 1559580721 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 848164321 # Number of instructions committed
+system.cpu.commit.committedOps 996610207 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 304406931 # Number of memory references committed
-system.cpu.commit.loads 159650471 # Number of loads committed
-system.cpu.commit.membars 6926449 # Number of memory barriers committed
-system.cpu.commit.branches 189300112 # Number of branches committed
-system.cpu.commit.fp_insts 898776 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 915651780 # Number of committed integer instructions.
-system.cpu.commit.function_calls 25280403 # Number of function calls committed.
+system.cpu.commit.refs 304407284 # Number of memory references committed
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+system.cpu.commit.membars 6926917 # Number of memory barriers committed
+system.cpu.commit.branches 189306416 # Number of branches committed
+system.cpu.commit.fp_insts 898488 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 915651510 # Number of committed integer instructions.
+system.cpu.commit.function_calls 25281717 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 689842559 69.22% 69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 2150231 0.22% 69.43% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 98139 0.01% 69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 689843263 69.22% 69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 2149527 0.22% 69.43% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 98159 0.01% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction
@@ -975,537 +985,537 @@ system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% #
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
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system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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-system.cpu.committedOps 996609834 # Number of Ops (including micro ops) Simulated
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-system.cpu.cpi_total 1.919550 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 0.520955 # IPC: Total IPC of All Threads
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-system.cpu.dcache.tags.sampled_refs 9683261 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 29.234327 # Average number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.WriteLineReq_mshr_hits::total 7058 # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218425 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 218425 # number of LoadLockedReq MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses::total 5104706 # number of ReadReq MSHR misses
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-system.cpu.dcache.SoftPFReq_mshr_misses::total 1163297 # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226745 # number of WriteLineReq MSHR misses
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-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227713 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 227713 # number of LoadLockedReq MSHR misses
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-system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84710979000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 84710979000 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 77672671390 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23648689000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50594844438 # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50594844438 # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3209583500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3209583500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 279500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 279500 # number of StoreCondReq MSHR miss cycles
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-system.cpu.dcache.demand_mshr_miss_latency::total 162383650390 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186032339390 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 186032339390 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191842000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191842000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228406964 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228406964 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420248964 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420248964 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032584 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032584 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014368 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014368 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751440 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751440 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787659 # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787659 # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060835 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060835 # mshr miss rate for LoadLockedReq accesses
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+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50670413473 # number of WriteLineReq MSHR miss cycles
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+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 292500 # number of StoreCondReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total 162503876437 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186189032937 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192022000 # number of ReadReq MSHR uncacheable cycles
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+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228178464 # number of WriteReq MSHR uncacheable cycles
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+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032710 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024004 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.024004 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027787 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.027787 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16594.683220 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16594.683220 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38752.958704 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38752.958704 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20329.020878 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20329.020878 # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41243.163362 # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41243.163362 # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14094.862832 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14094.862832 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46583.333333 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46583.333333 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22841.953132 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22841.953132 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22488.570828 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22488.570828 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183854.207495 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183854.207495 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184841.137346 # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184841.137346 # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.804257 # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.804257 # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024071 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.024071 # mshr miss rate for demand accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16569.831097 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16569.831097 # average ReadReq mshr miss latency
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+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38700.531577 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20349.173967 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20349.173967 # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41300.892908 # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41300.892908 # average WriteLineReq mshr miss latency
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+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14056.462311 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41785.714286 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41785.714286 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22787.479839 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22787.479839 # average overall mshr miss latency
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+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency
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+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184834.356125 # average WriteReq mshr uncacheable latency
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+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.084395 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 15019267 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.928693 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 340404778 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 15019779 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 22.663767 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 20448016500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.928693 # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements 15141033 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 15141545 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 22.502248 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 511.928986 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 371211305 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 371211305 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 340404778 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 340404778 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 340404778 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 340404778 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 340404778 # number of overall hits
-system.cpu.icache.overall_hits::total 340404778 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 15786521 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 15786521 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 15786521 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 15786521 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 15786521 # number of overall misses
-system.cpu.icache.overall_misses::total 15786521 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 213423777380 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 213423777380 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 213423777380 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 213423777380 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 213423777380 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 213423777380 # number of overall miss cycles
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-system.cpu.icache.ReadReq_accesses::total 356191299 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1514,8 +1524,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@@ -1526,33 +1536,33 @@ system.cpu.l2cache.demand_mshr_hits::total 22 #
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@@ -1561,158 +1571,158 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004563 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.011422 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005492 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.076769 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.030007 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004563 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.011422 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005492 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.076769 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.030007 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127418.457139 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.852976 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.852976 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129465.449687 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129465.449687 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124519.613263 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124519.613263 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129612.133934 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129612.133934 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69897.425416 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69897.425416 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171348.610369 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148974.778069 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.893993 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.893993 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172278.000416 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.572427 # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129277.111734 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129277.111734 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124885.825844 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124885.825844 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129580.272072 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129580.272072 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69893.357947 # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69893.357947 # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127286.821529 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127556.902158 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124885.825844 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129396.364961 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128871.703002 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 50149666 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 25446406 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 2163 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2163 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 1624231 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 23137410 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 8571764 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 15019267 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 2370936 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 43497 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 43503 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1964146 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1964146 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 15020006 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 6501231 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 1333409 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 1226745 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45101659 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29271837 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729068 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1925616 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 77028180 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922840864 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1021731230 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2408256 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6275144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2953255494 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 1860303 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 27780180 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.025443 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.157467 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty 8579850 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 15141033 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 2388844 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 43659 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 43666 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1963403 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1963403 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 15141775 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 6525421 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq 1333524 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp 1226860 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45466959 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29342845 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 722067 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1919121 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 77450992 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1938426848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023681310 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2369528 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6237568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2970715254 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 1868325 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 27924144 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.025024 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.156198 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 27073367 97.46% 97.46% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 706813 2.54% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 27225372 97.50% 97.50% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 698772 2.50% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 27780180 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 48093772959 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 27924144 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 48365955497 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1496382 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 1497386 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 22560257433 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 22743143976 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 13373462829 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 13408724401 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 428394234 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 426213261 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 1141603196 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40297 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40297 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40299 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40299 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
@@ -1729,11 +1739,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353740 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
@@ -1748,12 +1758,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 41874500 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7492176 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 41885000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
@@ -1765,83 +1775,83 @@ system.iobus.reqLayer4.occupancy 9500 # La
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 25162500 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 25104500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 36499500 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 36501000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 567349755 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 567373998 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
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+system.membus.pkt_size_system.iocache.mem_side::total 7267328 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 116709054 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 2596 # Total snoops (count)
+system.membus.snoop_fanout::samples 2739791 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2735759 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2739791 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2735759 # Request fanout histogram
-system.membus.reqLayer0.occupancy 103971500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2739791 # Request fanout histogram
+system.membus.reqLayer0.occupancy 103925500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5468000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 5584000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 7155774176 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 4068025704 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 4069623687 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 44802062 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index 3cb93332b..cec4ea48a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -1,167 +1,167 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 47.389788 # Number of seconds simulated
-sim_ticks 47389787812000 # Number of ticks simulated
-final_tick 47389787812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.389857 # Number of seconds simulated
+sim_ticks 47389857088000 # Number of ticks simulated
+final_tick 47389857088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 198747 # Simulator instruction rate (inst/s)
-host_op_rate 233711 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10002045644 # Simulator tick rate (ticks/s)
-host_mem_usage 770464 # Number of bytes of host memory used
-host_seconds 4738.01 # Real time elapsed on the host
-sim_insts 941666991 # Number of instructions simulated
-sim_ops 1107326086 # Number of ops (including micro ops) simulated
+host_inst_rate 145229 # Simulator instruction rate (inst/s)
+host_op_rate 170794 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7499087776 # Simulator tick rate (ticks/s)
+host_mem_usage 767912 # Number of bytes of host memory used
+host_seconds 6319.42 # Real time elapsed on the host
+sim_insts 917760909 # Number of instructions simulated
+sim_ops 1079317478 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 242048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 235072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 4481952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 17644744 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 24714560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 130176 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 100480 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2927520 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 10373200 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 13817664 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 418560 # Number of bytes read from this memory
-system.physmem.bytes_read::total 75085976 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 4481952 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 2927520 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 7409472 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 91336640 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 104896 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 67648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3518240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 12875080 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 14592448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 209856 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 206272 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 3409696 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 12665040 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 18241216 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 447104 # Number of bytes read from this memory
+system.physmem.bytes_read::total 66337496 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3518240 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 3409696 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6927936 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 83736832 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 91357224 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 3782 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 3673 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 85983 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 275712 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 386165 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2034 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1570 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 45786 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 162094 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 215901 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6540 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1189240 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1427135 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 83757416 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 1639 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1057 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 70925 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 201186 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 228007 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 3279 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 3223 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 53320 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 197904 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 285019 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6986 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1052545 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1308388 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1429709 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 5108 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 4960 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 94576 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 372332 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 521517 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 2747 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 2120 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 61775 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 218891 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 291575 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8832 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1584434 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 94576 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 61775 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 156352 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1927349 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1310962 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 2213 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 1427 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 74240 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 271684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 307923 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 4428 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 4353 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 71950 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 267252 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 384918 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 9435 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1399825 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 74240 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 71950 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 146190 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1766978 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1927783 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1927349 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 5108 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 4960 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 94576 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 372766 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 521517 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 2747 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 2120 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 61775 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 218891 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 291575 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8832 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3512217 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1189240 # Number of read requests accepted
-system.physmem.writeReqs 1429709 # Number of write requests accepted
-system.physmem.readBursts 1189240 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1429709 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 76085248 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 26112 # Total number of bytes read from write queue
-system.physmem.bytesWritten 91355968 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 75085976 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 91357224 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 408 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total 1767412 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1766978 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 2213 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 1427 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 74240 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 272119 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 307923 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 4428 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 4353 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 71950 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 267252 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 384918 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 9435 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3167237 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1052545 # Number of read requests accepted
+system.physmem.writeReqs 1310962 # Number of write requests accepted
+system.physmem.readBursts 1052545 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1310962 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 67342528 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 20352 # Total number of bytes read from write queue
+system.physmem.bytesWritten 83756608 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 66337496 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 83757416 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 318 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 75559 # Per bank write bursts
-system.physmem.perBankRdBursts::1 80347 # Per bank write bursts
-system.physmem.perBankRdBursts::2 72779 # Per bank write bursts
-system.physmem.perBankRdBursts::3 76774 # Per bank write bursts
-system.physmem.perBankRdBursts::4 67339 # Per bank write bursts
-system.physmem.perBankRdBursts::5 74455 # Per bank write bursts
-system.physmem.perBankRdBursts::6 73080 # Per bank write bursts
-system.physmem.perBankRdBursts::7 76470 # Per bank write bursts
-system.physmem.perBankRdBursts::8 66258 # Per bank write bursts
-system.physmem.perBankRdBursts::9 90024 # Per bank write bursts
-system.physmem.perBankRdBursts::10 66637 # Per bank write bursts
-system.physmem.perBankRdBursts::11 75253 # Per bank write bursts
-system.physmem.perBankRdBursts::12 70442 # Per bank write bursts
-system.physmem.perBankRdBursts::13 75330 # Per bank write bursts
-system.physmem.perBankRdBursts::14 75010 # Per bank write bursts
-system.physmem.perBankRdBursts::15 73075 # Per bank write bursts
-system.physmem.perBankWrBursts::0 90501 # Per bank write bursts
-system.physmem.perBankWrBursts::1 95401 # Per bank write bursts
-system.physmem.perBankWrBursts::2 90023 # Per bank write bursts
-system.physmem.perBankWrBursts::3 92589 # Per bank write bursts
-system.physmem.perBankWrBursts::4 84855 # Per bank write bursts
-system.physmem.perBankWrBursts::5 90903 # Per bank write bursts
-system.physmem.perBankWrBursts::6 89246 # Per bank write bursts
-system.physmem.perBankWrBursts::7 91287 # Per bank write bursts
-system.physmem.perBankWrBursts::8 85201 # Per bank write bursts
-system.physmem.perBankWrBursts::9 88427 # Per bank write bursts
-system.physmem.perBankWrBursts::10 83204 # Per bank write bursts
-system.physmem.perBankWrBursts::11 90055 # Per bank write bursts
-system.physmem.perBankWrBursts::12 88087 # Per bank write bursts
-system.physmem.perBankWrBursts::13 89545 # Per bank write bursts
-system.physmem.perBankWrBursts::14 89641 # Per bank write bursts
-system.physmem.perBankWrBursts::15 88472 # Per bank write bursts
+system.physmem.perBankRdBursts::0 66733 # Per bank write bursts
+system.physmem.perBankRdBursts::1 71928 # Per bank write bursts
+system.physmem.perBankRdBursts::2 60670 # Per bank write bursts
+system.physmem.perBankRdBursts::3 68962 # Per bank write bursts
+system.physmem.perBankRdBursts::4 64861 # Per bank write bursts
+system.physmem.perBankRdBursts::5 72347 # Per bank write bursts
+system.physmem.perBankRdBursts::6 66642 # Per bank write bursts
+system.physmem.perBankRdBursts::7 70254 # Per bank write bursts
+system.physmem.perBankRdBursts::8 57646 # Per bank write bursts
+system.physmem.perBankRdBursts::9 82139 # Per bank write bursts
+system.physmem.perBankRdBursts::10 57944 # Per bank write bursts
+system.physmem.perBankRdBursts::11 62634 # Per bank write bursts
+system.physmem.perBankRdBursts::12 58488 # Per bank write bursts
+system.physmem.perBankRdBursts::13 63067 # Per bank write bursts
+system.physmem.perBankRdBursts::14 63784 # Per bank write bursts
+system.physmem.perBankRdBursts::15 64128 # Per bank write bursts
+system.physmem.perBankWrBursts::0 82746 # Per bank write bursts
+system.physmem.perBankWrBursts::1 86394 # Per bank write bursts
+system.physmem.perBankWrBursts::2 79376 # Per bank write bursts
+system.physmem.perBankWrBursts::3 84859 # Per bank write bursts
+system.physmem.perBankWrBursts::4 81483 # Per bank write bursts
+system.physmem.perBankWrBursts::5 87954 # Per bank write bursts
+system.physmem.perBankWrBursts::6 81083 # Per bank write bursts
+system.physmem.perBankWrBursts::7 85604 # Per bank write bursts
+system.physmem.perBankWrBursts::8 78166 # Per bank write bursts
+system.physmem.perBankWrBursts::9 81607 # Per bank write bursts
+system.physmem.perBankWrBursts::10 78637 # Per bank write bursts
+system.physmem.perBankWrBursts::11 81487 # Per bank write bursts
+system.physmem.perBankWrBursts::12 76226 # Per bank write bursts
+system.physmem.perBankWrBursts::13 79682 # Per bank write bursts
+system.physmem.perBankWrBursts::14 80516 # Per bank write bursts
+system.physmem.perBankWrBursts::15 82877 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 54 # Number of times write queue was full causing retry
-system.physmem.totGap 47389786204500 # Total gap between requests
+system.physmem.numWrRetry 67 # Number of times write queue was full causing retry
+system.physmem.totGap 47389855480500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 21333 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1167882 # Read request sizes (log2)
+system.physmem.readPktSize::6 1031187 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1427135 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 517223 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 309889 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 86868 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 62308 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 44912 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 40171 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 37097 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 35200 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 31021 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 8620 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 4820 # What read queue length does an incoming req see
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@@ -188,160 +188,163 @@ system.physmem.wrQLenPdf::11 1 # Wh
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-system.physmem.totQLat 53856464568 # Total ticks spent queuing
-system.physmem.totMemAccLat 76147064568 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5944160000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 45302.00 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 64052.00 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.61 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.93 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.93 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 62310.76 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.42 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.40 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.77 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.02 # Average write queue length when enqueuing
-system.physmem.readRowHits 898304 # Number of row buffer hits during reads
-system.physmem.writeRowHits 551645 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 38.65 # Row buffer hit rate for writes
-system.physmem.avgGap 18094963.36 # Average gap between requests
-system.physmem.pageHitRate 55.42 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 4527963720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2470615125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4655063400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 4696736400 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3095270087520 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1182204826065 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27396846617250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31690671909480 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.723752 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45576929865903 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1582448920000 # Time in different power states
+system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 2.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.24 # Average write queue length when enqueuing
+system.physmem.readRowHits 793650 # Number of row buffer hits during reads
+system.physmem.writeRowHits 503408 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.43 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 38.47 # Row buffer hit rate for writes
+system.physmem.avgGap 20050651.63 # Average gap between requests
+system.physmem.pageHitRate 54.94 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 4147801560 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2263185375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 4230649800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 4338353520 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3095274664560 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1171144383615 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27406590797250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31687989835680 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.666167 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45593219352262 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1582451260000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 230401885347 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 214185512238 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 4289407920 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2340450750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4617779400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4553055360 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3095270087520 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1179475938810 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27399240378000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31689787097760 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.705081 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45580905738073 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1582448920000 # Time in different power states
+system.physmem_1.actEnergy 3894995160 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2125245375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3976658400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 4142003040 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3095274664560 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1168941164895 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27408523445250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31686878176680 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.642709 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45596430811261 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1582451260000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 226432462927 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 210971448239 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
@@ -375,15 +378,19 @@ system.cf0.dma_read_txs 122 # Nu
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 148316317 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 98700135 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 7173487 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 104790534 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 69246034 # Number of BTB hits
+system.cpu0.branchPred.lookups 134064980 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 88919550 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 6498041 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 94483455 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 58137091 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 66.080429 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 20257126 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 200970 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 61.531504 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 17960348 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 169436 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups 4224209 # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits 2670261 # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses 1553948 # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted 396228 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -414,92 +421,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 656451 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 656451 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15175 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 105539 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 311743 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 344708 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 2528.499484 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 15542.861274 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535 341657 99.11% 99.11% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071 1528 0.44% 99.56% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607 1197 0.35% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143 153 0.04% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679 49 0.01% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215 98 0.03% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks 535513 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 535513 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11169 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 82857 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 246420 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 289093 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 2351.355792 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 14312.568858 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535 286889 99.24% 99.24% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071 1266 0.44% 99.68% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607 685 0.24% 99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.05% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679 30 0.01% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215 61 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 19 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 344708 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 348998 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 21459.124408 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 17964.910208 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 23694.067201 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 343876 98.53% 98.53% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1141 0.33% 98.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2753 0.79% 99.65% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 227 0.07% 99.71% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 627 0.18% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 192 0.06% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 104 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 60 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 348998 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 578933652396 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.598699 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.548790 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 577357711896 99.73% 99.73% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3 896498000 0.15% 99.88% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5 316445000 0.05% 99.94% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7 146967500 0.03% 99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9 111299500 0.02% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11 56334000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13 19702000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15 27806500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17 847500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19 17500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-21 1000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-25 1500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::26-27 2500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-29 1500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::30-31 15000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 578933652396 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 105540 87.43% 87.43% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 15175 12.57% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 120715 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656451 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 289093 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 272039 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 19613.296255 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 17220.717357 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 14703.962270 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 270425 99.41% 99.41% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 632 0.23% 99.64% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 733 0.27% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 61 0.02% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 123 0.05% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 15 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::720896-786431 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 272039 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 510275836160 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 0.563308 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev 0.548439 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 509171724160 99.78% 99.78% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3 565791000 0.11% 99.89% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5 239447000 0.05% 99.94% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7 119430500 0.02% 99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9 85504500 0.02% 99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11 55232500 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13 15487000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15 22822000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17 392500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19 5000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 510275836160 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 82857 88.12% 88.12% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 11169 11.88% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 94026 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 535513 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656451 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 120715 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 535513 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94026 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 120715 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 777166 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94026 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 629539 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 108931388 # DTB read hits
-system.cpu0.dtb.read_misses 471682 # DTB read misses
-system.cpu0.dtb.write_hits 89197418 # DTB write hits
-system.cpu0.dtb.write_misses 184769 # DTB write misses
-system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 97385635 # DTB read hits
+system.cpu0.dtb.read_misses 369085 # DTB read misses
+system.cpu0.dtb.write_hits 80705124 # DTB write hits
+system.cpu0.dtb.write_misses 166428 # DTB write misses
+system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 44365 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 621 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 7762 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 44183 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1064 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 34685 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 254 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 6533 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 42293 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 109403070 # DTB read accesses
-system.cpu0.dtb.write_accesses 89382187 # DTB write accesses
+system.cpu0.dtb.perms_faults 38231 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 97754720 # DTB read accesses
+system.cpu0.dtb.write_accesses 80871552 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 198128806 # DTB hits
-system.cpu0.dtb.misses 656451 # DTB misses
-system.cpu0.dtb.accesses 198785257 # DTB accesses
+system.cpu0.dtb.hits 178090759 # DTB hits
+system.cpu0.dtb.misses 535513 # DTB misses
+system.cpu0.dtb.accesses 178626272 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -529,1182 +530,1181 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 90363 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 90363 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1091 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 64708 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 10655 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 79708 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 1706.014453 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 13195.811582 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767 78781 98.84% 98.84% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535 448 0.56% 99.40% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303 48 0.06% 99.46% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071 68 0.09% 99.54% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839 262 0.33% 99.87% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607 71 0.09% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 79708 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 76454 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 28396.329819 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23477.172430 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 32204.710724 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 73773 96.49% 96.49% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 162 0.21% 96.71% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 2119 2.77% 99.48% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 153 0.20% 99.68% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 135 0.18% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 40 0.05% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 46 0.06% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 76454 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 441465071924 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.843066 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.363947 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 69311314608 15.70% 15.70% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 372126528316 84.29% 99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 24340500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3 2776500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4 112000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 441465071924 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 64708 98.34% 98.34% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 1091 1.66% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 65799 # Table walker page sizes translated
+system.cpu0.itb.walker.walks 79425 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 79425 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 951 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 57153 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore 9771 # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples 69654 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean 1061.827031 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 8997.758844 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767 69210 99.36% 99.36% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535 270 0.39% 99.75% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303 5 0.01% 99.76% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071 37 0.05% 99.81% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839 88 0.13% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607 29 0.04% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 69654 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 67875 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 24239.233886 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 22083.564087 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 17866.594665 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 67243 99.07% 99.07% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 67 0.10% 99.17% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 462 0.68% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 35 0.05% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 34 0.05% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 16 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 67875 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 394215499668 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 0.849337 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev 0.357871 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 59413822884 15.07% 15.07% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 334782784784 84.92% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2 17900000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3 873000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4 119000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 394215499668 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 57153 98.36% 98.36% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 951 1.64% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 58104 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 90363 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 90363 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 79425 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 79425 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 65799 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 65799 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 156162 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 234328898 # ITB inst hits
-system.cpu0.itb.inst_misses 90363 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58104 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58104 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 137529 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 209912640 # ITB inst hits
+system.cpu0.itb.inst_misses 79425 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 32417 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 44183 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1064 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 24340 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 232055 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 193348 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 234419261 # ITB inst accesses
-system.cpu0.itb.hits 234328898 # DTB hits
-system.cpu0.itb.misses 90363 # DTB misses
-system.cpu0.itb.accesses 234419261 # DTB accesses
-system.cpu0.numCycles 866695747 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 209992065 # ITB inst accesses
+system.cpu0.itb.hits 209912640 # DTB hits
+system.cpu0.itb.misses 79425 # DTB misses
+system.cpu0.itb.accesses 209992065 # DTB accesses
+system.cpu0.numCycles 756853118 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 96427999 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 657049317 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 148316317 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 89503160 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 718043211 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 15454228 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 2249933 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 346517 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 6840136 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 871998 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 916038 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 234095625 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 1822748 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 30173 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 833422946 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.924189 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.205964 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 86258252 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 591637469 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 134064980 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 78767700 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 626674135 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 13960220 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 1708629 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 309159 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 5578419 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 726023 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 793198 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 209720229 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 1626111 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 25986 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 729027925 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.950211 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.213293 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 464359111 55.72% 55.72% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 143558418 17.23% 72.94% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 49834021 5.98% 78.92% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 175671396 21.08% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 397179270 54.48% 54.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 129433697 17.75% 72.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 43948284 6.03% 78.26% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 158466674 21.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 833422946 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.171128 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.758108 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 115740257 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 426691474 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 243999178 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 41506758 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 5485279 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 21281954 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 2285386 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 681861872 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 24692274 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 5485279 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 154051427 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 67882232 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 271801592 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 246639237 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 87563179 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 663764828 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 6318012 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 12552479 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 452890 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 885924 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 48607179 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents 12032 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 634283684 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 1028589268 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 784350114 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 810310 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 573100551 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 61183133 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 17365169 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 15184195 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 83196676 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 108756528 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 92814116 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 10086189 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 8556855 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 639440304 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 17486234 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 645371130 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 2878587 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 57563182 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 37565263 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 301808 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 833422946 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.774362 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.052683 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 729027925 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.177135 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.781707 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 101905293 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 364135087 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 222287988 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 35712800 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 4986757 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 19110947 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 2030964 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 613952929 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 22693715 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 4986757 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 135896080 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 55064795 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 234892830 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 223531264 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 74656199 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 597354053 # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts 5967968 # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents 10658303 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 242676 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 277310 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 41417072 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents 10715 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 569274330 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 919727485 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 705445437 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 845170 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 513762865 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 55511456 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 14761622 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 12913765 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 71848393 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 97600013 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 83873039 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 8761707 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 7520310 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 575959343 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 14902678 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 580046321 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 2619697 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 52147933 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 33732364 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 256005 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 729027925 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.795643 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.062696 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 480257343 57.62% 57.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 149217372 17.90% 75.53% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 124187121 14.90% 90.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 71270973 8.55% 98.98% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 8484088 1.02% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 6049 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 413752637 56.75% 56.75% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 130387752 17.89% 74.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 112730807 15.46% 90.10% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 64434367 8.84% 98.94% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 7717956 1.06% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 4406 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 833422946 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 729027925 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 66055625 45.01% 45.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 69293 0.05% 45.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 22404 0.02% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 38927283 26.53% 71.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 41671380 28.40% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 60438369 45.47% 45.47% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::IntDiv 17968 0.01% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.52% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.52% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 10 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 34488153 25.95% 71.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 37935532 28.54% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 440798988 68.30% 68.30% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 1592862 0.25% 68.55% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 83426 0.01% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.56% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 82619 0.01% 68.57% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 396224561 68.31% 68.31% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 1355740 0.23% 68.54% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 69556 0.01% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 26 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 78264 0.01% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 112232372 17.39% 85.96% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 90580861 14.04% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 100394563 17.31% 85.88% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 81923573 14.12% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 645371130 # Type of FU issued
-system.cpu0.iq.rate 0.744634 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 146746002 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.227382 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 2272436054 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 714094331 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 626839047 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 1353741 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 552796 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 503202 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 791281833 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 835299 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 3004923 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 580046321 # Type of FU issued
+system.cpu0.iq.rate 0.766392 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 132927074 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.229166 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 2023285471 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 642599747 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 563357563 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 1381865 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 550084 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 513487 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 712117129 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 856256 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 2617003 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 13275769 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 18782 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 159110 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 6200623 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 11923389 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 15941 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 140828 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 5327299 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2963562 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5149852 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2590097 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 4396592 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 5485279 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 8917054 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 3122413 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 657057128 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles 4986757 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 6158595 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 2729815 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 590987234 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 108756528 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 92814116 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 14923426 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 69667 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 2968943 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 159110 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 2170447 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 3075539 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 5245986 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 637077586 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 108926469 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 7646279 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts 97600013 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 83873039 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 12685897 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 60837 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 2608142 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 140828 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 1838258 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 2998999 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 4837257 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 572331002 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 97377740 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 7191247 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 130590 # number of nop insts executed
-system.cpu0.iew.exec_refs 198124159 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 119913450 # Number of branches executed
-system.cpu0.iew.exec_stores 89197690 # Number of stores executed
-system.cpu0.iew.exec_rate 0.735065 # Inst execution rate
-system.cpu0.iew.wb_sent 628157908 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 627342249 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 305063287 # num instructions producing a value
-system.cpu0.iew.wb_consumers 500478465 # num instructions consuming a value
-system.cpu0.iew.wb_rate 0.723832 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.609543 # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts 50300993 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 17184426 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 4931652 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 823863885 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.727503 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.534838 # Number of insts commited each cycle
+system.cpu0.iew.exec_nop 125213 # number of nop insts executed
+system.cpu0.iew.exec_refs 178083928 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 107921948 # Number of branches executed
+system.cpu0.iew.exec_stores 80706188 # Number of stores executed
+system.cpu0.iew.exec_rate 0.756198 # Inst execution rate
+system.cpu0.iew.wb_sent 564585754 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 563871050 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 273627354 # num instructions producing a value
+system.cpu0.iew.wb_consumers 449179775 # num instructions consuming a value
+system.cpu0.iew.wb_rate 0.745020 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.609171 # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts 45416795 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 14646672 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 4504688 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 720395645 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.747803 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.555225 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 560826617 68.07% 68.07% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 136759290 16.60% 84.67% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 58156007 7.06% 91.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 19570368 2.38% 94.11% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 13861730 1.68% 95.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 9557005 1.16% 96.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 6407217 0.78% 97.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 3899508 0.47% 98.20% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 14826143 1.80% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 485771326 67.43% 67.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 120512789 16.73% 84.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 52399936 7.27% 91.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 17702861 2.46% 93.89% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 12776683 1.77% 95.66% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 8497825 1.18% 96.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 5820958 0.81% 97.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 3534904 0.49% 98.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 13378363 1.86% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 823863885 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 510319417 # Number of instructions committed
-system.cpu0.commit.committedOps 599363355 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 720395645 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 458462253 # Number of instructions committed
+system.cpu0.commit.committedOps 538714081 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 182094252 # Number of memory references committed
-system.cpu0.commit.loads 95480759 # Number of loads committed
-system.cpu0.commit.membars 4094698 # Number of memory barriers committed
-system.cpu0.commit.branches 113994539 # Number of branches committed
-system.cpu0.commit.fp_insts 490256 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 549724602 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 15118537 # Number of function calls committed.
+system.cpu0.commit.refs 164222361 # Number of memory references committed
+system.cpu0.commit.loads 85676622 # Number of loads committed
+system.cpu0.commit.membars 3641024 # Number of memory barriers committed
+system.cpu0.commit.branches 102649552 # Number of branches committed
+system.cpu0.commit.fp_insts 504968 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 494164906 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 13432281 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 415786848 69.37% 69.37% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 1342849 0.22% 69.60% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 66347 0.01% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 73059 0.01% 69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 95480759 15.93% 85.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 86613493 14.45% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 373237846 69.28% 69.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 1127454 0.21% 69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 54738 0.01% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 71640 0.01% 69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 85676622 15.90% 85.42% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 78545739 14.58% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 599363355 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 14826143 # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads 1454251951 # The number of ROB reads
-system.cpu0.rob.rob_writes 1308847090 # The number of ROB writes
-system.cpu0.timesIdled 1090671 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 33272801 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 93912870328 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 510319417 # Number of Instructions Simulated
-system.cpu0.committedOps 599363355 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 1.698340 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 1.698340 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.588810 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.588810 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 752522588 # number of integer regfile reads
-system.cpu0.int_regfile_writes 446228364 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 791452 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 475504 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 139593627 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 140336082 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 1450242581 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 17300190 # number of misc regfile writes
-system.cpu0.dcache.tags.replacements 6628748 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 507.898673 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 168544062 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 6629257 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 25.424276 # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total 538714081 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 13378363 # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads 1287287379 # The number of ROB reads
+system.cpu0.rob.rob_writes 1176858570 # The number of ROB writes
+system.cpu0.timesIdled 934729 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 27825193 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 94022861092 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 458462253 # Number of Instructions Simulated
+system.cpu0.committedOps 538714081 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 1.650852 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 1.650852 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.605748 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.605748 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 675960762 # number of integer regfile reads
+system.cpu0.int_regfile_writes 401183302 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 830771 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 428332 # number of floating regfile writes
+system.cpu0.cc_regfile_reads 124727892 # number of cc regfile reads
+system.cpu0.cc_regfile_writes 125481667 # number of cc regfile writes
+system.cpu0.misc_regfile_reads 1276105833 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 14867290 # number of misc regfile writes
+system.cpu0.dcache.tags.replacements 5765600 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 490.322435 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 152640999 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 5766111 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 26.472088 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.898673 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991990 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.991990 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 377708512 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 377708512 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 88226592 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 88226592 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 75029005 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 75029005 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 221757 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 221757 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 177850 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 177850 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1970217 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1970217 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2022489 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 2022489 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 163255597 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 163255597 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 163477354 # number of overall hits
-system.cpu0.dcache.overall_hits::total 163477354 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 7367994 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 7367994 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 8340746 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 8340746 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 804684 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 804684 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 826218 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 826218 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 297937 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 297937 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 206643 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 206643 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 15708740 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 15708740 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 16513424 # number of overall misses
-system.cpu0.dcache.overall_misses::total 16513424 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 129957875000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 129957875000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 197611984656 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 197611984656 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 55152577242 # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total 55152577242 # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4832056500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 4832056500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5849414000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 5849414000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5216000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5216000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 327569859656 # number of demand (read+write) miss cycles
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.SoftPFReq_mshr_misses::total 797671 # number of SoftPFReq MSHR misses
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-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.777123 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.818709 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.818709 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063928 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063928 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092701 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092701 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029267 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.029267 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033532 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.033532 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16329.195937 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16329.195937 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27290.075096 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27290.075096 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26386.718961 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26386.718961 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65808.106956 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65808.106956 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14678.411575 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14678.411575 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27307.167434 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27307.167434 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 5765616 # number of writebacks
+system.cpu0.dcache.writebacks::total 5765616 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3289806 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 3289806 # number of ReadReq MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_hits::total 5763001 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4255 # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total 4255 # number of WriteLineReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 124637 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_misses::total 1429655 # number of WriteReq MSHR misses
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+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 791698 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total 791698 # number of WriteLineReq MSHR misses
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116660 # number of LoadLockedReq MSHR misses
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+system.cpu0.dcache.StoreCondReq_mshr_misses::total 189313 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19295 # number of ReadReq MSHR uncacheable
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+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 20724 # number of WriteReq MSHR uncacheable
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+system.cpu0.dcache.overall_mshr_miss_latency::total 102033849955 # number of overall MSHR miss cycles
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+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.766269 # mshr miss rate for SoftPFReq accesses
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+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.816121 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.816121 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056269 # mshr miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15278.600414 # average ReadReq mshr miss latency
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+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26610.946316 # average WriteReq mshr miss latency
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24501.211986 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 61813.327838 # average WriteLineReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14447.381279 # average LoadLockedReq mshr miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19760.878778 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19760.878778 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20636.577410 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20636.577410 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194253.030687 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194253.030687 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189071.693048 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189071.693048 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191543.803393 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191543.803393 # average overall mshr uncacheable latency
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+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196416.273646 # average ReadReq mshr uncacheable latency
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+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190213.158657 # average WriteReq mshr uncacheable latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193203.965616 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 6540239 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.944561 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 227144563 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 6540751 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 34.727597 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 18012149000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.944561 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999892 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy
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+system.cpu0.icache.tags.sampled_refs 5849915 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 34.788016 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 18014203000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.943926 # Average occupied blocks per requestor
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system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 457 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 474674738 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 474674738 # Number of data accesses
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-system.cpu0.icache.ReadReq_miss_latency::total 78815703700 # number of ReadReq miss cycles
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-system.cpu0.icache.overall_accesses::total 234066977 # number of overall (read+write) accesses
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-system.cpu0.icache.ReadReq_miss_rate::total 0.029575 # miss rate for ReadReq accesses
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-system.cpu0.icache.demand_miss_rate::total 0.029575 # miss rate for demand accesses
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-system.cpu0.icache.overall_miss_rate::total 0.029575 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11385.580767 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 11385.580767 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11385.580767 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 11385.580767 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11385.580767 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 11385.580767 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 12205805 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 1929 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 815036 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.975786 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets 148.384615 # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses 425234482 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 425234482 # Number of data accesses
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+system.cpu0.icache.overall_misses::total 6185325 # number of overall misses
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+system.cpu0.icache.ReadReq_miss_latency::total 68820233655 # number of ReadReq miss cycles
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+system.cpu0.icache.demand_miss_latency::total 68820233655 # number of demand (read+write) miss cycles
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-system.cpu0.icache.ReadReq_mshr_miss_latency::total 70913768580 # number of ReadReq MSHR miss cycles
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-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10841.784193 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10841.784193 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10841.784193 # average overall mshr miss latency
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system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32443.203574 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39856.122569 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37598.564237 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37575.923084 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36164.751994 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32443.203574 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39856.122569 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63083.605865 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45125.794791 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188395.024618 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158055.681482 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182436.304140 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182436.304140 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185309.277268 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 166296.548261 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 27325930 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14061042 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 2238708 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2238208 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 1035490 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 12208665 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 21607 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 21606 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty 6237038 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean 8831409 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 2977562 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 1194062 # Transaction distribution
+system.cpu0.toL2Bus.snoop_filter.tot_requests 24114479 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12402894 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2291 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 1959388 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1958967 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 421 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq 868302 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 10703945 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 20725 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 20724 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471023 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean 7766214 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 2549883 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 981532 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 497340 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368088 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 556890 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1397051 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1373685 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6540784 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5522441 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 877204 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 819959 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19664376 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21309678 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 452328 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1442065 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 42868447 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 837525072 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 808748037 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1730136 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5469168 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1653472413 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 7780551 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 22331077 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.118319 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.323054 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 467602 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343874 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 514595 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 137 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1212904 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1189199 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5849954 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4880551 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 848509 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 789376 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17591867 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18635587 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390565 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1180743 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 37798762 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 749097616 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 700307787 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1488232 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4460536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1455354171 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 6848442 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 19646181 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.117106 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.321630 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 19689394 88.17% 88.17% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 2641183 11.83% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 500 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 17346012 88.29% 88.29% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 2299647 11.71% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 522 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 22331077 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 27171038408 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 19646181 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 23957915414 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 185981894 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 186819649 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 9839167037 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 8802550782 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 9551310776 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 8265265885 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 236496624 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 204815934 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 759104112 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 623887061 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 126248667 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 84543955 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 6151855 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 88859655 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 57842551 # Number of BTB hits
+system.cpu1.branchPred.lookups 135174598 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 89157012 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 6771553 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 95119508 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 59219614 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 65.094278 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 16827370 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 172583 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 62.258116 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 18509493 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 199065 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups 4260619 # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits 2645570 # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses 1615049 # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted 400784 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1734,83 +1734,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 548057 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 548057 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11885 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 88263 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 254796 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 293261 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 2461.776370 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 15099.601662 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-131071 292248 99.65% 99.65% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-262143 874 0.30% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-393215 111 0.04% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-524287 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::655360-786431 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::917504-1.04858e+06 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::1.04858e+06-1.17965e+06 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 293261 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 284367 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 20156.804411 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17511.621467 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 17128.200610 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 282098 99.20% 99.20% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 636 0.22% 99.43% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1232 0.43% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 88 0.03% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 184 0.06% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 74 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 284367 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 458679401608 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.570209 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.555852 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 457501852108 99.74% 99.74% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3 610883500 0.13% 99.88% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5 255647500 0.06% 99.93% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7 124159500 0.03% 99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9 89499500 0.02% 99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11 56037000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13 17511000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15 23464500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17 345500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 458679401608 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 88263 88.13% 88.13% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 11885 11.87% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 100148 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 548057 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 620331 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 620331 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13694 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 99863 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 301286 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 319045 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 2609.283957 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 15339.812797 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535 316072 99.07% 99.07% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071 1597 0.50% 99.57% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607 1113 0.35% 99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143 132 0.04% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679 45 0.01% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215 65 0.02% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751 13 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 319045 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 336255 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 21304.924834 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17913.652779 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 23319.449537 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 331614 98.62% 98.62% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1015 0.30% 98.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 2524 0.75% 99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 218 0.06% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 559 0.17% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 132 0.04% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 112 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 49 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 16 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 12 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 336255 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 493108416476 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.613633 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.555238 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 491595088976 99.69% 99.69% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3 828838000 0.17% 99.86% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5 323227000 0.07% 99.93% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7 140968000 0.03% 99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9 113706500 0.02% 99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11 58901000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13 19970500 0.00% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15 26949000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17 748000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19 19500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 493108416476 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 99864 87.94% 87.94% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 13694 12.06% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 113558 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 620331 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 548057 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 100148 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 620331 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 113558 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 100148 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 648205 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 113558 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 733889 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 92943696 # DTB read hits
-system.cpu1.dtb.read_misses 375200 # DTB read misses
-system.cpu1.dtb.write_hits 76575759 # DTB write hits
-system.cpu1.dtb.write_misses 172857 # DTB write misses
-system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 99541236 # DTB read hits
+system.cpu1.dtb.read_misses 446261 # DTB read misses
+system.cpu1.dtb.write_hits 80566614 # DTB write hits
+system.cpu1.dtb.write_misses 174070 # DTB write misses
+system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 35565 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 273 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 6009 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 44183 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1064 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 43247 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 634 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 6731 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 39938 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 93318896 # DTB read accesses
-system.cpu1.dtb.write_accesses 76748616 # DTB write accesses
+system.cpu1.dtb.perms_faults 41159 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 99987497 # DTB read accesses
+system.cpu1.dtb.write_accesses 80740684 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 169519455 # DTB hits
-system.cpu1.dtb.misses 548057 # DTB misses
-system.cpu1.dtb.accesses 170067512 # DTB accesses
+system.cpu1.dtb.hits 180107850 # DTB hits
+system.cpu1.dtb.misses 620331 # DTB misses
+system.cpu1.dtb.accesses 180728181 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1840,1175 +1844,1175 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 81693 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 81693 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 804 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58754 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 9814 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 71879 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 1351.430877 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 10594.939676 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767 71238 99.11% 99.11% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535 384 0.53% 99.64% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303 26 0.04% 99.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071 48 0.07% 99.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839 113 0.16% 99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607 53 0.07% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::458752-491519 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 71879 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 69372 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 25253.272214 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 22467.195437 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 22091.390725 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 68357 98.54% 98.54% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 80 0.12% 98.65% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 757 1.09% 99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 76 0.11% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 55 0.08% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 11 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 69372 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 407136400556 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 0.838375 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev 0.368280 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 65826877124 16.17% 16.17% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 341288268432 83.83% 99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 19212000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3 1863000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4 150500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5 29500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 407136400556 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 58754 98.65% 98.65% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 804 1.35% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 59558 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 88034 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 88034 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1080 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62024 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore 10531 # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples 77503 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean 1737.752087 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 13376.771603 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767 76531 98.75% 98.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535 407 0.53% 99.27% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303 54 0.07% 99.34% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071 157 0.20% 99.54% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839 274 0.35% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607 44 0.06% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 77503 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 73635 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 28077.836627 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23325.571005 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 31326.629409 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 71135 96.60% 96.60% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 154 0.21% 96.81% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 1986 2.70% 99.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 113 0.15% 99.66% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 137 0.19% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 53 0.07% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 44 0.06% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 73635 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 428680982536 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean 0.877576 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev 0.328123 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 52527553308 12.25% 12.25% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1 376108944728 87.74% 99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2 42347500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3 2103500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4 33500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 428680982536 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 62024 98.29% 98.29% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 1080 1.71% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 63104 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 81693 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 81693 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 88034 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 88034 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59558 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59558 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 141251 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 198485673 # ITB inst hits
-system.cpu1.itb.inst_misses 81693 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63104 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63104 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 151138 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 212987962 # ITB inst hits
+system.cpu1.itb.inst_misses 88034 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 25168 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 44183 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1064 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 31450 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 206844 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 212403 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 198567366 # ITB inst accesses
-system.cpu1.itb.hits 198485673 # DTB hits
-system.cpu1.itb.misses 81693 # DTB misses
-system.cpu1.itb.accesses 198567366 # DTB accesses
-system.cpu1.numCycles 706357244 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 213075996 # ITB inst accesses
+system.cpu1.itb.hits 212987962 # DTB hits
+system.cpu1.itb.misses 88034 # DTB misses
+system.cpu1.itb.accesses 213075996 # DTB accesses
+system.cpu1.numCycles 763303942 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 79757859 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 558826368 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 126248667 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 74669921 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 588203471 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 13287396 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 1859618 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 301703 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 6107940 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 765855 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 800562 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 198257766 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 1531728 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 28220 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 684440706 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.958907 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.215902 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 89198965 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 599138491 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 135174598 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 80374677 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 631697152 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 14629606 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 2135822 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 325301 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 6190061 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 869593 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 862105 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 212754259 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 1709590 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 28554 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 738593802 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.951348 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.213932 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 370240796 54.09% 54.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 122429423 17.89% 71.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 41426108 6.05% 78.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 150344379 21.97% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 402298959 54.47% 54.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 130678569 17.69% 72.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 44867308 6.07% 78.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 160748966 21.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 684440706 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.178732 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.791138 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 96144629 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 340788757 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 207685438 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 35085697 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 4736185 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 17812454 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 1944962 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 579921351 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 21338656 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 4736185 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 128930138 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 49237812 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 228920665 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 209565208 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 63050698 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 564205236 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 5454916 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 10256691 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 240677 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 354262 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 30213880 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents 11171 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 537096625 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 872562806 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 667157366 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 686134 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 483982102 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 53114517 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 15098547 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 13303136 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 70645723 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 92937642 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 79702799 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 8581032 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 7318731 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 542982721 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 15290733 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 547999845 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 2492376 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 50310716 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 32527030 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 258040 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 684440706 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.800653 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.060998 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 738593802 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.177091 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.784928 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 106478117 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 366845169 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 222515957 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 37512815 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 5241744 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 19111386 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 2112679 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 619567000 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 23338360 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 5241744 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 141946273 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 54617946 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 243861784 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 224134357 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 68791698 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 602126263 # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts 6118576 # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents 11056239 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 380631 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 940722 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 33286587 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents 12083 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 573060902 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 928019832 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 710062229 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 649328 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 514926448 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 58134448 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 16118585 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 14068970 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 75560239 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 99853363 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 83838519 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 9473424 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 8115334 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 579120615 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 16293769 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 584059770 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 2714782 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 54810980 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 35376701 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 290425 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 738593802 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.790773 # Number of insts issued each cycle
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system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 384384408 56.16% 56.16% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 127393239 18.61% 74.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 104776738 15.31% 90.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 60496264 8.84% 98.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 7385947 1.08% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 4110 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 417929764 56.58% 56.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 136913052 18.54% 75.12% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 111746112 15.13% 90.25% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 64370034 8.72% 98.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 7629808 1.03% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 5032 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 684440706 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 738593802 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 55139379 44.00% 44.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 46977 0.04% 44.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 11488 0.01% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 7 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.05% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 33502933 26.74% 70.78% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 36611567 29.22% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 58567749 44.20% 44.20% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 70680 0.05% 44.25% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 16113 0.01% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 26 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.26% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 36085591 27.23% 71.50% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 37772354 28.50% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 373183107 68.10% 68.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 1202540 0.22% 68.32% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 67362 0.01% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 2 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 42387 0.01% 68.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 95737452 17.47% 85.81% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 77766935 14.19% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 36 0.00% 0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 397950619 68.14% 68.14% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 1394287 0.24% 68.37% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 80723 0.01% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.39% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 45828 0.01% 68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 102773744 17.60% 85.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 81814529 14.01% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 547999845 # Type of FU issued
-system.cpu1.iq.rate 0.775811 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 125312351 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.228672 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 1907132649 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 608283649 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 532258075 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 1112472 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 437179 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 408398 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 672616839 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 695346 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 2459057 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 584059770 # Type of FU issued
+system.cpu1.iq.rate 0.765173 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 132512513 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.226882 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 2040871763 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 649951389 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 566663887 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 1068872 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 423239 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 394625 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 715907019 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 665228 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 2663748 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 11465284 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 14564 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 137615 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 5482962 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 12784321 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 18121 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 150654 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 5561892 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 2463728 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 4019009 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 2706765 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 4288761 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 4736185 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 6263173 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 2375395 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 558389408 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles 5241744 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 8152179 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 2696224 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 595550479 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 92937642 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 79702799 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 13061254 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 63231 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2253383 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 137615 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 1902304 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 2611236 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 4513540 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 540870869 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 92937926 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 6592838 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts 99853363 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 83838519 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 13801566 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 59598 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2567849 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 150654 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 1960671 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 3092522 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 5053193 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 576018607 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 99536730 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 7427921 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 115954 # number of nop insts executed
-system.cpu1.iew.exec_refs 169513519 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 101590895 # Number of branches executed
-system.cpu1.iew.exec_stores 76575593 # Number of stores executed
-system.cpu1.iew.exec_rate 0.765719 # Inst execution rate
-system.cpu1.iew.wb_sent 533377466 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 532666473 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 257434056 # num instructions producing a value
-system.cpu1.iew.wb_consumers 422362739 # num instructions consuming a value
-system.cpu1.iew.wb_rate 0.754104 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.609509 # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts 44033715 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 15032693 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 4244342 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 676109975 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.751302 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.553770 # Number of insts commited each cycle
+system.cpu1.iew.exec_nop 136095 # number of nop insts executed
+system.cpu1.iew.exec_refs 180100552 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 107831822 # Number of branches executed
+system.cpu1.iew.exec_stores 80563822 # Number of stores executed
+system.cpu1.iew.exec_rate 0.754639 # Inst execution rate
+system.cpu1.iew.wb_sent 567845555 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 567058512 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 275064587 # num instructions producing a value
+system.cpu1.iew.wb_consumers 450436874 # num instructions consuming a value
+system.cpu1.iew.wb_rate 0.742900 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.610662 # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts 47911948 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 16003344 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 4698494 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 729478017 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.741083 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.544204 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 452513238 66.93% 66.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 117033560 17.31% 84.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 49159205 7.27% 91.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 16297256 2.41% 93.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 11766410 1.74% 95.66% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 7925929 1.17% 96.83% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 5496145 0.81% 97.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 3299018 0.49% 98.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 12619214 1.87% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 491334549 67.35% 67.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 124605119 17.08% 84.44% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 52434637 7.19% 91.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 17448264 2.39% 94.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 12346698 1.69% 95.71% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 8646744 1.19% 96.89% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 5821113 0.80% 97.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 3490122 0.48% 98.17% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 13350771 1.83% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 676109975 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 431347574 # Number of instructions committed
-system.cpu1.commit.committedOps 507962731 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 729478017 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 459298656 # Number of instructions committed
+system.cpu1.commit.committedOps 540603397 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 155692194 # Number of memory references committed
-system.cpu1.commit.loads 81472357 # Number of loads committed
-system.cpu1.commit.membars 3613840 # Number of memory barriers committed
-system.cpu1.commit.branches 96395557 # Number of branches committed
-system.cpu1.commit.fp_insts 400161 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 466077725 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 12507771 # Number of function calls committed.
+system.cpu1.commit.refs 165345668 # Number of memory references committed
+system.cpu1.commit.loads 87069041 # Number of loads committed
+system.cpu1.commit.membars 3858315 # Number of memory barriers committed
+system.cpu1.commit.branches 102318506 # Number of branches committed
+system.cpu1.commit.fp_insts 386565 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 496515316 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 13693042 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 351213617 69.14% 69.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 966298 0.19% 69.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 53161 0.01% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 37419 0.01% 69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 81472357 16.04% 85.39% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 74219837 14.61% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 374009133 69.18% 69.18% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 1144857 0.21% 69.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 64258 0.01% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 39481 0.01% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 87069041 16.11% 85.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 78276627 14.48% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 507962731 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 12619214 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 1211577193 # The number of ROB reads
-system.cpu1.rob.rob_writes 1112287280 # The number of ROB writes
-system.cpu1.timesIdled 906823 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 21916538 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 94073218429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 431347574 # Number of Instructions Simulated
-system.cpu1.committedOps 507962731 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 1.637559 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.637559 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.610665 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.610665 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 639350275 # number of integer regfile reads
-system.cpu1.int_regfile_writes 378298878 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 675031 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 302028 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 116956107 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 117682636 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 1203449961 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 15173732 # number of misc regfile writes
-system.cpu1.dcache.tags.replacements 5181385 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 448.144658 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 145015910 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5181896 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 27.985106 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8482612216500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.144658 # Average occupied blocks per requestor
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-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
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-system.cpu1.dcache.ReadReq_hits::total 75698887 # number of ReadReq hits
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-system.cpu1.dcache.SoftPFReq_hits::total 177630 # number of SoftPFReq hits
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-system.cpu1.dcache.LoadLockedReq_hits::total 1768516 # number of LoadLockedReq hits
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-system.cpu1.dcache.overall_hits::total 140574831 # number of overall hits
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-system.cpu1.dcache.SoftPFReq_misses::total 655927 # number of SoftPFReq misses
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-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4605500 # number of StoreCondFailReq miss cycles
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-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 571900 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total 571900 # number of WriteLineReq accesses(hits+misses)
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-system.cpu1.dcache.overall_accesses::total 154276960 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074248 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.074248 # miss rate for ReadReq accesses
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-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.786901 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.759892 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total 0.759892 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120875 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120875 # miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.overall_miss_rate::total 0.088815 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16651.721604 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16651.721604 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21456.415133 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21456.415133 # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36868.677808 # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36868.677808 # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16157.484136 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16157.484136 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27720.094415 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27720.094415 # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total 540603397 # Class of committed instruction
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+system.cpu1.rob.rob_reads 1300306905 # The number of ROB reads
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+system.cpu1.timesIdled 1002683 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 24710140 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu1.committedInsts 459298656 # Number of Instructions Simulated
+system.cpu1.committedOps 540603397 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 1.661890 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.661890 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.601724 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.601724 # IPC: Total IPC of All Threads
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+system.cpu1.dcache.overall_miss_rate::total 0.089566 # miss rate for overall accesses
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+system.cpu1.dcache.ReadReq_avg_miss_latency::total 17199.921809 # average ReadReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22076.530435 # average WriteReq miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19220.453810 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19220.453810 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18300.362151 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18300.362151 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 4223664 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 23883166 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 349910 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 702949 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.070715 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 33.975674 # average number of cycles each access was blocked
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system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 5181409 # number of writebacks
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-system.cpu1.dcache.StoreCondReq_mshr_misses::total 198274 # number of StoreCondReq MSHR misses
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-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.753775 # mshr miss rate for WriteLineReq accesses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057697 # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15185.398987 # average ReadReq mshr miss latency
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-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35689.369680 # average WriteLineReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17885.384480 # average overall mshr miss latency
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-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18819.005959 # average overall mshr miss latency
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-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165799.120630 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165799.120630 # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 170300.580481 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170300.580481 # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167921.637110 # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167921.637110 # average overall mshr uncacheable latency
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+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162185.394135 # average ReadReq mshr uncacheable latency
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+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167614.069728 # average WriteReq mshr uncacheable latency
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system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11261.185249 # average overall miss latency
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system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
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system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 58335043744 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58335043744 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 58335043744 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.icache.overall_mshr_miss_latency::total 58335043744 # number of overall MSHR miss cycles
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-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9645998 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9645998 # number of overall MSHR uncacheable cycles
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-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027408 # mshr miss rate for ReadReq accesses
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-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10735.857746 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10735.857746 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10735.857746 # average overall mshr miss latency
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-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 143970.119403 # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 143970.119403 # average overall mshr uncacheable latency
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+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136634.298507 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 47.585138 # Average occupied blocks per requestor
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-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 797.121970 # Average occupied blocks per requestor
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-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 201 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 613 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 375 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id
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-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31534.767177 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31534.767177 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19207.062102 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19207.062102 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 829199.800000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 829199.800000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46834.031226 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46834.031226 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31709.187167 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34078.669100 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34078.669100 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 47809.112331 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 47809.112331 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36652.754938 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35194.853490 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36652.754938 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 61725.447981 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42949.626773 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157792.808589 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 157715.959791 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162796.257105 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162796.257105 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 160152.021440 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 160106.841012 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.217994 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 51811.676353 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 71648.996357 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 71648.996357 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31670.734897 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31670.734897 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19631.181228 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19631.181228 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 577499.888889 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 577499.888889 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 51697.229002 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 51697.229002 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32511.694187 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32511.694187 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37055.329306 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37055.329306 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53334.613758 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53334.613758 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32511.694187 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 39977.048417 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 37759.216929 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 48178.129941 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 56617.490494 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32511.694187 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 39977.048417 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 71648.996357 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 48055.434692 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129119.402985 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154177.308652 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154090.315560 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160109.895069 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 160109.895069 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129119.402985 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 157022.728503 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 156972.234976 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 22091106 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11384004 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 1936993 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1936645 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 348 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 874786 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 10136227 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 16538 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 16538 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty 4413805 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean 7327056 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 2612396 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 936031 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 441152 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362021 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 491027 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1142611 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1118724 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5433664 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4777910 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 490221 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 429103 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16300596 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16818339 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 407716 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1217877 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 34744528 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 695476144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 648316997 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1556520 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4598760 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1349948421 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 6442202 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 18213717 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.125270 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.331083 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests 24388069 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12550954 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1330 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 2014096 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2013701 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 395 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq 959951 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 11237676 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 17726 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 17726 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty 4787619 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean 8213812 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 2728404 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 1028067 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 448479 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348012 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 489399 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 78 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 137 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1222080 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1199432 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6084570 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5051662 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 514998 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp 456882 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18253249 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18257850 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 433982 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1356808 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 38301889 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 778787952 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707763692 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1655168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5145936 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1493352748 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 6663078 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 19657279 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.121604 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.326890 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 15932433 87.47% 87.47% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 2280936 12.52% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 348 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 17267267 87.84% 87.84% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 2389617 12.16% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 395 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 18213717 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 21942621967 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 185589939 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 19657279 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 24252664474 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 176228657 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 8156255052 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 9133388497 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7729530656 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 8423069488 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 213583628 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 227423320 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 643750548 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 714183249 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40360 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40360 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136653 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136653 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47814 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 40322 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40322 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136632 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136632 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47654 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
@@ -3019,15 +3023,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122696 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231250 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231250 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122588 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231240 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231240 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354026 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47834 # Cumulative packet size per connected master and slave (bytes)
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@@ -3038,103 +3042,103 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
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-system.iocache.demand_avg_mshr_miss_latency::realview.ide 136925.487917 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 136717.362202 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90425 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 136925.487917 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 136717.362202 # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76759.417501 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76759.417501 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 142143.669928 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 141906.517353 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 142143.669928 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 141906.517353 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 1667118 # number of replacements
-system.l2c.tags.tagsinuse 63361.638008 # Cycle average of tags in use
-system.l2c.tags.total_refs 6455366 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1727204 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 3.737466 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 4891044000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 22165.641734 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 239.050229 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 385.051566 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4239.404809 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 8813.325361 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14013.639467 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 94.428510 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 121.397759 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 2981.044706 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 5621.582558 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4687.071308 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.338221 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.data 0.134481 # Average percentage of cache occupancy
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-system.l2c.tags.age_task_id_blocks_1022::3 415 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4 8111 # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1023::4 247 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2991 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 5625 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 40782 # Occupied blocks per task id
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-system.l2c.WritebackDirty_hits::total 3012753 # number of WritebackDirty hits
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-system.l2c.WritebackClean_hits::total 2 # number of WritebackClean hits
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-system.l2c.SCUpgradeReq_misses::cpu0.data 13748 # number of SCUpgradeReq misses
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system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174621.405067 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 153988.715131 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170383.753615 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111111.940299 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136186.402184 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138777.173583 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165411.940842 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143086.795385 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155119.729441 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167809.080387 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111111.940299 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 139496.185978 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 145167.281609 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 59609 # Transaction distribution
-system.membus.trans_dist::ReadResp 1087641 # Transaction distribution
-system.membus.trans_dist::WriteReq 38144 # Transaction distribution
-system.membus.trans_dist::WriteResp 38144 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1427135 # Transaction distribution
-system.membus.trans_dist::CleanEvict 277667 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 445891 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 321137 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
+system.membus.trans_dist::ReadReq 59885 # Transaction distribution
+system.membus.trans_dist::ReadResp 959045 # Transaction distribution
+system.membus.trans_dist::WriteReq 38450 # Transaction distribution
+system.membus.trans_dist::WriteResp 38450 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1308388 # Transaction distribution
+system.membus.trans_dist::CleanEvict 245549 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 443766 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 303375 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 24 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
-system.membus.trans_dist::ReadExReq 156981 # Transaction distribution
-system.membus.trans_dist::ReadExResp 142959 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1028032 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 712467 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122696 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq 149775 # Transaction distribution
+system.membus.trans_dist::ReadExResp 134703 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 899160 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 692677 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122588 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24870 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5347246 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 5494888 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237811 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 237811 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5732699 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155826 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26142 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4883481 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 5032287 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238261 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 238261 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5270548 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155695 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49740 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159196224 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 159402346 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7246976 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7246976 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 166649322 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 621233 # Total snoops (count)
-system.membus.snoop_fanout::samples 4467120 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52284 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142819456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 143027991 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7275456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7275456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 150303447 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 603397 # Total snoops (count)
+system.membus.snoop_fanout::samples 4141095 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 4467120 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4141095 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 4467120 # Request fanout histogram
-system.membus.reqLayer0.occupancy 98530997 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 4141095 # Request fanout histogram
+system.membus.reqLayer0.occupancy 97863497 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 20867984 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 22133983 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 9912231208 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 9091243819 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 6259994034 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 5543319054 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 45597361 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 45567476 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
@@ -3908,58 +3910,58 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 12663754 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 6874752 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 2026071 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 169438 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 153466 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 15972 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 59611 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4844529 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38144 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38144 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 4439938 # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests 12058125 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 6550145 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 1934123 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 145409 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 132628 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 12781 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 59887 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 4587364 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38450 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38450 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 4172911 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 2880952 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 762470 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 404798 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1167268 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 311901 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 311901 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 4792157 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 968815 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 862087 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10699681 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7828066 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 18527747 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 272166853 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 192849765 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 465016618 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 3356905 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 9121086 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.343228 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.478461 # Request fanout histogram
+system.toL2Bus.trans_dist::CleanEvict 2698369 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 743738 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 384448 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1128186 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 137 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 137 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 300120 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 300120 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 4534724 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 956843 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 850115 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9259077 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8380798 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 17639875 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229804683 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 209683148 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 439487831 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 3155812 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 8637402 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.346247 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.478873 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 6006442 65.85% 65.85% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 3098672 33.97% 99.82% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 15972 0.18% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 5659510 65.52% 65.52% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 2965111 34.33% 99.85% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 12781 0.15% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 9121086 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 9875342461 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 8637402 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 9396796139 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2628126 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2598429 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4863215068 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4205091357 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 3891669395 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4119595686 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 5261 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 5119 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 13576 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 13991 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index a4f8f5e6d..0db15e453 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -1,139 +1,139 @@
---------- Begin Simulation Statistics ----------
sim_seconds 51.327140 # Number of seconds simulated
-sim_ticks 51327140089000 # Number of ticks simulated
-final_tick 51327140089000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 51327139864000 # Number of ticks simulated
+final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 210997 # Simulator instruction rate (inst/s)
-host_op_rate 247928 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12768702843 # Simulator tick rate (ticks/s)
-host_mem_usage 688028 # Number of bytes of host memory used
-host_seconds 4019.76 # Real time elapsed on the host
-sim_insts 848158120 # Number of instructions simulated
-sim_ops 996609834 # Number of ops (including micro ops) simulated
+host_inst_rate 139665 # Simulator instruction rate (inst/s)
+host_op_rate 164109 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8451911555 # Simulator tick rate (ticks/s)
+host_mem_usage 688288 # Number of bytes of host memory used
+host_seconds 6072.84 # Real time elapsed on the host
+sim_insts 848164321 # Number of instructions simulated
+sim_ops 996610207 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 211968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 207872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5637664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 41611720 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 447104 # Number of bytes read from this memory
-system.physmem.bytes_read::total 48116328 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 5637664 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5637664 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 68318336 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 41583048 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 443008 # Number of bytes read from this memory
+system.physmem.bytes_read::total 48132008 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5661728 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5661728 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 68386496 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 68338916 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 3312 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3248 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 104041 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 650196 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6986 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 767783 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1067474 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 68407076 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 3558 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 3383 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 104417 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 649748 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6922 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 768028 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1068539 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1070047 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 4130 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 4050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 109838 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 810716 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8711 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 937444 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 109838 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 109838 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1331037 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1071112 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 4436 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 4218 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
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-system.physmem.bytesReadWrQ 40960 # Total number of bytes read from write queue
-system.physmem.bytesWritten 68336896 # Total number of bytes written to DRAM
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-system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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@@ -159,125 +159,126 @@ system.physmem.wrQLenPdf::11 1 # Wh
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+system.physmem.bytesPerActivate::640-767 9495 2.01% 89.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 7568 1.61% 90.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 6030 1.28% 91.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 37947 8.05% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 471440 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 54191 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 14.158790 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 76.596487 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 54185 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 54136 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 54136 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.723733 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.769647 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 8.988954 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 40635 75.06% 75.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 4496 8.31% 83.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 5195 9.60% 92.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 1325 2.45% 95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 409 0.76% 96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 232 0.43% 96.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 326 0.60% 97.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 142 0.26% 97.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 398 0.74% 98.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 56 0.10% 98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 67 0.12% 98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 319 0.59% 99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 37 0.07% 99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 24 0.04% 99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 111 0.21% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 168 0.31% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 2 0.00% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 3 0.01% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 3 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 2 0.00% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 5 0.01% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 1 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 54191 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 54191 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.723718 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.774638 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 8.948432 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 40576 74.88% 74.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 4593 8.48% 83.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 5177 9.55% 92.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 1373 2.53% 95.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 420 0.78% 96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 248 0.46% 96.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 301 0.56% 97.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 130 0.24% 97.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 393 0.73% 98.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 142 0.26% 98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 38 0.07% 98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 61 0.11% 98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 323 0.60% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 40 0.07% 99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 24 0.04% 99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 111 0.20% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 181 0.33% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 3 0.01% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 3 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 2 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 11 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 5 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 17 0.03% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 54136 # Writes before turning the bus around for reads
-system.physmem.totQLat 15242803686 # Total ticks spent queuing
-system.physmem.totMemAccLat 29626734936 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 3835715000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 19869.57 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 14 0.03% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 3 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 9 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 6 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 54191 # Writes before turning the bus around for reads
+system.physmem.totQLat 15195806089 # Total ticks spent queuing
+system.physmem.totMemAccLat 29582606089 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 3836480000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 19804.36 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 38619.57 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 38554.36 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s
@@ -286,41 +287,41 @@ system.physmem.peakBW 12800.00 # Th
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing
-system.physmem.readRowHits 579803 # Number of row buffer hits during reads
-system.physmem.writeRowHits 783916 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.42 # Row buffer hit rate for writes
-system.physmem.avgGap 27928121.03 # Average gap between requests
+system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing
+system.physmem.readRowHits 579763 # Number of row buffer hits during reads
+system.physmem.writeRowHits 784939 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.44 # Row buffer hit rate for writes
+system.physmem.avgGap 27908228.00 # Average gap between requests
system.physmem.pageHitRate 74.32 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1791077400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 977274375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2938244400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3468841200 # Energy for write commands per rank (pJ)
+system.physmem_0.actEnergy 1800088920 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 982191375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2947417200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3479286960 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1235175473835 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29712796340250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34309586468340 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.449224 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49429866192554 # Time in different power states
+system.physmem_0.actBackEnergy 1235810088180 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29712239669250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34309697958765 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.451396 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49428932348966 # Time in different power states
system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 183347171196 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 184281028534 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 1771020720 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 966330750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3045424200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3450165840 # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy 1763997480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 962498625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3037452600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3446848080 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1235608843410 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29712416191500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34309697193300 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.451381 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49429214230967 # Time in different power states
+system.physmem_1.actBackEnergy 1235330422065 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29712660420750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34309640856480 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.450284 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49429628001327 # Time in different power states
system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 183999255033 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
@@ -344,15 +345,19 @@ system.cf0.dma_read_txs 122 # Nu
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 224297572 # Number of BP lookups
-system.cpu.branchPred.condPredicted 149902957 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 12193787 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 158452721 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 103491021 # Number of BTB hits
+system.cpu.branchPred.lookups 225024609 # Number of BP lookups
+system.cpu.branchPred.condPredicted 149819801 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 12305268 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 158924221 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 98148969 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 65.313502 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 30817326 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 343319 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 61.758345 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 30872234 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 343569 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 6729545 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 4744517 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -383,85 +388,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 949838 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 949838 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15818 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155419 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 436827 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 513011 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 2225.817770 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 14567.134273 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535 509618 99.34% 99.34% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071 1930 0.38% 99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607 987 0.19% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143 197 0.04% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679 149 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751 53 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks 947007 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155482 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore 435407 # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples 511600 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 2285.571736 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 14838.819778 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535 508020 99.30% 99.30% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071 2030 0.40% 99.70% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607 1046 0.20% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143 222 0.04% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679 147 0.03% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751 54 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::458752-524287 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 513011 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 485512 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23036.801356 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 18084.539614 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20755.830536 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535 474265 97.68% 97.68% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071 7843 1.62% 99.30% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607 2427 0.50% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143 166 0.03% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679 551 0.11% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215 105 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751 109 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 485512 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 779669132376 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.722626 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.523315 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1 777439658376 99.71% 99.71% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3 1176099000 0.15% 99.86% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5 488850000 0.06% 99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7 205535000 0.03% 99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9 152105500 0.02% 99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11 121751500 0.02% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13 29187500 0.00% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15 53249500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17 2696000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 779669132376 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 155420 90.76% 90.76% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 15818 9.24% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 171238 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 949838 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 511600 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 486864 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 22927.774491 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 17879.583197 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20925.745088 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535 475438 97.65% 97.65% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071 7837 1.61% 99.26% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607 2530 0.52% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143 265 0.05% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679 545 0.11% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215 113 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751 104 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287 16 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 486864 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 779668807876 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean 0.725507 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev 0.522451 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1 777433889876 99.71% 99.71% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3 1160253500 0.15% 99.86% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5 513477500 0.07% 99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7 201866500 0.03% 99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9 152233500 0.02% 99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11 119773500 0.02% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13 32296000 0.00% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15 52448000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17 2569500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 779668807876 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 155483 90.77% 90.77% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 15816 9.23% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 171299 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 947007 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 949838 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171238 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 947007 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171299 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171238 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 1121076 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171299 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 1118306 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 169331819 # DTB read hits
-system.cpu.dtb.read_misses 674131 # DTB read misses
-system.cpu.dtb.write_hits 147501461 # DTB write hits
-system.cpu.dtb.write_misses 275707 # DTB write misses
+system.cpu.dtb.read_hits 169398877 # DTB read hits
+system.cpu.dtb.read_misses 674798 # DTB read misses
+system.cpu.dtb.write_hits 147332912 # DTB write hits
+system.cpu.dtb.write_misses 272209 # DTB write misses
system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 72020 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 10130 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 72102 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 9776 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 69829 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 170005950 # DTB read accesses
-system.cpu.dtb.write_accesses 147777168 # DTB write accesses
+system.cpu.dtb.perms_faults 69070 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 170073675 # DTB read accesses
+system.cpu.dtb.write_accesses 147605121 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 316833280 # DTB hits
-system.cpu.dtb.misses 949838 # DTB misses
-system.cpu.dtb.accesses 317783118 # DTB accesses
+system.cpu.dtb.hits 316731789 # DTB hits
+system.cpu.dtb.misses 947007 # DTB misses
+system.cpu.dtb.accesses 317678796 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -491,62 +498,65 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 161333 # Table walker walks requested
-system.cpu.itb.walker.walksLong 161333 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 121604 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore 17607 # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples 143726 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean 1329.870726 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev 9693.373994 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767 142645 99.25% 99.25% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535 592 0.41% 99.66% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303 67 0.05% 99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071 93 0.06% 99.77% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607 24 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks 162102 # Table walker walks requested
+system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3 120022 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore 17916 # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples 144186 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean 1142.128917 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 9607.655205 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767 143046 99.21% 99.21% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535 588 0.41% 99.62% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303 94 0.07% 99.68% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071 159 0.11% 99.79% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839 224 0.16% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607 44 0.03% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 143726 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 140644 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 29101.756918 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24236.740283 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 22905.442201 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 137486 97.75% 97.75% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 886 0.63% 98.38% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607 1961 1.39% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143 124 0.09% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679 124 0.09% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215 33 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 140644 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 672291747976 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean 0.944017 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev 0.230261 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 37693655356 5.61% 5.61% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1 634541752620 94.38% 99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2 55651000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3 688000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 672291747976 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 121604 98.84% 98.84% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 123037 # Table walker page sizes translated
+system.cpu.itb.walker.walkWaitTime::229376-262143 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 144186 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 139421 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28788.855337 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 23782.658152 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 24182.866310 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535 136254 97.73% 97.73% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071 690 0.49% 98.22% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607 2101 1.51% 99.73% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143 136 0.10% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679 151 0.11% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215 47 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751 30 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 139421 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 680881393568 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean 0.947864 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev 0.222600 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 35543211356 5.22% 5.22% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1 645294358712 94.77% 99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2 43207500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3 580000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4 36000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 680881393568 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 120022 98.78% 98.78% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1483 1.22% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 121505 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161333 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 161333 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162102 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 162102 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123037 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 123037 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 284370 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 356599136 # ITB inst hits
-system.cpu.itb.inst_misses 161333 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121505 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 121505 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 283607 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 357007788 # ITB inst hits
+system.cpu.itb.inst_misses 162102 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
@@ -555,261 +565,261 @@ system.cpu.itb.flush_tlb 10 # Nu
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 53042 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 52913 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 369633 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 357575 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 356760469 # ITB inst accesses
-system.cpu.itb.hits 356599136 # DTB hits
-system.cpu.itb.misses 161333 # DTB misses
-system.cpu.itb.accesses 356760469 # DTB accesses
-system.cpu.numCycles 1628081885 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 357169890 # ITB inst accesses
+system.cpu.itb.hits 357007788 # DTB hits
+system.cpu.itb.misses 162102 # DTB misses
+system.cpu.itb.accesses 357169890 # DTB accesses
+system.cpu.numCycles 1631144067 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 644023121 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1000825975 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 224297572 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 134308347 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 897356081 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 26042356 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 3815311 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 27434 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 9297529 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1037208 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 977 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 356212596 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 6096332 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 48851 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 1568578839 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.747604 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.149571 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 646909214 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1002667158 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 225024609 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 133765720 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 898024303 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 26265536 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 3811072 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 29306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 8704800 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1028212 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 873 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 356634442 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 6247312 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 47880 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 1571640548 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.747058 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.149321 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 1011708684 64.50% 64.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 213717515 13.62% 78.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 70499052 4.49% 82.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 272653588 17.38% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 1013991405 64.52% 64.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 214266060 13.63% 78.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 70309362 4.47% 82.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 273073721 17.38% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1568578839 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.137768 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.614727 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 523834599 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 552751170 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 433009950 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 49764409 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 9218711 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 33629126 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 3862659 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 1084582874 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 28977480 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 9218711 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 568372766 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 66217937 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 371830406 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 438295981 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 114643038 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1064838864 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 6775021 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 5115924 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 336846 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 638712 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 63601510 # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents 20546 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1012729668 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1640391275 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1259385666 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1476745 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 947192806 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 65536859 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 26910765 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 23247835 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 101832167 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 173436334 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 151069277 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 9864131 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8951241 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1029826470 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 27204925 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1045231227 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3279121 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 60421557 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33664917 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 313528 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1568578839 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.666356 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.920348 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 1571640548 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.137955 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.614702 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 526349627 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 552086440 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 434104674 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 49724049 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 9375758 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 33560071 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 3814526 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 1085977369 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 29430616 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 9375758 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 571292055 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 65924513 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 371563835 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 438965882 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 114518505 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1065686030 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 6908876 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 5086020 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 334343 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 634469 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 63514971 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 20439 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1013378726 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1640198292 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1259502846 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1473679 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 947186300 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 66192423 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 26900223 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 23242764 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 101754926 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 173828486 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 150818351 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 9879664 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 8976205 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1030662331 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 27200654 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1045735608 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3378731 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 61252774 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 34075299 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 309098 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1571640548 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.665378 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.919633 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 921654762 58.76% 58.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 333747896 21.28% 80.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 234544221 14.95% 94.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 72152324 4.60% 99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 6460263 0.41% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 19373 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 924076981 58.80% 58.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 334351644 21.27% 80.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 234725096 14.94% 95.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 72033056 4.58% 99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 6434251 0.41% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 19520 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1568578839 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1571640548 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 57742950 35.03% 35.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 99825 0.06% 35.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 625 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 44231739 26.83% 61.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 62727458 38.06% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 57663018 35.01% 35.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 100158 0.06% 35.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 26751 0.02% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 667 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 44277065 26.88% 61.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 62625013 38.03% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 719843938 68.87% 68.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2535420 0.24% 69.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 122954 0.01% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 380 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 121377 0.01% 69.14% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 720295550 68.88% 68.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2531326 0.24% 69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 122856 0.01% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 375 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 119220 0.01% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 173211987 16.57% 85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 149395124 14.29% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 173477536 16.59% 85.73% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 149188688 14.27% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1045231227 # Type of FU issued
-system.cpu.iq.rate 0.642002 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 164829337 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.157697 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 3824665950 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1116644145 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1027372601 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 2483800 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 950168 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 912054 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1208499896 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1560667 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 4304106 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1045735608 # Type of FU issued
+system.cpu.iq.rate 0.641106 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 164692672 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.157490 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 3828710884 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1118319185 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1027391540 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 2472282 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 938392 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 909608 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1208873256 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1555013 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 4278408 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 13785862 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 14456 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 142604 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 6312817 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 14178366 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 14475 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 143083 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 6061186 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2532139 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1442341 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2527357 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1438792 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 9218711 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 7060342 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 6923682 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1057253447 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 9375758 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 6990377 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 6913711 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1058098003 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 173436334 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 151069277 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 22822922 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 57401 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6792645 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 142604 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3655399 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 5100784 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8756183 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1034064574 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 169319677 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10227871 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 173828486 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 150818351 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 22818732 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 57696 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 6782714 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 143083 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3464744 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 5492402 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8957146 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1034225316 # Number of executed instructions
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+system.cpu.iew.iewExecSquashedInsts 10574140 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 222052 # number of nop insts executed
-system.cpu.iew.exec_refs 316816486 # number of memory reference insts executed
-system.cpu.iew.exec_branches 196206176 # Number of branches executed
-system.cpu.iew.exec_stores 147496809 # Number of stores executed
-system.cpu.iew.exec_rate 0.635143 # Inst execution rate
-system.cpu.iew.wb_sent 1029092840 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1028284655 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 437786008 # num instructions producing a value
-system.cpu.iew.wb_consumers 708231099 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.631593 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.618140 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 51332329 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 26891397 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 8391320 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1556613982 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.640242 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.274821 # Number of insts commited each cycle
+system.cpu.iew.exec_nop 235018 # number of nop insts executed
+system.cpu.iew.exec_refs 316715121 # number of memory reference insts executed
+system.cpu.iew.exec_branches 196182084 # Number of branches executed
+system.cpu.iew.exec_stores 147328228 # Number of stores executed
+system.cpu.iew.exec_rate 0.634049 # Inst execution rate
+system.cpu.iew.wb_sent 1029119140 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1028301148 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 437817967 # num instructions producing a value
+system.cpu.iew.wb_consumers 708345311 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.630417 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.618086 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 51892888 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 26891556 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 8548258 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1559580721 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.639024 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.273898 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 1044975044 67.13% 67.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 287768132 18.49% 85.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 120346121 7.73% 93.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 36551788 2.35% 95.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 28453995 1.83% 97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 14010396 0.90% 98.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 8635881 0.55% 98.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 4170150 0.27% 99.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 11702475 0.75% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 1047836838 67.19% 67.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 288037345 18.47% 85.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 120098323 7.70% 93.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 36644408 2.35% 95.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 28496008 1.83% 97.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 13936779 0.89% 98.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 8648827 0.55% 98.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 4175441 0.27% 99.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 11706752 0.75% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1556613982 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 848158120 # Number of instructions committed
-system.cpu.commit.committedOps 996609834 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 1559580721 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 848164321 # Number of instructions committed
+system.cpu.commit.committedOps 996610207 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 304406931 # Number of memory references committed
-system.cpu.commit.loads 159650471 # Number of loads committed
-system.cpu.commit.membars 6926449 # Number of memory barriers committed
-system.cpu.commit.branches 189300112 # Number of branches committed
-system.cpu.commit.fp_insts 898776 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 915651780 # Number of committed integer instructions.
-system.cpu.commit.function_calls 25280403 # Number of function calls committed.
+system.cpu.commit.refs 304407284 # Number of memory references committed
+system.cpu.commit.loads 159650119 # Number of loads committed
+system.cpu.commit.membars 6926917 # Number of memory barriers committed
+system.cpu.commit.branches 189306416 # Number of branches committed
+system.cpu.commit.fp_insts 898488 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 915651510 # Number of committed integer instructions.
+system.cpu.commit.function_calls 25281717 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 689842559 69.22% 69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 2150231 0.22% 69.43% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 98139 0.01% 69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 689843263 69.22% 69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 2149527 0.22% 69.43% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 98159 0.01% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction
@@ -836,537 +846,537 @@ system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% #
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 159650471 16.02% 85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 144756460 14.52% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 159650119 16.02% 85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 144757165 14.52% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 996609834 # Class of committed instruction
-system.cpu.commit.bw_lim_events 11702475 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 2585312705 # The number of ROB reads
-system.cpu.rob.rob_writes 2107755396 # The number of ROB writes
-system.cpu.timesIdled 8146940 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 59503046 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 101026198411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 848158120 # Number of Instructions Simulated
-system.cpu.committedOps 996609834 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.919550 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.919550 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.520955 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.520955 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1224113620 # number of integer regfile reads
-system.cpu.int_regfile_writes 731133953 # number of integer regfile writes
-system.cpu.fp_regfile_reads 1465257 # number of floating regfile reads
-system.cpu.fp_regfile_writes 785096 # number of floating regfile writes
-system.cpu.cc_regfile_reads 225210240 # number of cc regfile reads
-system.cpu.cc_regfile_writes 225863400 # number of cc regfile writes
-system.cpu.misc_regfile_reads 2555640420 # number of misc regfile reads
-system.cpu.misc_regfile_writes 26930775 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 9682749 # number of replacements
+system.cpu.commit.op_class_0::total 996610207 # Class of committed instruction
+system.cpu.commit.bw_lim_events 11706752 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 2588836198 # The number of ROB reads
+system.cpu.rob.rob_writes 2108972650 # The number of ROB writes
+system.cpu.timesIdled 8176252 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 59503519 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 101023135782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 848164321 # Number of Instructions Simulated
+system.cpu.committedOps 996610207 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.923146 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.923146 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.519981 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.519981 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1223740669 # number of integer regfile reads
+system.cpu.int_regfile_writes 731349757 # number of integer regfile writes
+system.cpu.fp_regfile_reads 1462624 # number of floating regfile reads
+system.cpu.fp_regfile_writes 780384 # number of floating regfile writes
+system.cpu.cc_regfile_reads 225040074 # number of cc regfile reads
+system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes
+system.cpu.misc_regfile_reads 2558050181 # number of misc regfile reads
+system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes
+system.cpu.dcache.tags.replacements 9706309 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 283083620 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9683261 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 29.234327 # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 9706821 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 29.171088 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1236470793 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1236470793 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 147113779 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 147113779 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 128236098 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 128236098 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 377977 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 377977 # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data 323653 # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total 323653 # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3296961 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3296961 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 3691090 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 3691090 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 275349877 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 275349877 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 275727854 # number of overall hits
-system.cpu.dcache.overall_hits::total 275727854 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 9547222 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 9547222 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 11260039 # number of WriteReq misses
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-system.cpu.dcache.SoftPFReq_misses::total 1170114 # number of SoftPFReq misses
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-system.cpu.dcache.LoadLockedReq_misses::total 446138 # number of LoadLockedReq misses
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-system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses
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-system.cpu.dcache.WriteReq_miss_latency::total 444932022751 # number of WriteReq miss cycles
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-system.cpu.dcache.WriteLineReq_miss_latency::total 52262346938 # number of WriteLineReq miss cycles
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-system.cpu.dcache.SoftPFReq_accesses::total 1548091 # number of SoftPFReq accesses(hits+misses)
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-system.cpu.dcache.overall_miss_rate::total 0.073823 # miss rate for overall accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.832048 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39514.252371 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39514.252371 # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42358.745228 # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42358.745228 # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15442.376574 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15442.376574 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47583.333333 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47583.333333 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29458.561569 # average overall miss latency
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.dcache.writebacks::writebacks 7504258 # number of writebacks
-system.cpu.dcache.writebacks::total 7504258 # number of writebacks
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-system.cpu.dcache.overall_mshr_miss_latency::total 186032339390 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191842000 # number of ReadReq MSHR uncacheable cycles
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-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20329.020878 # average SoftPFReq mshr miss latency
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-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14094.862832 # average LoadLockedReq mshr miss latency
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-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184841.137346 # average WriteReq mshr uncacheable latency
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-system.cpu.icache.tags.replacements 15019267 # number of replacements
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171355.053744 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148978.734629 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173199.949549 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173199.949549 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.748093 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.386340 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 50149666 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 25446406 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 2163 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2163 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 50432401 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 25583822 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 1624231 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 23137410 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 8571764 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 15019267 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 2370936 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 43497 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 43503 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1964146 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1964146 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 15020006 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 6501231 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 1333409 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 1226745 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45101659 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29271837 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729068 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1925616 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 77028180 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922840864 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1021731230 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2408256 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6275144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2953255494 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 1860303 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 27780180 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.025443 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.157467 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty 8579850 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 15141033 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 2388844 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 43659 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 43666 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1963403 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1963403 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 15141775 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 6525421 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq 1333524 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp 1226860 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45466959 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29342845 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 722067 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1919121 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 77450992 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1938426848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023681310 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2369528 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6237568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2970715254 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 1868325 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 27924144 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.025024 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.156198 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 27073367 97.46% 97.46% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 706813 2.54% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 27225372 97.50% 97.50% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 698772 2.50% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 27780180 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 48093772959 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 27924144 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 48365955497 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1496382 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 1497386 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 22560257433 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 22743143976 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 13373462829 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 13408724401 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 428394234 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 426213261 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 1141603196 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40297 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40297 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40299 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40299 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
@@ -1590,11 +1600,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353740 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
@@ -1609,12 +1619,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 41874500 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7492176 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 41885000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
@@ -1626,83 +1636,83 @@ system.iobus.reqLayer4.occupancy 9500 # La
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 25162500 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 25104500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 36499500 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 36501000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 567349755 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 567373998 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 147716000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115457 # number of replacements
-system.iocache.tags.tagsinuse 10.423127 # Cycle average of tags in use
+system.iocache.tags.replacements 115459 # number of replacements
+system.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13098803375000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.544202 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.878925 # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle 13098783117000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.878929 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.651445 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039641 # Number of tag accesses
-system.iocache.tags.data_accesses 1039641 # Number of data accesses
+system.iocache.tags.tag_accesses 1039659 # Number of tag accesses
+system.iocache.tags.data_accesses 1039659 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8852 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8854 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8812 # number of overall misses
-system.iocache.overall_misses::total 8852 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1683110232 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1688179732 # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide 8814 # number of overall misses
+system.iocache.overall_misses::total 8854 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1678338975 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1683410975 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 13415109023 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 13415109023 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 1683110232 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 1688530732 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 1683110232 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 1688530732 # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 13416126023 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 13416126023 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet 5423000 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 1678338975 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 1683761975 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet 5423000 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 1678338975 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 1683761975 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
@@ -1716,55 +1726,55 @@ system.iocache.demand_miss_rate::total 1 # mi
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 191002.068997 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 190776.328625 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 190417.401293 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 190194.438482 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125769.791335 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 125769.791335 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 190751.325350 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 190751.325350 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 34444 # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125779.325949 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 125779.325949 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135575 # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 190169.638017 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135575 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 190417.401293 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 190169.638017 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 34291 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 3518 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 9.824301 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 9.747300 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide 8814 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 8851 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 8814 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 8854 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1242510232 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1245729732 # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide 8814 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 8854 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3222000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237638975 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 1240860975 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076836456 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 8076836456 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 1242510232 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 1245930732 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 1242510232 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 1245930732 # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8077839572 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 8077839572 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet 3423000 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 1237638975 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 1241061975 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet 3423000 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 1237638975 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1241061975 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
@@ -1778,72 +1788,72 @@ system.iocache.demand_mshr_miss_rate::total 1 #
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141002.068997 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 140776.328625 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87081.081081 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140417.401293 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 140194.438482 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75722.234831 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75722.234831 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75731.639278 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75731.639278 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 140417.401293 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 140169.638017 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 54972 # Transaction distribution
-system.membus.trans_dist::ReadResp 409202 # Transaction distribution
+system.membus.trans_dist::ReadResp 410008 # Transaction distribution
system.membus.trans_dist::WriteReq 33696 # Transaction distribution
system.membus.trans_dist::WriteResp 33696 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1067474 # Transaction distribution
-system.membus.trans_dist::CleanEvict 191385 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 34855 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1068539 # Transaction distribution
+system.membus.trans_dist::CleanEvict 192763 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 34977 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
-system.membus.trans_dist::ReadExReq 394790 # Transaction distribution
-system.membus.trans_dist::ReadExResp 394790 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 354230 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 604321 # Transaction distribution
+system.membus.trans_dist::ReadExReq 394295 # Transaction distribution
+system.membus.trans_dist::ReadExResp 394295 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 355036 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 605480 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3203313 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3332933 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237959 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 237959 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 3570892 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3207653 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3337273 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237899 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 237899 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 3575172 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109183820 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109353790 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271424 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7271424 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 116625214 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 2530 # Total snoops (count)
-system.membus.snoop_fanout::samples 2735759 # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109271756 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109441726 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7267328 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7267328 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 116709054 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 2596 # Total snoops (count)
+system.membus.snoop_fanout::samples 2739791 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2735759 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2739791 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2735759 # Request fanout histogram
-system.membus.reqLayer0.occupancy 103971500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2739791 # Request fanout histogram
+system.membus.reqLayer0.occupancy 103925500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5468000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 5584000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 7155774176 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 7165123486 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 4068025704 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 4069623687 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 44802062 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
index 8afd4d6b4..665a239cf 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 47.460623 # Nu
sim_ticks 47460623015500 # Number of ticks simulated
final_tick 47460623015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1174285 # Simulator instruction rate (inst/s)
-host_op_rate 1381255 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 63679173545 # Simulator tick rate (ticks/s)
-host_mem_usage 746696 # Number of bytes of host memory used
-host_seconds 745.31 # Real time elapsed on the host
+host_inst_rate 731783 # Simulator instruction rate (inst/s)
+host_op_rate 860761 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39683148028 # Simulator tick rate (ticks/s)
+host_mem_usage 744736 # Number of bytes of host memory used
+host_seconds 1195.99 # Real time elapsed on the host
sim_insts 875204273 # Number of instructions simulated
sim_ops 1029460892 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -1151,6 +1151,7 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu0.l2cache.unused_prefetches 39383 # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks 1473434 # number of writebacks
system.cpu0.l2cache.writebacks::total 1473434 # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5831 # number of ReadExReq MSHR hits
@@ -2133,6 +2134,7 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu1.l2cache.unused_prefetches 39620 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 1103180 # number of writebacks
system.cpu1.l2cache.writebacks::total 1103180 # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6962 # number of ReadExReq MSHR hits
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index 90977c91b..eb3e33d10 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -1,194 +1,194 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 51.278323 # Number of seconds simulated
-sim_ticks 51278322908000 # Number of ticks simulated
-final_tick 51278322908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.278333 # Number of seconds simulated
+sim_ticks 51278333141000 # Number of ticks simulated
+final_tick 51278333141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 391318 # Simulator instruction rate (inst/s)
-host_op_rate 459835 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 23610419083 # Simulator tick rate (ticks/s)
-host_mem_usage 689044 # Number of bytes of host memory used
-host_seconds 2171.85 # Real time elapsed on the host
-sim_insts 849885052 # Number of instructions simulated
-sim_ops 998692344 # Number of ops (including micro ops) simulated
+host_inst_rate 303802 # Simulator instruction rate (inst/s)
+host_op_rate 357005 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 18317890976 # Simulator tick rate (ticks/s)
+host_mem_usage 688280 # Number of bytes of host memory used
+host_seconds 2799.36 # Real time elapsed on the host
+sim_insts 850450745 # Number of instructions simulated
+sim_ops 999383448 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 79744 # Number of bytes read from this memory
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-system.physmem.bytes_read::cpu0.data 18551240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 21056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 18624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 450240 # Number of bytes read from this memory
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-system.physmem.bytes_read::cpu2.dtb.walker 31808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker 29568 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 1509568 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 6342336 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker 66432 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.itb.walker 61184 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 1749760 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 11675328 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 416192 # Number of bytes read from this memory
-system.physmem.bytes_read::total 48647868 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 2584308 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 450240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 1509568 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 1749760 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 6293876 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 68210816 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 68231396 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1246 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1267 # Number of read requests responded to by this memory
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-system.physmem.num_reads::cpu1.itb.walker 291 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 7035 # Number of read requests responded to by this memory
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-system.physmem.num_reads::cpu2.itb.walker 462 # Number of read requests responded to by this memory
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-system.physmem.num_reads::cpu2.data 99099 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker 1038 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.itb.walker 956 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 27340 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 182427 # Number of read requests responded to by this memory
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-system.physmem.num_reads::total 800543 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1065794 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1068367 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 1555 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 1581 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 50398 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 361775 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 411 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 363 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 8780 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 97105 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 620 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker 577 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 29439 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 123685 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker 1296 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.itb.walker 1193 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 34123 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 227685 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8116 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 948702 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 50398 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 8780 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 29439 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 34123 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 122740 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1330208 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1072901 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 1600 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu3.dtb.walker 1380 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.itb.walker 1036 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::total 956402 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 49805 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::total 119971 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1335866 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1330609 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1330208 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 1555 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 1581 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 50398 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 362177 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 411 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 363 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 8780 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 97105 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 620 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker 577 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 29439 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 123685 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker 1296 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.itb.walker 1193 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 34123 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 227685 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8116 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2279311 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 425112 # Number of read requests accepted
-system.physmem.writeReqs 454625 # Number of write requests accepted
-system.physmem.readBursts 425112 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 454625 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 27178752 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 28416 # Total number of bytes read from write queue
-system.physmem.bytesWritten 29094208 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 27207168 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 29096000 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 444 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total 1336268 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1335866 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 1600 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 1679 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 49805 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu1.itb.walker 495 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 8799 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 97402 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 671 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker 584 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 28510 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 130306 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker 1380 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.itb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 32857 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 227336 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 7773 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2292669 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 428538 # Number of read requests accepted
+system.physmem.writeReqs 456847 # Number of write requests accepted
+system.physmem.readBursts 428538 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 456847 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 27408320 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue
+system.physmem.bytesWritten 29236416 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 27426432 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 29238208 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 27658 # Per bank write bursts
-system.physmem.perBankRdBursts::1 29828 # Per bank write bursts
-system.physmem.perBankRdBursts::2 28706 # Per bank write bursts
-system.physmem.perBankRdBursts::3 26688 # Per bank write bursts
-system.physmem.perBankRdBursts::4 26134 # Per bank write bursts
-system.physmem.perBankRdBursts::5 30288 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24980 # Per bank write bursts
-system.physmem.perBankRdBursts::7 26114 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23639 # Per bank write bursts
-system.physmem.perBankRdBursts::9 28679 # Per bank write bursts
-system.physmem.perBankRdBursts::10 26865 # Per bank write bursts
-system.physmem.perBankRdBursts::11 27723 # Per bank write bursts
-system.physmem.perBankRdBursts::12 26411 # Per bank write bursts
-system.physmem.perBankRdBursts::13 25648 # Per bank write bursts
-system.physmem.perBankRdBursts::14 22535 # Per bank write bursts
-system.physmem.perBankRdBursts::15 22772 # Per bank write bursts
-system.physmem.perBankWrBursts::0 28961 # Per bank write bursts
-system.physmem.perBankWrBursts::1 29340 # Per bank write bursts
-system.physmem.perBankWrBursts::2 30073 # Per bank write bursts
-system.physmem.perBankWrBursts::3 30333 # Per bank write bursts
-system.physmem.perBankWrBursts::4 28091 # Per bank write bursts
-system.physmem.perBankWrBursts::5 30746 # Per bank write bursts
-system.physmem.perBankWrBursts::6 26981 # Per bank write bursts
-system.physmem.perBankWrBursts::7 28675 # Per bank write bursts
-system.physmem.perBankWrBursts::8 26142 # Per bank write bursts
-system.physmem.perBankWrBursts::9 29950 # Per bank write bursts
-system.physmem.perBankWrBursts::10 27880 # Per bank write bursts
-system.physmem.perBankWrBursts::11 29356 # Per bank write bursts
-system.physmem.perBankWrBursts::12 28075 # Per bank write bursts
-system.physmem.perBankWrBursts::13 28226 # Per bank write bursts
-system.physmem.perBankWrBursts::14 25398 # Per bank write bursts
-system.physmem.perBankWrBursts::15 26370 # Per bank write bursts
+system.physmem.perBankRdBursts::0 26649 # Per bank write bursts
+system.physmem.perBankRdBursts::1 30049 # Per bank write bursts
+system.physmem.perBankRdBursts::2 26532 # Per bank write bursts
+system.physmem.perBankRdBursts::3 25500 # Per bank write bursts
+system.physmem.perBankRdBursts::4 26079 # Per bank write bursts
+system.physmem.perBankRdBursts::5 32966 # Per bank write bursts
+system.physmem.perBankRdBursts::6 25199 # Per bank write bursts
+system.physmem.perBankRdBursts::7 25237 # Per bank write bursts
+system.physmem.perBankRdBursts::8 24838 # Per bank write bursts
+system.physmem.perBankRdBursts::9 28373 # Per bank write bursts
+system.physmem.perBankRdBursts::10 26870 # Per bank write bursts
+system.physmem.perBankRdBursts::11 27983 # Per bank write bursts
+system.physmem.perBankRdBursts::12 26309 # Per bank write bursts
+system.physmem.perBankRdBursts::13 25787 # Per bank write bursts
+system.physmem.perBankRdBursts::14 24479 # Per bank write bursts
+system.physmem.perBankRdBursts::15 25405 # Per bank write bursts
+system.physmem.perBankWrBursts::0 27847 # Per bank write bursts
+system.physmem.perBankWrBursts::1 29934 # Per bank write bursts
+system.physmem.perBankWrBursts::2 27360 # Per bank write bursts
+system.physmem.perBankWrBursts::3 28363 # Per bank write bursts
+system.physmem.perBankWrBursts::4 28817 # Per bank write bursts
+system.physmem.perBankWrBursts::5 32577 # Per bank write bursts
+system.physmem.perBankWrBursts::6 27869 # Per bank write bursts
+system.physmem.perBankWrBursts::7 28879 # Per bank write bursts
+system.physmem.perBankWrBursts::8 27745 # Per bank write bursts
+system.physmem.perBankWrBursts::9 30902 # Per bank write bursts
+system.physmem.perBankWrBursts::10 28100 # Per bank write bursts
+system.physmem.perBankWrBursts::11 29746 # Per bank write bursts
+system.physmem.perBankWrBursts::12 27536 # Per bank write bursts
+system.physmem.perBankWrBursts::13 27471 # Per bank write bursts
+system.physmem.perBankWrBursts::14 26272 # Per bank write bursts
+system.physmem.perBankWrBursts::15 27401 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 27 # Number of times write queue was full causing retry
-system.physmem.totGap 51277322578500 # Total gap between requests
+system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
+system.physmem.totGap 51277332920000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 425112 # Read request sizes (log2)
+system.physmem.readPktSize::6 428538 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 454625 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 320658 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 71523 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 20097 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 8919 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 382 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 348 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 332 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 736 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 454 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 254 # What read queue length does an incoming req see
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+system.physmem.wrPerTurnAround::samples 24743 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 18.462555 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.679981 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 8.466510 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 17 0.07% 0.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 18 0.07% 0.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 7 0.03% 0.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 50 0.20% 0.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 22406 90.55% 90.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 1021 4.13% 95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 245 0.99% 96.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 205 0.83% 96.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 59 0.24% 97.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 45 0.18% 97.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 91 0.37% 97.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 19 0.08% 97.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 158 0.64% 98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 47 0.19% 98.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 11 0.04% 98.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 29 0.12% 98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 119 0.48% 99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 17 0.07% 99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 15 0.06% 99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 48 0.19% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 83 0.34% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.00% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.00% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 2 0.01% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 2 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 2 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 7 0.03% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 4 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 2 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 24743 # Writes before turning the bus around for reads
+system.physmem.totQLat 8299174160 # Total ticks spent queuing
+system.physmem.totMemAccLat 16328955410 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2141275000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 19379.05 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 38374.66 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 38129.05 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.53 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.53 # Average system read bandwidth in MiByte/s
@@ -353,40 +354,40 @@ system.physmem.busUtil 0.01 # Da
system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 6.41 # Average write queue length when enqueuing
-system.physmem.readRowHits 310449 # Number of row buffer hits during reads
-system.physmem.writeRowHits 304265 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 73.10 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 66.93 # Row buffer hit rate for writes
-system.physmem.avgGap 58287104.64 # Average gap between requests
-system.physmem.pageHitRate 69.91 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1040339160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 565834500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1719073200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 1511136000 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3310423515360 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1181162631510 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 30835777461750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 35332199991480 # Total energy per rank (pJ)
-system.physmem_0.averagePower 665.141706 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 48866215203670 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1692445560000 # Time in different power states
+system.physmem.avgWrQLen 5.79 # Average write queue length when enqueuing
+system.physmem.readRowHits 313353 # Number of row buffer hits during reads
+system.physmem.writeRowHits 304366 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 73.17 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 66.62 # Row buffer hit rate for writes
+system.physmem.avgGap 57915294.39 # Average gap between requests
+system.physmem.pageHitRate 69.79 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 1033164720 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 562076625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1701999000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 1501066080 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3310356385440 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1179927426690 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 30447593029500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34942675148055 # Total energy per rank (pJ)
+system.physmem_0.averagePower 665.942257 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 48866965519857 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1692411240000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 125694518580 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 123966214393 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 959651280 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 522080625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1593267000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 1434652560 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3310423515360 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1174137422265 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29654012520750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34143083109840 # Total energy per rank (pJ)
-system.physmem_1.averagePower 667.640404 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 48876586216946 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1692445560000 # Time in different power states
+system.physmem_1.actEnergy 988023960 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 537516375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1638335400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 1459121040 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3310356385440 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1177251222825 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29686423716000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34178654321040 # Total energy per rank (pJ)
+system.physmem_1.averagePower 667.571395 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 48870902891583 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1692411240000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 115306042554 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 120022768167 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
@@ -446,47 +447,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 90589 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 90589 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 90589 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 90589 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 90589 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 384648913196 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 1.541506 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -208289583554 -54.15% -54.15% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 592938496750 154.15% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 384648913196 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 66121 84.68% 84.68% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 11962 15.32% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 78083 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90589 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 90231 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 90231 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 90231 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 90231 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 90231 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 388941119992 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.527073 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -205000507008 -52.71% -52.71% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 593941627000 152.71% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 388941119992 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 65649 84.67% 84.67% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 11889 15.33% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 77538 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90231 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90589 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78083 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90231 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77538 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78083 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 168672 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77538 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 167769 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 64905943 # DTB read hits
-system.cpu0.dtb.read_misses 68632 # DTB read misses
-system.cpu0.dtb.write_hits 59387283 # DTB write hits
-system.cpu0.dtb.write_misses 21957 # DTB write misses
-system.cpu0.dtb.flush_tlb 1195 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 64940650 # DTB read hits
+system.cpu0.dtb.read_misses 68234 # DTB read misses
+system.cpu0.dtb.write_hits 59349095 # DTB write hits
+system.cpu0.dtb.write_misses 21997 # DTB write misses
+system.cpu0.dtb.flush_tlb 1197 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 16181 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 404 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 41245 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid 16324 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 40980 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 2795 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 2794 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 7554 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 64974575 # DTB read accesses
-system.cpu0.dtb.write_accesses 59409240 # DTB write accesses
+system.cpu0.dtb.perms_faults 7599 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 65008884 # DTB read accesses
+system.cpu0.dtb.write_accesses 59371092 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 124293226 # DTB hits
-system.cpu0.dtb.misses 90589 # DTB misses
-system.cpu0.dtb.accesses 124383815 # DTB accesses
+system.cpu0.dtb.hits 124289745 # DTB hits
+system.cpu0.dtb.misses 90231 # DTB misses
+system.cpu0.dtb.accesses 124379976 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -516,699 +517,699 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 53629 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 53629 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 53629 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 53629 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 53629 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 384648913196 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 1.541605 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -208327943554 -54.16% -54.16% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 592976856750 154.16% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 384648913196 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 46675 94.93% 94.93% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 2493 5.07% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 49168 # Table walker page sizes translated
+system.cpu0.itb.walker.walks 52885 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 52885 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 52885 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 52885 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 52885 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 388941119992 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 1.527164 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -205035740008 -52.72% -52.72% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 593976860000 152.72% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 388941119992 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 45865 94.85% 94.85% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 2491 5.15% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 48356 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53629 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53629 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52885 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 52885 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49168 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49168 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 102797 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 346758065 # ITB inst hits
-system.cpu0.itb.inst_misses 53629 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48356 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48356 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 101241 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 347148099 # ITB inst hits
+system.cpu0.itb.inst_misses 52885 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 1195 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 1197 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 16181 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 404 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 28950 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 16324 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 28527 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 346811694 # ITB inst accesses
-system.cpu0.itb.hits 346758065 # DTB hits
-system.cpu0.itb.misses 53629 # DTB misses
-system.cpu0.itb.accesses 346811694 # DTB accesses
-system.cpu0.numCycles 418356627 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 347200984 # ITB inst accesses
+system.cpu0.itb.hits 347148099 # DTB hits
+system.cpu0.itb.misses 52885 # DTB misses
+system.cpu0.itb.accesses 347200984 # DTB accesses
+system.cpu0.numCycles 418851699 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 16523 # number of quiesce instructions executed
-system.cpu0.committedInsts 346615446 # Number of instructions committed
-system.cpu0.committedOps 407794224 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 374692963 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 359996 # Number of float alu accesses
-system.cpu0.num_func_calls 21015198 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 52493274 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 374692963 # number of integer instructions
-system.cpu0.num_fp_insts 359996 # number of float instructions
-system.cpu0.num_int_register_reads 546961774 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 297330498 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 576159 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 315016 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 89964300 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 89735253 # number of times the CC registers were written
-system.cpu0.num_mem_refs 124366560 # number of memory refs
-system.cpu0.num_load_insts 64963335 # Number of load instructions
-system.cpu0.num_store_insts 59403225 # Number of store instructions
-system.cpu0.num_idle_cycles 408478241.491071 # Number of idle cycles
-system.cpu0.num_busy_cycles 9878385.508929 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.023612 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.976388 # Percentage of idle cycles
-system.cpu0.Branches 77357953 # Number of branches fetched
+system.cpu0.kern.inst.quiesce 16522 # number of quiesce instructions executed
+system.cpu0.committedInsts 347002044 # Number of instructions committed
+system.cpu0.committedOps 408295196 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 375110913 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 357489 # Number of float alu accesses
+system.cpu0.num_func_calls 20952666 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 52632755 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 375110913 # number of integer instructions
+system.cpu0.num_fp_insts 357489 # number of float instructions
+system.cpu0.num_int_register_reads 548276980 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 297820090 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 571479 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 314936 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 90391371 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 90175878 # number of times the CC registers were written
+system.cpu0.num_mem_refs 124362861 # number of memory refs
+system.cpu0.num_load_insts 64997668 # Number of load instructions
+system.cpu0.num_store_insts 59365193 # Number of store instructions
+system.cpu0.num_idle_cycles 408653989.262248 # Number of idle cycles
+system.cpu0.num_busy_cycles 10197709.737752 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.024347 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.975653 # Percentage of idle cycles
+system.cpu0.Branches 77385391 # Number of branches fetched
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
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-system.cpu0.op_class::IntMult 882754 0.22% 69.50% # Class of executed instruction
-system.cpu0.op_class::IntDiv 40502 0.01% 69.51% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
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-system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
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-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
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-system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 48552 0.01% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::MemRead 64963335 15.92% 85.44% # Class of executed instruction
-system.cpu0.op_class::MemWrite 59403225 14.56% 100.00% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 408029136 # Class of executed instruction
-system.cpu0.dcache.tags.replacements 9683863 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.999715 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 293338565 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 9684375 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 30.289881 # Average number of references to valid blocks.
+system.cpu0.op_class::total 408532732 # Class of executed instruction
+system.cpu0.dcache.tags.replacements 9687552 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.999716 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 293952506 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 9688064 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 30.341718 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.042783 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 6.501939 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.121621 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data 4.333371 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968834 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.012699 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010003 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data 0.008464 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.138446 # Average occupied blocks per requestor
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+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970974 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id
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-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
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system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu0.dcache.ReadReq_hits::total 150838230 # number of ReadReq hits
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-system.cpu0.dcache.SoftPFReq_hits::total 395348 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 127860 # number of WriteLineReq hits
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-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 563586 # number of LoadLockedReq hits
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-system.cpu0.dcache.LoadLockedReq_hits::total 3400504 # number of LoadLockedReq hits
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-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 179586 # number of LoadLockedReq misses
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-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 806972 # number of WriteLineReq accesses(hits+misses)
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-system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 381192 # number of WriteLineReq accesses(hits+misses)
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-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.841556 # miss rate for WriteLineReq accesses
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-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.160503 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095081 # miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.tags.data_accesses 1245495121 # Number of data accesses
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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13321.581304 # average LoadLockedReq miss latency
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-system.cpu0.dcache.overall_avg_miss_latency::total 18007.249075 # average overall miss latency
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
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+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.089243 # mshr miss rate for overall accesses
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+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12815.239067 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12739.395425 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12529.567356 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12737.403425 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12815.239067 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12739.395425 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12529.567356 # average overall mshr miss latency
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+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12815.239067 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12739.395425 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -1239,68 +1240,70 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 31825 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 31825 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4653 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23077 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 31819 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 1.099972 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 196.211646 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095 31818 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks 32812 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 32812 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4690 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 24112 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 32807 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 1.066845 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 193.234552 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095 32806 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 31819 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 27736 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 24896.776752 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21479.770946 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15609.675218 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 27586 99.46% 99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.01% 99.47% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 129 0.47% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 2 0.01% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 11 0.04% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 27736 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 3125373784 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.674826 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.468440 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1016289500 32.52% 32.52% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 2109084284 67.48% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 3125373784 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 23077 83.22% 83.22% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 4653 16.78% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 27730 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31825 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total 32807 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 28807 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 25324.695387 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21900.388938 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15981.091084 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767 18461 64.09% 64.09% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535 10165 35.29% 99.37% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839 148 0.51% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607 13 0.05% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375 1 0.00% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143 1 0.00% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911 7 0.02% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 28807 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 2784865428 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.637616 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.480689 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1009190500 36.24% 36.24% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 1775674928 63.76% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 2784865428 # Table walker pending requests distribution
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+system.cpu1.dtb.walker.walkPageSizes::2M 4690 16.28% 100.00% # Table walker page sizes translated
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+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 32812 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31825 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27730 # Table walker requests started/completed, data/inst
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system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27730 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 59555 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 28802 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 61614 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 20322566 # DTB read hits
-system.cpu1.dtb.read_misses 24426 # DTB read misses
-system.cpu1.dtb.write_hits 18362474 # DTB write hits
-system.cpu1.dtb.write_misses 7399 # DTB write misses
-system.cpu1.dtb.flush_tlb 1186 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 20290778 # DTB read hits
+system.cpu1.dtb.read_misses 25288 # DTB read misses
+system.cpu1.dtb.write_hits 18371397 # DTB write hits
+system.cpu1.dtb.write_misses 7524 # DTB write misses
+system.cpu1.dtb.flush_tlb 1188 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 5702 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 134 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 18006 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 5447 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 18352 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 961 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 929 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 2721 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 20346992 # DTB read accesses
-system.cpu1.dtb.write_accesses 18369873 # DTB write accesses
+system.cpu1.dtb.perms_faults 2632 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 20316066 # DTB read accesses
+system.cpu1.dtb.write_accesses 18378921 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 38685040 # DTB hits
-system.cpu1.dtb.misses 31825 # DTB misses
-system.cpu1.dtb.accesses 38716865 # DTB accesses
+system.cpu1.dtb.hits 38662175 # DTB hits
+system.cpu1.dtb.misses 32812 # DTB misses
+system.cpu1.dtb.accesses 38694987 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1330,133 +1333,139 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 20346 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 20346 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 938 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17905 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 20346 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 20346 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 20346 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 18843 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 28149.073927 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24906.041063 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 17543.804263 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767 9517 50.51% 50.51% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535 9170 48.67% 99.17% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839 113 0.60% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607 25 0.13% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911 7 0.04% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447 2 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks 20715 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 20715 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 943 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 18376 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 20715 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 20715 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 20715 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 19319 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 28783.140949 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 25411.076231 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 19382.499659 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767 9731 50.37% 50.37% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535 9374 48.52% 98.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071 1 0.01% 98.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839 168 0.87% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607 22 0.11% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.05% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 18843 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 19319 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 17905 95.02% 95.02% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 938 4.98% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 18843 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 18376 95.12% 95.12% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 943 4.88% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 19319 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20346 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20346 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20715 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20715 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18843 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18843 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 39189 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 108575555 # ITB inst hits
-system.cpu1.itb.inst_misses 20346 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 19319 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 19319 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 40034 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 108288078 # ITB inst hits
+system.cpu1.itb.inst_misses 20715 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 1186 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 1188 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 5702 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 134 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 13443 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 5447 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 13933 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 108595901 # ITB inst accesses
-system.cpu1.itb.hits 108575555 # DTB hits
-system.cpu1.itb.misses 20346 # DTB misses
-system.cpu1.itb.accesses 108595901 # DTB accesses
-system.cpu1.numCycles 1186099317 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 108308793 # ITB inst accesses
+system.cpu1.itb.hits 108288078 # DTB hits
+system.cpu1.itb.misses 20715 # DTB misses
+system.cpu1.itb.accesses 108308793 # DTB accesses
+system.cpu1.numCycles 1188105502 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.committedInsts 108493989 # Number of instructions committed
-system.cpu1.committedOps 127332484 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 116990571 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 112697 # Number of float alu accesses
-system.cpu1.num_func_calls 6392203 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 16488906 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 116990571 # number of integer instructions
-system.cpu1.num_fp_insts 112697 # number of float instructions
-system.cpu1.num_int_register_reads 169322857 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 92877962 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 186200 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 85320 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 28186380 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 28117162 # number of times the CC registers were written
-system.cpu1.num_mem_refs 38682469 # number of memory refs
-system.cpu1.num_load_insts 20321860 # Number of load instructions
-system.cpu1.num_store_insts 18360609 # Number of store instructions
-system.cpu1.num_idle_cycles 1161291203.919647 # Number of idle cycles
-system.cpu1.num_busy_cycles 24808113.080353 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.020916 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.979084 # Percentage of idle cycles
-system.cpu1.Branches 24140854 # Number of branches fetched
+system.cpu1.committedInsts 108209898 # Number of instructions committed
+system.cpu1.committedOps 126974949 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 116708707 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 113927 # Number of float alu accesses
+system.cpu1.num_func_calls 6429899 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 16402371 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 116708707 # number of integer instructions
+system.cpu1.num_fp_insts 113927 # number of float instructions
+system.cpu1.num_int_register_reads 168563743 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 92548799 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 187994 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 86044 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 27990654 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 27915757 # number of times the CC registers were written
+system.cpu1.num_mem_refs 38659204 # number of memory refs
+system.cpu1.num_load_insts 20289811 # Number of load instructions
+system.cpu1.num_store_insts 18369393 # Number of store instructions
+system.cpu1.num_idle_cycles 1163060687.092743 # Number of idle cycles
+system.cpu1.num_busy_cycles 25044814.907257 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.021080 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.978920 # Percentage of idle cycles
+system.cpu1.Branches 24096387 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 88426718 69.40% 69.40% # Class of executed instruction
-system.cpu1.op_class::IntMult 282557 0.22% 69.62% # Class of executed instruction
-system.cpu1.op_class::IntDiv 11066 0.01% 69.63% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.63% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 11198 0.01% 69.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.64% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.64% # Class of executed instruction
-system.cpu1.op_class::MemRead 20321860 15.95% 85.59% # Class of executed instruction
-system.cpu1.op_class::MemWrite 18360609 14.41% 100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 88104313 69.34% 69.34% # Class of executed instruction
+system.cpu1.op_class::IntMult 267805 0.21% 69.56% # Class of executed instruction
+system.cpu1.op_class::IntDiv 10742 0.01% 69.56% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.56% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 11023 0.01% 69.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction
+system.cpu1.op_class::MemRead 20289811 15.97% 85.54% # Class of executed instruction
+system.cpu1.op_class::MemWrite 18369393 14.46% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 127414050 # Class of executed instruction
-system.cpu2.branchPred.lookups 39333191 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 27294641 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 2001884 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 28467796 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 20146403 # Number of BTB hits
+system.cpu1.op_class::total 127053129 # Class of executed instruction
+system.cpu2.branchPred.lookups 39776917 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 27483460 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 2037436 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 28756518 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 19292729 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 70.769100 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 4823620 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 322221 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 67.089934 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 4859404 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 317380 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.indirectLookups 1168446 # Number of indirect predictor lookups.
+system.cpu2.branchPred.indirectHits 802318 # Number of indirect target hits.
+system.cpu2.branchPred.indirectMisses 366128 # Number of indirect misses.
+system.cpu2.branchPredindirectMispredicted 149530 # Number of mispredicted indirect branches.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1486,60 +1495,66 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.dtb.walker.walks 93913 # Table walker walks requested
-system.cpu2.dtb.walker.walksLong 93913 # Table walker walks initiated with long descriptors
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6917 # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29157 # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples 93913 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0 93913 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total 93913 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples 36074 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 25782.752121 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 22543.379913 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 16665.993144 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-65535 35851 99.38% 99.38% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::131072-196607 193 0.54% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::196608-262143 7 0.02% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-327679 7 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::327680-393215 2 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::393216-458751 12 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total 36074 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walks 93967 # Table walker walks requested
+system.cpu2.dtb.walker.walksLong 93967 # Table walker walks initiated with long descriptors
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6944 # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29768 # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples 93967 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0 93967 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total 93967 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples 36712 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 25539.442144 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 22201.127196 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 16823.219049 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-32767 24012 65.41% 65.41% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12449 33.91% 99.32% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-163839 190 0.52% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::163840-196607 24 0.07% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::196608-229375 5 0.01% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::229376-262143 3 0.01% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::262144-294911 13 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::360448-393215 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::393216-425983 6 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::425984-458751 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total 36712 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 2000224000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000224000 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000224000 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K 29157 80.83% 80.83% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::2M 6917 19.17% 100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total 36074 # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93913 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K 29768 81.09% 81.09% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::2M 6944 18.91% 100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total 36712 # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93967 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93913 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36074 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93967 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36712 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36074 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total 129987 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36712 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total 130679 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 28226009 # DTB read hits
-system.cpu2.dtb.read_misses 78415 # DTB read misses
-system.cpu2.dtb.write_hits 24563003 # DTB write hits
-system.cpu2.dtb.write_misses 15498 # DTB write misses
-system.cpu2.dtb.flush_tlb 1186 # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits 28283757 # DTB read hits
+system.cpu2.dtb.read_misses 78317 # DTB read misses
+system.cpu2.dtb.write_hits 24727017 # DTB write hits
+system.cpu2.dtb.write_misses 15650 # DTB write misses
+system.cpu2.dtb.flush_tlb 1188 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid 6329 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid 174 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 21839 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 87 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 2106 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_tlb_mva_asid 6736 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid 178 # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries 22142 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 90 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 2053 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 3581 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 28304424 # DTB read accesses
-system.cpu2.dtb.write_accesses 24578501 # DTB write accesses
+system.cpu2.dtb.perms_faults 3761 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 28362074 # DTB read accesses
+system.cpu2.dtb.write_accesses 24742667 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 52789012 # DTB hits
-system.cpu2.dtb.misses 93913 # DTB misses
-system.cpu2.dtb.accesses 52882925 # DTB accesses
+system.cpu2.dtb.hits 53010774 # DTB hits
+system.cpu2.dtb.misses 93967 # DTB misses
+system.cpu2.dtb.accesses 53104741 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1569,85 +1584,125 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.walker.walks 26523 # Table walker walks requested
-system.cpu2.itb.walker.walksLong 26523 # Table walker walks initiated with long descriptors
-system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1844 # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22169 # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples 26523 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0 26523 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total 26523 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples 24013 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 29387.415150 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 26253.368545 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 17691.333892 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-32767 11731 48.85% 48.85% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-65535 12005 49.99% 98.85% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::65536-98303 1 0.00% 98.85% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::131072-163839 207 0.86% 99.71% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::163840-196607 44 0.18% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::229376-262143 5 0.02% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::262144-294911 11 0.05% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::294912-327679 4 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total 24013 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walks 27720 # Table walker walks requested
+system.cpu2.itb.walker.walksLong 27720 # Table walker walks initiated with long descriptors
+system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1832 # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksLongTerminationLevel::Level3 23079 # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples 27720 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0 27720 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total 27720 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples 24911 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 29141.122396 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 25972.278022 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 17945.677356 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-32767 12737 51.13% 51.13% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-65535 11873 47.66% 98.79% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.80% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::131072-163839 235 0.94% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::163840-196607 44 0.18% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::229376-262143 2 0.01% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::262144-294911 11 0.04% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total 24911 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K 22169 92.32% 92.32% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::2M 1844 7.68% 100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total 24013 # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K 23079 92.65% 92.65% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::2M 1832 7.35% 100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total 24911 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 26523 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total 26523 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27720 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27720 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24013 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24013 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total 50536 # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits 67723691 # ITB inst hits
-system.cpu2.itb.inst_misses 26523 # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24911 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24911 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total 52631 # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits 67934299 # ITB inst hits
+system.cpu2.itb.inst_misses 27720 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.flush_tlb 1186 # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb 1188 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid 6329 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid 174 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 16138 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid 6736 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid 178 # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries 16373 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 54061 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 46985 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 67750214 # ITB inst accesses
-system.cpu2.itb.hits 67723691 # DTB hits
-system.cpu2.itb.misses 26523 # DTB misses
-system.cpu2.itb.accesses 67750214 # DTB accesses
-system.cpu2.numCycles 6659048617 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 67962019 # ITB inst accesses
+system.cpu2.itb.hits 67934299 # DTB hits
+system.cpu2.itb.misses 27720 # DTB misses
+system.cpu2.itb.accesses 67962019 # DTB accesses
+system.cpu2.numCycles 6665035719 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 144506436 # Number of instructions committed
-system.cpu2.committedOps 169371182 # Number of ops (including micro ops) committed
-system.cpu2.discardedOps 13466455 # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends 1418 # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles 95896546126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi 46.081329 # CPI: cycles per instruction
-system.cpu2.ipc 0.021701 # IPC: instructions per cycle
+system.cpu2.committedInsts 145016271 # Number of instructions committed
+system.cpu2.committedOps 170167286 # Number of ops (including micro ops) committed
+system.cpu2.discardedOps 13691437 # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends 1431 # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles 95890552078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi 45.960606 # CPI: cycles per instruction
+system.cpu2.ipc 0.021758 # IPC: instructions per cycle
+system.cpu2.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
+system.cpu2.op_class_0::IntAlu 117737819 69.19% 69.19% # Class of committed instruction
+system.cpu2.op_class_0::IntMult 373156 0.22% 69.41% # Class of committed instruction
+system.cpu2.op_class_0::IntDiv 14991 0.01% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMisc 14732 0.01% 69.43% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction
+system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction
+system.cpu2.op_class_0::MemRead 27395173 16.10% 85.53% # Class of committed instruction
+system.cpu2.op_class_0::MemWrite 24631415 14.47% 100.00% # Class of committed instruction
+system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
+system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
+system.cpu2.op_class_0::total 170167286 # Class of committed instruction
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.tickCycles 268737972 # Number of cycles that the object actually ticked
-system.cpu2.idleCycles 6390310645 # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups 73239801 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 49591629 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 3277800 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 49581893 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 35671982 # Number of BTB hits
+system.cpu2.tickCycles 269996715 # Number of cycles that the object actually ticked
+system.cpu2.idleCycles 6395039004 # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups 74192352 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 49437452 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 3347278 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 50136785 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 33881997 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 71.945583 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 9593725 # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect 104101 # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct 67.579118 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 9625210 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect 106045 # Number of incorrect RAS predictions.
+system.cpu3.branchPred.indirectLookups 2919697 # Number of indirect predictor lookups.
+system.cpu3.branchPred.indirectHits 1497835 # Number of indirect target hits.
+system.cpu3.branchPred.indirectMisses 1421862 # Number of indirect misses.
+system.cpu3.branchPredindirectMispredicted 235981 # Number of mispredicted indirect branches.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1677,86 +1732,88 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.dtb.walker.walks 505460 # Table walker walks requested
-system.cpu3.dtb.walker.walksLong 505460 # Table walker walks initiated with long descriptors
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8485 # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50148 # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore 317089 # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples 188371 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean 2400.557942 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 14374.756208 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-65535 187128 99.34% 99.34% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-131071 697 0.37% 99.71% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::131072-196607 376 0.20% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::196608-262143 72 0.04% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::262144-327679 52 0.03% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::327680-393215 16 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::393216-458751 17 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::458752-524287 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total 188371 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples 238710 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 23086.443802 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 18810.822067 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 18314.114651 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-65535 233850 97.96% 97.96% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3840 1.61% 99.57% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-196607 732 0.31% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::196608-262143 60 0.03% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::262144-327679 102 0.04% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::327680-393215 74 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::393216-458751 30 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::458752-524287 19 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total 238710 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -29357088016 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean 0.121049 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-3 -29941141016 101.99% 101.99% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-7 322648500 -1.10% 100.89% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-11 112094000 -0.38% 100.51% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-15 67602000 -0.23% 100.28% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-19 26479500 -0.09% 100.19% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-23 15506000 -0.05% 100.14% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-27 14594500 -0.05% 100.09% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-31 20339000 -0.07% 100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::32-35 4463500 -0.02% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::36-39 262500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::40-43 36500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::44-47 11000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::48-51 16000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -29357088016 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K 50148 85.53% 85.53% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::2M 8485 14.47% 100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total 58633 # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 505460 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walks 504531 # Table walker walks requested
+system.cpu3.dtb.walker.walksLong 504531 # Table walker walks initiated with long descriptors
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8579 # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49642 # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore 315573 # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples 188958 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean 2466.701595 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 15451.703294 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-65535 187621 99.29% 99.29% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-131071 761 0.40% 99.70% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::131072-196607 388 0.21% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::196608-262143 66 0.03% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::262144-327679 68 0.04% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::327680-393215 12 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::393216-458751 16 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::458752-524287 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::720896-786431 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total 188958 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples 235670 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 22726.303730 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 18499.636586 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 17978.207208 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-65535 231036 98.03% 98.03% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3674 1.56% 99.59% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-196607 687 0.29% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::196608-262143 78 0.03% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::262144-327679 114 0.05% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::327680-393215 27 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::393216-458751 37 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::524288-589823 12 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total 235670 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -29346850516 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean 0.109432 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-3 -29931174016 101.99% 101.99% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-7 321600000 -1.10% 100.90% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-11 109899000 -0.37% 100.52% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-15 66660000 -0.23% 100.29% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-19 26916000 -0.09% 100.20% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-23 15037500 -0.05% 100.15% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-27 15685000 -0.05% 100.10% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-31 23345000 -0.08% 100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::32-35 4979000 -0.02% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::36-39 163000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::40-43 37500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::44-47 1500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -29346850516 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K 49642 85.26% 85.26% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::2M 8579 14.74% 100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total 58221 # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 504531 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 505460 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58633 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 504531 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58221 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58633 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total 564093 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58221 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total 562752 # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
-system.cpu3.dtb.read_hits 58374270 # DTB read hits
-system.cpu3.dtb.read_misses 343208 # DTB read misses
-system.cpu3.dtb.write_hits 45394406 # DTB write hits
-system.cpu3.dtb.write_misses 162252 # DTB write misses
-system.cpu3.dtb.flush_tlb 1185 # Number of times complete TLB was flushed
+system.cpu3.dtb.read_hits 58858607 # DTB read hits
+system.cpu3.dtb.read_misses 345619 # DTB read misses
+system.cpu3.dtb.write_hits 45337458 # DTB write hits
+system.cpu3.dtb.write_misses 158912 # DTB write misses
+system.cpu3.dtb.flush_tlb 1187 # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu3.dtb.flush_tlb_mva_asid 11285 # Number of times TLB was flushed by MVA & ASID
-system.cpu3.dtb.flush_tlb_asid 309 # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries 30021 # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults 85 # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults 4958 # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_tlb_mva_asid 11014 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dtb.flush_tlb_asid 317 # Number of times TLB was flushed by ASID
+system.cpu3.dtb.flush_entries 30161 # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults 96 # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults 4984 # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults 33059 # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses 58717478 # DTB read accesses
-system.cpu3.dtb.write_accesses 45556658 # DTB write accesses
+system.cpu3.dtb.perms_faults 31824 # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses 59204226 # DTB read accesses
+system.cpu3.dtb.write_accesses 45496370 # DTB write accesses
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu3.dtb.hits 103768676 # DTB hits
-system.cpu3.dtb.misses 505460 # DTB misses
-system.cpu3.dtb.accesses 104274136 # DTB accesses
+system.cpu3.dtb.hits 104196065 # DTB hits
+system.cpu3.dtb.misses 504531 # DTB misses
+system.cpu3.dtb.accesses 104700596 # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1786,391 +1843,391 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.itb.walker.walks 59314 # Table walker walks requested
-system.cpu3.itb.walker.walksLong 59314 # Table walker walks initiated with long descriptors
-system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1821 # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40895 # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore 8206 # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples 51108 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean 1703.676528 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev 11026.142257 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-65535 50913 99.62% 99.62% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-131071 102 0.20% 99.82% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::131072-196607 75 0.15% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::196608-262143 8 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::262144-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::327680-393215 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total 51108 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples 50922 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 29945.907466 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 25308.766579 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 21817.874172 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-32767 25421 49.92% 49.92% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-65535 24387 47.89% 97.81% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::65536-98303 352 0.69% 98.50% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::98304-131071 53 0.10% 98.61% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::131072-163839 469 0.92% 99.53% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::163840-196607 137 0.27% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::196608-229375 21 0.04% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::229376-262143 18 0.04% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::262144-294911 34 0.07% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::294912-327679 8 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::393216-425983 10 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walks 57749 # Table walker walks requested
+system.cpu3.itb.walker.walksLong 57749 # Table walker walks initiated with long descriptors
+system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1869 # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksLongTerminationLevel::Level3 39849 # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore 8061 # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples 49688 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean 1392.157060 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev 9705.040089 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-32767 49238 99.09% 99.09% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-65535 280 0.56% 99.66% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-98303 20 0.04% 99.70% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::98304-131071 53 0.11% 99.80% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::131072-163839 71 0.14% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::163840-196607 11 0.02% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::229376-262143 8 0.02% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total 49688 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples 49779 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 28899.797103 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 24686.192128 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 20239.281965 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-32767 26767 53.77% 53.77% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-65535 22147 44.49% 98.26% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::65536-98303 258 0.52% 98.78% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::98304-131071 22 0.04% 98.82% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::131072-163839 390 0.78% 99.61% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::163840-196607 115 0.23% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::196608-229375 17 0.03% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::262144-294911 35 0.07% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::393216-425983 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total 50922 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -29359762516 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean 0.915313 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::stdev 0.271710 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0 -2440067696 8.31% 8.31% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1 -26959816320 91.83% 100.14% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2 35306500 -0.12% 100.02% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3 3658500 -0.01% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4 936500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::5 210500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::6 9500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -29359762516 # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K 40895 95.74% 95.74% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::2M 1821 4.26% 100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total 42716 # Table walker page sizes translated
+system.cpu3.itb.walker.walkCompletionTime::total 49779 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -29349528016 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean 0.914056 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev 0.275786 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0 -2489826708 8.48% 8.48% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1 -26888510808 91.61% 100.10% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2 25356500 -0.09% 100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3 3132000 -0.01% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4 321000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -29349528016 # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K 39849 95.52% 95.52% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::2M 1869 4.48% 100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total 41718 # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 59314 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total 59314 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 57749 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total 57749 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42716 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42716 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total 102030 # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits 52851082 # ITB inst hits
-system.cpu3.itb.inst_misses 59314 # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 41718 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total 41718 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total 99467 # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits 52942414 # ITB inst hits
+system.cpu3.itb.inst_misses 57749 # ITB inst misses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.itb.flush_tlb 1185 # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb 1187 # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu3.itb.flush_tlb_mva_asid 11285 # Number of times TLB was flushed by MVA & ASID
-system.cpu3.itb.flush_tlb_asid 309 # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries 23077 # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_tlb_mva_asid 11014 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.itb.flush_tlb_asid 317 # Number of times TLB was flushed by ASID
+system.cpu3.itb.flush_entries 23395 # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults 115085 # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults 105407 # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.inst_accesses 52910396 # ITB inst accesses
-system.cpu3.itb.hits 52851082 # DTB hits
-system.cpu3.itb.misses 59314 # DTB misses
-system.cpu3.itb.accesses 52910396 # DTB accesses
-system.cpu3.numCycles 366771262 # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses 53000163 # ITB inst accesses
+system.cpu3.itb.hits 52942414 # DTB hits
+system.cpu3.itb.misses 57749 # DTB misses
+system.cpu3.itb.accesses 53000163 # DTB accesses
+system.cpu3.numCycles 367393110 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 138418640 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 325485816 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 73239801 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 45265707 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 205393679 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 7423141 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles 1497672 # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles 9430 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles 1874 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles 2924706 # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles 99692 # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles 5815 # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines 52718711 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 2024184 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes 23519 # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples 352062887 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.083114 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.330461 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles 140035519 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 329019087 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 74192352 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 45005042 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 204823297 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 7558478 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles 1392210 # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles 11060 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles 2040 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles 2559054 # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles 98792 # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles 5855 # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines 52820449 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 2085044 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes 22116 # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples 352706869 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.090104 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.342261 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 271718451 77.18% 77.18% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 10078354 2.86% 80.04% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 10184487 2.89% 82.93% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 7481893 2.13% 85.06% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 15414285 4.38% 89.44% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 5033705 1.43% 90.87% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 5437919 1.54% 92.41% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 4732299 1.34% 93.76% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 21981494 6.24% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 272076000 77.14% 77.14% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 10117728 2.87% 80.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 10161980 2.88% 82.89% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 7427862 2.11% 85.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 15229127 4.32% 89.31% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 5034181 1.43% 90.74% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 5424859 1.54% 92.28% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 4755580 1.35% 93.63% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 22479552 6.37% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 352062887 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.199688 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 0.887435 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 113153102 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 169455061 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 59387304 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 7156871 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 2908724 # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved 10935425 # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred 813859 # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts 356017985 # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts 2501114 # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles 2908724 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 117268615 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 13616294 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 135215564 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 62340466 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 20711186 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 347737029 # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents 54468 # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents 1175747 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents 937238 # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents 10392106 # Number of times rename has blocked due to SQ full
-system.cpu3.rename.FullRegisterEvents 2088 # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands 332468090 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 532744217 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 410951019 # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups 499537 # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps 279653291 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 52814794 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 7988531 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 6878375 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 39718769 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 56231921 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 47708003 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 7270204 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 7954464 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 330360579 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 7980408 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 330210395 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 469256 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 44146528 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 28275391 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 197239 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 352062887 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 0.937930 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.662080 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 352706869 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.201943 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 0.895551 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 114206086 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 168667065 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 59684206 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 7159093 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 2988451 # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved 11027683 # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred 801920 # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts 358900429 # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts 2465138 # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles 2988451 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 118341629 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 14120881 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 134077735 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 62618980 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 20557126 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 350288916 # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents 64776 # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents 1233598 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents 933453 # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents 10294511 # Number of times rename has blocked due to SQ full
+system.cpu3.rename.FullRegisterEvents 2108 # Number of times there has been no free registers
+system.cpu3.rename.RenamedOperands 333834443 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 533414827 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 412704170 # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups 534789 # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps 279088781 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 54745657 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 7872437 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 6763416 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 39440190 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 56882383 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 47659648 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 7390317 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 8048428 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 332440192 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 7866599 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 331640119 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 487315 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 46360769 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 29124307 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 191271 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 352706869 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 0.940271 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.666990 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 223668227 63.53% 63.53% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 53015699 15.06% 78.59% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 24255391 6.89% 85.48% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 17227433 4.89% 90.37% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 12830165 3.64% 94.02% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 9047221 2.57% 96.59% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 6060563 1.72% 98.31% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 3584032 1.02% 99.33% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 2374156 0.67% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 224298657 63.59% 63.59% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 52689618 14.94% 78.53% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 24223023 6.87% 85.40% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 17391351 4.93% 90.33% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 12809979 3.63% 93.96% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 9108183 2.58% 96.54% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 6180606 1.75% 98.30% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 3577681 1.01% 99.31% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 2427771 0.69% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 352062887 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 352706869 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 1667670 25.64% 25.64% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 16900 0.26% 25.90% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 1465 0.02% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 2 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.93% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 2634602 40.51% 66.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 2182377 33.56% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 1672825 25.77% 25.77% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 16469 0.25% 26.02% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 1475 0.02% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.05% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 2639879 40.67% 66.72% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 2160482 33.28% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 223824222 67.78% 67.78% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 774202 0.23% 68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 40056 0.01% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 168 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 44646 0.01% 68.04% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 59535864 18.03% 86.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 45991226 13.93% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 224723694 67.76% 67.76% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 782210 0.24% 68.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 40081 0.01% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 289 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.01% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 42689 0.01% 68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 60119649 18.13% 86.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 45931480 13.85% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 330210395 # Type of FU issued
-system.cpu3.iq.rate 0.900317 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 6503016 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.019694 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 1018785662 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 382537276 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 318334132 # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads 670287 # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes 332759 # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses 299480 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 336355093 # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses 358307 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 2644941 # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total 331640119 # Type of FU issued
+system.cpu3.iq.rate 0.902685 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 6491130 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.019573 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 1022298212 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 386704326 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 319186755 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads 667340 # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes 341320 # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses 298656 # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses 337775175 # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses 356047 # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads 2654997 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 8880043 # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses 11323 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 388636 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 4860112 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 9481961 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 11664 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 384451 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 4830568 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads 2108647 # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked 4155835 # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads 2150262 # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked 4167982 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 2908724 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 8517603 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 3858124 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 338416485 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 997667 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 56231921 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 47708003 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 6730848 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 119383 # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents 3692835 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 388636 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 1480307 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 1295138 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 2775445 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 326459428 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 58365019 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 3251449 # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles 2988451 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 8896535 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 3943315 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 340388861 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 1005407 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 56882383 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 47659648 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 6617026 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 121260 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents 3776054 # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents 384451 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 1420846 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 1561965 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 2982811 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 327664673 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 58849807 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 3477335 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 75498 # number of nop insts executed
-system.cpu3.iew.exec_refs 103758179 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 60585574 # Number of branches executed
-system.cpu3.iew.exec_stores 45393160 # Number of stores executed
-system.cpu3.iew.exec_rate 0.890090 # Inst execution rate
-system.cpu3.iew.wb_sent 319299995 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 318633612 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 157331551 # num instructions producing a value
-system.cpu3.iew.wb_consumers 273213532 # num instructions consuming a value
-system.cpu3.iew.wb_rate 0.868753 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.575856 # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts 44171670 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 7783169 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 2474762 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 344535281 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 0.853888 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 1.850951 # Number of insts commited each cycle
+system.cpu3.iew.exec_nop 82070 # number of nop insts executed
+system.cpu3.iew.exec_refs 104185879 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 60732264 # Number of branches executed
+system.cpu3.iew.exec_stores 45336072 # Number of stores executed
+system.cpu3.iew.exec_rate 0.891864 # Inst execution rate
+system.cpu3.iew.wb_sent 320275931 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 319485411 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 157730975 # num instructions producing a value
+system.cpu3.iew.wb_consumers 273958307 # num instructions consuming a value
+system.cpu3.iew.wb_rate 0.869601 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.575748 # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts 46394137 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 7675328 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 2556293 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 344852948 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 0.852381 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.849144 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 237617500 68.97% 68.97% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 51794932 15.03% 84.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 18673564 5.42% 89.42% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 8409945 2.44% 91.86% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 6103204 1.77% 93.63% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 3702818 1.07% 94.71% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 3412254 0.99% 95.70% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 2146383 0.62% 96.32% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 12674681 3.68% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 238109143 69.05% 69.05% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 51559449 14.95% 84.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 18667514 5.41% 89.41% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 8519895 2.47% 91.88% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 6096374 1.77% 93.65% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 3704494 1.07% 94.72% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 3440464 1.00% 95.72% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 2103815 0.61% 96.33% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 12651800 3.67% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 344535281 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 250269181 # Number of instructions committed
-system.cpu3.commit.committedOps 294194454 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 344852948 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 250222532 # Number of instructions committed
+system.cpu3.commit.committedOps 293946017 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 90199768 # Number of memory references committed
-system.cpu3.commit.loads 47351877 # Number of loads committed
-system.cpu3.commit.membars 1984419 # Number of memory barriers committed
-system.cpu3.commit.branches 55927856 # Number of branches committed
-system.cpu3.commit.fp_insts 287957 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 270378967 # Number of committed integer instructions.
-system.cpu3.commit.function_calls 7437415 # Number of function calls committed.
+system.cpu3.commit.refs 90229501 # Number of memory references committed
+system.cpu3.commit.loads 47400421 # Number of loads committed
+system.cpu3.commit.membars 1979442 # Number of memory barriers committed
+system.cpu3.commit.branches 55926403 # Number of branches committed
+system.cpu3.commit.fp_insts 287180 # Number of committed floating point instructions.
+system.cpu3.commit.int_insts 270155076 # Number of committed integer instructions.
+system.cpu3.commit.function_calls 7460078 # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu 203317857 69.11% 69.11% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult 607807 0.21% 69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv 30328 0.01% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc 38694 0.01% 69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead 47351877 16.10% 85.44% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite 42847891 14.56% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu 203036725 69.07% 69.07% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult 612324 0.21% 69.28% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv 30368 0.01% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc 37099 0.01% 69.30% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead 47400421 16.13% 85.43% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite 42829080 14.57% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total 294194454 # Class of committed instruction
-system.cpu3.commit.bw_lim_events 12674681 # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads 668190501 # The number of ROB reads
-system.cpu3.rob.rob_writes 684271435 # The number of ROB writes
-system.cpu3.timesIdled 2367007 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 14708375 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 98631571593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 250269181 # Number of Instructions Simulated
-system.cpu3.committedOps 294194454 # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi 1.465507 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 1.465507 # CPI: Total CPI of All Threads
-system.cpu3.ipc 0.682358 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 0.682358 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 384861666 # number of integer regfile reads
-system.cpu3.int_regfile_writes 227851781 # number of integer regfile writes
-system.cpu3.fp_regfile_reads 577247 # number of floating regfile reads
-system.cpu3.fp_regfile_writes 366452 # number of floating regfile writes
-system.cpu3.cc_regfile_reads 69640374 # number of cc regfile reads
-system.cpu3.cc_regfile_writes 70304463 # number of cc regfile writes
-system.cpu3.misc_regfile_reads 653638120 # number of misc regfile reads
-system.cpu3.misc_regfile_writes 7847503 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 40268 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40268 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136537 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136537 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes)
+system.cpu3.commit.op_class_0::total 293946017 # Class of committed instruction
+system.cpu3.commit.bw_lim_events 12651800 # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads 670506126 # The number of ROB reads
+system.cpu3.rob.rob_writes 688548433 # The number of ROB writes
+system.cpu3.timesIdled 2399442 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 14686241 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 98624955783 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 250222532 # Number of Instructions Simulated
+system.cpu3.committedOps 293946017 # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi 1.468265 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 1.468265 # CPI: Total CPI of All Threads
+system.cpu3.ipc 0.681076 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 0.681076 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 385596565 # number of integer regfile reads
+system.cpu3.int_regfile_writes 228796101 # number of integer regfile writes
+system.cpu3.fp_regfile_reads 580685 # number of floating regfile reads
+system.cpu3.fp_regfile_writes 358952 # number of floating regfile writes
+system.cpu3.cc_regfile_reads 69302556 # number of cc regfile reads
+system.cpu3.cc_regfile_writes 69940425 # number of cc regfile writes
+system.cpu3.misc_regfile_reads 654940348 # number of misc regfile reads
+system.cpu3.misc_regfile_writes 7733963 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 40259 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40259 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136539 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136539 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
@@ -2183,13 +2240,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122568 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230940 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230940 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353610 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353596 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
@@ -2202,21 +2259,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155698 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334192 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334192 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492064 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 30025500 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7491984 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 28447500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 5500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 84500 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 82500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
@@ -2224,70 +2281,70 @@ system.iobus.reqLayer14.occupancy 10000 # La
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 5500 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 5000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 12632000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 12315500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 21450000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 21455000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 266387325 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 262449133 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 55488000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 54866000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 76928000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 76206000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115463 # number of replacements
-system.iocache.tags.tagsinuse 10.420638 # Cycle average of tags in use
+system.iocache.tags.replacements 115457 # number of replacements
+system.iocache.tags.tagsinuse 10.420631 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13089107754009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.547310 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.873329 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.221707 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.429583 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.651290 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 13089104998009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 5.909087 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 4.511544 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.369318 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.281971 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.651289 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
-system.iocache.tags.data_accesses 1039686 # Number of data accesses
+system.iocache.tags.tag_accesses 1039587 # Number of tag accesses
+system.iocache.tags.data_accesses 1039587 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8806 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8843 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
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@@ -2301,507 +2358,508 @@ system.iocache.demand_miss_rate::total 1 # mi
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
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system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.snoops 2019 # Total snoops (count)
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system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2770738 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2784335 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1770502 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1759502 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 3078925491 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 3098675220 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2289724659 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 2309466891 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 28858376 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 28779324 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
@@ -3191,61 +3249,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 51493979 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 26073999 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 3069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests 51706902 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 26184437 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 3148 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 2316 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 2316 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 1482158 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 23699758 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 33644 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 33644 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 7970176 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 15734993 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 2276280 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 43214 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 43217 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 1978540 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 1978540 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 15735581 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 6487298 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 1273838 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 1224286 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47292320 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29274050 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 815247 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1729718 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 79111335 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2014283796 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1022659326 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2960744 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6155576 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 3046059442 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1649768 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 38047944 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.016242 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.126407 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 1482882 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 23802645 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33648 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 7959053 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 15833779 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 2295611 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 43290 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 43295 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 1978465 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 1978465 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 15834389 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 6490632 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 1273555 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 1224699 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47588616 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29285291 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 809621 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1728313 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 79411841 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2026923028 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1022015642 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2929800 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6124520 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 3057992990 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1664727 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 38155395 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.016407 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.127033 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 37429952 98.38% 98.38% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 617992 1.62% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 37529393 98.36% 98.36% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 626002 1.64% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 38047944 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 30711072482 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 38155395 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 30930828488 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 825172 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 835176 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 15222500163 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 15386050434 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 7880833554 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 7871932216 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 287037671 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 287489224 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 701756875 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 705270826 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
index e1c1def32..272e9258d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
@@ -1,161 +1,161 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 51.284914 # Number of seconds simulated
-sim_ticks 51284914333000 # Number of ticks simulated
-final_tick 51284914333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.761757 # Number of seconds simulated
+sim_ticks 51761756862000 # Number of ticks simulated
+final_tick 51761756862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 235872 # Simulator instruction rate (inst/s)
-host_op_rate 277167 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 13557886882 # Simulator tick rate (ticks/s)
-host_mem_usage 696464 # Number of bytes of host memory used
-host_seconds 3782.66 # Real time elapsed on the host
-sim_insts 892223547 # Number of instructions simulated
-sim_ops 1048428696 # Number of ops (including micro ops) simulated
+host_inst_rate 265912 # Simulator instruction rate (inst/s)
+host_op_rate 283734 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5899295346 # Simulator tick rate (ticks/s)
+host_mem_usage 696216 # Number of bytes of host memory used
+host_seconds 8774.23 # Real time elapsed on the host
+sim_insts 2333170820 # Number of instructions simulated
+sim_ops 2489548001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 145024 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 130496 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 3660544 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 27123808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 158784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 143040 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3643072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 26095080 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 424512 # Number of bytes read from this memory
-system.physmem.bytes_read::total 61524360 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 3660544 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3643072 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 7303616 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 79842048 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 151872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 131712 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3595840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 25977120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 153216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 139456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 3729408 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 26080296 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 414272 # Number of bytes read from this memory
+system.physmem.bytes_read::total 60373192 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3595840 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 3729408 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 7325248 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 78844864 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory
-system.physmem.bytes_written::total 79862628 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 2266 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2039 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 57196 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 423818 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2481 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 2235 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 56923 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 407740 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6633 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 961331 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1247532 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 78865444 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 2373 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2058 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 56185 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 405901 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 2394 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 2179 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 58272 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 407509 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6473 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 943344 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1231951 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1250105 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 2828 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1234524 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 2934 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2545 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 71377 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 528885 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 3096 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 2789 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 71036 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 508826 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8278 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1199658 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 71377 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 71036 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 142413 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1556833 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 69469 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 501859 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 2960 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 2694 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 72049 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 503853 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8003 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1166367 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 69469 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 72049 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 141519 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1523226 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 401 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1557234 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1556833 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 2828 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 398 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1523624 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1523226 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 2934 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2545 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 71377 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 528885 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 3096 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 2789 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 71036 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 509227 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8278 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2756892 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 961331 # Number of read requests accepted
-system.physmem.writeReqs 1250105 # Number of write requests accepted
-system.physmem.readBursts 961331 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1250105 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 61479104 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 46080 # Total number of bytes read from write queue
-system.physmem.bytesWritten 79862656 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 61524360 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 79862628 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 720 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu0.inst 69469 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 501859 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 2960 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 2694 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 72049 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 504250 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8003 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2689991 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 943344 # Number of read requests accepted
+system.physmem.writeReqs 1234524 # Number of write requests accepted
+system.physmem.readBursts 943344 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1234524 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 60330432 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 43584 # Total number of bytes read from write queue
+system.physmem.bytesWritten 78865536 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 60373192 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 78865444 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 681 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 54441 # Per bank write bursts
-system.physmem.perBankRdBursts::1 61427 # Per bank write bursts
-system.physmem.perBankRdBursts::2 55898 # Per bank write bursts
-system.physmem.perBankRdBursts::3 54692 # Per bank write bursts
-system.physmem.perBankRdBursts::4 58805 # Per bank write bursts
-system.physmem.perBankRdBursts::5 68407 # Per bank write bursts
-system.physmem.perBankRdBursts::6 58313 # Per bank write bursts
-system.physmem.perBankRdBursts::7 55590 # Per bank write bursts
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+system.physmem.wrPerTurnAround::samples 63900 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.284413 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.392697 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 8.437503 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-7 96 0.15% 0.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-15 63 0.10% 0.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23 55368 85.45% 85.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31 6790 10.48% 96.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39 705 1.09% 97.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47 466 0.72% 97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55 493 0.76% 98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63 108 0.17% 98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71 328 0.51% 99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79 159 0.25% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87 155 0.24% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-15 74 0.12% 0.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23 54483 85.26% 85.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31 6734 10.54% 96.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39 692 1.08% 97.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47 454 0.71% 97.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55 539 0.84% 98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63 107 0.17% 98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-71 351 0.55% 99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79 150 0.23% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-87 153 0.24% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 9 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103 3 0.00% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111 3 0.00% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103 2 0.00% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-111 6 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 5 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127 3 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135 16 0.02% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143 4 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151 10 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183 7 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191 3 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215 3 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-127 2 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-135 11 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-143 5 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-151 15 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-167 4 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-175 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-183 5 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::328-335 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 64799 # Writes before turning the bus around for reads
-system.physmem.totQLat 25248874155 # Total ticks spent queuing
-system.physmem.totMemAccLat 43260330405 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4803055000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 26284.18 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 63900 # Writes before turning the bus around for reads
+system.physmem.totQLat 25011662426 # Total ticks spent queuing
+system.physmem.totMemAccLat 42686593676 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4713315000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 26532.98 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 45034.18 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.20 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 45282.98 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.17 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.17 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing
-system.physmem.readRowHits 736430 # Number of row buffer hits during reads
-system.physmem.writeRowHits 910858 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.66 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 72.99 # Row buffer hit rate for writes
-system.physmem.avgGap 23190774.27 # Average gap between requests
-system.physmem.pageHitRate 74.59 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2124654840 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1159285875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3647069400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 4023470880 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3349681296000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1235871193320 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29686851168000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34283358138315 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.488160 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49386595452825 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1712515740000 # Time in different power states
+system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 9.19 # Average write queue length when enqueuing
+system.physmem.readRowHits 724331 # Number of row buffer hits during reads
+system.physmem.writeRowHits 903369 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 76.84 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.31 # Row buffer hit rate for writes
+system.physmem.avgGap 23767168.45 # Average gap between requests
+system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 2099502720 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1145562000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3609886800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 4003979040 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3380826018960 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1247139310140 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29963069496750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34601893756410 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.483818 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49846129273502 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1728438660000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 185803070925 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 187184326498 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2117843280 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1155569250 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3845696400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4062623040 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3349681296000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1240883143470 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29682454712250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34284200883690 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.504593 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49379236035062 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1712515740000 # Time in different power states
+system.physmem_1.actEnergy 2037593880 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1111782375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3742837800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3981156480 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3380826018960 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1247115577050 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29963090307000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34601905273545 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.484040 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49846127379717 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1728438660000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 193162474938 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 187190202783 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
@@ -346,29 +347,33 @@ system.realview.nvmem.num_reads::total 38 # Nu
system.realview.nvmem.bw_read::cpu0.inst 21 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 20 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 42 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 41 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 21 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 20 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 41 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 21 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 20 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 42 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 41 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 131222767 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 88895341 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 5715566 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 88848195 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 63996903 # Number of BTB hits
+system.cpu0.branchPred.lookups 441769882 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 346318853 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 5806285 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 315736094 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 267112052 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 72.029491 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 17247708 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 186935 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 84.599784 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 17170317 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 190049 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.indirectLookups 5021410 # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits 2619937 # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses 2401473 # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted 415468 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -399,89 +404,93 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 901787 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 901787 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17510 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90865 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 558240 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 343547 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 2647.495103 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 15829.601271 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535 340846 99.21% 99.21% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071 1379 0.40% 99.62% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607 917 0.27% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143 154 0.04% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679 149 0.04% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215 34 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751 34 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287 32 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 343547 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 423455 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23285.712768 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18859.753792 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 19582.519957 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 414421 97.87% 97.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6698 1.58% 99.45% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1655 0.39% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 124 0.03% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 334 0.08% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 125 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 53 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 24 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 17 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 892710 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 892710 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17744 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 89453 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 550305 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 342405 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 2673.589755 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 15902.851063 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535 339616 99.19% 99.19% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071 1452 0.42% 99.61% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607 967 0.28% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143 143 0.04% 99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679 137 0.04% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215 16 0.00% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751 33 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287 35 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 342405 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 416567 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 23523.175143 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18877.823931 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 19885.199602 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 406963 97.69% 97.69% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 7350 1.76% 99.46% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1585 0.38% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 137 0.03% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 275 0.07% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 156 0.04% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 65 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 27 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 423455 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 376351808512 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.148701 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.701209 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-3 375305951012 99.72% 99.72% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-7 568976500 0.15% 99.87% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-11 204601500 0.05% 99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-15 126494000 0.03% 99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-19 49142500 0.01% 99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-23 26958000 0.01% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-27 28402000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-31 34222000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::32-35 6583500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::36-39 370000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::40-43 35500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::44-47 29500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::48-51 42000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 376351808512 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 90865 83.84% 83.84% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 17510 16.16% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 108375 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 901787 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total 416567 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 844595026420 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 0.078472 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev 0.490568 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-3 843548733920 99.88% 99.88% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-7 573107500 0.07% 99.94% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-11 199238500 0.02% 99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-15 117034000 0.01% 99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-19 49115000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-23 33953000 0.00% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-27 28746000 0.00% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-31 36613000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::32-35 8069500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::36-39 361500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::40-43 23000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::44-47 9000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::48-51 14500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::52-55 3000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::56-59 3000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::60-63 2000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 844595026420 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 89453 83.45% 83.45% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 17744 16.55% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 107197 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 892710 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 901787 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 108375 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 892710 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107197 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 108375 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 1010162 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107197 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 999907 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 104844993 # DTB read hits
-system.cpu0.dtb.read_misses 617686 # DTB read misses
-system.cpu0.dtb.write_hits 81833158 # DTB write hits
-system.cpu0.dtb.write_misses 284101 # DTB write misses
-system.cpu0.dtb.flush_tlb 1099 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 311659377 # DTB read hits
+system.cpu0.dtb.read_misses 618746 # DTB read misses
+system.cpu0.dtb.write_hits 81669046 # DTB write hits
+system.cpu0.dtb.write_misses 273964 # DTB write misses
+system.cpu0.dtb.flush_tlb 1566 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 21489 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 548 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 56009 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 176 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 9405 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 21904 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 550 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 56873 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 200 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 9024 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 58104 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 105462679 # DTB read accesses
-system.cpu0.dtb.write_accesses 82117259 # DTB write accesses
+system.cpu0.dtb.perms_faults 58972 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 312278123 # DTB read accesses
+system.cpu0.dtb.write_accesses 81943010 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 186678151 # DTB hits
-system.cpu0.dtb.misses 901787 # DTB misses
-system.cpu0.dtb.accesses 187579938 # DTB accesses
+system.cpu0.dtb.hits 393328423 # DTB hits
+system.cpu0.dtb.misses 892710 # DTB misses
+system.cpu0.dtb.accesses 394221133 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -511,831 +520,832 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 105051 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 105051 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3103 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 71842 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 14498 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 90553 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 1891.361965 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 11942.072265 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767 89471 98.81% 98.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535 577 0.64% 99.44% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303 86 0.09% 99.54% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071 126 0.14% 99.68% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839 214 0.24% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607 41 0.05% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375 17 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 90553 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 89443 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 29726.837204 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24825.436238 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 23450.909148 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 87272 97.57% 97.57% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 672 0.75% 98.32% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 1265 1.41% 99.74% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 85 0.10% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 111 0.12% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 21 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 100670 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 100670 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3435 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 68577 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore 13827 # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples 86843 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean 1681.770551 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 11901.774457 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767 85828 98.83% 98.83% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535 525 0.60% 99.44% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303 54 0.06% 99.50% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071 177 0.20% 99.70% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839 176 0.20% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607 42 0.05% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375 17 0.02% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 86843 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 85839 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 29252.396929 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 24357.820404 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 23461.302389 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 83908 97.75% 97.75% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 516 0.60% 98.35% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 1196 1.39% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 80 0.09% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 102 0.12% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 89443 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 402102979288 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 1.378343 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -152052427072 -37.81% -37.81% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 554084756860 137.80% 99.98% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 62143500 0.02% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3 7613500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4 640000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5 190500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6 62000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 402102979288 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 71842 95.86% 95.86% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 3103 4.14% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 74945 # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total 85839 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 638425660712 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 0.889219 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev 0.314244 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 70792067924 11.09% 11.09% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 567575291288 88.90% 99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2 51231500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3 6018000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4 857500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5 106500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::6 88000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 638425660712 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 68577 95.23% 95.23% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 3435 4.77% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 72012 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 105051 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 105051 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 74945 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 74945 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 179996 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 94456447 # ITB inst hits
-system.cpu0.itb.inst_misses 105051 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72012 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72012 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 172682 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 300349481 # ITB inst hits
+system.cpu0.itb.inst_misses 100670 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 1099 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 1566 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 21489 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 548 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 41420 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 21904 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 550 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 41410 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 203143 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 188775 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 94561498 # ITB inst accesses
-system.cpu0.itb.hits 94456447 # DTB hits
-system.cpu0.itb.misses 105051 # DTB misses
-system.cpu0.itb.accesses 94561498 # DTB accesses
-system.cpu0.numCycles 688838520 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 300450151 # ITB inst accesses
+system.cpu0.itb.hits 300349481 # DTB hits
+system.cpu0.itb.misses 100670 # DTB misses
+system.cpu0.itb.accesses 300450151 # DTB accesses
+system.cpu0.numCycles 1153591288 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 245587927 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 584587978 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 131222767 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 81244611 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 399140958 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 13083080 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 2697287 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 23591 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 4020 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 5373314 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 168933 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 3234 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 94235768 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 3541356 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 41927 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 659540531 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.038718 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.291266 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 452660277 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 1310968350 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 441769882 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 286902306 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 657569557 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 13257965 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 2520501 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 22487 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 4210 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 4808989 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 163286 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 3813 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 300145403 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 3627233 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 38474 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 1124381714 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.254786 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.113096 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 515133348 78.10% 78.10% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 18089863 2.74% 80.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 18214710 2.76% 83.61% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 13345415 2.02% 85.63% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 28172960 4.27% 89.90% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 9014281 1.37% 91.27% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 9743812 1.48% 92.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 8313958 1.26% 94.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 39512184 5.99% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 722021873 64.22% 64.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 121051325 10.77% 74.98% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 18164334 1.62% 76.60% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 13282328 1.18% 77.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 182681747 16.25% 94.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 8985206 0.80% 94.82% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 9665427 0.86% 95.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 8249650 0.73% 96.42% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 40279824 3.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 659540531 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.190499 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.848658 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 199724344 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 336015345 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 105250676 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 13405220 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 5142823 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 19593113 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 1418693 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 638893412 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 4361205 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 5142823 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 207245201 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 27037727 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 261836460 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 110999671 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 47276188 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 624046996 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 101675 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 2286594 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 1931238 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 27774354 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents 3807 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 596597233 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 959951672 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 737729971 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 774177 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 503848315 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 92748918 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 15071360 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 13097285 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 74895654 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 100276299 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 85965913 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 13583222 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 14599367 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 592457087 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 15151612 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 594148769 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 834633 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 77960575 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 49583395 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 368092 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 659540531 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.900853 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.637513 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 1124381714 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.382952 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 1.136424 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 405971329 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 336686919 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 362849881 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 13601656 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 5263930 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 71142613 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 1385162 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 1364494980 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 4266008 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 5263930 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 413565658 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 26498073 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 263444659 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 368730385 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 46870910 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 1349255091 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 116974 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 2261616 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 1896807 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 27181012 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents 3751 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 1320809578 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 1942299251 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 1409770765 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 775838 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 1225247186 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 95562392 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 15257380 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 13270852 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 75639942 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 307378259 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 85793639 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 13768177 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 14589388 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 1316697465 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 15319190 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 1317684473 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 854895 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 81379212 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 50931090 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 359979 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 1124381714 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 1.171919 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.498403 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 427069171 64.75% 64.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 97668979 14.81% 79.56% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 43298472 6.56% 86.13% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 30774138 4.67% 90.79% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 22917395 3.47% 94.27% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 16090465 2.44% 96.71% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 10921608 1.66% 98.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 6493545 0.98% 99.35% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 4306758 0.65% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 479017696 42.60% 42.60% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 355860200 31.65% 74.25% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 94607581 8.41% 82.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 82377744 7.33% 89.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 74414845 6.62% 96.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 16123062 1.43% 98.05% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 11093083 0.99% 99.03% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 6457333 0.57% 99.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 4430170 0.39% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 659540531 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 1124381714 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 3033811 25.57% 25.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 25491 0.21% 25.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 3073 0.03% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 1 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.81% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4852849 40.90% 66.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 3949019 33.29% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 3027806 25.46% 25.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 21993 0.18% 25.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 1913 0.02% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 4879295 41.03% 66.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 3961438 33.31% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 26 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 402837369 67.80% 67.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 1388159 0.23% 68.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 66027 0.01% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 24 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 5 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 70383 0.01% 68.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 106898292 17.99% 86.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 82888484 13.95% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 30 0.00% 0.00% # Type of FU issued
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+system.cpu0.iq.FU_type_0::IntMult 1403204 0.11% 69.89% # Type of FU issued
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+system.cpu0.iq.FU_type_0::FloatAdd 184 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.90% # Type of FU issued
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+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.90% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.90% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.90% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.90% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 313882941 23.82% 93.72% # Type of FU issued
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system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 594148769 # Type of FU issued
-system.cpu0.iq.rate 0.862537 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 11864244 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.019968 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 1859480838 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 685772005 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 572455649 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 1056108 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 523485 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 471348 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 605449446 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 563541 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 4712997 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 1317684473 # Type of FU issued
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+system.cpu0.iq.fu_busy_rate 0.009025 # FU busy rate (busy events/executed inst)
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+system.cpu0.iq.int_inst_queue_writes 1413606609 # Number of integer instruction queue writes
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+system.cpu0.iq.fp_inst_queue_reads 975276 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 499965 # Number of floating instruction queue writes
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system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 15710215 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 20540 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 737635 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 8733080 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 16714956 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 20317 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 722500 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 8583352 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 3961996 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 8114796 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 3995442 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 8184292 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 5142823 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 15863683 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 9219529 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 607741320 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 1739282 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 100276299 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 85965913 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 12807299 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 229576 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 8904673 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 737635 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 2585247 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 2254078 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 4839325 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 587599487 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 104834587 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 5659877 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 5263930 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 15793558 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 8769722 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 1332158998 # Number of instructions dispatched to IQ
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system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 132621 # number of nop insts executed
-system.cpu0.iew.exec_refs 186666893 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 108670121 # Number of branches executed
-system.cpu0.iew.exec_stores 81832306 # Number of stores executed
-system.cpu0.iew.exec_rate 0.853029 # Inst execution rate
-system.cpu0.iew.wb_sent 574140659 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 572926997 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 282868675 # num instructions producing a value
-system.cpu0.iew.wb_consumers 490940827 # num instructions consuming a value
-system.cpu0.iew.wb_rate 0.831729 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.576177 # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts 78001898 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 14783520 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 4316576 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 646201132 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.819634 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.819531 # Number of insts commited each cycle
+system.cpu0.iew.exec_nop 142343 # number of nop insts executed
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+system.cpu0.iew.exec_rate 1.136247 # Inst execution rate
+system.cpu0.iew.wb_sent 1296930060 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 1295522362 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 592614892 # num instructions producing a value
+system.cpu0.iew.wb_consumers 1110609614 # num instructions consuming a value
+system.cpu0.iew.wb_rate 1.123034 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.533594 # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts 81425087 # The number of squashed insts skipped by commit
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+system.cpu0.commit.branchMispredicts 4440844 # The number of times a branch was mispredicted
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+system.cpu0.commit.committed_per_cycle::mean 1.126151 # Number of insts commited each cycle
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system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 452584963 70.04% 70.04% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 95102471 14.72% 84.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 32986108 5.10% 89.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 15275406 2.36% 92.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 10838243 1.68% 93.90% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 6597010 1.02% 94.92% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 6118779 0.95% 95.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 3888693 0.60% 96.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 22809459 3.53% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 504262189 45.41% 45.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 302033951 27.20% 72.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 135703334 12.22% 84.82% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 118428443 10.66% 95.49% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 10778674 0.97% 96.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 6605089 0.59% 97.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 6100457 0.55% 97.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 3862548 0.35% 97.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 22766347 2.05% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 646201132 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 450421520 # Number of instructions committed
-system.cpu0.commit.committedOps 529648124 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 1110541032 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 1171621966 # Number of instructions committed
+system.cpu0.commit.committedOps 1250637443 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 161798917 # Number of memory references committed
-system.cpu0.commit.loads 84566084 # Number of loads committed
-system.cpu0.commit.membars 3697077 # Number of memory barriers committed
-system.cpu0.commit.branches 100455887 # Number of branches committed
-system.cpu0.commit.fp_insts 452989 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 486555488 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 13358896 # Number of function calls committed.
+system.cpu0.commit.refs 367873590 # Number of memory references committed
+system.cpu0.commit.loads 290663303 # Number of loads committed
+system.cpu0.commit.membars 3675290 # Number of memory barriers committed
+system.cpu0.commit.branches 409547032 # Number of branches committed
+system.cpu0.commit.fp_insts 413703 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 1052721176 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 13293497 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
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-system.cpu0.commit.op_class_0::IntMult 1084981 0.20% 69.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 49052 0.01% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 60464 0.01% 69.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 84566084 15.97% 85.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 77232833 14.58% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 881582024 70.49% 70.49% # Class of committed instruction
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+system.cpu0.commit.op_class_0::IntDiv 47670 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.58% # Class of committed instruction
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060327 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.writebacks::writebacks 8078087 # number of writebacks
+system.cpu0.dcache.writebacks::total 8078087 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3526105 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3409163 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 6935268 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5405186 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5181209 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 10586395 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3376 # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3483 # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total 6859 # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 204163 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 196814 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 400977 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 8931291 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data 8590372 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 17521663 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 8931291 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data 8590372 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 17521663 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2857115 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2832930 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 5690045 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1092445 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1058766 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 2151211 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 668680 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 599708 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 1268388 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 570295 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 661102 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total 1231397 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 127451 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 121478 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 248929 # number of LoadLockedReq MSHR misses
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+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.demand_mshr_misses::cpu1.data 3891696 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 7841256 # number of demand (read+write) MSHR misses
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+system.cpu0.dcache.overall_mshr_misses::cpu1.data 4491404 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 9109644 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16758 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16944 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15500 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 18208 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32258 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 35152 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48892925500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 49984550000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 98877475500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 50989234756 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 50617210449 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 101606445205 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13305949000 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11256900000 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 24562849000 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 21948256934 # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 29156940361 # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 51105197295 # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1850360000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1748512000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3598872000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 133500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 94000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 227500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99882160256 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 100601760449 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 200483920705 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 113188109256 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111858660449 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 225046769705 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3097490500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3134623000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6232113500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2979818500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3228691491 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6208509991 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6077309000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6363314491 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12440623491 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.009749 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.009728 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009738 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014676 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014592 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014635 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750530 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.745614 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.748198 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.758833 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.814954 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787965 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061506 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058429 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059965 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000002 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024528 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024513 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.024521 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028440 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028265 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.028354 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17353.927566 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17886.272928 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17616.834367 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47572.682423 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47135.880559 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47356.290457 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21536.193491 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18340.035847 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19989.610840 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 39015.237232 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44550.264590 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41946.295275 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14451.060284 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14509.206681 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14479.003180 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12833.333333 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 47375 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26650 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25666.385159 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25968.021990 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25815.480762 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25078.960317 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24921.276744 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25001.248351 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185947.184583 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184104.346043 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185012.960983 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 194039.582225 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176328.305722 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184229.418863 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189792.205329 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 180043.232448 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184621.085255 # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.010747 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.010698 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.010722 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.012536 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.012319 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.012428 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17112.690774 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17644.117574 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17377.274784 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46674.418168 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47807.740756 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47232.207908 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19898.829036 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18770.635042 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19365.406327 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 38485.795832 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44103.542813 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41501.804288 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14518.206997 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14393.651525 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14457.423603 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26700 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 47000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 32500 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25289.439901 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25850.364584 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25567.832590 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24508.927482 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24905.054288 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24704.233196 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184836.525838 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184998.996695 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.209602 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 192246.354839 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177322.687335 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184185.059659 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188396.955794 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 181022.829170 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184551.602003 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 16001570 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.932596 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 169345332 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 16002082 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 10.582706 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 19421691500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.339337 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 234.593260 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.541678 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.458190 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 16336648 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.932732 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 580722956 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 16337160 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 35.546139 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 19421278500 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 279.802291 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 232.130441 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.546489 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.453380 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id
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+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12830.432136 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969 # average ReadReq mshr uncacheable latency
@@ -1343,15 +1353,19 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 129319671 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 87966891 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 5641555 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 87944289 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 63362458 # Number of BTB hits
+system.cpu1.branchPred.lookups 439037695 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 344630545 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 5789779 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 303336917 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 265424368 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 72.048406 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 16739508 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 187311 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 87.501505 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 16925953 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 188094 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.indirectLookups 4924647 # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits 2613751 # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses 2310896 # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted 404882 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1381,89 +1395,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 895803 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 895803 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16863 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90438 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 556335 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 339468 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 2716.724404 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 17179.301997 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-131071 338161 99.61% 99.61% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-262143 1033 0.30% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-393215 187 0.06% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-524287 66 0.02% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-655359 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::655360-786431 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::786432-917503 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::917504-1.04858e+06 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::1.04858e+06-1.17965e+06 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 339468 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 421969 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23447.781709 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 18889.456511 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 20397.447622 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 412488 97.75% 97.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6847 1.62% 99.38% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1883 0.45% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 119 0.03% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 376 0.09% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 119 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 93 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 24 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 421969 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 329421639756 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.099906 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.712348 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-3 328385721256 99.69% 99.69% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-7 558806000 0.17% 99.86% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-11 205948500 0.06% 99.92% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-15 123798000 0.04% 99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-19 49482000 0.02% 99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-23 27267000 0.01% 99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-27 29508000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-31 34215500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::32-35 6315000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::36-39 466000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::40-43 60500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::44-47 19000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::48-51 33000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 329421639756 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 90439 84.28% 84.28% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 16863 15.72% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 107302 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 895803 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 918796 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 918796 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17982 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92529 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 574433 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 344363 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 2764.463662 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 16303.117040 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535 341501 99.17% 99.17% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071 1458 0.42% 99.59% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607 968 0.28% 99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143 172 0.05% 99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679 169 0.05% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215 19 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751 30 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287 39 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 344363 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 435626 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23794.009081 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 19218.933550 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 19692.719928 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 425832 97.75% 97.75% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 7550 1.73% 99.48% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1569 0.36% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 124 0.03% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 287 0.07% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 141 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 90 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 14 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 435626 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 784789358776 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.079913 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.520502 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-3 783688095276 99.86% 99.86% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-7 587470000 0.07% 99.93% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-11 214780500 0.03% 99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-15 128162000 0.02% 99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-19 51938500 0.01% 99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-23 36138500 0.00% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-27 30357500 0.00% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-31 44039000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::32-35 7811000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::36-39 500500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::40-43 27000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::44-47 17000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::48-51 22000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 784789358776 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 92530 83.73% 83.73% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 17982 16.27% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 110512 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 918796 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 895803 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 107302 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 918796 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 110512 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 107302 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 1003105 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 110512 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 1029308 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 102542814 # DTB read hits
-system.cpu1.dtb.read_misses 610673 # DTB read misses
-system.cpu1.dtb.write_hits 79662745 # DTB write hits
-system.cpu1.dtb.write_misses 285130 # DTB write misses
-system.cpu1.dtb.flush_tlb 1093 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 308677787 # DTB read hits
+system.cpu1.dtb.read_misses 638033 # DTB read misses
+system.cpu1.dtb.write_hits 79810213 # DTB write hits
+system.cpu1.dtb.write_misses 280763 # DTB write misses
+system.cpu1.dtb.flush_tlb 1558 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 21297 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 54160 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 170 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 9133 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 20842 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 54702 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 194 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 8626 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 55274 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 103153487 # DTB read accesses
-system.cpu1.dtb.write_accesses 79947875 # DTB write accesses
+system.cpu1.dtb.perms_faults 52744 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 309315820 # DTB read accesses
+system.cpu1.dtb.write_accesses 80090976 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 182205559 # DTB hits
-system.cpu1.dtb.misses 895803 # DTB misses
-system.cpu1.dtb.accesses 183101362 # DTB accesses
+system.cpu1.dtb.hits 388488000 # DTB hits
+system.cpu1.dtb.misses 918796 # DTB misses
+system.cpu1.dtb.accesses 389406796 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1493,383 +1505,382 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 104787 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 104787 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2997 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 70975 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 14401 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 90386 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 1987.890824 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 12865.387454 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-65535 89845 99.40% 99.40% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-131071 221 0.24% 99.65% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-196607 266 0.29% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-262143 26 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-327679 17 0.02% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-393215 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 90386 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 88373 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 30169.316420 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 25114.673173 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 23994.465704 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 86083 97.41% 97.41% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 728 0.82% 98.23% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 1319 1.49% 99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 85 0.10% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 120 0.14% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 16 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 88373 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 612887048792 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 0.894295 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev 0.308036 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 64872157396 10.58% 10.58% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 547942164396 89.40% 99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 62720500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3 7937000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4 1056500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5 430500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::6 357000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::7 15000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::8 210500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 612887048792 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 70975 95.95% 95.95% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 2997 4.05% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 73972 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 101960 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 101960 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3266 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68775 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore 14205 # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples 87755 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean 1682.627770 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 11960.911223 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-65535 87281 99.46% 99.46% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-131071 225 0.26% 99.72% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-196607 206 0.23% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-262143 30 0.03% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 87755 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 86246 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 29588.885282 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24514.620158 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 24839.457997 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 84146 97.57% 97.57% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 550 0.64% 98.20% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 1295 1.50% 99.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 86 0.10% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 109 0.13% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 19 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 86246 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 630168052620 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean 0.901316 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev 0.298682 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 62259907956 9.88% 9.88% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1 567845557664 90.11% 99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2 54142000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3 7434500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4 754500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5 241500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::6 14500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 630168052620 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 68775 95.47% 95.47% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 3266 4.53% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 72041 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 104787 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 104787 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101960 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101960 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 73972 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 73972 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 178759 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 92590548 # ITB inst hits
-system.cpu1.itb.inst_misses 104787 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72041 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72041 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 174001 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 298391001 # ITB inst hits
+system.cpu1.itb.inst_misses 101960 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 1093 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 1558 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 21297 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 40602 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 20842 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 40396 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 205634 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 187550 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 92695335 # ITB inst accesses
-system.cpu1.itb.hits 92590548 # DTB hits
-system.cpu1.itb.misses 104787 # DTB misses
-system.cpu1.itb.accesses 92695335 # DTB accesses
-system.cpu1.numCycles 681850895 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 298492961 # ITB inst accesses
+system.cpu1.itb.hits 298391001 # DTB hits
+system.cpu1.itb.misses 101960 # DTB misses
+system.cpu1.itb.accesses 298492961 # DTB accesses
+system.cpu1.numCycles 1146540967 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 239388954 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 575024708 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 129319671 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 80101966 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 399222814 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 12867675 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 2725843 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 25092 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 3697 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 5482930 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 182777 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 3937 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 92362358 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 3459969 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 41770 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 653469609 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.029599 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.281240 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 449143632 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 1300356824 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 439037695 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 284964072 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 654346336 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 13178215 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 2532163 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 23392 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 4389 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 4759392 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 175720 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 3551 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 298182140 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 3594914 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 39494 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 1117577293 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.251423 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.109409 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 511473047 78.27% 78.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 17746068 2.72% 80.99% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 17876069 2.74% 83.72% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 13147863 2.01% 85.73% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 28062649 4.29% 90.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 8778442 1.34% 91.37% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 9526239 1.46% 92.83% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 8304050 1.27% 94.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 38555182 5.90% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 718189985 64.26% 64.26% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 120476918 10.78% 75.04% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 17851977 1.60% 76.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 13155756 1.18% 77.82% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 181640077 16.25% 94.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 8775776 0.79% 94.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 9591150 0.86% 95.71% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 8236988 0.74% 96.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 39658666 3.55% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 653469609 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.189660 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.843329 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 194540645 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 337340525 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 103135857 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 13376974 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 5073310 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 19204285 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 1379859 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 627304700 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 4258915 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 5073310 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 201998899 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 27311844 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 261169019 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 108909949 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 49003878 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 612618911 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 137031 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 1952354 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 1962506 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 29516744 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents 3823 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 587164162 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 946758307 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 724795926 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 781641 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 494885886 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 92278271 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 15082252 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 13144529 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 75005032 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 98707880 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 83757072 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 13358555 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 14229040 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 581184996 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 15164742 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 582092616 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 825653 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 77569161 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 49788978 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 351791 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 653469609 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.890772 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.626680 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 1117577293 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.382924 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.134156 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 403258788 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 335088582 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 360694363 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 13294705 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 5232856 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 70476298 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 1375606 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 1352424044 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 4253100 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 5232856 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 410740551 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 28469825 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 258278982 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 366370165 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 48476952 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 1337170119 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 127982 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 1950398 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 1918017 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 29294510 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents 3829 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 1310108256 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 1925124078 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 1396779335 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 887250 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 1214507358 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 95600893 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 14870121 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 12952577 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 74043380 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 305276022 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 83874418 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 13450040 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 14282158 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 1304947133 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 14993052 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 1304763464 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 862160 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 81029622 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 50869342 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 350473 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 1117577293 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.167493 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.494205 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 424481416 64.96% 64.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 97055692 14.85% 79.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 42445288 6.50% 86.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 30251514 4.63% 90.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 22439866 3.43% 94.37% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 15693652 2.40% 96.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 10715111 1.64% 98.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 6223144 0.95% 99.36% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 4163926 0.64% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 477542007 42.73% 42.73% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 353173077 31.60% 74.33% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 93863937 8.40% 82.73% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 81886889 7.33% 90.06% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 73787788 6.60% 96.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 15804378 1.41% 98.07% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 10888709 0.97% 99.05% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 6347514 0.57% 99.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 4282994 0.38% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 653469609 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 1117577293 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 2929813 25.60% 25.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 22943 0.20% 25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 2467 0.02% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.82% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4683520 40.92% 66.74% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 3806309 33.26% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 2956708 25.80% 25.80% # attempts to use FU when none available
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+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.06% # attempts to use FU when none available
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+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.06% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4659115 40.65% 66.71% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 3815684 33.29% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 87 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 395178561 67.89% 67.89% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 1472120 0.25% 68.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 66548 0.01% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 83 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 18 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 58655 0.01% 68.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 104607338 17.97% 86.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 80709157 13.87% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 86 0.00% 0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 911406413 69.85% 69.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 1450716 0.11% 69.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 68809 0.01% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 242 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 74568 0.01% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 310913309 23.83% 93.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 80849259 6.20% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 582092616 # Type of FU issued
-system.cpu1.iq.rate 0.853695 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 11445052 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.019662 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 1828886082 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 674065927 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 561183745 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 1039464 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 516201 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 461714 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 592981793 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 555788 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 4619757 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 1304763464 # Type of FU issued
+system.cpu1.iq.rate 1.138000 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 11461380 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.008784 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 3738310574 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 1401077508 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 1283063938 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 1117187 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 574367 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 497584 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 1315629411 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 595347 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 4624780 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 15740565 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 19881 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 674311 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 8622171 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 16729306 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 20042 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 692952 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 8476645 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 3783711 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 7638228 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 3812143 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 7452647 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 5073310 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 16098431 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 8955476 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 596484662 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 1704911 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 98707880 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 83757072 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 12853261 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 236300 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 8632331 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 674311 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 2559005 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 2239379 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 4798384 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 575610941 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 102532690 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 5599160 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 5232856 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 16688704 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 9539057 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 1320087759 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 1712091 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 305276022 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 83874418 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 12664409 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 233480 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 9218245 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 692952 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 2475150 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 2684103 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 5159253 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 1297880089 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 308665532 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 5977092 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 134924 # number of nop insts executed
-system.cpu1.iew.exec_refs 182199156 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 106955524 # Number of branches executed
-system.cpu1.iew.exec_stores 79666466 # Number of stores executed
-system.cpu1.iew.exec_rate 0.844189 # Inst execution rate
-system.cpu1.iew.wb_sent 562846195 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 561645459 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 277406088 # num instructions producing a value
-system.cpu1.iew.wb_consumers 482095859 # num instructions consuming a value
-system.cpu1.iew.wb_rate 0.823707 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.575417 # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts 77620005 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 14812951 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 4280755 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 640233275 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.810299 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.807739 # Number of insts commited each cycle
+system.cpu1.iew.exec_nop 147574 # number of nop insts executed
+system.cpu1.iew.exec_refs 388478968 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 415337436 # Number of branches executed
+system.cpu1.iew.exec_stores 79813436 # Number of stores executed
+system.cpu1.iew.exec_rate 1.131996 # Inst execution rate
+system.cpu1.iew.wb_sent 1284971111 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 1283561522 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 586897530 # num instructions producing a value
+system.cpu1.iew.wb_consumers 1100487939 # num instructions consuming a value
+system.cpu1.iew.wb_rate 1.119508 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.533307 # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts 81091096 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 14642579 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 4433138 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 1103802352 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.122403 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.555476 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 449273024 70.17% 70.17% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 94745433 14.80% 84.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 32328499 5.05% 90.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 14864939 2.32% 92.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 10716802 1.67% 94.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 6304065 0.98% 95.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 5887950 0.92% 95.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 3832413 0.60% 96.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 22280150 3.48% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 502258397 45.50% 45.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 299485709 27.13% 72.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 134986499 12.23% 84.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 117786431 10.67% 95.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 10837119 0.98% 96.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 6401807 0.58% 97.10% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 5917729 0.54% 97.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 3800615 0.34% 97.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 22328046 2.02% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 640233275 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 441802027 # Number of instructions committed
-system.cpu1.commit.committedOps 518780572 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 1103802352 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 1161548854 # Number of instructions committed
+system.cpu1.commit.committedOps 1238910558 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 158102215 # Number of memory references committed
-system.cpu1.commit.loads 82967314 # Number of loads committed
-system.cpu1.commit.membars 3638779 # Number of memory barriers committed
-system.cpu1.commit.branches 98771468 # Number of branches committed
-system.cpu1.commit.fp_insts 442327 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 475908422 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 12958317 # Number of function calls committed.
+system.cpu1.commit.refs 363944488 # Number of memory references committed
+system.cpu1.commit.loads 288546715 # Number of loads committed
+system.cpu1.commit.membars 3671917 # Number of memory barriers committed
+system.cpu1.commit.branches 406943707 # Number of branches committed
+system.cpu1.commit.fp_insts 477645 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 1042234207 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 13083843 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 359445517 69.29% 69.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 1133059 0.22% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 49873 0.01% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 49866 0.01% 69.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 82967314 15.99% 85.52% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 75134901 14.48% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 873720787 70.52% 70.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 1128470 0.09% 70.61% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 51728 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 65043 0.01% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.62% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 288546715 23.29% 93.91% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 75397773 6.09% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 518780572 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 22280150 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 1210397617 # The number of ROB reads
-system.cpu1.rob.rob_writes 1206057669 # The number of ROB writes
-system.cpu1.timesIdled 4036845 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 28381286 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 48640587426 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 441802027 # Number of Instructions Simulated
-system.cpu1.committedOps 518780572 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 1.543340 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.543340 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.647945 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.647945 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 679308932 # number of integer regfile reads
-system.cpu1.int_regfile_writes 400707036 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 840716 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 480942 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 124429179 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 125518608 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 1192080281 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 14931224 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 40297 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40297 # Transaction distribution
+system.cpu1.commit.op_class_0::total 1238910558 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 22328046 # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads 2397538789 # The number of ROB reads
+system.cpu1.rob.rob_writes 2653800851 # The number of ROB writes
+system.cpu1.timesIdled 4140984 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 28963674 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 48004396286 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 1161548854 # Number of Instructions Simulated
+system.cpu1.committedOps 1238910558 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 0.987079 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.987079 # CPI: Total CPI of All Threads
+system.cpu1.ipc 1.013090 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.013090 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 1349751752 # number of integer regfile reads
+system.cpu1.int_regfile_writes 814694732 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 925132 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 580436 # number of floating regfile writes
+system.cpu1.cc_regfile_reads 432060294 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 433189790 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 2477616684 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 14758914 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 40289 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40289 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
@@ -1886,11 +1897,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353720 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
@@ -1905,100 +1916,100 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334176 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334176 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 47817000 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7492096 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 47809000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 346500 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 351500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 25488000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 25705000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 40144000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 40136000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 567038102 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 566925706 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 147696000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115457 # number of replacements
-system.iocache.tags.tagsinuse 10.419652 # Cycle average of tags in use
+system.iocache.tags.replacements 115449 # number of replacements
+system.iocache.tags.tagsinuse 10.471056 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115465 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13096643979000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.546599 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.873052 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.221662 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.429566 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.651228 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 13096638509000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.513940 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.957116 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.219621 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.434820 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.654441 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039641 # Number of tag accesses
-system.iocache.tags.data_accesses 1039641 # Number of data accesses
+system.iocache.tags.tag_accesses 1039569 # Number of tag accesses
+system.iocache.tags.data_accesses 1039569 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8804 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8841 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
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@@ -2012,55 +2023,55 @@ system.iocache.demand_miss_rate::total 1 # mi
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@@ -2385,290 +2398,294 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
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+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 180743.451613 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165735.226164 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172636.480895 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 177762.983216 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 176373.674747 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 168018.440272 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 158425.505544 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 168993.385810 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 158378.395521 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 54324 # Transaction distribution
-system.membus.trans_dist::ReadResp 474547 # Transaction distribution
-system.membus.trans_dist::WriteReq 33696 # Transaction distribution
-system.membus.trans_dist::WriteResp 33696 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1247532 # Transaction distribution
-system.membus.trans_dist::CleanEvict 221010 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 37031 # Transaction distribution
+system.membus.trans_dist::ReadReq 54348 # Transaction distribution
+system.membus.trans_dist::ReadResp 460331 # Transaction distribution
+system.membus.trans_dist::WriteReq 33708 # Transaction distribution
+system.membus.trans_dist::WriteResp 33708 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1231951 # Transaction distribution
+system.membus.trans_dist::CleanEvict 210742 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 37070 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
-system.membus.trans_dist::ReadExReq 523357 # Transaction distribution
-system.membus.trans_dist::ReadExResp 523357 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 420223 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 618325 # Transaction distribution
+system.membus.trans_dist::ReadExReq 519762 # Transaction distribution
+system.membus.trans_dist::ReadExResp 519762 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 405983 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 610510 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3816979 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 3946617 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237606 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 237606 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4184223 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3747708 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 3877418 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237430 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 237430 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4114848 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 134138156 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 134309854 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7248832 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7248832 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 141558686 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 2885 # Total snoops (count)
-system.membus.snoop_fanout::samples 3155536 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 132000044 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 132171886 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7238592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7238592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 139410478 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 3037 # Total snoops (count)
+system.membus.snoop_fanout::samples 3104114 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3155536 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3104114 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3155536 # Request fanout histogram
-system.membus.reqLayer0.occupancy 113887000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3104114 # Request fanout histogram
+system.membus.reqLayer0.occupancy 114095000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5512000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 5418502 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 8359087618 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 8237516188 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 5141778971 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 5046734585 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 44612371 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 44568865 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
@@ -2685,11 +2702,11 @@ system.realview.ethernet.descDMAReads 0 # Nu
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
@@ -2722,61 +2739,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 53860854 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 27356918 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 4389 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 2115 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 2115 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests 54620375 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 27739287 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 4920 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 2097 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 2097 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 2036938 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 25194555 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 9275862 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 16001570 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 2694937 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 46206 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 46216 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 2116229 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 2116229 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 16002213 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 7163507 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 1337442 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 1230778 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48047123 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31732395 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 915561 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2519584 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 83214663 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2049552896 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1107385822 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3096672 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8523576 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 3168558966 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 2116170 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 30205961 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.026968 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.161993 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 2026549 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 25559589 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty 9310073 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 16336648 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 2676872 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 46329 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 46336 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 2117344 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 2117344 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 16337404 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 7203745 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 1338061 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 1231397 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49052277 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31858634 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 875155 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2530262 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 84316328 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2092430528 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1113218798 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2941176 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8524552 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 3217115054 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 2099522 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 30547038 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.026857 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.161665 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 29391361 97.30% 97.30% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 814592 2.70% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 29726637 97.31% 97.31% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 820401 2.69% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 30205961 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 51608527894 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 30547038 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 52365395385 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 1422395 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 1392915 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 24050258287 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 24553415616 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 14601873318 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 14664140678 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 528950493 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 507934109 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 1457147305 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 1467755168 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 16352 # number of quiesce instructions executed