diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | |
parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 2543 |
1 files changed, 1270 insertions, 1273 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 369e97796..da1db81af 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.125717 # Number of seconds simulated -sim_ticks 5125716951000 # Number of ticks simulated -final_tick 5125716951000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133763 # Number of seconds simulated +sim_ticks 5133762710000 # Number of ticks simulated +final_tick 5133762710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 203249 # Simulator instruction rate (inst/s) -host_op_rate 401765 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2555120499 # Simulator tick rate (ticks/s) -host_mem_usage 728844 # Number of bytes of host memory used -host_seconds 2006.06 # Real time elapsed on the host -sim_insts 407728401 # Number of instructions simulated -sim_ops 805963181 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2441920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1027200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10734912 # Number of bytes read from this memory -system.physmem.bytes_read::total 14208320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1027200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1027200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9480000 # Number of bytes written to this memory -system.physmem.bytes_written::total 9480000 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38155 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167733 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222005 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148125 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148125 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 200401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2094324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2771967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 200401 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 200401 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1849497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1849497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1849497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 200401 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2094324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4621465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222005 # Total number of read requests seen -system.physmem.writeReqs 148125 # Total number of write requests seen -system.physmem.cpureqs 371863 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14208320 # Total number of bytes read from memory -system.physmem.bytesWritten 9480000 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14208320 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9480000 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 92 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13839 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 14596 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 13757 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13936 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13421 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13920 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 13971 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14183 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 13262 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9305 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 9392 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 9725 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 9208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 9406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 9142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8981 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8580 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8586 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 9338 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 10150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9429 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 9215 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8819 # Track writes on a per bank basis +host_inst_rate 199223 # Simulator instruction rate (inst/s) +host_op_rate 393808 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2508257843 # Simulator tick rate (ticks/s) +host_mem_usage 730904 # Number of bytes of host memory used +host_seconds 2046.74 # Real time elapsed on the host +sim_insts 407759186 # Number of instructions simulated +sim_ops 806023868 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2444032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1025408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10767936 # Number of bytes read from this memory +system.physmem.bytes_read::total 14241664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1025408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1025408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9508160 # Number of bytes written to this memory +system.physmem.bytes_written::total 9508160 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16022 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168249 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222526 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148565 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148565 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 476070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2097474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2774118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1852084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 476070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2097474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4626202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222526 # Total number of read requests seen +system.physmem.writeReqs 148565 # Total number of write requests seen +system.physmem.cpureqs 372829 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14241664 # Total number of bytes read from memory +system.physmem.bytesWritten 9508160 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14241664 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9508160 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1733 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14338 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13735 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 14393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 13573 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13866 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13175 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 13794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13878 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13620 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13949 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 13975 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 14441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14348 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 14346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 13392 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9773 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 9207 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 9622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 9014 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 9405 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 9183 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8703 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9254 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 9156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 9240 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 9684 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9527 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 9658 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8799 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 5125716897500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry +system.physmem.totGap 5133762656000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 222005 # Categorize read packet sizes +system.physmem.readPktSize::6 222526 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 148125 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 174153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 864 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148565 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 174531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2509 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 849 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 711 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see @@ -136,247 +136,244 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 754 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62409 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.447836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.150732 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1279.689060 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 27741 44.45% 44.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 9677 15.51% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 5899 9.45% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 3942 6.32% 75.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2509 4.02% 79.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 2016 3.23% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1522 2.44% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1230 1.97% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 938 1.50% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 940 1.51% 90.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 553 0.89% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 567 0.91% 92.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 409 0.66% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 381 0.61% 93.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 350 0.56% 94.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 427 0.68% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 299 0.48% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 221 0.35% 95.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 165 0.26% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 170 0.27% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 190 0.30% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 458 0.73% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 188 0.30% 97.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 102 0.16% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 75 0.12% 97.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 65 0.10% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 60 0.10% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 37 0.06% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 23 0.04% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 21 0.03% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 32 0.05% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 22 0.04% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 13 0.02% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 21 0.03% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 12 0.02% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 13 0.02% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 12 0.02% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 9 0.01% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 5 0.01% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 7 0.01% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 4 0.01% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 9 0.01% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 9 0.01% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 9 0.01% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 2 0.00% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 3 0.00% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 13 0.02% 98.70% # Bytes accessed per row activation +system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62801 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 377.966975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.936826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1272.632195 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 27908 44.44% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 9784 15.58% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 5938 9.46% 69.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 3957 6.30% 75.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2545 4.05% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 2018 3.21% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1524 2.43% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1187 1.89% 87.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 1022 1.63% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 897 1.43% 90.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 594 0.95% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 559 0.89% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 423 0.67% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 383 0.61% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 375 0.60% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 421 0.67% 94.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 292 0.46% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 205 0.33% 95.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 163 0.26% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 146 0.23% 96.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 144 0.23% 96.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 476 0.76% 97.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 183 0.29% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 124 0.20% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 88 0.14% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 60 0.10% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 51 0.08% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 42 0.07% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 29 0.05% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 32 0.05% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 30 0.05% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 17 0.03% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 11 0.02% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 16 0.03% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 17 0.03% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 10 0.02% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 13 0.02% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 7 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 4 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 8 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 3 0.00% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 6 0.01% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 8 0.01% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 6 0.01% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 6 0.01% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 8 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 4 0.01% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 8 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 7 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 4 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 2 0.00% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 3 0.00% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 8 0.01% 98.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 5 0.01% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 4 0.01% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 3 0.00% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 22 0.04% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 5 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 3 0.00% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 5 0.01% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 1 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 3 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 3 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 6 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 5 0.01% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 3 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 7 0.01% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 4 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 4 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 3 0.00% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 4 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 4 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 1 0.00% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 5 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 27 0.04% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 3 0.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 4 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 3 0.00% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4739 3 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 3 0.00% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 8 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 3 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5635 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 3 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 1 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 2 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6659 2 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 1 0.00% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 4 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 3 0.00% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 5 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 2 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 3 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7491 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 3 0.00% 98.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 3 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 4 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 2 0.00% 98.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 4 0.01% 98.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8195 337 0.54% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8259 2 0.00% 99.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 7 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 10 0.02% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 3 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12995 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9987 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 3 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13315 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14083 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 34 0.05% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 5 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 3 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 7 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 7 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 6 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 6 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 11 0.02% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 13 0.02% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 65 0.10% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17219 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62409 # Bytes accessed per row activation -system.physmem.totQLat 4001177249 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8265005999 # Sum of mem lat for all requests -system.physmem.totBusLat 1109565000 # Total cycles spent in databus access -system.physmem.totBankLat 3154263750 # Total cycles spent in bank access -system.physmem.avgQLat 18030.39 # Average queueing delay per request -system.physmem.avgBankLat 14213.97 # Average bank access latency per request +system.physmem.bytesPerActivate::14464-14467 2 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 3 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 33 0.05% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 11 0.02% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 12 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 9 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 8 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 6 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 5 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 3 0.00% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 7 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 6 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 3 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 10 0.02% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 5 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 10 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 6 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 10 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 63 0.10% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16963 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17155 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17856-17859 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18371 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62801 # Bytes accessed per row activation +system.physmem.totQLat 4020206249 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8301079999 # Sum of mem lat for all requests +system.physmem.totBusLat 1112255000 # Total cycles spent in databus access +system.physmem.totBankLat 3168618750 # Total cycles spent in bank access +system.physmem.avgQLat 18072.32 # Average queueing delay per request +system.physmem.avgBankLat 14244.12 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37244.35 # Average memory access latency +system.physmem.avgMemAccLat 37316.44 # Average memory access latency system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s @@ -384,99 +381,99 @@ system.physmem.avgConsumedWrBW 1.85 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.40 # Average write queue length over time -system.physmem.readRowHits 198637 # Number of row buffer hits during reads -system.physmem.writeRowHits 108987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads +system.physmem.avgWrQLen 13.16 # Average write queue length over time +system.physmem.readRowHits 198897 # Number of row buffer hits during reads +system.physmem.writeRowHits 109310 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes -system.physmem.avgGap 13848423.25 # Average gap between requests -system.membus.throughput 5098961 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662131 # Transaction distribution -system.membus.trans_dist::ReadResp 662131 # Transaction distribution -system.membus.trans_dist::WriteReq 13694 # Transaction distribution -system.membus.trans_dist::WriteResp 13694 # Transaction distribution -system.membus.trans_dist::Writeback 148125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2235 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1745 # Transaction distribution -system.membus.trans_dist::ReadExReq 179249 # Transaction distribution -system.membus.trans_dist::ReadExResp 179246 # Transaction distribution -system.membus.trans_dist::MessageReq 1640 # Transaction distribution -system.membus.trans_dist::MessageResp 1640 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473788 # Packet count per connected master and slave (bytes) +system.physmem.avgGap 13834241.89 # Average gap between requests +system.membus.throughput 5102506 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662304 # Transaction distribution +system.membus.trans_dist::ReadResp 662304 # Transaction distribution +system.membus.trans_dist::WriteReq 13698 # Transaction distribution +system.membus.trans_dist::WriteResp 13698 # Transaction distribution +system.membus.trans_dist::Writeback 148565 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2229 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1751 # Transaction distribution +system.membus.trans_dist::ReadExReq 179560 # Transaction distribution +system.membus.trans_dist::ReadExResp 179558 # Transaction distribution +system.membus.trans_dist::MessageReq 1642 # Transaction distribution +system.membus.trans_dist::MessageResp 1642 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475204 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719634 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 606242 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 607688 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1855368 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18259712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.pio 775072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.cpu.interrupts.int_slave 3284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1856826 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319104 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20051511 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5428608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5428608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 23688320 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20110919 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5430720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5430720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 23749824 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25486679 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25486679 # Total data (bytes) -system.membus.snoop_data_through_bus 649152 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1603689497 # Layer occupancy (ticks) +system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550141 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25548207 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25548207 # Total data (bytes) +system.membus.snoop_data_through_bus 646848 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1608355497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 250319000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 250293000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 583198000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 583289000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3280000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3284000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1640000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3152452403 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3156883661 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429424246 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429399995 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.replacements 47577 # number of replacements -system.iocache.tagsinuse 0.079131 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47593 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4992752531000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.079131 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.004946 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.004946 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses -system.iocache.ReadReq_misses::total 912 # number of ReadReq misses +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.103958 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4992794933000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103958 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006497 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006497 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses -system.iocache.demand_misses::total 47632 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses -system.iocache.overall_misses::total 47632 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152414185 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 152414185 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10346136346 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10346136346 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10498550531 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10498550531 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10498550531 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10498550531 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses +system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses +system.iocache.overall_misses::total 47629 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151796185 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 151796185 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10322328602 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10322328602 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10474124787 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10474124787 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10474124787 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10474124787 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -485,40 +482,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167120.816886 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167120.816886 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221449.836173 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 221449.836173 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220409.609737 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220409.609737 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 148997 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166992.502750 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 166992.502750 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 220940.252611 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 220940.252611 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 219910.659199 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 219910.659199 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 219910.659199 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 219910.659199 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 148616 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13662 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 13635 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.905943 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.899597 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104973685 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104973685 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7915976600 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7915976600 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8020950285 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8020950285 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104494685 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104494685 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7891444112 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7891444112 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7995938797 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7995938797 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7995938797 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7995938797 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -527,14 +524,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115102.724781 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115102.724781 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169434.430651 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 169434.430651 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114955.649065 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114955.649065 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 168909.334589 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 168909.334589 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 167879.627895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 167879.627895 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -548,13 +545,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 639145 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225496 # Transaction distribution -system.iobus.trans_dist::ReadResp 225496 # Transaction distribution +system.iobus.throughput 638140 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225493 # Transaction distribution +system.iobus.trans_dist::ReadResp 225493 # Transaction distribution system.iobus.trans_dist::WriteReq 57527 # Transaction distribution system.iobus.trans_dist::WriteResp 57527 # Transaction distribution -system.iobus.trans_dist::MessageReq 1640 # Transaction distribution -system.iobus.trans_dist::MessageResp 1640 # Transaction distribution +system.iobus.trans_dist::MessageReq 1642 # Transaction distribution +system.iobus.trans_dist::MessageResp 1642 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) @@ -574,11 +571,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 470782 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95264 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3280 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3284 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.apicbridge.slave 3284 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) @@ -596,9 +593,9 @@ system.iobus.pkt_count::system.pc.fake_com_2.pio 12 system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569326 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569324 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -618,11 +615,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 241674 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027840 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.apicbridge.slave 6568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -640,11 +637,11 @@ system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276074 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3909656 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 3276058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276058 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3920600 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -680,154 +677,154 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424474531 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424430792 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 459975000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52352000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53423005 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1640000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 85601186 # Number of BP lookups -system.cpu.branchPred.condPredicted 85601186 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 878782 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79197718 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77534768 # Number of BTB hits +system.cpu.branchPred.lookups 85618831 # Number of BP lookups +system.cpu.branchPred.condPredicted 85618831 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 881906 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79126559 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77540225 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.900255 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1440711 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 178764 # Number of incorrect RAS predictions. -system.cpu.numCycles 453375451 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.995194 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1441540 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180626 # Number of incorrect RAS predictions. +system.cpu.numCycles 453839632 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25513858 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422800544 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85601186 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78975479 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162663365 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3996734 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 101966 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 70853615 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 42658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 89309 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8479708 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 381834 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2341 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262338796 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.182647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25514423 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422776164 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85618831 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78981765 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162666633 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3997481 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 100403 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 71304729 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 44393 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94570 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 219 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8483452 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 380361 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2201 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262796476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.177336 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411374 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100089762 38.15% 38.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1543248 0.59% 38.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71824716 27.38% 66.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 898472 0.34% 66.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1568808 0.60% 67.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2394853 0.91% 67.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1014354 0.39% 68.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1328708 0.51% 68.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81675875 31.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100544783 38.26% 38.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1535684 0.58% 38.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71830288 27.33% 66.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 894888 0.34% 66.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1570094 0.60% 67.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2394528 0.91% 68.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1014297 0.39% 68.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1322217 0.50% 68.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81689697 31.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262338796 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188809 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.932562 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29417456 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68001358 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158506679 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3339559 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3073744 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832592947 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 926 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3073744 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32109829 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 42827309 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12461023 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158801746 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13065145 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829696742 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21430 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6044181 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5137835 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 10653 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 991365298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1800497636 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1800497180 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963871300 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27493996 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 453983 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 458205 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29510312 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16729516 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9820056 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1138043 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 956999 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824928716 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1184630 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820966425 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 150849 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19304203 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29360127 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 130755 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262338796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.129413 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.399539 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262796476 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188654 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.931554 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29415381 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68460720 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158509709 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3339560 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3071106 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832655242 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 935 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3071106 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32114015 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43120028 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12611794 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158799152 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13080381 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829727330 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21673 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6047730 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5146675 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 9377 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 991375726 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800594508 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1800594068 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 440 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963942859 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27432865 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 453030 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 459006 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29568179 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16736842 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9827220 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1098890 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 921986 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824947174 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1184809 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820992991 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 145624 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19292542 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29357019 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 130694 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262796476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.124064 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.400943 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 75996420 28.97% 28.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15740261 6.00% 34.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10531012 4.01% 38.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7367834 2.81% 41.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75736075 28.87% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3750663 1.43% 72.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72297854 27.56% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 773517 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 145160 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76438982 29.09% 29.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15751400 5.99% 35.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10538627 4.01% 39.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7358771 2.80% 41.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75737390 28.82% 70.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3750331 1.43% 72.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72306613 27.51% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 767765 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 146597 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262338796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262796476 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 351269 33.33% 33.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 200 0.02% 33.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1810 0.17% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547247 51.93% 85.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 153387 14.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 351017 33.38% 33.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 33.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 348 0.03% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547344 52.04% 85.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152992 14.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 304863 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793498796 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149830 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124227 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 308184 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793508376 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149615 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124401 0.02% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued @@ -854,280 +851,280 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17669358 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9219351 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17677574 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9224841 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820966425 # Type of FU issued -system.cpu.iq.rate 1.810787 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1053913 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905583532 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 845427964 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817056658 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821715388 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1694689 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820992991 # Type of FU issued +system.cpu.iq.rate 1.808994 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1051702 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001281 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1906088677 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845434927 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817071068 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 189 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 196 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821736420 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 89 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1694381 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2746767 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18051 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1403061 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2750139 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17720 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12102 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1408836 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931249 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12313 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931381 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12080 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3073744 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30976434 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2152665 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826113346 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 242094 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16729516 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9820056 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 689859 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1619870 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14784 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 494405 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 508019 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1002424 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819559028 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17368747 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1407396 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3071106 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31257120 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2152669 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826131983 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 242676 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16736842 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9827220 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 690491 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1620064 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13028 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12102 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 497258 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506632 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1003890 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819577252 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17369785 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1415738 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26403485 # number of memory reference insts executed -system.cpu.iew.exec_branches 83095032 # Number of branches executed -system.cpu.iew.exec_stores 9034738 # Number of stores executed -system.cpu.iew.exec_rate 1.807683 # Inst execution rate -system.cpu.iew.wb_sent 819157526 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817056708 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638600685 # num instructions producing a value -system.cpu.iew.wb_consumers 1043925557 # num instructions consuming a value +system.cpu.iew.exec_refs 26409608 # number of memory reference insts executed +system.cpu.iew.exec_branches 83098710 # Number of branches executed +system.cpu.iew.exec_stores 9039823 # Number of stores executed +system.cpu.iew.exec_rate 1.805874 # Inst execution rate +system.cpu.iew.wb_sent 819172462 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817071124 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638600161 # num instructions producing a value +system.cpu.iew.wb_consumers 1043929120 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.802164 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back +system.cpu.iew.wb_rate 1.800352 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 20041054 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1053875 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 888667 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259265052 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.108646 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863485 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19998846 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054115 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 892238 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259725370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.103370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863932 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87759364 33.85% 33.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11842879 4.57% 38.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3826328 1.48% 39.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74742270 28.83% 68.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2381968 0.92% 69.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1473831 0.57% 70.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 858574 0.33% 70.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70846339 27.33% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5533499 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88203628 33.96% 33.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11848657 4.56% 38.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3832219 1.48% 40.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74739253 28.78% 68.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2381920 0.92% 69.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1474779 0.57% 70.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 859132 0.33% 70.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70849609 27.28% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5536173 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259265052 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407728401 # Number of instructions committed -system.cpu.commit.committedOps 805963181 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259725370 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407759186 # Number of instructions committed +system.cpu.commit.committedOps 806023868 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22399743 # Number of memory references committed -system.cpu.commit.loads 13982748 # Number of loads committed -system.cpu.commit.membars 474399 # Number of memory barriers committed -system.cpu.commit.branches 82153759 # Number of branches committed +system.cpu.commit.refs 22405086 # Number of memory references committed +system.cpu.commit.loads 13986702 # Number of loads committed +system.cpu.commit.membars 474409 # Number of memory barriers committed +system.cpu.commit.branches 82159690 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734952654 # Number of committed integer instructions. -system.cpu.commit.function_calls 1154691 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5533499 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 735008844 # Number of committed integer instructions. +system.cpu.commit.function_calls 1154896 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5536173 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1079657633 # The number of ROB reads -system.cpu.rob.rob_writes 1655096826 # The number of ROB writes -system.cpu.timesIdled 1258785 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 191036655 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9798064041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407728401 # Number of Instructions Simulated -system.cpu.committedOps 805963181 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407728401 # Number of Instructions Simulated -system.cpu.cpi 1.111955 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.111955 # CPI: Total CPI of All Threads -system.cpu.ipc 0.899317 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.899317 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1504349061 # number of integer regfile reads -system.cpu.int_regfile_writes 975319683 # number of integer regfile writes -system.cpu.fp_regfile_reads 50 # number of floating regfile reads -system.cpu.misc_regfile_reads 264080509 # number of misc regfile reads -system.cpu.misc_regfile_writes 401987 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53625221 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3010668 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3010129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13694 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13694 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1578360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2289 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2289 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334262 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287551 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1907708 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6121795 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 17377 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 150658 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 8197538 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61043136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207549047 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 553408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5256448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 274402039 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 274377591 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 490112 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4031070918 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1080133651 # The number of ROB reads +system.cpu.rob.rob_writes 1655131261 # The number of ROB writes +system.cpu.timesIdled 1259877 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 191043156 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9813691352 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407759186 # Number of Instructions Simulated +system.cpu.committedOps 806023868 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407759186 # Number of Instructions Simulated +system.cpu.cpi 1.113009 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.113009 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898465 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898465 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1504423855 # number of integer regfile reads +system.cpu.int_regfile_writes 975340027 # number of integer regfile writes +system.cpu.fp_regfile_reads 56 # number of floating regfile reads +system.cpu.misc_regfile_reads 264091330 # number of misc regfile reads +system.cpu.misc_regfile_writes 402284 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53596956 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3010019 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3009469 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1583020 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334736 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288025 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1906694 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6122854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 16266 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 154977 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 8200791 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61010496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207591623 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 510912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5512832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 274625863 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 274602311 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 551744 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4037956918 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 552000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1431698822 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1434043234 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3102593965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3142652791 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 13102485 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 12430241 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 102839393 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 103328135 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 953322 # number of replacements -system.cpu.icache.tagsinuse 510.127378 # Cycle average of tags in use -system.cpu.icache.total_refs 7473092 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 953834 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.834793 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 147390294000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.127378 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996343 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996343 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7473092 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7473092 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7473092 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7473092 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7473092 # number of overall hits -system.cpu.icache.overall_hits::total 7473092 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1006614 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1006614 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1006614 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1006614 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1006614 # number of overall misses -system.cpu.icache.overall_misses::total 1006614 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14222924496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14222924496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14222924496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14222924496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14222924496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14222924496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8479706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8479706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8479706 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8479706 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8479706 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8479706 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118709 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.118709 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.118709 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.118709 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.118709 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.118709 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14129.472167 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14129.472167 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14129.472167 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14129.472167 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8172 # number of cycles access was blocked +system.cpu.icache.tags.replacements 952820 # number of replacements +system.cpu.icache.tags.tagsinuse 509.973198 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7477461 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 953332 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.843502 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147437101250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.973198 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996041 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996041 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7477461 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7477461 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7477461 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7477461 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7477461 # number of overall hits +system.cpu.icache.overall_hits::total 7477461 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1005989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1005989 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1005989 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1005989 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1005989 # number of overall misses +system.cpu.icache.overall_misses::total 1005989 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14232079935 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14232079935 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14232079935 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14232079935 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14232079935 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14232079935 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8483450 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8483450 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8483450 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8483450 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8483450 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8483450 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118583 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.118583 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.118583 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.118583 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.118583 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.118583 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14147.351447 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14147.351447 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14147.351447 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14147.351447 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14147.351447 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14147.351447 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6191 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 174 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.238095 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 35.580460 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52705 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 52705 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 52705 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 52705 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 52705 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 52705 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953909 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 953909 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 953909 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 953909 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 953909 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 953909 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11745970674 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11745970674 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11745970674 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11745970674 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11745970674 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11745970674 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112493 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.112493 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.112493 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12313.512792 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12313.512792 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52584 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 52584 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 52584 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 52584 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 52584 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 52584 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953405 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 953405 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 953405 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 953405 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 953405 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 953405 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11737352011 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11737352011 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11737352011 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11737352011 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11737352011 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11737352011 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112384 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.112384 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112384 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112384 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12310.982228 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12310.982228 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12310.982228 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12310.982228 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12310.982228 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 7857 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.317656 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 21864 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 7868 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.778851 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5104284128000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.317656 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.394853 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.394853 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21875 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 21875 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 7402 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.006857 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 21909 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 7416 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.954288 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5104253177000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006857 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375429 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.375429 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21911 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 21911 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21877 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 21877 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21877 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 21877 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8730 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 8730 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8730 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 8730 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8730 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 8730 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 99800500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 99800500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 99800500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 99800500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 99800500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 99800500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30605 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30605 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21913 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 21913 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21913 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 21913 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8283 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 8283 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8283 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 8283 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8283 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 8283 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 92582993 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 92582993 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 92582993 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 92582993 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 92582993 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 92582993 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30194 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30194 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30607 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30607 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30607 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30607 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285248 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285248 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285229 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.285229 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285229 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.285229 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11431.901489 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11431.901489 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11431.901489 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11431.901489 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30196 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30196 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30196 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30196 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.274326 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.274326 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.274308 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.274308 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.274308 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.274308 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11177.471085 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11177.471085 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11177.471085 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11177.471085 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11177.471085 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11177.471085 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1136,78 +1133,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1569 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1569 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8730 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8730 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8730 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 8730 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8730 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 8730 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 82333015 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 82333015 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 82333015 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 82333015 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 82333015 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 82333015 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285248 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285248 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285229 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285229 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9431.044101 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1499 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1499 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8283 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8283 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8283 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 8283 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8283 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 8283 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 76005511 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 76005511 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 76005511 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 76005511 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 76005511 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 76005511 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.274326 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.274326 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.274308 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.274308 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.274308 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.274308 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9176.084873 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9176.084873 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9176.084873 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9176.084873 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 67431 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 14.830291 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 90986 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 67447 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.349000 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 4994048518000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.830291 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.926893 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.926893 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90986 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 90986 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90986 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 90986 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90986 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 90986 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68526 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 68526 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68526 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 68526 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68526 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 68526 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 854232500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 854232500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 854232500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 854232500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 854232500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 854232500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 159512 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 159512 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 159512 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 159512 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 159512 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 159512 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429598 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429598 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429598 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429598 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429598 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429598 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12465.815895 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.815895 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.815895 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12465.815895 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 67804 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 13.886481 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 92487 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 67819 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.363733 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101460528500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.886481 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.867905 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.867905 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92498 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 92498 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92498 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 92498 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92498 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 92498 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68839 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 68839 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68839 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 68839 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68839 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 68839 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 851625712 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 851625712 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 851625712 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 851625712 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 851625712 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 851625712 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161337 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 161337 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161337 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 161337 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161337 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 161337 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.426678 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.426678 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.426678 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.426678 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.426678 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.426678 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12371.267915 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12371.267915 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12371.267915 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12371.267915 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12371.267915 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12371.267915 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1216,146 +1213,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 18479 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 18479 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68526 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68526 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68526 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 68526 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68526 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 68526 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 717130107 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 717130107 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 717130107 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 717130107 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 717130107 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 717130107 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429598 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429598 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429598 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10465.080510 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 23017 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 23017 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68839 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68839 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68839 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 68839 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68839 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 68839 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 713808442 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 713808442 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 713808442 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 713808442 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 713808442 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 713808442 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.426678 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.426678 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.426678 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.426678 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10369.244789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10369.244789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10369.244789 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1656381 # number of replacements -system.cpu.dcache.tagsinuse 511.996762 # Cycle average of tags in use -system.cpu.dcache.total_refs 18981789 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1656893 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.456255 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 37864000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.996762 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10887156 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10887156 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8091896 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8091896 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18979052 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18979052 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18979052 # number of overall hits -system.cpu.dcache.overall_hits::total 18979052 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2237799 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2237799 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315625 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315625 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2553424 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2553424 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2553424 # number of overall misses -system.cpu.dcache.overall_misses::total 2553424 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33108471000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33108471000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12021128996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12021128996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45129599996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45129599996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45129599996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45129599996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13124955 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13124955 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8407521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8407521 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21532476 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21532476 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21532476 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21532476 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170500 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170500 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037541 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037541 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118585 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118585 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118585 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118585 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14795.104922 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14795.104922 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38086.745334 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38086.745334 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17674.150472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17674.150472 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 405217 # number of cycles access was blocked +system.cpu.dcache.tags.replacements 1656828 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997492 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18985847 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657340 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.455614 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10890330 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10890330 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8092849 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8092849 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 18983179 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18983179 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18983179 # number of overall hits +system.cpu.dcache.overall_hits::total 18983179 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2236067 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2236067 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316060 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316060 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2552127 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2552127 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2552127 # number of overall misses +system.cpu.dcache.overall_misses::total 2552127 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33180539725 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33180539725 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12164482246 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12164482246 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45345021971 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45345021971 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45345021971 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45345021971 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13126397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13126397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8408909 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8408909 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21535306 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21535306 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21535306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21535306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170349 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170349 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037586 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037586 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118509 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118509 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118509 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118509 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.794958 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.794958 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38487.889154 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38487.889154 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17767.541337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17767.541337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17767.541337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17767.541337 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 401774 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42719 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42434 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.485639 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.468209 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558312 # number of writebacks -system.cpu.dcache.writebacks::total 1558312 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868331 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 868331 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25900 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25900 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 894231 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 894231 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 894231 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 894231 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369468 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1369468 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289725 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289725 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1659193 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1659193 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1659193 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1659193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17883109030 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17883109030 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11189452001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11189452001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29072561031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29072561031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29072561031 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29072561031 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349104500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349104500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2521383000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2521383000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99870487500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99870487500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104341 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104341 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034460 # 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