diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:41:27 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:41:27 -0500 |
| commit | af2e83c7f13098b66ceb6ba69599f1959da44ea1 (patch) | |
| tree | a634f32d705cb32d614dcd43d819d8e3e26dd547 /tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing | |
| parent | 22b60c57e697289baa205f11b164f356363c2bee (diff) | |
| download | gem5-af2e83c7f13098b66ceb6ba69599f1959da44ea1.tar.xz | |
x86, regressions: updates stats
This is due to op class, function call, walker patches.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 2029 |
1 files changed, 1013 insertions, 1016 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 77940f18e..8f4e7d03c 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.132953 # Number of seconds simulated -sim_ticks 5132953103000 # Number of ticks simulated -final_tick 5132953103000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.140938 # Number of seconds simulated +sim_ticks 5140937585000 # Number of ticks simulated +final_tick 5140937585000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118788 # Simulator instruction rate (inst/s) -host_op_rate 234812 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1494512187 # Simulator tick rate (ticks/s) -host_mem_usage 768808 # Number of bytes of host memory used -host_seconds 3434.53 # Real time elapsed on the host -sim_insts 407981680 # Number of instructions simulated -sim_ops 806469686 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2427072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1080064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10859584 # Number of bytes read from this memory -system.physmem.bytes_read::total 14370176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1080064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1080064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9570112 # Number of bytes written to this memory -system.physmem.bytes_written::total 9570112 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 37923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16876 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169681 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224534 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149533 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149533 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 472841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2115660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2799592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1864446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1864446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1864446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 472841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2115660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4664038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 224534 # Total number of read requests seen -system.physmem.writeReqs 149533 # Total number of write requests seen -system.physmem.cpureqs 378540 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14370176 # Total number of bytes read from memory -system.physmem.bytesWritten 9570112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14370176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9570112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 118 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4466 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14182 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13672 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13087 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 16327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13931 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 15686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13366 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15652 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8678 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8635 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 11642 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8788 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8537 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8431 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 11660 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 9003 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 11092 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8524 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8172 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8641 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 11087 # Track writes on a per bank basis +host_inst_rate 121697 # Simulator instruction rate (inst/s) +host_op_rate 240559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1534230705 # Simulator tick rate (ticks/s) +host_mem_usage 773616 # Number of bytes of host memory used +host_seconds 3350.82 # Real time elapsed on the host +sim_insts 407786881 # Number of instructions simulated +sim_ops 806071515 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2479872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1026240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10765120 # Number of bytes read from this memory +system.physmem.bytes_read::total 14275328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1026240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1026240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9536256 # Number of bytes written to this memory +system.physmem.bytes_written::total 9536256 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38748 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16035 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168205 # Number of read requests responded to by this memory +system.physmem.num_reads::total 223052 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149004 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149004 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2093999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2776795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199621 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199621 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1854964 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1854964 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1854964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2093999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4631759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 223052 # Total number of read requests seen +system.physmem.writeReqs 149004 # Total number of write requests seen +system.physmem.cpureqs 373790 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14275328 # Total number of bytes read from memory +system.physmem.bytesWritten 9536256 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14275328 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9536256 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 13636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13124 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13111 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13382 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13394 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 15885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13088 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12601 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13202 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15809 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 8387 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8583 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 11810 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8818 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8522 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 11661 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8790 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8601 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8761 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 11230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8431 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8093 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8583 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 11174 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 5132953050000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry +system.physmem.totGap 5140937531500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 224534 # Categorize read packet sizes +system.physmem.readPktSize::6 223052 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 149533 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 174096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 19313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1047 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149004 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 172997 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 18175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -136,92 +136,92 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.totQLat 4726159249 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9244557999 # Sum of mem lat for all requests -system.physmem.totBusLat 1122080000 # Total cycles spent in databus access -system.physmem.totBankLat 3396318750 # Total cycles spent in bank access -system.physmem.avgQLat 21059.81 # Average queueing delay per request -system.physmem.avgBankLat 15134.03 # Average bank access latency per request +system.physmem.totQLat 4794975750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9301923250 # Sum of mem lat for all requests +system.physmem.totBusLat 1114905000 # Total cycles spent in databus access +system.physmem.totBankLat 3392042500 # Total cycles spent in bank access +system.physmem.avgQLat 21503.97 # Average queueing delay per request +system.physmem.avgBankLat 15212.25 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41193.85 # Average memory access latency -system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 41716.21 # Average memory access latency +system.physmem.avgRdBW 2.78 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.69 # Average write queue length over time -system.physmem.readRowHits 193610 # Number of row buffer hits during reads -system.physmem.writeRowHits 105925 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.84 # Row buffer hit rate for writes -system.physmem.avgGap 13722015.17 # Average gap between requests -system.iocache.replacements 47570 # number of replacements -system.iocache.tagsinuse 0.103974 # Cycle average of tags in use +system.physmem.avgWrQLen 15.58 # Average write queue length over time +system.physmem.readRowHits 191257 # Number of row buffer hits during reads +system.physmem.writeRowHits 105612 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.88 # Row buffer hit rate for writes +system.physmem.avgGap 13817644.47 # Average gap between requests +system.iocache.replacements 47576 # number of replacements +system.iocache.tagsinuse 0.128763 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991995541000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.103974 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006498 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006498 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 905 # number of ReadReq misses +system.iocache.warmup_cycle 4991974997000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.128763 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.008048 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.008048 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses -system.iocache.demand_misses::total 47625 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses -system.iocache.overall_misses::total 47625 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 145555660 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 145555660 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10008674105 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10008674105 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10154229765 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10154229765 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10154229765 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10154229765 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses +system.iocache.demand_misses::total 47631 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses +system.iocache.overall_misses::total 47631 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147497397 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 147497397 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10072244306 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10072244306 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10219741703 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10219741703 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10219741703 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10219741703 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -230,40 +230,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160834.983425 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 160834.983425 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214226.757384 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 214226.757384 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213212.173543 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 213212.173543 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213212.173543 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 213212.173543 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 133059 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 161907.131723 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 161907.131723 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215587.420933 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 215587.420933 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 214560.721022 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 214560.721022 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 139153 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12235 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12645 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.875276 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.004587 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 905 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47625 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47625 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47625 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47625 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98473941 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 98473941 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7577901783 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7577901783 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7676375724 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7676375724 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7676375724 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7676375724 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100104427 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100104427 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7641446543 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7641446543 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7741550970 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7741550970 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -272,18 +272,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108810.984530 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 108810.984530 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162198.240218 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 162198.240218 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161183.742236 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 161183.742236 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161183.742236 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 161183.742236 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 109884.113063 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 109884.113063 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163558.359225 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 163558.359225 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -293,410 +293,410 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 86237029 # Number of BP lookups -system.cpu.branchPred.condPredicted 86237029 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1109949 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 81299216 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79239397 # Number of BTB hits +system.cpu.branchPred.lookups 85620726 # Number of BP lookups +system.cpu.branchPred.condPredicted 85620726 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 882198 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79268619 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77534559 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.466373 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.numCycles 448469531 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.812426 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1442315 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180251 # Number of incorrect RAS predictions. +system.cpu.numCycles 447791761 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27529474 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 426122909 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86237029 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79239397 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163627324 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4728707 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 117219 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 63156445 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36498 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 53889 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 420 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9038392 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 487130 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2791 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 258101520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.259173 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.417982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25559948 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422856490 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85620726 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78976874 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162677741 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4000997 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 98298 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 65919320 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 43594 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86507 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 459 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8492083 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 383635 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2345 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257461374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.243647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.415529 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94901402 36.77% 36.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1566001 0.61% 37.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71924847 27.87% 65.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 935145 0.36% 65.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1600289 0.62% 66.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2428838 0.94% 67.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1075499 0.42% 67.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1377865 0.53% 68.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82291634 31.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95198026 36.98% 36.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1534816 0.60% 37.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71825104 27.90% 65.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 895357 0.35% 65.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1570607 0.61% 66.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2391332 0.93% 67.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1020158 0.40% 67.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1325162 0.51% 68.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81700812 31.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 258101520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192292 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.950171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31223769 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60616281 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159439032 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3242187 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3580251 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838065302 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 921 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3580251 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33968457 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37481730 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11034324 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159610574 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12426184 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834407058 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18980 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5821881 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4760224 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8257 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 995986207 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1811362671 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1811361735 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 936 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964469787 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31516413 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 458013 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 465231 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28772388 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17093245 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10135018 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1252851 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1005934 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828306143 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1250828 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823325440 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 150511 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22168488 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33636711 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 196648 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 258101520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.189929 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.384557 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257461374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.191207 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.944315 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29461192 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63064302 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158550724 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3309649 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3075507 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832761340 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 863 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3075507 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32153278 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38465118 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12079112 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158824437 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12863922 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829829025 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19879 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6055166 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4924546 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11525 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 991492877 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800847756 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1800847292 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 464 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963999366 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27493506 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 456551 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 462682 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29304477 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16752339 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9837983 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1099709 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 928773 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 825036488 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1186686 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 821069910 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 146070 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19309743 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29357166 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 131932 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257461374 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.189099 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.383585 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71580535 27.73% 27.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15499802 6.01% 33.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10327986 4.00% 37.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7455254 2.89% 40.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75927506 29.42% 70.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3856019 1.49% 71.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72517162 28.10% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 787235 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 150021 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71259249 27.68% 27.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15575755 6.05% 33.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10479111 4.07% 37.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7383615 2.87% 40.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75752504 29.42% 70.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3772068 1.47% 71.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72307575 28.08% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 782694 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 148803 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 258101520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257461374 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 366750 34.22% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553108 51.61% 85.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 151931 14.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 356313 33.63% 33.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 241 0.02% 33.66% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 2452 0.23% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547502 51.68% 85.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 152922 14.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 309801 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795758940 96.65% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17866354 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9390345 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 308526 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793557907 96.65% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150412 0.02% 96.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124298 0.02% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17694567 2.16% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9234200 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823325440 # Type of FU issued -system.cpu.iq.rate 1.835856 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1071789 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001302 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1906104602 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851735215 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818848735 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 378 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 94 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 824087257 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 171 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1645357 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 821069910 # Type of FU issued +system.cpu.iq.rate 1.833598 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1059430 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001290 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1900915279 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845543458 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 817157785 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 194 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821820724 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1686147 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3104742 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 23669 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11440 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1716567 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2748440 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17101 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11930 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1411969 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932461 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11842 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931504 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11624 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3580251 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26245227 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2113533 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829556971 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 304073 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17093245 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10135018 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 718533 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1617499 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11192 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11440 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 653820 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 594083 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1247903 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821445654 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17451760 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1879785 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3075507 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26873503 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2150322 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826223174 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241070 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16752339 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9837983 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 692103 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1621529 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12267 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11930 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 498132 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506603 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1004735 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819660888 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17391685 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1409021 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26608752 # number of memory reference insts executed -system.cpu.iew.exec_branches 83225006 # Number of branches executed -system.cpu.iew.exec_stores 9156992 # Number of stores executed -system.cpu.iew.exec_rate 1.831664 # Inst execution rate -system.cpu.iew.wb_sent 820984205 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818848829 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639993786 # num instructions producing a value -system.cpu.iew.wb_consumers 1045886534 # num instructions consuming a value +system.cpu.iew.exec_refs 26440023 # number of memory reference insts executed +system.cpu.iew.exec_branches 83107253 # Number of branches executed +system.cpu.iew.exec_stores 9048338 # Number of stores executed +system.cpu.iew.exec_rate 1.830451 # Inst execution rate +system.cpu.iew.wb_sent 819258374 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 817157837 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638799704 # num instructions producing a value +system.cpu.iew.wb_consumers 1044337102 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.825874 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611915 # average fanout of values written-back +system.cpu.iew.wb_rate 1.824861 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611680 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22977930 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054178 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1115022 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254521269 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.168575 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.855004 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 20042352 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054753 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 891546 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254385866 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.168696 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.858566 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82765060 32.52% 32.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11818595 4.64% 37.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3860584 1.52% 38.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74956276 29.45% 68.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2441275 0.96% 69.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1480165 0.58% 69.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 888603 0.35% 70.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70922136 27.86% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5388575 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82972146 32.62% 32.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11724447 4.61% 37.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3813249 1.50% 38.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74747378 29.38% 68.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2384925 0.94% 69.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1476326 0.58% 69.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 865615 0.34% 69.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70850824 27.85% 97.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5550956 2.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254521269 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407981680 # Number of instructions committed -system.cpu.commit.committedOps 806469686 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254385866 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407786881 # Number of instructions committed +system.cpu.commit.committedOps 806071515 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22406951 # Number of memory references committed -system.cpu.commit.loads 13988500 # Number of loads committed -system.cpu.commit.membars 474453 # Number of memory barriers committed -system.cpu.commit.branches 82201236 # Number of branches committed +system.cpu.commit.refs 22429911 # Number of memory references committed +system.cpu.commit.loads 14003897 # Number of loads committed +system.cpu.commit.membars 474463 # Number of memory barriers committed +system.cpu.commit.branches 82163817 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735408262 # Number of committed integer instructions. -system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5388575 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 735061477 # Number of committed integer instructions. +system.cpu.commit.function_calls 1156045 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5550956 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1078502153 # The number of ROB reads -system.cpu.rob.rob_writes 1662494402 # The number of ROB writes -system.cpu.timesIdled 1221401 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190368011 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9817434094 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407981680 # Number of Instructions Simulated -system.cpu.committedOps 806469686 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407981680 # Number of Instructions Simulated -system.cpu.cpi 1.099239 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.099239 # CPI: Total CPI of All Threads -system.cpu.ipc 0.909720 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.909720 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1507130605 # number of integer regfile reads -system.cpu.int_regfile_writes 977067823 # number of integer regfile writes -system.cpu.fp_regfile_reads 94 # number of floating regfile reads -system.cpu.misc_regfile_reads 264732336 # number of misc regfile reads -system.cpu.misc_regfile_writes 402254 # number of misc regfile writes -system.cpu.icache.replacements 1049385 # number of replacements -system.cpu.icache.tagsinuse 509.447090 # Cycle average of tags in use -system.cpu.icache.total_refs 7923264 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1049897 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.546706 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56158934000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.447090 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.995014 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.995014 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7923264 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7923264 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7923264 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7923264 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7923264 # number of overall hits -system.cpu.icache.overall_hits::total 7923264 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1115125 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1115125 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1115125 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1115125 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1115125 # number of overall misses -system.cpu.icache.overall_misses::total 1115125 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15322207492 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15322207492 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15322207492 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15322207492 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15322207492 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15322207492 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9038389 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9038389 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9038389 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9038389 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9038389 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9038389 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123377 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123377 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123377 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123377 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123377 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123377 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13740.349729 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13740.349729 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13740.349729 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13740.349729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13740.349729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13740.349729 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 10877 # number of cycles access was blocked +system.cpu.rob.rob_reads 1074870508 # The number of ROB reads +system.cpu.rob.rob_writes 1655318425 # The number of ROB writes +system.cpu.timesIdled 1256763 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190330387 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9834088814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407786881 # Number of Instructions Simulated +system.cpu.committedOps 806071515 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407786881 # Number of Instructions Simulated +system.cpu.cpi 1.098102 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.098102 # CPI: Total CPI of All Threads +system.cpu.ipc 0.910662 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.910662 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1504614065 # number of integer regfile reads +system.cpu.int_regfile_writes 975429838 # number of integer regfile writes +system.cpu.fp_regfile_reads 52 # number of floating regfile reads +system.cpu.misc_regfile_reads 264130300 # number of misc regfile reads +system.cpu.misc_regfile_writes 403010 # number of misc regfile writes +system.cpu.icache.replacements 955437 # number of replacements +system.cpu.icache.tagsinuse 509.903328 # Cycle average of tags in use +system.cpu.icache.total_refs 7482159 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 955949 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.826944 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 146514700000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.903328 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.995905 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.995905 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7482159 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7482159 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7482159 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7482159 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7482159 # number of overall hits +system.cpu.icache.overall_hits::total 7482159 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1009922 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1009922 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1009922 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1009922 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1009922 # number of overall misses +system.cpu.icache.overall_misses::total 1009922 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13938284992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13938284992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13938284992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13938284992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13938284992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13938284992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8492081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8492081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8492081 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8492081 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8492081 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8492081 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13801.348017 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8199 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 301 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 36.136213 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.389163 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62547 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 62547 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 62547 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 62547 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 62547 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 62547 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1052578 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1052578 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1052578 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1052578 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1052578 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1052578 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12612158993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12612158993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12612158993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12612158993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12612158993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12612158993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116456 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116456 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116456 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116456 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116456 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116456 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11982.160935 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11982.160935 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11982.160935 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11982.160935 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11982.160935 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11982.160935 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53908 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53908 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53908 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53908 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11502740492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11502740492 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11502740492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112577 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.112577 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112577 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.979126 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.979126 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 8504 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.007408 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 27369 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 8519 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 3.212701 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5106816403500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.007408 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375463 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375463 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27369 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 27369 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 7960 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.326712 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 20386 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 7973 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.556879 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5107329698000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.326712 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.395420 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.395420 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20403 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 20403 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27371 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 27371 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27371 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 27371 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9373 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9373 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9373 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 9373 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 104966500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 104966500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 104966500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 104966500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 104966500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 104966500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36742 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 36742 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20405 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 20405 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20405 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 20405 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8843 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 8843 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8843 # 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number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 29246 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36744 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 36744 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36744 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 36744 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.255103 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.255103 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.255089 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.255089 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.255089 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.255089 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11198.815747 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11198.815747 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11198.815747 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11198.815747 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11198.815747 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11198.815747 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 29248 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 29248 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 29248 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 29248 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.302366 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.302366 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.302345 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.302345 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.302345 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.302345 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10948.942667 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10948.942667 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10948.942667 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10948.942667 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10948.942667 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10948.942667 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -705,78 +705,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1896 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1896 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9373 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9373 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9373 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9373 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9373 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9373 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86220500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86220500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86220500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86220500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86220500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86220500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.255103 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.255103 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.255089 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.255089 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.255089 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.255089 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9198.815747 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9198.815747 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9198.815747 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9198.815747 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9198.815747 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9198.815747 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1394 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1394 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8843 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8843 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8843 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 8843 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8843 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 8843 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 79135500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 79135500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 79135500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 79135500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 79135500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 79135500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.302366 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.302366 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.302345 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.302345 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8948.942667 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 107843 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.947477 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 134583 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 107858 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.247779 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5099863447000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.947477 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809217 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.809217 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134601 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 134601 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134601 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 134601 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134601 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 134601 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108812 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 108812 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108812 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 108812 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108812 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 108812 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1371802000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1371802000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1371802000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1371802000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1371802000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1371802000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243413 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 243413 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243413 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 243413 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243413 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 243413 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447026 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447026 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447026 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447026 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447026 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447026 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12607.083778 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12607.083778 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12607.083778 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12607.083778 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12607.083778 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12607.083778 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 67560 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 14.837353 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 92239 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 67575 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.364987 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100574572500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.837353 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.927335 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.927335 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92240 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 92240 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92240 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 92240 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92240 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 92240 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68644 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 68644 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68644 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 68644 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68644 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 68644 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 852599000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 852599000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 852599000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 852599000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 852599000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 852599000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160884 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 160884 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160884 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 160884 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160884 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 160884 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.426668 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.426668 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.426668 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.426668 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.426668 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.426668 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12420.590292 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12420.590292 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12420.590292 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12420.590292 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -785,146 +785,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 34946 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 34946 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108812 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108812 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108812 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 108812 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108812 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 108812 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1154178000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1154178000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1154178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1154178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1154178000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1154178000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447026 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447026 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447026 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447026 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447026 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447026 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10607.083778 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10607.083778 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10607.083778 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 19876 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 19876 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68644 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68644 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68644 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 68644 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68644 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 68644 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 715311000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 715311000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 715311000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 715311000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 715311000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 715311000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.426668 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.426668 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.426668 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10420.590292 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1657617 # number of replacements -system.cpu.dcache.tagsinuse 511.997737 # Cycle average of tags in use -system.cpu.dcache.total_refs 19103102 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1658129 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.520878 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27986000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997737 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11006955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11006955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8090467 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8090467 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19097422 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19097422 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19097422 # number of overall hits -system.cpu.dcache.overall_hits::total 19097422 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2237002 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2237002 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318492 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318492 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2555494 # 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number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13243957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13243957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8408959 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8408959 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21652916 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21652916 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21652916 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21652916 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168907 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.168907 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037875 # 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number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103518 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103518 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034730 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034730 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076804 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076804 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076804 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076804 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12704.874299 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12704.874299 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30268.664186 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30268.664186 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15789.233505 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15789.233505 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15789.233505 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15789.233505 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1557214 # number of writebacks +system.cpu.dcache.writebacks::total 1557214 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 870911 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 870911 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25892 # 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