diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:15:59 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:15:59 -0400 |
commit | b387d8e2136b6eccf590e5223096dce6830a66ec (patch) | |
tree | e1ec53e315c313a54a612b54b74164375dcc0a1d /tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing | |
parent | 6f6adbf0f6a4ca96cf44a24ea575860af56eb7b2 (diff) | |
download | gem5-b387d8e2136b6eccf590e5223096dce6830a66ec.tar.xz |
stats: Update the stats to reflect the 1GHz default system clock
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 1940 |
1 files changed, 970 insertions, 970 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 0613cfd5e..46e54af4f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.128875 # Number of seconds simulated -sim_ticks 5128875494000 # Number of ticks simulated -final_tick 5128875494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.132866 # Number of seconds simulated +sim_ticks 5132866386000 # Number of ticks simulated +final_tick 5132866386000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179743 # Simulator instruction rate (inst/s) -host_op_rate 355302 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2259848354 # Simulator tick rate (ticks/s) -host_mem_usage 404644 # Number of bytes of host memory used -host_seconds 2269.57 # Real time elapsed on the host -sim_insts 407937807 # Number of instructions simulated -sim_ops 806381430 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2484160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1082048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10897856 # Number of bytes read from this memory -system.physmem.bytes_read::total 14467456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1082048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1082048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9613376 # Number of bytes written to this memory -system.physmem.bytes_written::total 9613376 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38815 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 170279 # Number of read requests responded to by this memory -system.physmem.num_reads::total 226054 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 150209 # Number of write requests responded to by this memory -system.physmem.num_writes::total 150209 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 484348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2124804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2820785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1874363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1874363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1874363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 484348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2124804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4695148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 226054 # Total number of read requests seen -system.physmem.writeReqs 150209 # Total number of write requests seen -system.physmem.cpureqs 390083 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14467456 # Total number of bytes read from memory -system.physmem.bytesWritten 9613376 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14467456 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9613376 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 85 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3870 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 13592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 14674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12790 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 14969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 14849 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12900 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13720 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 14770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 14195 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 14927 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13783 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12863 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15009 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 10212 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 10302 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8995 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 10163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9599 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8962 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 10025 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 9289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 10268 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8898 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 10138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8164 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 10156 # Track writes on a per bank basis +host_inst_rate 195837 # Simulator instruction rate (inst/s) +host_op_rate 387119 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2464119438 # Simulator tick rate (ticks/s) +host_mem_usage 403620 # Number of bytes of host memory used +host_seconds 2083.04 # Real time elapsed on the host +sim_insts 407937545 # Number of instructions simulated +sim_ops 806384911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2474752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1081536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10883712 # Number of bytes read from this memory +system.physmem.bytes_read::total 14443712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1081536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1081536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9597376 # Number of bytes written to this memory +system.physmem.bytes_written::total 9597376 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 170058 # Number of read requests responded to by this memory +system.physmem.num_reads::total 225683 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149959 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149959 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 210708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2120397 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2813966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 210708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 210708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1869789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1869789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1869789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 210708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2120397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4683755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 225683 # Total number of read requests seen +system.physmem.writeReqs 149959 # Total number of write requests seen +system.physmem.cpureqs 389568 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14443712 # Total number of bytes read from memory +system.physmem.bytesWritten 9597376 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14443712 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9597376 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 89 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3846 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 13634 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14670 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 15197 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 14751 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12899 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 14175 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13762 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 14847 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 14072 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 14685 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 14758 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 10128 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8462 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 10559 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 9080 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 10102 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8151 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9598 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8927 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 10197 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 9975 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 9903 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 5128875413000 # Total gap between requests +system.physmem.totGap 5132866305000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 226054 # Categorize read packet sizes +system.physmem.readPktSize::6 225683 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,7 +105,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 150209 # categorize write packet sizes +system.physmem.writePktSize::6 149959 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -114,30 +114,30 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3870 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3846 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 177383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21698 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1091 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 177236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2832 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2887 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 440 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -150,93 +150,93 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 6395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 6370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3329517724 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7605839724 # Sum of mem lat for all requests -system.physmem.totBusLat 903876000 # Total cycles spent in databus access -system.physmem.totBankLat 3372446000 # Total cycles spent in bank access -system.physmem.avgQLat 14734.40 # Average queueing delay per request -system.physmem.avgBankLat 14924.37 # Average bank access latency per request +system.physmem.totQLat 3339090244 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7604182244 # Sum of mem lat for all requests +system.physmem.totBusLat 902376000 # Total cycles spent in databus access +system.physmem.totBankLat 3362716000 # Total cycles spent in bank access +system.physmem.avgQLat 14801.33 # Average queueing delay per request +system.physmem.avgBankLat 14906.05 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33658.77 # Average memory access latency -system.physmem.avgRdBW 2.82 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 33707.38 # Average memory access latency +system.physmem.avgRdBW 2.81 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.82 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.81 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 14.06 # Average write queue length over time -system.physmem.readRowHits 199198 # Number of row buffer hits during reads -system.physmem.writeRowHits 88428 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.87 # Row buffer hit rate for writes -system.physmem.avgGap 13631091.58 # Average gap between requests -system.iocache.replacements 47576 # number of replacements -system.iocache.tagsinuse 0.091613 # Cycle average of tags in use +system.physmem.avgWrQLen 10.11 # Average write queue length over time +system.physmem.readRowHits 199074 # Number of row buffer hits during reads +system.physmem.writeRowHits 88511 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.02 # Row buffer hit rate for writes +system.physmem.avgGap 13664250.28 # Average gap between requests +system.iocache.replacements 47575 # number of replacements +system.iocache.tagsinuse 0.103977 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47591 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4991895066000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.091613 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.005726 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.005726 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses -system.iocache.ReadReq_misses::total 911 # number of ReadReq misses +system.iocache.warmup_cycle 4991894063000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.103977 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006499 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses +system.iocache.ReadReq_misses::total 910 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses -system.iocache.demand_misses::total 47631 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses -system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143697932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143697932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8983849160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 8983849160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 9127547092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9127547092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 9127547092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9127547092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses +system.iocache.demand_misses::total 47630 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses +system.iocache.overall_misses::total 47630 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143902932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 143902932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9034164160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9034164160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 9178067092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9178067092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 9178067092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9178067092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,40 +245,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157736.478595 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 157736.478595 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 192291.291952 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 192291.291952 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 191630.389704 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 191630.389704 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56345 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158135.090110 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158135.090110 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 193368.239726 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 193368.239726 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 192695.089062 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 192695.089062 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 192695.089062 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 60674 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7566 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7530 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.447132 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.057636 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96295990 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 96295990 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6552154765 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 6552154765 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6648450755 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6648450755 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96552990 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96552990 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6602427338 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 6602427338 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6698980328 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6698980328 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6698980328 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,14 +287,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105703.611416 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 105703.611416 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 140243.038634 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 140243.038634 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106102.186813 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 106102.186813 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 141319.078296 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 141319.078296 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 140646.238253 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 140646.238253 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -308,141 +308,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 448887765 # number of cpu cycles simulated +system.cpu.numCycles 448858777 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86493598 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 86493598 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1184200 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 81985656 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 79438611 # Number of BTB hits +system.cpu.BPredUnit.lookups 86511552 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86511552 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1187540 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 81908216 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 79448034 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28044653 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427268280 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86493598 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79438611 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 164008180 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5056188 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 124973 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 62751260 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 62335 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9257771 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 519239 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3803 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 258861392 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.258152 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.417945 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28014488 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427358956 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86511552 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79448034 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 164036376 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5076610 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125788 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 62760738 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36372 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 61645 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 359 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9269515 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 518863 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3783 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 258886753 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.258580 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418024 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95283812 36.81% 36.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1591927 0.61% 37.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71954404 27.80% 65.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 971846 0.38% 65.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1615863 0.62% 66.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2450126 0.95% 67.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1121647 0.43% 67.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1424659 0.55% 68.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82447108 31.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95280988 36.80% 36.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1593075 0.62% 37.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71954141 27.79% 65.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 971709 0.38% 65.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1620643 0.63% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2451488 0.95% 67.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1122205 0.43% 67.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1426657 0.55% 68.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82465847 31.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 258861392 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192684 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.951838 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31762033 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60235448 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159762632 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3267698 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3833581 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 840104917 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1244 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3833581 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34530134 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37412206 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10702091 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159938633 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12444747 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 836257763 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19698 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5896480 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4716940 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7816 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 997992319 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1816026440 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1816025416 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1024 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964353103 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33639209 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 466352 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 473282 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28808345 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17312855 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10260076 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1206444 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 946818 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829834961 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1255797 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824342965 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165215 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23689940 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36113140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 203193 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 258861392 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.184496 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.385380 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 258886753 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192737 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.952101 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31742461 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60237035 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159788942 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3267328 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3850987 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 840289565 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1231 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3850987 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34512001 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37373607 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10738522 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159961860 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12449776 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 836423195 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19229 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5893988 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4723761 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 7727 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 998196840 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1816454110 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1816453462 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 648 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964349930 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33846903 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 467065 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 474165 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28825004 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17330743 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10271430 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1207742 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 944493 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829965735 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1256270 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824405499 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167750 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23821216 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36350655 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 203504 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 258886753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.184425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.385403 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72001826 27.81% 27.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15596239 6.02% 33.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10365970 4.00% 37.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7555139 2.92% 40.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75952295 29.34% 70.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3901347 1.51% 71.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72539766 28.02% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 795622 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 153188 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72013044 27.82% 27.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15598777 6.03% 33.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10365143 4.00% 37.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7553925 2.92% 40.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75959659 29.34% 70.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3903196 1.51% 71.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72545029 28.02% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 793969 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 154011 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 258861392 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 258886753 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 354431 33.41% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 554175 52.24% 85.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 152275 14.35% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 353413 33.31% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 554407 52.25% 85.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153287 14.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 306719 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796534260 96.63% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 307308 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796584719 96.63% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued @@ -471,246 +471,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18029662 2.19% 98.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9472324 1.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18039231 2.19% 98.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9474241 1.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824342965 # Type of FU issued -system.cpu.iq.rate 1.836412 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1060881 # FU busy when requested +system.cpu.iq.FU_type_0::total 824405499 # Type of FU issued +system.cpu.iq.rate 1.836670 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1061107 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1908906757 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854790380 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819662460 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 438 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 58 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825097030 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1650086 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 1909060731 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 855053110 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819712115 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 306 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825159176 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1650601 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3338406 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 26898 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11294 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1845192 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3355072 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26592 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11367 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1855422 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932288 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 11793 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932171 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 11828 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3833581 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26182715 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2118325 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831090758 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 325842 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17312855 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10260082 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 724912 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1616921 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15962 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11294 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 708686 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 624381 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1333067 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822327193 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17600649 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2015771 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3850987 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26145840 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2117101 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831222005 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 328364 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17330743 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10271430 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 725551 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1616789 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12654 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11367 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 710665 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 625080 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1335745 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822377334 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17606524 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2028164 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26823265 # number of memory reference insts executed -system.cpu.iew.exec_branches 83275848 # Number of branches executed -system.cpu.iew.exec_stores 9222616 # Number of stores executed -system.cpu.iew.exec_rate 1.831922 # Inst execution rate -system.cpu.iew.wb_sent 821819072 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819662518 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640525310 # num instructions producing a value -system.cpu.iew.wb_consumers 1046521436 # num instructions consuming a value +system.cpu.iew.exec_refs 26829889 # number of memory reference insts executed +system.cpu.iew.exec_branches 83279279 # Number of branches executed +system.cpu.iew.exec_stores 9223365 # Number of stores executed +system.cpu.iew.exec_rate 1.832152 # Inst execution rate +system.cpu.iew.wb_sent 821869918 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819712181 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640562059 # num instructions producing a value +system.cpu.iew.wb_consumers 1046574799 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.825985 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.612052 # average fanout of values written-back +system.cpu.iew.wb_rate 1.826214 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.612056 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24603279 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052602 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1189396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255043204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.161744 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.853415 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24730610 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052764 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1192382 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255051171 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.161659 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.853306 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 83146159 32.60% 32.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11856679 4.65% 37.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3955758 1.55% 38.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74970525 29.40% 68.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2479858 0.97% 69.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1486016 0.58% 69.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 951787 0.37% 70.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70929950 27.81% 97.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5266472 2.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 83143291 32.60% 32.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11860450 4.65% 37.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3961812 1.55% 38.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74971665 29.39% 68.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2481439 0.97% 69.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1489878 0.58% 69.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 950647 0.37% 70.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70929098 27.81% 97.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5262891 2.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255043204 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407937807 # Number of instructions committed -system.cpu.commit.committedOps 806381430 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 255051171 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407937545 # Number of instructions committed +system.cpu.commit.committedOps 806384911 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22389336 # Number of memory references committed -system.cpu.commit.loads 13974446 # Number of loads committed -system.cpu.commit.membars 473457 # Number of memory barriers committed -system.cpu.commit.branches 82191509 # Number of branches committed +system.cpu.commit.refs 22391676 # Number of memory references committed +system.cpu.commit.loads 13975668 # Number of loads committed +system.cpu.commit.membars 473465 # Number of memory barriers committed +system.cpu.commit.branches 82190309 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735317730 # Number of committed integer instructions. +system.cpu.commit.int_insts 735319938 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5266472 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5262891 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080683249 # The number of ROB reads -system.cpu.rob.rob_writes 1665823647 # The number of ROB writes -system.cpu.timesIdled 1223181 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190026373 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9808860643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407937807 # Number of Instructions Simulated -system.cpu.committedOps 806381430 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407937807 # Number of Instructions Simulated -system.cpu.cpi 1.100383 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.100383 # CPI: Total CPI of All Threads -system.cpu.ipc 0.908775 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.908775 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1508172140 # number of integer regfile reads -system.cpu.int_regfile_writes 977803744 # number of integer regfile writes -system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.misc_regfile_reads 265152690 # number of misc regfile reads -system.cpu.misc_regfile_writes 402177 # number of misc regfile writes -system.cpu.icache.replacements 1074366 # number of replacements -system.cpu.icache.tagsinuse 510.322538 # Cycle average of tags in use -system.cpu.icache.total_refs 8113553 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1074878 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.548348 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1080825517 # The number of ROB reads +system.cpu.rob.rob_writes 1666103017 # The number of ROB writes +system.cpu.timesIdled 1222907 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 189972024 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9816871415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407937545 # Number of Instructions Simulated +system.cpu.committedOps 806384911 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407937545 # Number of Instructions Simulated +system.cpu.cpi 1.100312 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.100312 # CPI: Total CPI of All Threads +system.cpu.ipc 0.908833 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.908833 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1508250980 # number of integer regfile reads +system.cpu.int_regfile_writes 977858997 # number of integer regfile writes +system.cpu.fp_regfile_reads 66 # number of floating regfile reads +system.cpu.misc_regfile_reads 265171411 # number of misc regfile reads +system.cpu.misc_regfile_writes 402390 # number of misc regfile writes +system.cpu.icache.replacements 1072344 # number of replacements +system.cpu.icache.tagsinuse 510.326715 # Cycle average of tags in use +system.cpu.icache.total_refs 8127499 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1072855 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.575580 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 56079311000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.322538 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996724 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996724 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8113553 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8113553 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8113553 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8113553 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8113553 # number of overall hits -system.cpu.icache.overall_hits::total 8113553 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1144218 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1144218 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1144218 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1144218 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1144218 # number of overall misses -system.cpu.icache.overall_misses::total 1144218 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15461286493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15461286493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15461286493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15461286493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15461286493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15461286493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9257771 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9257771 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9257771 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9257771 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9257771 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9257771 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123595 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123595 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123595 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123595 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123595 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123595 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13512.535630 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13512.535630 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13512.535630 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13512.535630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13512.535630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13512.535630 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7080 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.326715 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996732 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996732 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8127499 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8127499 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8127499 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8127499 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8127499 # number of overall hits +system.cpu.icache.overall_hits::total 8127499 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1142014 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1142014 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1142014 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1142014 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1142014 # number of overall misses +system.cpu.icache.overall_misses::total 1142014 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15424181989 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15424181989 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15424181989 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15424181989 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15424181989 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15424181989 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9269513 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9269513 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9269513 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9269513 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9269513 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9269513 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123201 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123201 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123201 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123201 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123201 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123201 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.123383 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13506.123383 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.123383 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13506.123383 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.123383 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13506.123383 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7378 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 251 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 254 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.207171 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.047244 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67124 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67124 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67124 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67124 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67124 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67124 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077094 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1077094 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1077094 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1077094 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1077094 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1077094 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12721673493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12721673493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12721673493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12721673493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12721673493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12721673493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116345 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116345 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116345 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11811.107938 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11811.107938 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11811.107938 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11811.107938 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11811.107938 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11811.107938 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66936 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 66936 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 66936 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 66936 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 66936 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 66936 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075078 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1075078 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1075078 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1075078 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1075078 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1075078 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12692625989 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12692625989 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12692625989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12692625989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12692625989 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12692625989 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115980 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115980 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115980 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115980 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.237305 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.237305 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.237305 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.237305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.237305 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.237305 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 10271 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.965877 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 29367 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 10284 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.855601 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5103910768500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.965877 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.435367 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.435367 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 29379 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 29379 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 10190 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.008148 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 29715 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 10203 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.912379 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5103977180500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.008148 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375509 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375509 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 29719 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 29719 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 29382 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 29382 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 29382 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 29382 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11163 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 11163 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11163 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 11163 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11163 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 11163 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 123160000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 123160000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 123160000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 123160000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 123160000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 123160000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 40542 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 40542 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 29722 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 29722 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 29722 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 29722 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11072 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 11072 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11072 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 11072 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11072 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 11072 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 125220500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 125220500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 125220500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 125220500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 125220500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 125220500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 40791 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 40791 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40545 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 40545 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40545 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 40545 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275344 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275344 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275324 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.275324 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275324 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.275324 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11032.876467 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11032.876467 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11032.876467 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11032.876467 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40794 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 40794 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40794 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 40794 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.271432 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.271432 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.271412 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.271412 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.271412 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.271412 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11309.654986 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11309.654986 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11309.654986 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11309.654986 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11309.654986 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11309.654986 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -719,78 +719,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1731 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1731 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11163 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11163 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11163 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 11163 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11163 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 11163 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 100834000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 100834000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 100834000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 100834000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 100834000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 100834000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275344 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275344 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275324 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275324 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9032.876467 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1966 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1966 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11072 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11072 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11072 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 11072 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11072 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 11072 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 103076500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 103076500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 103076500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 103076500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 103076500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 103076500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.271432 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.271432 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.271412 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.271412 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.271412 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.271412 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9309.654986 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9309.654986 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9309.654986 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9309.654986 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109401 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.751867 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 137796 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109417 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.259366 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100515626500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.751867 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.859492 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.859492 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137796 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 137796 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137796 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 137796 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137796 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 137796 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110443 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110443 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110443 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110443 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110443 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110443 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1382584000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1382584000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1382584000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1382584000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1382584000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1382584000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248239 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 248239 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248239 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 248239 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248239 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 248239 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.444906 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.444906 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.444906 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.444906 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.444906 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.444906 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12518.529920 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12518.529920 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12518.529920 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12518.529920 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 112521 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.957581 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 137445 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 112536 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.221343 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100518873000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.957581 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809849 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.809849 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137452 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 137452 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137452 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 137452 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137452 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 137452 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 113500 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 113500 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 113500 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 113500 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 113500 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 113500 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1432388500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1432388500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1432388500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1432388500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1432388500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1432388500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 250952 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 250952 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 250952 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 250952 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 250952 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 250952 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.452278 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.452278 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.452278 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.452278 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.452278 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.452278 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12620.162996 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12620.162996 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12620.162996 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12620.162996 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12620.162996 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,146 +799,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 36585 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 36585 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110443 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110443 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110443 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110443 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110443 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110443 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1161698000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1161698000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1161698000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.444906 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.444906 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.444906 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10518.529920 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10518.529920 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10518.529920 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 37324 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 37324 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 113500 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 113500 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 113500 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 113500 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 113500 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 113500 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1205388500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1205388500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1205388500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1205388500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.452278 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.452278 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.452278 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.452278 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10620.162996 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10620.162996 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10620.162996 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10620.162996 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1672817 # number of replacements -system.cpu.dcache.tagsinuse 511.996932 # Cycle average of tags in use -system.cpu.dcache.total_refs 19210877 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1673329 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.480634 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1671903 # number of replacements +system.cpu.dcache.tagsinuse 511.996701 # Cycle average of tags in use +system.cpu.dcache.total_refs 19219910 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1672415 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.492309 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.996932 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.996701 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11119324 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11119324 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8086692 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8086692 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19206016 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19206016 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19206016 # number of overall hits -system.cpu.dcache.overall_hits::total 19206016 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2269518 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2269518 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318969 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318969 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2588487 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2588487 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2588487 # number of overall misses -system.cpu.dcache.overall_misses::total 2588487 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32394569000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32394569000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9644667991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9644667991 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42039236991 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42039236991 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42039236991 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42039236991 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13388842 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13388842 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8405661 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8405661 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21794503 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21794503 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21794503 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21794503 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169508 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.169508 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037947 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037947 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118768 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118768 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118768 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118768 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14273.766060 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14273.766060 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30237.007330 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30237.007330 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16240.853051 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16240.853051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16240.853051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16240.853051 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 395046 # number of cycles access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 11126974 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11126974 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8088054 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8088054 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19215028 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19215028 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19215028 # number of overall hits +system.cpu.dcache.overall_hits::total 19215028 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2267052 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2267052 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318719 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318719 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2585771 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2585771 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2585771 # number of overall misses +system.cpu.dcache.overall_misses::total 2585771 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32362735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32362735000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9617362993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9617362993 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41980097993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41980097993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41980097993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41980097993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13394026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13394026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8406773 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8406773 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21800799 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21800799 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21800799 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21800799 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169258 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169258 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037912 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037912 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118609 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118609 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118609 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118609 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14275.250413 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14275.250413 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30175.053866 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30175.053866 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16235.040919 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16235.040919 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16235.040919 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16235.040919 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 395929 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42533 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42571 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.287988 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.300439 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1572293 # number of writebacks -system.cpu.dcache.writebacks::total 1572293 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 885972 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 885972 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24759 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24759 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 910731 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 910731 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 910731 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 910731 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1383546 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1383546 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294210 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 294210 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1677756 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1677756 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1677756 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1677756 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17475799000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17475799000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8804968491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8804968491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26280767491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26280767491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26280767491 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26280767491 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296545000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296545000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470181000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470181000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766726000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766726000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103336 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103336 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035001 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035001 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076981 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076981 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076981 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076981 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12631.165859 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12631.165859 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29927.495636 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29927.495636 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15664.236928 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15664.236928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15664.236928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15664.236928 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1571444 # number of writebacks +system.cpu.dcache.writebacks::total 1571444 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 884224 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 884224 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24733 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 24733 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 908957 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 908957 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 908957 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 908957 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1382828 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1382828 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293986 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 293986 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1676814 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1676814 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1676814 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1676814 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17466154000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17466154000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8776924993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8776924993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26243078993 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26243078993 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26243078993 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26243078993 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296687500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296687500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470134500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470134500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766822000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766822000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034970 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034970 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076915 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076915 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076915 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076915 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12630.749450 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12630.749450 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29854.908033 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29854.908033 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15650.560523 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15650.560523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15650.560523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15650.560523 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -946,141 +946,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 1.120501 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3151.862131 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11528.846024 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.765088 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000183 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000017 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.048094 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.175916 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.989298 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102782 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8459 # 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number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133929 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133929 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16908 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 171224 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 188185 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 46 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16908 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 171224 # number of overall misses -system.cpu.l2cache.overall_misses::total 188185 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3948500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 482500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1010290500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2408831998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3423553498 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17078500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17078500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6857854500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6857854500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3948500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 482500 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1382418 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2568539 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1610609 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1610609 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3925 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 3925 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 290331 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 290331 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 102828 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 8466 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1074827 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1672749 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2858870 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 102828 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 8466 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1074827 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1672749 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2858870 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000447 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000827 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015731 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026978 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021123 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.916178 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.916178 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461298 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.461298 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000447 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000827 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015731 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102361 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.065825 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000447 # 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