tests: update reference outputs

Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes.  There are a few stats.txt updates too, but
they are in the minority.

1 files changed, 25 insertions, 25 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 83ecaea08..e925af082 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:24:02
+Real time: Sep/22/2013 07:54:54
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 771
-Elapsed_time_in_minutes: 12.85
-Elapsed_time_in_hours: 0.214167
-Elapsed_time_in_days: 0.00892361
+Elapsed_time_in_seconds: 689
+Elapsed_time_in_minutes: 11.4833
+Elapsed_time_in_hours: 0.191389
+Elapsed_time_in_days: 0.00797454
 
-Virtual_time_in_seconds: 767.55
-Virtual_time_in_minutes: 12.7925
-Virtual_time_in_hours:   0.213208
-Virtual_time_in_days:    0.00888368
+Virtual_time_in_seconds: 688.52
+Virtual_time_in_minutes: 11.4753
+Virtual_time_in_hours:   0.191256
+Virtual_time_in_days:    0.00796898
 
 Ruby_current_time: 10608810122
 Ruby_start_time: 0
 Ruby_cycles: 10608810122
 
-mbytes_resident: 612.449
-mbytes_total: 859.008
-resident_ratio: 0.712982
+mbytes_resident: 589.816
+mbytes_total: 810.262
+resident_ratio: 0.727933
 
 Busy Controller Counts:
 L1Cache-0:10  L1Cache-1:9  
@@ -28,28 +28,28 @@ DMA-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154826686 average: 1.00012 | standard deviation: 0.0109671 | 0 154808062 18624 ]
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154826690 average: 1.00012 | standard deviation: 0.0109671 | 0 154808066 18624 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-latency: [binsize: 8 max: 146 count: 154826685 average: 3.40667 | standard deviation: 3.89546 | 152128103 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88160 4468 159 160 697 95 ]
-latency: LD: [binsize: 8 max: 145 count: 15355330 average: 5.00367 | standard deviation: 7.1602 | 13922963 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20230 1017 49 23 146 37 ]
-latency: ST: [binsize: 8 max: 146 count: 9754589 average: 4.6097 | standard deviation: 10.5962 | 9399925 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
-latency: IFETCH: [binsize: 8 max: 145 count: 128502467 average: 3.10882 | standard deviation: 1.62805 | 127704896 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 17 24 76 1 ]
-latency: RMW_Read: [binsize: 8 max: 143 count: 526559 average: 6.05821 | standard deviation: 8.42497 | 454440 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
+latency: [binsize: 8 max: 146 count: 154826689 average: 3.40667 | standard deviation: 3.89546 | 152128107 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ]
+latency: LD: [binsize: 8 max: 145 count: 15355330 average: 5.00367 | standard deviation: 7.16019 | 13922963 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ]
+latency: ST: [binsize: 8 max: 146 count: 9754590 average: 4.6097 | standard deviation: 10.5962 | 9399926 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
+latency: IFETCH: [binsize: 8 max: 145 count: 128502469 average: 3.10882 | standard deviation: 1.62805 | 127704898 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ]
+latency: RMW_Read: [binsize: 8 max: 143 count: 526560 average: 6.05821 | standard deviation: 8.42496 | 454441 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
 latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 343870 average: 5.61917 | standard deviation: 7.40449 | 302009 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ]
 latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average:     3 | standard deviation: 0 | 0 0 0 343870 ]
-hit latency: [binsize: 1 max: 3 count: 152128103 average:     3 | standard deviation: 0 | 0 0 0 152128103 ]
+hit latency: [binsize: 1 max: 3 count: 152128107 average:     3 | standard deviation: 0 | 0 0 0 152128107 ]
 hit latency: LD: [binsize: 1 max: 3 count: 13922963 average:     3 | standard deviation: 0 | 0 0 0 13922963 ]
-hit latency: ST: [binsize: 1 max: 3 count: 9399925 average:     3 | standard deviation: 0 | 0 0 0 9399925 ]
-hit latency: IFETCH: [binsize: 1 max: 3 count: 127704896 average:     3 | standard deviation: 0 | 0 0 0 127704896 ]
-hit latency: RMW_Read: [binsize: 1 max: 3 count: 454440 average:     3 | standard deviation: 0 | 0 0 0 454440 ]
+hit latency: ST: [binsize: 1 max: 3 count: 9399926 average:     3 | standard deviation: 0 | 0 0 0 9399926 ]
+hit latency: IFETCH: [binsize: 1 max: 3 count: 127704898 average:     3 | standard deviation: 0 | 0 0 0 127704898 ]
+hit latency: RMW_Read: [binsize: 1 max: 3 count: 454441 average:     3 | standard deviation: 0 | 0 0 0 454441 ]
 hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 302009 average:     3 | standard deviation: 0 | 0 0 0 302009 ]
 hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average:     3 | standard deviation: 0 | 0 0 0 343870 ]
-miss latency: [binsize: 8 max: 146 count: 2698582 average: 26.332 | standard deviation: 18.3228 | 0 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88160 4468 159 160 697 95 ]
-miss latency: LD: [binsize: 8 max: 145 count: 1432367 average: 24.4798 | standard deviation: 11.4572 | 0 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20230 1017 49 23 146 37 ]
+miss latency: [binsize: 8 max: 146 count: 2698582 average: 26.332 | standard deviation: 18.3228 | 0 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ]
+miss latency: LD: [binsize: 8 max: 145 count: 1432367 average: 24.4798 | standard deviation: 11.4571 | 0 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ]
 miss latency: ST: [binsize: 8 max: 146 count: 354664 average: 47.2728 | standard deviation: 34.6308 | 0 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
-miss latency: IFETCH: [binsize: 8 max: 145 count: 797571 average: 20.5324 | standard deviation: 11.0261 | 0 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 17 24 76 1 ]
+miss latency: IFETCH: [binsize: 8 max: 145 count: 797571 average: 20.5323 | standard deviation: 11.026 | 0 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ]
 miss latency: RMW_Read: [binsize: 8 max: 143 count: 72119 average: 25.3288 | standard deviation: 9.37846 | 0 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
 miss latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 41861 average: 24.5153 | standard deviation: 6.61955 | 0 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ]