test: update stats

Update stats for recent changes.  Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.

1 files changed, 28 insertions, 43 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
index e925af082..6473a5fed 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -1,57 +1,42 @@
-Real time: Sep/22/2013 07:54:54
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 689
-Elapsed_time_in_minutes: 11.4833
-Elapsed_time_in_hours: 0.191389
-Elapsed_time_in_days: 0.00797454
-
-Virtual_time_in_seconds: 688.52
-Virtual_time_in_minutes: 11.4753
-Virtual_time_in_hours:   0.191256
-Virtual_time_in_days:    0.00796898
-
-Ruby_current_time: 10608810122
+Ruby_current_time: 10608984467
 Ruby_start_time: 0
-Ruby_cycles: 10608810122
-
-mbytes_resident: 589.816
-mbytes_total: 810.262
-resident_ratio: 0.727933
+Ruby_cycles: 10608984467
 
 Busy Controller Counts:
 L1Cache-0:10  L1Cache-1:9  
-L2Cache-0:0  
+L2Cache-0:1  
 Directory-0:0  
 DMA-0:0  
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154826690 average: 1.00012 | standard deviation: 0.0109671 | 0 154808066 18624 ]
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154865725 average: 1.00012 | standard deviation: 0.0109654 | 0 154847102 18623 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-latency: [binsize: 8 max: 146 count: 154826689 average: 3.40667 | standard deviation: 3.89546 | 152128107 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ]
-latency: LD: [binsize: 8 max: 145 count: 15355330 average: 5.00367 | standard deviation: 7.16019 | 13922963 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ]
-latency: ST: [binsize: 8 max: 146 count: 9754590 average: 4.6097 | standard deviation: 10.5962 | 9399926 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
-latency: IFETCH: [binsize: 8 max: 145 count: 128502469 average: 3.10882 | standard deviation: 1.62805 | 127704898 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ]
-latency: RMW_Read: [binsize: 8 max: 143 count: 526560 average: 6.05821 | standard deviation: 8.42496 | 454441 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
-latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 343870 average: 5.61917 | standard deviation: 7.40449 | 302009 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ]
-latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average:     3 | standard deviation: 0 | 0 0 0 343870 ]
-hit latency: [binsize: 1 max: 3 count: 152128107 average:     3 | standard deviation: 0 | 0 0 0 152128107 ]
-hit latency: LD: [binsize: 1 max: 3 count: 13922963 average:     3 | standard deviation: 0 | 0 0 0 13922963 ]
-hit latency: ST: [binsize: 1 max: 3 count: 9399926 average:     3 | standard deviation: 0 | 0 0 0 9399926 ]
-hit latency: IFETCH: [binsize: 1 max: 3 count: 127704898 average:     3 | standard deviation: 0 | 0 0 0 127704898 ]
-hit latency: RMW_Read: [binsize: 1 max: 3 count: 454441 average:     3 | standard deviation: 0 | 0 0 0 454441 ]
-hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 302009 average:     3 | standard deviation: 0 | 0 0 0 302009 ]
-hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average:     3 | standard deviation: 0 | 0 0 0 343870 ]
-miss latency: [binsize: 8 max: 146 count: 2698582 average: 26.332 | standard deviation: 18.3228 | 0 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ]
-miss latency: LD: [binsize: 8 max: 145 count: 1432367 average: 24.4798 | standard deviation: 11.4571 | 0 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ]
-miss latency: ST: [binsize: 8 max: 146 count: 354664 average: 47.2728 | standard deviation: 34.6308 | 0 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
-miss latency: IFETCH: [binsize: 8 max: 145 count: 797571 average: 20.5323 | standard deviation: 11.026 | 0 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ]
-miss latency: RMW_Read: [binsize: 8 max: 143 count: 72119 average: 25.3288 | standard deviation: 9.37846 | 0 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
-miss latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 41861 average: 24.5153 | standard deviation: 6.61955 | 0 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ]
+latency: [binsize: 8 max: 146 count: 154865724 average: 3.40663 | standard deviation: 3.89597 | 152167065 0 2401413 123717 793 1 0 0 0 77289 1392 70 170 88137 4539 155 157 714 112 ]
+latency: LD: [binsize: 8 max: 144 count: 15359723 average: 5.00324 | standard deviation: 7.16109 | 13927349 0 1353226 47181 696 0 0 0 0 9514 194 17 27 20186 1048 50 27 160 48 ]
+latency: ST: [binsize: 8 max: 146 count: 9756253 average: 4.61012 | standard deviation: 10.5987 | 9401531 0 199293 31091 52 0 0 0 0 62477 1152 44 130 56479 3272 89 110 469 64 ]
+latency: IFETCH: [binsize: 8 max: 140 count: 128535441 average: 3.1088 | standard deviation: 1.62806 | 127737856 0 781770 369 6 0 0 0 0 4126 24 8 11 10975 181 16 20 79 ]
+latency: RMW_Read: [binsize: 8 max: 140 count: 526545 average: 6.05786 | standard deviation: 8.42243 | 454428 0 43164 27522 7 1 0 0 0 1003 18 1 2 364 31 0 0 4 ]
+latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 343881 average: 5.61911 | standard deviation: 7.40549 | 302020 0 23960 17554 32 0 0 0 0 169 4 0 0 133 7 0 0 2 ]
+latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343881 average:     3 | standard deviation: 0 | 0 0 0 343881 ]
+hit latency: [binsize: 1 max: 3 count: 152167065 average:     3 | standard deviation: 0 | 0 0 0 152167065 ]
+hit latency: LD: [binsize: 1 max: 3 count: 13927349 average:     3 | standard deviation: 0 | 0 0 0 13927349 ]
+hit latency: ST: [binsize: 1 max: 3 count: 9401531 average:     3 | standard deviation: 0 | 0 0 0 9401531 ]
+hit latency: IFETCH: [binsize: 1 max: 3 count: 127737856 average:     3 | standard deviation: 0 | 0 0 0 127737856 ]
+hit latency: RMW_Read: [binsize: 1 max: 3 count: 454428 average:     3 | standard deviation: 0 | 0 0 0 454428 ]
+hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 302020 average:     3 | standard deviation: 0 | 0 0 0 302020 ]
+hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343881 average:     3 | standard deviation: 0 | 0 0 0 343881 ]
+miss latency: [binsize: 8 max: 146 count: 2698659 average: 26.3349 | standard deviation: 18.3306 | 0 0 2401413 123717 793 1 0 0 0 77289 1392 70 170 88137 4539 155 157 714 112 ]
+miss latency: LD: [binsize: 8 max: 144 count: 1432374 average: 24.4813 | standard deviation: 11.4669 | 0 0 1353226 47181 696 0 0 0 0 9514 194 17 27 20186 1048 50 27 160 48 ]
+miss latency: ST: [binsize: 8 max: 146 count: 354722 average: 47.2848 | standard deviation: 34.6376 | 0 0 199293 31091 52 0 0 0 0 62477 1152 44 130 56479 3272 89 110 469 64 ]
+miss latency: IFETCH: [binsize: 8 max: 140 count: 797585 average: 20.5333 | standard deviation: 11.0294 | 0 0 781770 369 6 0 0 0 0 4126 24 8 11 10975 181 16 20 79 ]
+miss latency: RMW_Read: [binsize: 8 max: 140 count: 72117 average: 25.3262 | standard deviation: 9.36709 | 0 0 43164 27522 7 1 0 0 0 1003 18 1 2 364 31 0 0 4 ]
+miss latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 41861 average: 24.5155 | standard deviation: 6.62905 | 0 0 23960 17554 32 0 0 0 0 169 4 0 0 133 7 0 0 2 ]
 
 Request vs. RubySystem State Profile
 --------------------------------
@@ -60,10 +45,10 @@ Request vs. RubySystem State Profile
 
 Message Delayed Cycles
 ----------------------
-Total_delay_cycles: [binsize: 1 max: 15 count: 11145866 average: 0.602427 | standard deviation: 1.43356 | 9466902 2991 1616 2582 1666934 2480 317 253 407 1077 12 18 80 196 0 1 ]
-  virtual_network_0_delay_cycles: [binsize: 1 max: 15 count: 6232784 average: 1.04523 | standard deviation: 1.76212 | 4606142 1096 355 706 1619950 2278 313 251 380 1006 12 18 80 196 0 1 ]
-  virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4782799 average: 0.0411809 | standard deviation: 0.401372 | 4731531 1706 955 1706 46644 155 4 2 27 69 ]
-  virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 130283 average: 0.0224435 | standard deviation: 0.272229 | 129229 189 306 170 340 47 0 0 0 2 ]
+Total_delay_cycles: [binsize: 1 max: 15 count: 11146337 average: 0.602409 | standard deviation: 1.43347 | 9467254 3019 1636 2634 1666996 2474 322 244 418 1037 10 19 80 193 0 1 ]
+  virtual_network_0_delay_cycles: [binsize: 1 max: 15 count: 6232935 average: 1.0452 | standard deviation: 1.76202 | 4606233 1132 350 702 1620005 2287 321 242 393 967 10 19 80 193 0 1 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4783100 average: 0.041195 | standard deviation: 0.40134 | 4731792 1686 982 1765 46636 142 1 2 25 69 ]
+  virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 130302 average: 0.0227472 | standard deviation: 0.27339 | 129229 201 304 167 355 45 0 0 0 1 ]
   virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
   virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
   virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]