diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-04-23 00:03:05 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-04-23 00:03:05 -0500 |
| commit | 3295e6de699d2baa8a73cc9280f1929a42314f00 (patch) | |
| tree | bb411b7de503d564a0964a36d3b30c57350490d4 /tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory | |
| parent | 25a6b1866e7c195c45c3d23f00937aa13bb2a2ff (diff) | |
| download | gem5-3295e6de699d2baa8a73cc9280f1929a42314f00.tar.xz | |
x86, stats: updates due to lret bugfix
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory')
3 files changed, 425 insertions, 436 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats index 098094868..6d0e83626 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,26 +1,26 @@ -Real time: Mar/28/2013 10:19:36 +Real time: Apr/22/2013 16:53:22 Profiler Stats -------------- -Elapsed_time_in_seconds: 824 -Elapsed_time_in_minutes: 13.7333 -Elapsed_time_in_hours: 0.228889 -Elapsed_time_in_days: 0.00953704 +Elapsed_time_in_seconds: 481 +Elapsed_time_in_minutes: 8.01667 +Elapsed_time_in_hours: 0.133611 +Elapsed_time_in_days: 0.00556713 -Virtual_time_in_seconds: 785.96 -Virtual_time_in_minutes: 13.0993 -Virtual_time_in_hours: 0.218322 -Virtual_time_in_days: 0.00909676 +Virtual_time_in_seconds: 480.45 +Virtual_time_in_minutes: 8.0075 +Virtual_time_in_hours: 0.133458 +Virtual_time_in_days: 0.00556076 -Ruby_current_time: 10416271238 +Ruby_current_time: 10410297758 Ruby_start_time: 0 -Ruby_cycles: 10416271238 +Ruby_cycles: 10410297758 -mbytes_resident: 597.965 -mbytes_total: 848.508 -resident_ratio: 0.704734 +mbytes_resident: 604.641 +mbytes_total: 843.926 +resident_ratio: 0.716471 -ruby_cycles_executed: [ 10416271239 10416271239 ] +ruby_cycles_executed: [ 10410297759 10410297759 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 @@ -30,18 +30,18 @@ DMA-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 151895075 average: 1.00011 | standard deviation: 0.0104983 | 0 151878333 16742 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 151886718 average: 1.00011 | standard deviation: 0.0104983 | 0 151869977 16741 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 270 count: 151895074 average: 3.45632 | standard deviation: 5.15571 | 0 149239942 0 0 0 0 0 0 0 967471 601 1437653 515 54191 578 16215 159 100 5 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 6095 8851 10338 50892 181 524 114 95 129 11 19 5 10 11 7 17 11 13 20 10 22 6 8 20 12 460 4446 10447 18595 13927 42308 850 876 2239 314 825 19 13 50 26 40 9 27 54 19 22 11 23 46 13 18 16 21 30 78 155 130 157 221 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 218 count: 14874061 average: 5.10543 | standard deviation: 8.68005 | 0 13485161 0 0 0 0 0 0 0 129669 71 1200389 321 19342 354 4658 120 69 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 946 797 3688 3455 2377 59 103 45 35 24 6 0 1 3 5 3 8 4 3 2 5 4 5 2 7 3 3 1340 2962 4560 6434 5662 323 275 230 120 126 7 4 3 16 9 3 17 8 8 3 7 7 6 3 3 5 5 12 23 21 44 49 12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 270 count: 9471875 average: 5.1858 | standard deviation: 15.4023 | 0 9121731 0 0 0 0 0 0 0 27134 22 181251 122 14247 125 1633 27 16 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 3347 3709 6401 48396 97 398 53 53 99 4 17 4 4 4 3 7 5 7 15 3 18 1 5 10 6 457 1055 3050 9771 7123 36234 361 508 1904 182 686 8 8 45 4 27 3 7 43 7 17 3 13 40 5 12 5 11 15 22 105 69 105 209 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 213 count: 126380154 average: 3.11846 | standard deviation: 2.02437 | 0 125567964 0 0 0 0 0 0 0 794781 477 434 39 45 17 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1899 1850 989 40 49 13 20 10 1 5 1 2 0 2 1 1 2 1 1 3 0 0 0 1 2 2 0 2035 4358 4208 198 205 161 86 103 7 4 4 1 2 6 4 3 3 3 4 1 1 2 0 5 2 6 5 2 33 28 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_RMW_Read: [binsize: 2 max: 214 count: 490994 average: 6.03795 | standard deviation: 9.42736 | 0 425859 0 0 0 0 0 0 0 10420 25 32755 15 11997 35 8470 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 81 392 393 46 9 3 4 5 1 0 0 0 1 0 0 0 1 2 0 2 0 0 0 1 1 0 8 55 15 120 161 1 4 2 4 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Read: [binsize: 2 max: 212 count: 338995 average: 5.4473 | standard deviation: 7.76902 | 0 300232 0 0 0 0 0 0 0 5467 6 22824 18 8560 47 1454 7 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 73 49 24 3 0 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 8 22 41 52 46 4 3 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338995 average: 3 | standard deviation: 0 | 0 0 0 338995 ] -miss_latency_NULL: [binsize: 2 max: 270 count: 151895074 average: 3.45632 | standard deviation: 5.15571 | 0 149239942 0 0 0 0 0 0 0 967471 601 1437653 515 54191 578 16215 159 100 5 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 6095 8851 10338 50892 181 524 114 95 129 11 19 5 10 11 7 17 11 13 20 10 22 6 8 20 12 460 4446 10447 18595 13927 42308 850 876 2239 314 825 19 13 50 26 40 9 27 54 19 22 11 23 46 13 18 16 21 30 78 155 130 157 221 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 2 max: 270 count: 151886717 average: 3.45795 | standard deviation: 5.18215 | 0 149232339 0 0 0 0 0 0 0 967168 602 1434707 493 54299 574 16370 170 112 2 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3741 6150 8984 10304 51755 196 509 88 111 143 4 23 9 11 17 5 17 5 8 27 4 15 2 9 6 9 472 4506 10321 18243 13984 43613 883 877 2441 340 822 17 25 50 17 23 15 17 60 7 30 13 21 47 21 27 9 21 24 90 134 133 147 269 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 216 count: 14872957 average: 5.10751 | standard deviation: 8.69983 | 0 13484012 0 0 0 0 0 0 0 129492 97 1200237 320 19353 366 4823 123 70 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 919 791 3671 3477 2370 72 98 38 42 34 2 3 2 5 2 3 1 0 2 0 1 4 1 3 1 5 6 1421 2829 4534 6423 5889 348 264 260 122 133 10 9 4 7 1 7 4 5 1 6 6 4 4 8 6 4 10 4 25 22 57 48 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 270 count: 9468113 average: 5.20871 | standard deviation: 15.524 | 0 9118662 0 0 0 0 0 0 0 27223 26 178592 96 14286 118 1530 29 18 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 770 3337 3846 6346 49267 90 393 32 59 105 1 20 4 2 15 2 13 3 2 21 2 9 0 4 4 3 465 1055 3041 9490 7168 37336 375 495 2067 204 683 2 13 45 6 20 6 10 50 5 24 6 14 40 6 18 3 9 17 31 81 62 93 235 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 214 count: 126376928 average: 3.11849 | standard deviation: 2.02507 | 0 125564891 0 0 0 0 0 0 0 794588 449 385 48 51 21 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1937 1912 1006 41 48 20 17 14 2 3 1 0 2 3 0 0 3 2 2 6 1 2 1 1 0 1 1 2014 4386 4163 214 182 154 101 111 7 3 5 3 1 4 2 2 3 5 1 0 1 3 3 7 3 1 2 3 33 29 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_RMW_Read: [binsize: 2 max: 215 count: 490895 average: 6.04017 | standard deviation: 9.43848 | 0 425774 0 0 0 0 0 0 0 10405 25 32646 14 12062 22 8519 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 86 87 389 392 44 14 0 4 7 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 9 45 16 122 165 3 12 1 6 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 338912 average: 5.45579 | standard deviation: 7.80876 | 0 300088 0 0 0 0 0 0 0 5460 5 22847 15 8547 47 1498 13 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 23 72 48 26 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 7 20 40 57 41 3 5 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338912 average: 3 | standard deviation: 0 | 0 0 0 338912 ] +miss_latency_NULL: [binsize: 2 max: 270 count: 151886717 average: 3.45795 | standard deviation: 5.18215 | 0 149232339 0 0 0 0 0 0 0 967168 602 1434707 493 54299 574 16370 170 112 2 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3741 6150 8984 10304 51755 196 509 88 111 143 4 23 9 11 17 5 17 5 8 27 4 15 2 9 6 9 472 4506 10321 18243 13984 43613 883 877 2441 340 822 17 25 50 17 23 15 17 60 7 30 13 21 47 21 27 9 21 24 90 134 133 147 269 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -52,12 +52,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 2 max: 218 count: 14874061 average: 5.10543 | standard deviation: 8.68005 | 0 13485161 0 0 0 0 0 0 0 129669 71 1200389 321 19342 354 4658 120 69 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 946 797 3688 3455 2377 59 103 45 35 24 6 0 1 3 5 3 8 4 3 2 5 4 5 2 7 3 3 1340 2962 4560 6434 5662 323 275 230 120 126 7 4 3 16 9 3 17 8 8 3 7 7 6 3 3 5 5 12 23 21 44 49 12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_NULL: [binsize: 2 max: 270 count: 9471875 average: 5.1858 | standard deviation: 15.4023 | 0 9121731 0 0 0 0 0 0 0 27134 22 181251 122 14247 125 1633 27 16 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 3347 3709 6401 48396 97 398 53 53 99 4 17 4 4 4 3 7 5 7 15 3 18 1 5 10 6 457 1055 3050 9771 7123 36234 361 508 1904 182 686 8 8 45 4 27 3 7 43 7 17 3 13 40 5 12 5 11 15 22 105 69 105 209 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_NULL: [binsize: 2 max: 213 count: 126380154 average: 3.11846 | standard deviation: 2.02437 | 0 125567964 0 0 0 0 0 0 0 794781 477 434 39 45 17 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1899 1850 989 40 49 13 20 10 1 5 1 2 0 2 1 1 2 1 1 3 0 0 0 1 2 2 0 2035 4358 4208 198 205 161 86 103 7 4 4 1 2 6 4 3 3 3 4 1 1 2 0 5 2 6 5 2 33 28 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 490994 average: 6.03795 | standard deviation: 9.42736 | 0 425859 0 0 0 0 0 0 0 10420 25 32755 15 11997 35 8470 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 81 392 393 46 9 3 4 5 1 0 0 0 1 0 0 0 1 2 0 2 0 0 0 1 1 0 8 55 15 120 161 1 4 2 4 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 212 count: 338995 average: 5.4473 | standard deviation: 7.76902 | 0 300232 0 0 0 0 0 0 0 5467 6 22824 18 8560 47 1454 7 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 73 49 24 3 0 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 8 22 41 52 46 4 3 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338995 average: 3 | standard deviation: 0 | 0 0 0 338995 ] +miss_latency_LD_NULL: [binsize: 2 max: 216 count: 14872957 average: 5.10751 | standard deviation: 8.69983 | 0 13484012 0 0 0 0 0 0 0 129492 97 1200237 320 19353 366 4823 123 70 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 919 791 3671 3477 2370 72 98 38 42 34 2 3 2 5 2 3 1 0 2 0 1 4 1 3 1 5 6 1421 2829 4534 6423 5889 348 264 260 122 133 10 9 4 7 1 7 4 5 1 6 6 4 4 8 6 4 10 4 25 22 57 48 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 270 count: 9468113 average: 5.20871 | standard deviation: 15.524 | 0 9118662 0 0 0 0 0 0 0 27223 26 178592 96 14286 118 1530 29 18 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 770 3337 3846 6346 49267 90 393 32 59 105 1 20 4 2 15 2 13 3 2 21 2 9 0 4 4 3 465 1055 3041 9490 7168 37336 375 495 2067 204 683 2 13 45 6 20 6 10 50 5 24 6 14 40 6 18 3 9 17 31 81 62 93 235 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_NULL: [binsize: 2 max: 214 count: 126376928 average: 3.11849 | standard deviation: 2.02507 | 0 125564891 0 0 0 0 0 0 0 794588 449 385 48 51 21 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1937 1912 1006 41 48 20 17 14 2 3 1 0 2 3 0 0 3 2 2 6 1 2 1 1 0 1 1 2014 4386 4163 214 182 154 101 111 7 3 5 3 1 4 2 2 3 5 1 0 1 3 3 7 3 1 2 3 33 29 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_RMW_Read_NULL: [binsize: 2 max: 215 count: 490895 average: 6.04017 | standard deviation: 9.43848 | 0 425774 0 0 0 0 0 0 0 10405 25 32646 14 12062 22 8519 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 86 87 389 392 44 14 0 4 7 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 9 45 16 122 165 3 12 1 6 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 338912 average: 5.45579 | standard deviation: 7.80876 | 0 300088 0 0 0 0 0 0 0 5460 5 22847 15 8547 47 1498 13 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 23 72 48 26 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 7 20 40 57 41 3 5 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338912 average: 3 | standard deviation: 0 | 0 0 0 338912 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -71,10 +71,10 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 19 count: 10868463 average: 0.59509 | standard deviation: 1.42425 | 9251200 1053 635 975 1612868 1042 121 110 109 275 4 9 9 51 0 0 1 0 0 1 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 19 count: 6100210 average: 1.0435 | standard deviation: 1.75778 | 4509207 549 222 262 1588385 908 120 110 101 271 4 9 9 51 0 0 1 0 0 1 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4687708 average: 0.0215679 | standard deviation: 0.291665 | 4661845 408 333 614 24389 107 1 0 8 3 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 80545 average: 0.0133217 | standard deviation: 0.21003 | 80148 96 80 99 94 27 0 0 0 1 ] +Total_delay_cycles: [binsize: 1 max: 13 count: 10870925 average: 0.594928 | standard deviation: 1.42414 | 9253812 1012 651 887 1612847 1000 118 100 122 292 7 8 8 61 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6098339 average: 1.04364 | standard deviation: 1.75794 | 4507669 499 240 245 1588105 876 117 99 116 289 7 8 8 61 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4691441 average: 0.0216927 | standard deviation: 0.292466 | 4665403 421 342 554 24629 83 1 0 6 2 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 81145 average: 0.0143817 | standard deviation: 0.224975 | 80740 92 69 88 113 41 0 1 0 1 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -86,82 +86,82 @@ Total_delay_cycles: [binsize: 1 max: 19 count: 10868463 average: 0.59509 | stand Resource Usage -------------- page_size: 4096 -user_time: 784 -system_time: 1 -page_reclaims: 148403 -page_faults: 35 +user_time: 479 +system_time: 0 +page_reclaims: 146294 +page_faults: 18 swaps: 0 -block_inputs: 20600 -block_outputs: 736 +block_inputs: 16016 +block_outputs: 528 Network Stats ------------- -total_msg_count_Control: 8498316 67986528 -total_msg_count_Request_Control: 239871 1918968 -total_msg_count_Response_Data: 8796423 633342456 -total_msg_count_Response_Control: 10879743 87037944 -total_msg_count_Writeback_Data: 4769004 343368288 -total_msg_count_Writeback_Control: 289518 2316144 -total_msgs: 33472875 total_bytes: 1135970328 +total_msg_count_Control: 8502765 68022120 +total_msg_count_Request_Control: 241699 1933592 +total_msg_count_Response_Data: 8804706 633938832 +total_msg_count_Response_Control: 10887918 87103344 +total_msg_count_Writeback_Data: 4768101 343303272 +total_msg_count_Writeback_Control: 288537 2308296 +total_msgs: 33493726 total_bytes: 1136609456 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.0315382 - links_utilized_percent_switch_0_link_0: 0.037253 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.0258234 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 41862 334896 [ 41862 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 805815 58018680 [ 0 805815 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 466550 3732400 [ 0 466550 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 817583 6540664 [ 817583 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 39381 2835432 [ 0 39381 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 495523 3964184 [ 0 15983 479540 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 408673 29424456 [ 408575 98 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 34072 272576 [ 34072 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.0345328 + links_utilized_percent_switch_0_link_0: 0.0411595 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.0279062 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 42248 337984 [ 42248 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 890958 64148976 [ 0 890958 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 508775 4070200 [ 0 508775 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 902852 7222816 [ 902852 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 39576 2849472 [ 0 39576 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 538021 4304168 [ 0 16306 521715 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 441060 31756320 [ 440947 113 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 43642 349136 [ 43642 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0764968 - links_utilized_percent_switch_1_link_0: 0.0852244 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.0677692 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 38683 309464 [ 38683 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 1828030 131618160 [ 0 1828030 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 1263466 10107728 [ 0 1263466 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 1837549 14700392 [ 1837549 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 32554 2343888 [ 0 32554 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 1296124 10368992 [ 0 16536 1279588 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 1180995 85031640 [ 1180869 126 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 62434 499472 [ 62434 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.0735425 + links_utilized_percent_switch_1_link_0: 0.0813498 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.0657351 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 38897 311176 [ 38897 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 1741967 125421624 [ 0 1741967 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 1220914 9767312 [ 0 1220914 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 1751526 14012208 [ 1751526 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 32667 2352024 [ 0 32667 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1253613 10028904 [ 0 16665 1236948 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 1148307 82678104 [ 1148172 135 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 52537 420296 [ 52537 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.112511 - links_utilized_percent_switch_2_link_0: 0.0996306 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.125392 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Control: 2655132 21241056 [ 2655132 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 201773 14527656 [ 0 201773 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 1880978 15047824 [ 0 121850 1759128 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 1589668 114456096 [ 1589444 224 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 96506 772048 [ 96506 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 78781 630248 [ 78781 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 2682566 193144752 [ 0 2682566 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 1722824 13782592 [ 0 1722824 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.112637 + links_utilized_percent_switch_2_link_0: 0.0997841 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.125489 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Control: 2654378 21235024 [ 2654378 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 204194 14701968 [ 0 204194 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 1883048 15064384 [ 0 124385 1758663 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 1589367 114434424 [ 1589119 248 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 96179 769432 [ 96179 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 79409 635272 [ 79409 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 2682782 193160304 [ 0 2682782 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 1723320 13786560 [ 0 1723320 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.00665498 - links_utilized_percent_switch_3_link_0: 0.00509748 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.00821249 bw: 16000 base_latency: 1 +links_utilized_percent_switch_3: 0.0067475 + links_utilized_percent_switch_3_link_0: 0.00517033 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.00832467 bw: 16000 base_latency: 1 - outgoing_messages_switch_3_link_0_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 96523 6949656 [ 0 96523 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 15587 124696 [ 0 15587 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 177640 12790080 [ 0 177640 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 112110 896880 [ 0 112110 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 97783 7040376 [ 0 97783 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 16569 132552 [ 0 16569 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 179877 12951144 [ 0 179877 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 114352 914816 [ 0 114352 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 @@ -172,117 +172,117 @@ links_utilized_percent_switch_4: 0 switch_5_inlinks: 5 switch_5_outlinks: 5 -links_utilized_percent_switch_5: 0.0454411 - links_utilized_percent_switch_5_link_0: 0.037253 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.0852244 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_2: 0.0996306 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_3: 0.00509748 bw: 16000 base_latency: 1 +links_utilized_percent_switch_5: 0.0454927 + links_utilized_percent_switch_5_link_0: 0.0411595 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.0813498 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_2: 0.0997841 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_3: 0.00517033 bw: 16000 base_latency: 1 links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1 - outgoing_messages_switch_5_link_0_Request_Control: 41862 334896 [ 41862 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 805815 58018680 [ 0 805815 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 466550 3732400 [ 0 466550 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 38683 309464 [ 38683 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 1828030 131618160 [ 0 1828030 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 1263466 10107728 [ 0 1263466 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Control: 2655132 21241056 [ 2655132 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Response_Data: 201773 14527656 [ 0 201773 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Response_Control: 1880978 15047824 [ 0 121850 1759128 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Writeback_Data: 1589668 114456096 [ 1589444 224 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Writeback_Control: 96506 772048 [ 96506 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Response_Data: 96523 6949656 [ 0 96523 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Response_Control: 15587 124696 [ 0 15587 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Request_Control: 42248 337984 [ 42248 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 890958 64148976 [ 0 890958 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 508775 4070200 [ 0 508775 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 38897 311176 [ 38897 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 1741967 125421624 [ 0 1741967 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 1220914 9767312 [ 0 1220914 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Control: 2654378 21235024 [ 2654378 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Response_Data: 204194 14701968 [ 0 204194 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Response_Control: 1883048 15064384 [ 0 124385 1758663 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Writeback_Data: 1589367 114434424 [ 1589119 248 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Writeback_Control: 96179 769432 [ 96179 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Response_Data: 97783 7040376 [ 0 97783 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Response_Control: 16569 132552 [ 0 16569 0 0 0 0 0 0 0 0 ] base_latency: 1 Cache Stats: system.ruby.l1_cntrl0.L1IcacheMemory - system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 313126 - system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 313126 + system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 352190 + system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 352190 system.ruby.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 system.ruby.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 system.ruby.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 system.ruby.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 313126 100% + system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 352190 100% Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory - system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 504457 - system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 504457 + system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 550662 + system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 550662 system.ruby.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.ruby.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.ruby.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 54.7331% - system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 45.2669% + system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 55.6706% + system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 44.3294% - system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 504457 100% + system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 550662 100% --- L1Cache --- - Event Counts - -Load [6004899 8869162 ] 14874061 -Ifetch [67402410 58977750 ] 126380160 -Store [5078812 5562047 ] 10640859 -Inv [16081 16662 ] 32743 -L1_Replacement [790678 1810849 ] 2601527 -Fwd_GETX [12181 11488 ] 23669 -Fwd_GETS [13596 10533 ] 24129 +Load [6569518 8303439 ] 14872957 +Ifetch [70368031 56008906 ] 126376937 +Store [5484765 5152067 ] 10636832 +Inv [16419 16800 ] 33219 +L1_Replacement [875917 1724584 ] 2600501 +Fwd_GETX [12082 11527 ] 23609 +Fwd_GETS [13743 10570 ] 24313 Fwd_GET_INSTR [4 0 ] 4 -Data [367 1125 ] 1492 -Data_Exclusive [240655 1040298 ] 1280953 -DataS_fromL1 [10533 13600 ] 24133 -Data_all_Acks [554260 773007 ] 1327267 -Ack [11768 9519 ] 21287 -Ack_all [12135 10644 ] 22779 -WB_Ack [442647 1243303 ] 1685950 +Data [398 1087 ] 1485 +Data_Exclusive [267040 1013910 ] 1280950 +DataS_fromL1 [10570 13747 ] 24317 +Data_all_Acks [612950 713223 ] 1326173 +Ack [11894 9559 ] 21453 +Ack_all [12292 10646 ] 22938 +WB_Ack [484589 1200709 ] 1685298 PF_Load [0 0 ] 0 PF_Ifetch [0 0 ] 0 PF_Store [0 0 ] 0 - Transitions - -NP Load [267792 1102795 ] 1370587 -NP Ifetch [313000 498627 ] 811627 -NP Store [210910 210451 ] 421361 -NP Inv [5429 3933 ] 9362 +NP Load [298305 1072264 ] 1370569 +NP Ifetch [352056 459391 ] 811447 +NP Store [226579 193953 ] 420532 +NP Inv [5722 3873 ] 9595 NP L1_Replacement [0 0 ] 0 NP PF_Load [0 0 ] 0 NP PF_Ifetch [0 0 ] 0 NP PF_Store [0 0 ] 0 -I Load [8313 10000 ] 18313 -I Ifetch [126 437 ] 563 -I Store [5674 5720 ] 11394 +I Load [8252 10124 ] 18376 +I Ifetch [134 456 ] 590 +I Store [5632 5779 ] 11411 I Inv [0 0 ] 0 -I L1_Replacement [8682 8060 ] 16742 +I L1_Replacement [8759 7985 ] 16744 I PF_Load [0 0 ] 0 I PF_Ifetch [0 0 ] 0 I PF_Store [0 0 ] 0 -S Load [551889 484566 ] 1036455 -S Ifetch [67089280 58478684 ] 125567964 -S Store [11768 9519 ] 21287 -S Inv [10451 12551 ] 23002 -S L1_Replacement [339349 559486 ] 898835 +S Load [574695 455064 ] 1029759 +S Ifetch [70015833 55549058 ] 125564891 +S Store [11894 9559 ] 21453 +S Inv [10461 12745 ] 23206 +S L1_Replacement [382569 515890 ] 898459 S PF_Load [0 0 ] 0 S PF_Store [0 0 ] 0 -E Load [1058703 2799902 ] 3858605 +E Load [1245572 2614603 ] 3860175 E Ifetch [0 0 ] 0 -E Store [78784 87850 ] 166634 -E Inv [103 52 ] 155 -E L1_Replacement [160570 950900 ] 1111470 -E Fwd_GETX [228 182 ] 410 -E Fwd_GETS [848 1108 ] 1956 +E Store [84229 82251 ] 166480 +E Inv [123 47 ] 170 +E L1_Replacement [181344 930396 ] 1111740 +E Fwd_GETX [229 170 ] 399 +E Fwd_GETS [930 990 ] 1920 E Fwd_GET_INSTR [0 0 ] 0 E PF_Load [0 0 ] 0 E PF_Store [0 0 ] 0 -M Load [4118202 4471899 ] 8590101 +M Load [4442694 4151384 ] 8594078 M Ifetch [0 0 ] 0 -M Store [4771676 5248507 ] 10020183 -M Inv [98 126 ] 224 -M L1_Replacement [282077 292403 ] 574480 -M Fwd_GETX [11953 11306 ] 23259 -M Fwd_GETS [12747 9423 ] 22170 +M Store [5156431 4860525 ] 10016956 +M Inv [113 135 ] 248 +M L1_Replacement [303245 270313 ] 573558 +M Fwd_GETX [11853 11357 ] 23210 +M Fwd_GETS [12813 9580 ] 22393 M Fwd_GET_INSTR [4 0 ] 4 M PF_Load [0 0 ] 0 M PF_Store [0 0 ] 0 @@ -292,9 +292,9 @@ IS Ifetch [0 0 ] 0 IS Store [0 0 ] 0 IS Inv [0 0 ] 0 IS L1_Replacement [0 0 ] 0 -IS Data_Exclusive [240655 1040298 ] 1280953 -IS DataS_fromL1 [10533 13600 ] 24133 -IS Data_all_Acks [338043 557961 ] 896004 +IS Data_Exclusive [267040 1013910 ] 1280950 +IS DataS_fromL1 [10570 13747 ] 24317 +IS Data_all_Acks [381137 514578 ] 895715 IS PF_Load [0 0 ] 0 IS PF_Store [0 0 ] 0 @@ -303,8 +303,8 @@ IM Ifetch [0 0 ] 0 IM Store [0 0 ] 0 IM Inv [0 0 ] 0 IM L1_Replacement [0 0 ] 0 -IM Data [367 1125 ] 1492 -IM Data_all_Acks [216217 215046 ] 431263 +IM Data [398 1087 ] 1485 +IM Data_all_Acks [231813 198645 ] 430458 IM Ack [0 0 ] 0 IM PF_Load [0 0 ] 0 IM PF_Store [0 0 ] 0 @@ -314,8 +314,8 @@ SM Ifetch [0 0 ] 0 SM Store [0 0 ] 0 SM Inv [0 0 ] 0 SM L1_Replacement [0 0 ] 0 -SM Ack [11768 9519 ] 21287 -SM Ack_all [12135 10644 ] 22779 +SM Ack [11894 9559 ] 21453 +SM Ack_all [12292 10646 ] 22938 SM PF_Load [0 0 ] 0 SM PF_Store [0 0 ] 0 @@ -331,14 +331,14 @@ IS_I PF_Load [0 0 ] 0 IS_I PF_Store [0 0 ] 0 M_I Load [0 0 ] 0 -M_I Ifetch [4 2 ] 6 +M_I Ifetch [8 1 ] 9 M_I Store [0 0 ] 0 M_I Inv [0 0 ] 0 M_I L1_Replacement [0 0 ] 0 M_I Fwd_GETX [0 0 ] 0 -M_I Fwd_GETS [1 2 ] 3 +M_I Fwd_GETS [0 0 ] 0 M_I Fwd_GET_INSTR [0 0 ] 0 -M_I WB_Ack [442646 1243301 ] 1685947 +M_I WB_Ack [484589 1200709 ] 1685298 M_I PF_Load [0 0 ] 0 M_I PF_Store [0 0 ] 0 @@ -347,7 +347,7 @@ SINK_WB_ACK Ifetch [0 0 ] 0 SINK_WB_ACK Store [0 0 ] 0 SINK_WB_ACK Inv [0 0 ] 0 SINK_WB_ACK L1_Replacement [0 0 ] 0 -SINK_WB_ACK WB_Ack [1 2 ] 3 +SINK_WB_ACK WB_Ack [0 0 ] 0 SINK_WB_ACK PF_Load [0 0 ] 0 SINK_WB_ACK PF_Store [0 0 ] 0 @@ -390,98 +390,98 @@ PF_IS_I DataS_fromL1 [0 0 ] 0 PF_IS_I Data_all_Acks [0 0 ] 0 Cache Stats: system.ruby.l1_cntrl1.L1IcacheMemory - system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 499064 - system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 499064 + system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 459847 + system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 459847 system.ruby.l1_cntrl1.L1IcacheMemory_total_prefetches: 0 system.ruby.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0 system.ruby.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0 system.ruby.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100% - system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 499064 100% + system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 459847 100% Cache Stats: system.ruby.l1_cntrl1.L1DcacheMemory - system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 1338485 - system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1338485 + system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 1291679 + system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1291679 system.ruby.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 system.ruby.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 system.ruby.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 - system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 83.1384% - system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 16.8616% + system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 83.797% + system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 16.203% - system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 1338485 100% + system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 1291679 100% Cache Stats: system.ruby.l2_cntrl0.L2cacheMemory - system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 225442 - system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 225442 + system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 227803 + system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 227803 system.ruby.l2_cntrl0.L2cacheMemory_total_prefetches: 0 system.ruby.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.ruby.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 25.7405% - system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 7.27238% - system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 66.9871% + system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 25.6248% + system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 7.23871% + system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 67.1365% - system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 225442 100% + system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 227803 100% --- L2Cache --- - Event Counts - -L1_GET_INSTR [812190 ] 812190 -L1_GETS [1389132 ] 1389132 -L1_GETX [432758 ] 432758 -L1_UPGRADE [21287 ] 21287 -L1_PUTX [1685953 ] 1685953 +L1_GET_INSTR [812037 ] 812037 +L1_GETS [1389190 ] 1389190 +L1_GETX [431946 ] 431946 +L1_UPGRADE [21453 ] 21453 +L1_PUTX [1685298 ] 1685298 L1_PUTX_old [0 ] 0 Fwd_L1_GETX [0 ] 0 Fwd_L1_GETS [0 ] 0 Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [96407 ] 96407 -L2_Replacement_clean [15703 ] 15703 -Mem_Data [177640 ] 177640 -Mem_Ack [112110 ] 112110 -WB_Data [23855 ] 23855 -WB_Data_clean [502 ] 502 -Ack [1764 ] 1764 -Ack_all [7976 ] 7976 -Unblock [24133 ] 24133 +L2_Replacement [97649 ] 97649 +L2_Replacement_clean [16703 ] 16703 +Mem_Data [179877 ] 179877 +Mem_Ack [114352 ] 114352 +WB_Data [24047 ] 24047 +WB_Data_clean [518 ] 518 +Ack [1736 ] 1736 +Ack_all [8297 ] 8297 +Unblock [24317 ] 24317 Unblock_Cancel [0 ] 0 -Exclusive_Unblock [1734995 ] 1734995 +Exclusive_Unblock [1734346 ] 1734346 MEM_Inv [0 ] 0 - Transitions - -NP L1_GET_INSTR [16391 ] 16391 -NP L1_GETS [33901 ] 33901 -NP L1_GETX [127348 ] 127348 +NP L1_GET_INSTR [16486 ] 16486 +NP L1_GETS [34061 ] 34061 +NP L1_GETX [129330 ] 129330 NP L1_PUTX [0 ] 0 NP L1_PUTX_old [0 ] 0 -SS L1_GET_INSTR [795630 ] 795630 -SS L1_GETS [83818 ] 83818 -SS L1_GETX [1691 ] 1691 -SS L1_UPGRADE [21287 ] 21287 -SS L1_PUTX [3 ] 3 +SS L1_GET_INSTR [795239 ] 795239 +SS L1_GETS [83682 ] 83682 +SS L1_GETX [1684 ] 1684 +SS L1_UPGRADE [21453 ] 21453 +SS L1_PUTX [0 ] 0 SS L1_PUTX_old [0 ] 0 -SS L2_Replacement [258 ] 258 -SS L2_Replacement_clean [7563 ] 7563 +SS L2_Replacement [262 ] 262 +SS L2_Replacement_clean [7865 ] 7865 SS MEM_Inv [0 ] 0 -M L1_GET_INSTR [165 ] 165 -M L1_GETS [1247052 ] 1247052 -M L1_GETX [280047 ] 280047 +M L1_GET_INSTR [308 ] 308 +M L1_GETS [1246889 ] 1246889 +M L1_GETX [277320 ] 277320 M L1_PUTX [0 ] 0 M L1_PUTX_old [0 ] 0 -M L2_Replacement [95992 ] 95992 -M L2_Replacement_clean [7918 ] 7918 +M L2_Replacement [97222 ] 97222 +M L2_Replacement_clean [8585 ] 8585 M MEM_Inv [0 ] 0 MT L1_GET_INSTR [4 ] 4 -MT L1_GETS [24129 ] 24129 -MT L1_GETX [23669 ] 23669 -MT L1_PUTX [1685947 ] 1685947 +MT L1_GETS [24313 ] 24313 +MT L1_GETX [23609 ] 23609 +MT L1_PUTX [1685298 ] 1685298 MT L1_PUTX_old [0 ] 0 -MT L2_Replacement [157 ] 157 -MT L2_Replacement_clean [222 ] 222 +MT L2_Replacement [165 ] 165 +MT L2_Replacement_clean [253 ] 253 MT MEM_Inv [0 ] 0 M_I L1_GET_INSTR [0 ] 0 @@ -490,7 +490,7 @@ M_I L1_GETX [0 ] 0 M_I L1_UPGRADE [0 ] 0 M_I L1_PUTX [0 ] 0 M_I L1_PUTX_old [0 ] 0 -M_I Mem_Ack [112110 ] 112110 +M_I Mem_Ack [114352 ] 114352 M_I MEM_Inv [0 ] 0 MT_I L1_GET_INSTR [0 ] 0 @@ -499,9 +499,9 @@ MT_I L1_GETX [0 ] 0 MT_I L1_UPGRADE [0 ] 0 MT_I L1_PUTX [0 ] 0 MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [108 ] 108 +MT_I WB_Data [114 ] 114 MT_I WB_Data_clean [0 ] 0 -MT_I Ack_all [49 ] 49 +MT_I Ack_all [51 ] 51 MT_I MEM_Inv [0 ] 0 MCT_I L1_GET_INSTR [0 ] 0 @@ -510,9 +510,9 @@ MCT_I L1_GETX [0 ] 0 MCT_I L1_UPGRADE [0 ] 0 MCT_I L1_PUTX [0 ] 0 MCT_I L1_PUTX_old [0 ] 0 -MCT_I WB_Data [116 ] 116 +MCT_I WB_Data [134 ] 134 MCT_I WB_Data_clean [0 ] 0 -MCT_I Ack_all [106 ] 106 +MCT_I Ack_all [119 ] 119 I_I L1_GET_INSTR [0 ] 0 I_I L1_GETS [0 ] 0 @@ -520,8 +520,8 @@ I_I L1_GETX [0 ] 0 I_I L1_UPGRADE [0 ] 0 I_I L1_PUTX [0 ] 0 I_I L1_PUTX_old [0 ] 0 -I_I Ack [1506 ] 1506 -I_I Ack_all [7563 ] 7563 +I_I Ack [1475 ] 1475 +I_I Ack_all [7865 ] 7865 S_I L1_GET_INSTR [0 ] 0 S_I L1_GETS [0 ] 0 @@ -529,8 +529,8 @@ S_I L1_GETX [0 ] 0 S_I L1_UPGRADE [0 ] 0 S_I L1_PUTX [0 ] 0 S_I L1_PUTX_old [0 ] 0 -S_I Ack [258 ] 258 -S_I Ack_all [258 ] 258 +S_I Ack [261 ] 261 +S_I Ack_all [262 ] 262 S_I MEM_Inv [0 ] 0 ISS L1_GET_INSTR [0 ] 0 @@ -540,7 +540,7 @@ ISS L1_PUTX [0 ] 0 ISS L1_PUTX_old [0 ] 0 ISS L2_Replacement [0 ] 0 ISS L2_Replacement_clean [0 ] 0 -ISS Mem_Data [33901 ] 33901 +ISS Mem_Data [34061 ] 34061 ISS MEM_Inv [0 ] 0 IS L1_GET_INSTR [0 ] 0 @@ -550,7 +550,7 @@ IS L1_PUTX [0 ] 0 IS L1_PUTX_old [0 ] 0 IS L2_Replacement [0 ] 0 IS L2_Replacement_clean [0 ] 0 -IS Mem_Data [16391 ] 16391 +IS Mem_Data [16486 ] 16486 IS MEM_Inv [0 ] 0 IM L1_GET_INSTR [0 ] 0 @@ -560,11 +560,11 @@ IM L1_PUTX [0 ] 0 IM L1_PUTX_old [0 ] 0 IM L2_Replacement [0 ] 0 IM L2_Replacement_clean [0 ] 0 -IM Mem_Data [127348 ] 127348 +IM Mem_Data [129330 ] 129330 IM MEM_Inv [0 ] 0 SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [186 ] 186 +SS_MB L1_GETS [183 ] 183 SS_MB L1_GETX [1 ] 1 SS_MB L1_UPGRADE [0 ] 0 SS_MB L1_PUTX [0 ] 0 @@ -572,11 +572,11 @@ SS_MB L1_PUTX_old [0 ] 0 SS_MB L2_Replacement [0 ] 0 SS_MB L2_Replacement_clean [0 ] 0 SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [22978 ] 22978 +SS_MB Exclusive_Unblock [23137 ] 23137 SS_MB MEM_Inv [0 ] 0 MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [46 ] 46 +MT_MB L1_GETS [62 ] 62 MT_MB L1_GETX [2 ] 2 MT_MB L1_UPGRADE [0 ] 0 MT_MB L1_PUTX [0 ] 0 @@ -584,31 +584,20 @@ MT_MB L1_PUTX_old [0 ] 0 MT_MB L2_Replacement [0 ] 0 MT_MB L2_Replacement_clean [0 ] 0 MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [1712017 ] 1712017 +MT_MB Exclusive_Unblock [1711209 ] 1711209 MT_MB MEM_Inv [0 ] 0 -M_MB L1_GET_INSTR [0 ] 0 -M_MB L1_GETS [0 ] 0 -M_MB L1_GETX [0 ] 0 -M_MB L1_UPGRADE [0 ] 0 -M_MB L1_PUTX [0 ] 0 -M_MB L1_PUTX_old [0 ] 0 -M_MB L2_Replacement [0 ] 0 -M_MB L2_Replacement_clean [0 ] 0 -M_MB Exclusive_Unblock [0 ] 0 -M_MB MEM_Inv [0 ] 0 - MT_IIB L1_GET_INSTR [0 ] 0 MT_IIB L1_GETS [0 ] 0 MT_IIB L1_GETX [0 ] 0 MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [3 ] 3 +MT_IIB L1_PUTX [0 ] 0 MT_IIB L1_PUTX_old [0 ] 0 MT_IIB L2_Replacement [0 ] 0 MT_IIB L2_Replacement_clean [0 ] 0 -MT_IIB WB_Data [23620 ] 23620 -MT_IIB WB_Data_clean [502 ] 502 -MT_IIB Unblock [11 ] 11 +MT_IIB WB_Data [23791 ] 23791 +MT_IIB WB_Data_clean [518 ] 518 +MT_IIB Unblock [8 ] 8 MT_IIB MEM_Inv [0 ] 0 MT_IB L1_GET_INSTR [0 ] 0 @@ -619,7 +608,7 @@ MT_IB L1_PUTX [0 ] 0 MT_IB L1_PUTX_old [0 ] 0 MT_IB L2_Replacement [0 ] 0 MT_IB L2_Replacement_clean [0 ] 0 -MT_IB WB_Data [11 ] 11 +MT_IB WB_Data [8 ] 8 MT_IB WB_Data_clean [0 ] 0 MT_IB Unblock_Cancel [0 ] 0 MT_IB MEM_Inv [0 ] 0 @@ -632,41 +621,41 @@ MT_SB L1_PUTX [0 ] 0 MT_SB L1_PUTX_old [0 ] 0 MT_SB L2_Replacement [0 ] 0 MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [24122 ] 24122 +MT_SB Unblock [24309 ] 24309 MT_SB MEM_Inv [0 ] 0 Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 274163 - memory_reads: 177640 - memory_writes: 96523 - memory_refreshes: 588410 - memory_total_request_delays: 1038324 - memory_delays_per_request: 3.78725 - memory_delays_in_input_queue: 39505 - memory_delays_behind_head_of_bank_queue: 7889 - memory_delays_stalled_at_head_of_bank_queue: 990930 - memory_stalls_for_bank_busy: 981321 + memory_total_requests: 277660 + memory_reads: 179877 + memory_writes: 97783 + memory_refreshes: 595612 + memory_total_request_delays: 1053031 + memory_delays_per_request: 3.79252 + memory_delays_in_input_queue: 41105 + memory_delays_behind_head_of_bank_queue: 8032 + memory_delays_stalled_at_head_of_bank_queue: 1003894 + memory_stalls_for_bank_busy: 993997 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 2239 - memory_stalls_for_bus: 7329 + memory_stalls_for_arbitration: 2275 + memory_stalls_for_bus: 7591 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 29 - memory_stalls_for_read_read_turnaround: 12 - accesses_per_bank: 9082 9112 8244 8400 9230 8573 8966 8230 8398 8230 8230 8246 8347 8114 8111 7298 8351 8467 8382 8429 8595 8485 8298 8250 8587 8384 8675 9378 9287 9169 10231 8384 + memory_stalls_for_read_write_turnaround: 24 + memory_stalls_for_read_read_turnaround: 7 + accesses_per_bank: 9197 9271 8435 8566 9408 8743 9113 8368 8530 8379 8370 8376 8453 8237 8220 7443 8424 8515 8423 8429 8600 8511 8363 8339 8693 8492 8814 9468 9371 9231 10342 8536 --- Directory --- - Event Counts - -Fetch [177640 ] 177640 -Data [96523 ] 96523 -Memory_Data [177640 ] 177640 -Memory_Ack [96523 ] 96523 +Fetch [179877 ] 179877 +Data [97783 ] 97783 +Memory_Data [179877 ] 179877 +Memory_Ack [97783 ] 97783 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -CleanReplacement [15587 ] 15587 +CleanReplacement [16569 ] 16569 - Transitions - -I Fetch [177640 ] 177640 +I Fetch [179877 ] 179877 I DMA_READ [0 ] 0 I DMA_WRITE [0 ] 0 @@ -682,20 +671,20 @@ ID_W Memory_Ack [0 ] 0 ID_W DMA_READ [0 ] 0 ID_W DMA_WRITE [0 ] 0 -M Data [96523 ] 96523 +M Data [97783 ] 97783 M DMA_READ [0 ] 0 M DMA_WRITE [0 ] 0 -M CleanReplacement [15587 ] 15587 +M CleanReplacement [16569 ] 16569 IM Fetch [0 ] 0 IM Data [0 ] 0 -IM Memory_Data [177640 ] 177640 +IM Memory_Data [179877 ] 179877 IM DMA_READ [0 ] 0 IM DMA_WRITE [0 ] 0 MI Fetch [0 ] 0 MI Data [0 ] 0 -MI Memory_Ack [96523 ] 96523 +MI Memory_Ack [97783 ] 97783 MI DMA_READ [0 ] 0 MI DMA_WRITE [0 ] 0 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index ddc70162e..0fb07bdf2 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-bo gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 28 2013 10:05:24 -gem5 started Mar 28 2013 10:05:51 +gem5 compiled Apr 18 2013 13:38:36 +gem5 started Apr 18 2013 13:38:48 gem5 executing on ribera.cs.wisc.edu command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5208135619000 because m5_exit instruction encountered +Exiting @ tick 5205148879000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index d9c7ac7b1..79f3ff0c1 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.208136 # Number of seconds simulated -sim_ticks 5208135619000 # Number of ticks simulated -final_tick 5208135619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.205149 # Number of seconds simulated +sim_ticks 5205148879000 # Number of ticks simulated +final_tick 5205148879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129465 # Simulator instruction rate (inst/s) -host_op_rate 248187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6321029655 # Simulator tick rate (ticks/s) -host_mem_usage 868876 # Number of bytes of host memory used -host_seconds 823.94 # Real time elapsed on the host -sim_insts 106670761 # Number of instructions simulated -sim_ops 204490715 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 35248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 110464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 48224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 539219248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 38302123 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 112752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 59160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 471821984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 55029081 # Number of bytes read from this memory -system.physmem.bytes_read::total 1104738284 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 539219248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 471821984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1011041232 # Number of instructions bytes read from this memory +host_inst_rate 128983 # Simulator instruction rate (inst/s) +host_op_rate 247272 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6293860084 # Simulator tick rate (ticks/s) +host_mem_usage 868904 # Number of bytes of host memory used +host_seconds 827.02 # Real time elapsed on the host +sim_insts 106671342 # Number of instructions simulated +sim_ops 204498755 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 35240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 160344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 75328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 562944184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 41978278 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 62896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 30152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448071240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 51341424 # Number of bytes read from this memory +system.physmem.bytes_read::total 1104699086 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 562944184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448071240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1011015424 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 30881325 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 36960563 # Number of bytes written to this memory -system.physmem.bytes_written::total 70833008 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 822 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 13808 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 6028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 67402406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 6418181 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14094 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 7395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 58977748 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9244544 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142085026 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu0.data 33612947 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 34199698 # Number of bytes written to this memory +system.physmem.bytes_written::total 70803765 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 821 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 20043 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 9416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 70368023 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 6999506 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 7862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3769 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56008905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8662168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142080513 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4645692 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 5165176 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9857606 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 21210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 9259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 103534026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7354287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 21649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 11359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 90593260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 10565985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 212117803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 103534026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 90593260 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 194127286 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 574314 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 5025316 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 4781707 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9853761 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 30805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 14472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 108151409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 8064760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 12083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 5793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 86082310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 9863584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 212231986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 108151409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 86082310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 194233719 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 574643 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 5929439 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 7096697 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13600454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 581082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 21210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 9262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 103534026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13283726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 21649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 11359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 90593260 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 17662682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 225718257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 822 # Total number of read requests seen +system.physmem.bw_write::cpu0.data 6457634 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6570359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13602640 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 581414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 30805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 14475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 108151409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 14522394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 12083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 5793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 86082310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 16433943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 225834626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 821 # Total number of read requests seen system.physmem.writeReqs 46736 # Total number of write requests seen -system.physmem.cpureqs 47278 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 52608 # Total number of bytes read from memory +system.physmem.cpureqs 47279 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 52544 # Total number of bytes read from memory system.physmem.bytesWritten 2991104 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 35248 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 35240 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 64 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 32 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 32 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 48 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 2992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2928 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2784 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2944 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2848 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2856 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2848 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 3024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 3024 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2944 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2960 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 2856 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 2896 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2960 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2928 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry -system.physmem.totGap 67214585000 # Total gap between requests +system.physmem.numWrRetry 31 # Number of times wr buffer was full causing retry +system.physmem.totGap 64277169000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 310 # Categorize read packet sizes +system.physmem.readPktSize::3 309 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 512 # Categorize read packet sizes @@ -130,7 +130,7 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 46736 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 339 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see @@ -162,15 +162,15 @@ system.physmem.rdQLenPdf::28 2 # Wh system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1974 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1999 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see @@ -185,23 +185,23 @@ system.physmem.wrQLenPdf::19 2032 # Wh system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 58 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32 # What write queue length does an incoming req see -system.physmem.totQLat 44820022 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 56685022 # Sum of mem lat for all requests -system.physmem.totBusLat 4110000 # Total cycles spent in databus access -system.physmem.totBankLat 7755000 # Total cycles spent in bank access -system.physmem.avgQLat 54525.57 # Average queueing delay per request -system.physmem.avgBankLat 9434.31 # Average bank access latency per request +system.physmem.wrQLenPdf::26 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see +system.physmem.totQLat 41690522 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 53523022 # Sum of mem lat for all requests +system.physmem.totBusLat 4105000 # Total cycles spent in databus access +system.physmem.totBankLat 7727500 # Total cycles spent in bank access +system.physmem.avgQLat 50780.17 # Average queueing delay per request +system.physmem.avgBankLat 9412.30 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 68959.88 # Average memory access latency +system.physmem.avgMemAccLat 65192.48 # Average memory access latency system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s @@ -210,11 +210,11 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.00 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.15 # Average write queue length over time -system.physmem.readRowHits 707 # Number of row buffer hits during reads +system.physmem.readRowHits 704 # Number of row buffer hits during reads system.physmem.writeRowHits 45223 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.01 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes -system.physmem.avgGap 1413318.16 # Average gap between requests +system.physmem.avgGap 1351581.66 # Average gap between requests system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -275,52 +275,52 @@ system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.numCycles 10415384713 # number of cpu cycles simulated +system.cpu0.numCycles 10410297758 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 58007070 # Number of instructions committed -system.cpu0.committedOps 111693294 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 104699305 # Number of integer alu accesses +system.cpu0.committedInsts 60288276 # Number of instructions committed +system.cpu0.committedOps 115773081 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108731496 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9926831 # number of instructions that are conditional controls -system.cpu0.num_int_insts 104699305 # number of integer instructions +system.cpu0.num_conditional_control_insts 10277696 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108731496 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 256785271 # number of times the integer registers were read -system.cpu0.num_int_register_writes 132412981 # number of times the integer registers were written +system.cpu0.num_int_register_reads 267473663 # number of times the integer registers were read +system.cpu0.num_int_register_writes 137108635 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 11918647 # number of memory refs -system.cpu0.num_load_insts 7262283 # Number of load instructions -system.cpu0.num_store_insts 4656364 # Number of store instructions -system.cpu0.num_idle_cycles 9902585340.160280 # Number of idle cycles -system.cpu0.num_busy_cycles 512799372.839719 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049235 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950765 # Percentage of idle cycles +system.cpu0.num_mem_refs 12880520 # number of memory refs +system.cpu0.num_load_insts 7843945 # Number of load instructions +system.cpu0.num_store_insts 5036575 # Number of store instructions +system.cpu0.num_idle_cycles 9879714305.974102 # Number of idle cycles +system.cpu0.num_busy_cycles 530583452.025898 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050967 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949033 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10416271238 # number of cpu cycles simulated +system.cpu1.numCycles 10407399002 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48663691 # Number of instructions committed -system.cpu1.committedOps 92797421 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 89245391 # Number of integer alu accesses +system.cpu1.committedInsts 46383066 # Number of instructions committed +system.cpu1.committedOps 88725674 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 85218419 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8303775 # number of instructions that are conditional controls -system.cpu1.num_int_insts 89245391 # number of integer instructions +system.cpu1.num_conditional_control_insts 7955161 # number of instructions that are conditional controls +system.cpu1.num_int_insts 85218419 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 224679883 # number of times the integer registers were read -system.cpu1.num_int_register_writes 106822538 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213998429 # number of times the integer registers were read +system.cpu1.num_int_register_writes 102139748 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 14447171 # number of memory refs -system.cpu1.num_load_insts 9256256 # Number of load instructions -system.cpu1.num_store_insts 5190915 # Number of store instructions -system.cpu1.num_idle_cycles 10072379281.574066 # Number of idle cycles -system.cpu1.num_busy_cycles 343891956.425934 # Number of busy cycles -system.cpu1.not_idle_fraction 0.033015 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.966985 # Percentage of idle cycles +system.cpu1.num_mem_refs 13480502 # number of memory refs +system.cpu1.num_load_insts 8673583 # Number of load instructions +system.cpu1.num_store_insts 4806919 # Number of store instructions +system.cpu1.num_idle_cycles 10081113907.619320 # Number of idle cycles +system.cpu1.num_busy_cycles 326285094.380681 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031351 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968649 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |