diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-10 18:06:43 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-10 18:06:43 -0600 |
| commit | e76442e203bd4ce18e897658a17756a3d00bdeb8 (patch) | |
| tree | 93af3959085146bd965f4f7e8ad8e1dad142ce3d /tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level | |
| parent | 7bb65dd4345401f40eccb5c23b563558dfd9e854 (diff) | |
| download | gem5-e76442e203bd4ce18e897658a17756a3d00bdeb8.tar.xz | |
stats: changes due to recent changesets.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt | 1862 |
1 files changed, 927 insertions, 935 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 92c4535bc..384e2ffa5 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.305804 # Number of seconds simulated -sim_ticks 5305803886500 # Number of ticks simulated -final_tick 5305803886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.305853 # Number of seconds simulated +sim_ticks 5305853045500 # Number of ticks simulated +final_tick 5305853045500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199055 # Simulator instruction rate (inst/s) -host_op_rate 381625 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9885187347 # Simulator tick rate (ticks/s) -host_mem_usage 854320 # Number of bytes of host memory used -host_seconds 536.74 # Real time elapsed on the host -sim_insts 106841423 # Number of instructions simulated -sim_ops 204834575 # Number of ops (including micro ops) simulated +host_inst_rate 145601 # Simulator instruction rate (inst/s) +host_op_rate 279059 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7202357719 # Simulator tick rate (ticks/s) +host_mem_usage 842312 # Number of bytes of host memory used +host_seconds 736.68 # Real time elapsed on the host +sim_insts 107261903 # Number of instructions simulated +sim_ops 205578304 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11434048 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 11434048 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9128256 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 9128256 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 178657 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 178657 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 142629 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 142629 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 2155008 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 2155008 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1720428 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1720428 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3875436 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3875436 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 178657 # Number of read requests accepted -system.mem_ctrls.writeReqs 142629 # Number of write requests accepted -system.mem_ctrls.readBursts 178657 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 142629 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 11379712 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 54336 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 9119680 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 11434048 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 9128256 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 849 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 104 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11415232 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11415232 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9161984 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9161984 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 178363 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 178363 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 143156 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 143156 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 2151441 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2151441 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1726769 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1726769 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 3878211 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3878211 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 178363 # Number of read requests accepted +system.mem_ctrls.writeReqs 143156 # Number of write requests accepted +system.mem_ctrls.readBursts 178363 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 143156 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 11360576 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 54656 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9153536 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11415232 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9161984 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 854 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 108 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 10773 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 10609 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 10875 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 11019 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 11847 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 12404 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 11308 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 10254 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 10790 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 10382 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 10431 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 13895 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 11043 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 10450 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 11056 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 10672 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 8646 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 8740 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 8909 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 9072 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 9699 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 9645 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 8889 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 8365 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 8684 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 8653 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 8512 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 9107 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 8716 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 8645 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 9206 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 9007 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 10856 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10881 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10729 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11226 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 11595 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 12060 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 11357 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10544 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 10640 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 10408 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 10338 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 14247 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 10851 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10291 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10803 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10683 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 8741 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 8453 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8515 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 9195 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9530 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9557 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 9142 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8665 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 8844 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 8855 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 8455 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9314 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 8873 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 8616 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 9161 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 9108 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5305803752000 # Total gap between requests +system.mem_ctrls.totGap 5305852911000 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 178657 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 178363 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 142629 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 177742 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 66 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 143156 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 177440 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 69 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,39 +135,39 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2048 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2805 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8516 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9095 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8606 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 9164 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9192 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8373 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9017 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9032 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8415 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8498 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8325 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8422 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8038 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8077 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8151 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 7943 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 129 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 121 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 110 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 90 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 88 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 71 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2057 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2808 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8578 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9141 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8600 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 9229 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9219 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8361 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9057 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9077 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8449 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8526 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8348 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8471 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8060 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8092 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8178 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 7986 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 125 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 114 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 101 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 94 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 84 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 73 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 59 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::40 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 36 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 13 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 33 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 27 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 19 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 9 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see @@ -184,370 +184,373 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 60600 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 338.272739 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 199.847297 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 343.861949 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20364 33.60% 33.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 14670 24.21% 57.81% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6315 10.42% 68.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3448 5.69% 73.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2734 4.51% 78.43% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1855 3.06% 81.50% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1401 2.31% 83.81% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1433 2.36% 86.17% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8380 13.83% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 60600 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 7887 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.539115 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 318.374099 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 7881 99.92% 99.92% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 60721 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 337.841076 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 199.411090 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 344.057801 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20489 33.74% 33.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 14673 24.16% 57.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6364 10.48% 68.39% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3396 5.59% 73.98% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2745 4.52% 78.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1826 3.01% 81.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1362 2.24% 83.75% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1430 2.36% 86.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8436 13.89% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 60721 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 7928 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.388118 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 317.537098 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 7922 99.92% 99.92% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::1024-2047 2 0.03% 99.95% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::2048-3071 2 0.03% 99.97% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 7887 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 7887 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 18.067072 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.711824 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 4.086646 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 5792 73.44% 73.44% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 14 0.18% 73.61% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 155 1.97% 75.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 18 0.23% 75.81% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 48 0.61% 76.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 474 6.01% 82.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 162 2.05% 84.48% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 48 0.61% 85.09% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 632 8.01% 93.10% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 129 1.64% 94.74% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 11 0.14% 94.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 12 0.15% 95.03% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 299 3.79% 98.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 7 0.09% 98.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 7 0.09% 99.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 8 0.10% 99.10% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 7 0.09% 99.19% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 5 0.06% 99.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 6 0.08% 99.33% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.37% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 1 0.01% 99.38% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 4 0.05% 99.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 1 0.01% 99.44% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 3 0.04% 99.48% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 11 0.14% 99.62% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 6 0.08% 99.70% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 3 0.04% 99.73% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 1 0.01% 99.75% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 8 0.10% 99.85% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 2 0.03% 99.87% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 3 0.04% 99.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::51 7 0.09% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 7887 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1946379497 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5280279497 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 889040000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 10946.52 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 7928 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 7928 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 18.040363 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.696882 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 3.983964 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 5814 73.34% 73.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 14 0.18% 73.51% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 181 2.28% 75.79% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 14 0.18% 75.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 36 0.45% 76.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 489 6.17% 82.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 149 1.88% 84.47% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 53 0.67% 85.14% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 653 8.24% 93.38% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 113 1.43% 94.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 3 0.04% 94.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 13 0.16% 95.01% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 312 3.94% 98.94% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 4 0.05% 98.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 10 0.13% 99.12% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 5 0.06% 99.18% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 9 0.11% 99.29% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 9 0.11% 99.41% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 2 0.03% 99.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.47% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::36 4 0.05% 99.52% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 5 0.06% 99.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 2 0.03% 99.61% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 3 0.04% 99.65% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 6 0.08% 99.72% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 2 0.03% 99.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 1 0.01% 99.76% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 3 0.04% 99.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 6 0.08% 99.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 2 0.03% 99.90% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::46 1 0.01% 99.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 1 0.01% 99.94% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::49 2 0.03% 99.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::51 3 0.04% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 7928 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1963253998 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5291547748 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 887545000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 11060.03 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29696.52 # Average memory access latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29810.03 # Average memory access latency per DRAM burst system.mem_ctrls.avgRdBW 2.14 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1.73 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2.15 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1.73 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 0.03 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.29 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 141783 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 117919 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.74 # Row buffer hit rate for reads +system.mem_ctrls.avgWrQLen 24.94 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 141459 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 118352 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.69 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 82.74 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 16514270.00 # Average gap between requests -system.mem_ctrls.pageHitRate 81.07 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 229566960 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 125259750 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 694894200 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 466333200 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 346549057920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 149180699250 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 3052619831250 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 3549865642530 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 669.053779 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 5078135564501 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 177172320000 # Time in different power states +system.mem_ctrls.avgGap 16502455.25 # Average gap between requests +system.mem_ctrls.pageHitRate 81.05 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 231139440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 126117750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 696134400 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 465251040 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 346552109280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 149731396200 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3052164794250 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3549966942360 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 669.066980 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5077378950000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 177173880000 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 50492285499 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 51294057500 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 228569040 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 124715250 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 692000400 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 457034400 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 346549057920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 149006937600 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3052772253750 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3549830568360 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 669.047168 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5078398943499 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 177172320000 # Time in different power states +system.mem_ctrls_1.actEnergy 227911320 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 124356375 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 688428000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 461544480 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 346552109280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 149042883510 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3052768752750 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3549865985715 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 669.047952 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5078391595500 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 177173880000 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 50232498501 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 50287445500 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10611607773 # number of cpu cycles simulated +system.cpu0.numCycles 10611706091 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 58312369 # Number of instructions committed -system.cpu0.committedOps 112077158 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 105052932 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 985826 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9959513 # number of instructions that are conditional controls -system.cpu0.num_int_insts 105052932 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 198024346 # number of times the integer registers were read -system.cpu0.num_int_register_writes 89262745 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.committedInsts 59111887 # Number of instructions committed +system.cpu0.committedOps 113456709 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 106426265 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu0.num_func_calls 1016173 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 10055603 # number of instructions that are conditional controls +system.cpu0.num_int_insts 106426265 # number of integer instructions +system.cpu0.num_fp_insts 48 # number of float instructions +system.cpu0.num_int_register_reads 200823032 # number of times the integer registers were read +system.cpu0.num_int_register_writes 90335124 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 60301130 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 43624803 # number of times the CC registers were written -system.cpu0.num_mem_refs 12143482 # number of memory refs -system.cpu0.num_load_insts 7354533 # Number of load instructions -system.cpu0.num_store_insts 4788949 # Number of store instructions -system.cpu0.num_idle_cycles 10094720432.678099 # Number of idle cycles -system.cpu0.num_busy_cycles 516887340.321903 # Number of busy cycles -system.cpu0.not_idle_fraction 0.048710 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.951290 # Percentage of idle cycles -system.cpu0.Branches 11277737 # Number of branches fetched -system.cpu0.op_class::No_OpClass 133660 0.12% 0.12% # Class of executed instruction -system.cpu0.op_class::IntAlu 99659673 88.92% 89.04% # Class of executed instruction -system.cpu0.op_class::IntMult 84103 0.08% 89.11% # Class of executed instruction -system.cpu0.op_class::IntDiv 57076 0.05% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.17% # Class of executed instruction -system.cpu0.op_class::MemRead 7354533 6.56% 95.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 4788949 4.27% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 61044422 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44109295 # number of times the CC registers were written +system.cpu0.num_mem_refs 12452626 # number of memory refs +system.cpu0.num_load_insts 7522002 # Number of load instructions +system.cpu0.num_store_insts 4930624 # Number of store instructions +system.cpu0.num_idle_cycles 10088968020.334099 # Number of idle cycles +system.cpu0.num_busy_cycles 522738070.665901 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049261 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950739 # Percentage of idle cycles +system.cpu0.Branches 11433567 # Number of branches fetched +system.cpu0.op_class::No_OpClass 130284 0.11% 0.11% # Class of executed instruction +system.cpu0.op_class::IntAlu 100735872 88.79% 88.90% # Class of executed instruction +system.cpu0.op_class::IntMult 86129 0.08% 88.98% # Class of executed instruction +system.cpu0.op_class::IntDiv 56904 0.05% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatCvt 16 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.03% # Class of executed instruction +system.cpu0.op_class::MemRead 7517799 6.63% 95.65% # Class of executed instruction +system.cpu0.op_class::MemWrite 4930624 4.35% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 112077994 # Class of executed instruction +system.cpu0.op_class::total 113457628 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10608678164 # number of cpu cycles simulated +system.cpu1.numCycles 10608768454 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48529054 # Number of instructions committed -system.cpu1.committedOps 92757417 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 89083939 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 1759211 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8292881 # number of instructions that are conditional controls -system.cpu1.num_int_insts 89083939 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 172769101 # number of times the integer registers were read -system.cpu1.num_int_register_writes 73668949 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.committedInsts 48150016 # Number of instructions committed +system.cpu1.committedOps 92121595 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 88447961 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses +system.cpu1.num_func_calls 1752470 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 8220366 # number of instructions that are conditional controls +system.cpu1.num_int_insts 88447961 # number of integer instructions +system.cpu1.num_fp_insts 48 # number of float instructions +system.cpu1.num_int_register_reads 171418684 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73201141 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 51289512 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 33065409 # number of times the CC registers were written -system.cpu1.num_mem_refs 14308473 # number of memory refs -system.cpu1.num_load_insts 9217545 # Number of load instructions -system.cpu1.num_store_insts 5090928 # Number of store instructions -system.cpu1.num_idle_cycles 10270312186.995054 # Number of idle cycles -system.cpu1.num_busy_cycles 338365977.004946 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031895 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968105 # Percentage of idle cycles -system.cpu1.Branches 10658677 # Number of branches fetched -system.cpu1.op_class::No_OpClass 173276 0.19% 0.19% # Class of executed instruction -system.cpu1.op_class::IntAlu 78104057 84.20% 84.39% # Class of executed instruction -system.cpu1.op_class::IntMult 100669 0.11% 84.50% # Class of executed instruction -system.cpu1.op_class::IntDiv 71662 0.08% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.57% # Class of executed instruction -system.cpu1.op_class::MemRead 9217545 9.94% 94.51% # Class of executed instruction -system.cpu1.op_class::MemWrite 5090928 5.49% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 50927854 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 32747914 # number of times the CC registers were written +system.cpu1.num_mem_refs 14125904 # number of memory refs +system.cpu1.num_load_insts 9133896 # Number of load instructions +system.cpu1.num_store_insts 4992008 # Number of store instructions +system.cpu1.num_idle_cycles 10273983246.713898 # Number of idle cycles +system.cpu1.num_busy_cycles 334785207.286102 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031557 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968443 # Percentage of idle cycles +system.cpu1.Branches 10582274 # Number of branches fetched +system.cpu1.op_class::No_OpClass 169782 0.18% 0.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 77660292 84.30% 84.49% # Class of executed instruction +system.cpu1.op_class::IntMult 98483 0.11% 84.59% # Class of executed instruction +system.cpu1.op_class::IntDiv 71910 0.08% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatCvt 16 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.67% # Class of executed instruction +system.cpu1.op_class::MemRead 9129755 9.91% 94.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 4992008 5.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 92758137 # Class of executed instruction +system.cpu1.op_class::total 92122246 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 857916 # Transaction distribution -system.iobus.trans_dist::ReadResp 857916 # Transaction distribution -system.iobus.trans_dist::WriteReq 36558 # Transaction distribution -system.iobus.trans_dist::WriteResp 36558 # Transaction distribution -system.iobus.trans_dist::MessageReq 1920 # Transaction distribution -system.iobus.trans_dist::MessageResp 1920 # Transaction distribution -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1644 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3344 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 857753 # Transaction distribution +system.iobus.trans_dist::ReadResp 857753 # Transaction distribution +system.iobus.trans_dist::WriteReq 36065 # Transaction distribution +system.iobus.trans_dist::WriteResp 36065 # Transaction distribution +system.iobus.trans_dist::MessageReq 1791 # Transaction distribution +system.iobus.trans_dist::MessageResp 1791 # Transaction distribution +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5802 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5758 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 964 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 66 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 964 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14942 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 238 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14814 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 742772 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 158 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1702492 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5240 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5284 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 400 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 396 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 28 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 348 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12178 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12448 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5238 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 86270 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1792788 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6688 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 85378 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1791218 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3294 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3266 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 482 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 484 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 33 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1932 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1928 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7471 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486378 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 476 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7407 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1485538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 316 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1971862 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1970762 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3366 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3394 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 200 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 198 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 14 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15582 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15626 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6089 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15471 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15515 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 516 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10473 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 52670 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2031220 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9225 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 51075 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2028533 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 50000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10107000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10224000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 145000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 143500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1059500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 96000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 97500 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 55000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 56000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 28599000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 20660000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 700937500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1327000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1276000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 39157000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 31144500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks) +system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 23099500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 23664000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 469010624 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 468374820 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8240920 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 7594080 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 1330000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 1329500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2415044 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2404400 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 2023919000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 2023552000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 76513000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 60655000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). @@ -564,48 +567,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 10911216 # delay histogram for all message -system.ruby.delayHist::mean 0.442136 # delay histogram for all message -system.ruby.delayHist::stdev 1.829254 # delay histogram for all message -system.ruby.delayHist | 10308626 94.48% 94.48% | 1272 0.01% 94.49% | 600907 5.51% 100.00% | 150 0.00% 100.00% | 203 0.00% 100.00% | 20 0.00% 100.00% | 38 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 10911216 # delay histogram for all message +system.ruby.delayHist::samples 10895286 # delay histogram for all message +system.ruby.delayHist::mean 0.442462 # delay histogram for all message +system.ruby.delayHist::stdev 1.830078 # delay histogram for all message +system.ruby.delayHist | 10293202 94.47% 94.47% | 1309 0.01% 94.49% | 600320 5.51% 100.00% | 166 0.00% 100.00% | 230 0.00% 100.00% | 12 0.00% 100.00% | 47 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10895286 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 152209035 -system.ruby.outstanding_req_hist::mean 1.000112 -system.ruby.outstanding_req_hist::gmean 1.000078 -system.ruby.outstanding_req_hist::stdev 0.010600 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152191931 99.99% 99.99% | 17104 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 152209035 +system.ruby.outstanding_req_hist::samples 152835093 +system.ruby.outstanding_req_hist::mean 1.000166 +system.ruby.outstanding_req_hist::gmean 1.000115 +system.ruby.outstanding_req_hist::stdev 0.012900 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152809657 99.98% 99.98% | 25436 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152835093 system.ruby.latency_hist::bucket_size 256 system.ruby.latency_hist::max_bucket 2559 -system.ruby.latency_hist::samples 152209034 -system.ruby.latency_hist::mean 3.436503 -system.ruby.latency_hist::gmean 3.107893 -system.ruby.latency_hist::stdev 5.762527 -system.ruby.latency_hist | 152200028 99.99% 99.99% | 6260 0.00% 100.00% | 2677 0.00% 100.00% | 43 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 152209034 +system.ruby.latency_hist::samples 152835092 +system.ruby.latency_hist::mean 3.434217 +system.ruby.latency_hist::gmean 3.107238 +system.ruby.latency_hist::stdev 5.763379 +system.ruby.latency_hist | 152826007 99.99% 99.99% | 6324 0.00% 100.00% | 2683 0.00% 100.00% | 40 0.00% 100.00% | 37 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 152835092 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 149542283 +system.ruby.hit_latency_hist::samples 150173515 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149542283 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 149542283 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 150173515 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 150173515 system.ruby.miss_latency_hist::bucket_size 256 system.ruby.miss_latency_hist::max_bucket 2559 -system.ruby.miss_latency_hist::samples 2666751 -system.ruby.miss_latency_hist::mean 27.914090 -system.ruby.miss_latency_hist::gmean 22.539704 -system.ruby.miss_latency_hist::stdev 35.853723 -system.ruby.miss_latency_hist | 2657745 99.66% 99.66% | 6260 0.23% 99.90% | 2677 0.10% 100.00% | 43 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 2666751 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 10785659 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 531574 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11317233 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 67530179 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 328872 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 67859051 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 2661577 +system.ruby.miss_latency_hist::mean 27.933965 +system.ruby.miss_latency_hist::gmean 22.542647 +system.ruby.miss_latency_hist::stdev 36.007083 +system.ruby.miss_latency_hist | 2652492 99.66% 99.66% | 6324 0.24% 99.90% | 2683 0.10% 100.00% | 40 0.00% 100.00% | 37 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 2661577 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 11100819 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 532265 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11633084 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 68582952 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 323144 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 68906096 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -616,12 +619,12 @@ system.ruby.l1_cntrl0.prefetcher.partial_hits 0 system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l1_cntrl0.fully_busy_cycles 15 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 12972395 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1316773 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14289168 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 58254050 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 489532 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 58743582 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 12795048 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313851 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14108899 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 57694696 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 492317 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58187013 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -631,613 +634,602 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.fully_busy_cycles 10 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2439158 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 227593 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2666751 # Number of cache demand accesses +system.ruby.l1_cntrl1.fully_busy_cycles 7 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_hits 2434372 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 227205 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2661577 # Number of cache demand accesses system.ruby.l2_cntrl0.fully_busy_cycles 1 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 0.030084 -system.ruby.network.routers0.msg_count.Control::0 860446 -system.ruby.network.routers0.msg_count.Request_Control::2 42982 -system.ruby.network.routers0.msg_count.Response_Data::1 889304 -system.ruby.network.routers0.msg_count.Response_Control::1 509254 -system.ruby.network.routers0.msg_count.Response_Control::2 506406 -system.ruby.network.routers0.msg_count.Writeback_Data::0 297072 -system.ruby.network.routers0.msg_count.Writeback_Data::1 216 -system.ruby.network.routers0.msg_count.Writeback_Control::0 171015 -system.ruby.network.routers0.msg_bytes.Control::0 6883568 -system.ruby.network.routers0.msg_bytes.Request_Control::2 343856 -system.ruby.network.routers0.msg_bytes.Response_Data::1 64029888 -system.ruby.network.routers0.msg_bytes.Response_Control::1 4074032 -system.ruby.network.routers0.msg_bytes.Response_Control::2 4051248 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21389184 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-system.ruby.network.routers6.msg_count.Control::0 2844938 -system.ruby.network.routers6.msg_count.Request_Control::2 83201 -system.ruby.network.routers6.msg_count.Response_Data::1 2946593 -system.ruby.network.routers6.msg_count.Response_Control::1 1875593 -system.ruby.network.routers6.msg_count.Response_Control::2 1764444 -system.ruby.network.routers6.msg_count.Writeback_Data::0 575124 -system.ruby.network.routers6.msg_count.Writeback_Data::1 402 -system.ruby.network.routers6.msg_count.Writeback_Control::0 1160957 +system.ruby.network.routers6.percent_links_utilized 0.030950 +system.ruby.network.routers6.msg_count.Control::0 2839493 +system.ruby.network.routers6.msg_count.Request_Control::2 82703 +system.ruby.network.routers6.msg_count.Response_Data::1 2941298 +system.ruby.network.routers6.msg_count.Response_Control::1 1872805 +system.ruby.network.routers6.msg_count.Response_Control::2 1763102 +system.ruby.network.routers6.msg_count.Writeback_Data::0 574628 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system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12888144 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 925440 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12868200 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 919520 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle0.link_utilization 0.000255 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 815 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 809 system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58680 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58248 system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle1.link_utilization 0.000224 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47551 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380408 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47545 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers5.throttle0.link_utilization 0 system.ruby.network.routers5.throttle1.link_utilization 0 -system.ruby.network.routers6.throttle0.link_utilization 0.038501 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 42982 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 848348 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 493076 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 343856 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 61081056 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 3944608 -system.ruby.network.routers6.throttle1.link_utilization 0.082209 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 40219 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 1796151 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 1241782 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 321752 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129322872 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9934256 -system.ruby.network.routers6.throttle2.link_utilization 0.059751 -system.ruby.network.routers6.throttle2.msg_count.Control::0 2666751 -system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 203534 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 124997 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1764444 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 575124 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 402 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1113406 -system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21334008 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14654448 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 999976 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14115552 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41408928 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 28944 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8907248 -system.ruby.network.routers6.throttle3.link_utilization 0.005283 -system.ruby.network.routers6.throttle3.msg_count.Control::0 178187 -system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97745 -system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15738 -system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47551 -system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1425496 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7037640 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 125904 -system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380408 +system.ruby.network.routers6.throttle0.link_utilization 0.038287 +system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 42371 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 843260 +system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 494161 +system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 338968 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 60714720 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 3953288 +system.ruby.network.routers6.throttle1.link_utilization 0.082198 +system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 40332 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 1796167 +system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 1239377 +system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 322656 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 129324024 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 9915016 +system.ruby.network.routers6.throttle2.link_utilization 0.059676 +system.ruby.network.routers6.throttle2.msg_count.Control::0 2661577 +system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 203207 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 123979 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1763102 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 574628 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 370 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1112755 +system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21292616 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 14630904 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 991832 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14104816 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41373216 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 26640 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 8902040 +system.ruby.network.routers6.throttle3.link_utilization 0.005284 +system.ruby.network.routers6.throttle3.msg_count.Control::0 177916 +system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 97855 +system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 15288 +system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47545 +system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1423328 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7045560 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 122304 +system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380360 system.ruby.network.routers6.throttle4.link_utilization 0.000255 -system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 815 +system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 809 system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58680 +system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58248 system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6119725 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.753707 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.339234 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5543761 90.59% 90.59% | 388 0.01% 90.59% | 575170 9.40% 99.99% | 147 0.00% 100.00% | 201 0.00% 100.00% | 20 0.00% 100.00% | 38 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6119725 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6112062 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.754100 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.339998 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5536581 90.58% 90.58% | 390 0.01% 90.59% | 574653 9.40% 99.99% | 162 0.00% 100.00% | 217 0.00% 100.00% | 12 0.00% 100.00% | 47 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6112062 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4708290 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.044976 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.595659 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4681222 99.43% 99.43% | 442 0.01% 99.43% | 339 0.01% 99.44% | 545 0.01% 99.45% | 25596 0.54% 100.00% | 141 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4708290 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4700521 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.045023 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.596216 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4673467 99.42% 99.42% | 451 0.01% 99.43% | 352 0.01% 99.44% | 567 0.01% 99.45% | 25509 0.54% 100.00% | 158 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 10 0.00% 100.00% | 3 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4700521 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 83201 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000120 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.015504 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 83196 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 83201 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 82703 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000121 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.015550 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 82698 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 82703 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 128 system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 14928118 -system.ruby.LD.latency_hist::mean 4.887199 -system.ruby.LD.latency_hist::gmean 3.596426 -system.ruby.LD.latency_hist::stdev 9.328249 -system.ruby.LD.latency_hist | 14912021 99.89% 99.89% | 13966 0.09% 99.99% | 828 0.01% 99.99% | 820 0.01% 100.00% | 357 0.00% 100.00% | 111 0.00% 100.00% | 2 0.00% 100.00% | 8 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.latency_hist::total 14928118 +system.ruby.LD.latency_hist::samples 15017729 +system.ruby.LD.latency_hist::mean 4.875602 +system.ruby.LD.latency_hist::gmean 3.591894 +system.ruby.LD.latency_hist::stdev 9.357091 +system.ruby.LD.latency_hist | 15001612 99.89% 99.89% | 13925 0.09% 99.99% | 816 0.01% 99.99% | 883 0.01% 100.00% | 364 0.00% 100.00% | 107 0.00% 100.00% | 3 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.LD.latency_hist::total 15017729 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13535758 +system.ruby.LD.hit_latency_hist::samples 13626729 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13535758 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13535758 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13626729 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13626729 system.ruby.LD.miss_latency_hist::bucket_size 128 system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 1392360 -system.ruby.LD.miss_latency_hist::mean 23.233506 -system.ruby.LD.miss_latency_hist::gmean 20.962083 -system.ruby.LD.miss_latency_hist::stdev 23.700852 -system.ruby.LD.miss_latency_hist | 1376263 98.84% 98.84% | 13966 1.00% 99.85% | 828 0.06% 99.91% | 820 0.06% 99.97% | 357 0.03% 99.99% | 111 0.01% 100.00% | 2 0.00% 100.00% | 8 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1392360 +system.ruby.LD.miss_latency_hist::samples 1391000 +system.ruby.LD.miss_latency_hist::mean 23.249665 +system.ruby.LD.miss_latency_hist::gmean 20.961439 +system.ruby.LD.miss_latency_hist::stdev 23.941766 +system.ruby.LD.miss_latency_hist | 1374883 98.84% 98.84% | 13925 1.00% 99.84% | 816 0.06% 99.90% | 883 0.06% 99.96% | 364 0.03% 99.99% | 107 0.01% 100.00% | 3 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1391000 system.ruby.ST.latency_hist::bucket_size 256 system.ruby.ST.latency_hist::max_bucket 2559 -system.ruby.ST.latency_hist::samples 9504180 -system.ruby.ST.latency_hist::mean 5.187204 -system.ruby.ST.latency_hist::gmean 3.302390 -system.ruby.ST.latency_hist::stdev 17.665644 -system.ruby.ST.latency_hist | 9498362 99.94% 99.94% | 3775 0.04% 99.98% | 1993 0.02% 100.00% | 29 0.00% 100.00% | 20 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 9504180 +system.ruby.ST.latency_hist::samples 9551573 +system.ruby.ST.latency_hist::mean 5.175450 +system.ruby.ST.latency_hist::gmean 3.300314 +system.ruby.ST.latency_hist::stdev 17.651144 +system.ruby.ST.latency_hist | 9545752 99.94% 99.94% | 3768 0.04% 99.98% | 2002 0.02% 100.00% | 25 0.00% 100.00% | 25 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 9551573 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9152723 +system.ruby.ST.hit_latency_hist::samples 9200826 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9152723 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9152723 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9200826 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9200826 system.ruby.ST.miss_latency_hist::bucket_size 256 system.ruby.ST.miss_latency_hist::max_bucket 2559 -system.ruby.ST.miss_latency_hist::samples 351457 -system.ruby.ST.miss_latency_hist::mean 62.146880 -system.ruby.ST.miss_latency_hist::gmean 40.269218 -system.ruby.ST.miss_latency_hist::stdev 71.205537 -system.ruby.ST.miss_latency_hist | 345639 98.34% 98.34% | 3775 1.07% 99.42% | 1993 0.57% 99.99% | 29 0.01% 99.99% | 20 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 351457 +system.ruby.ST.miss_latency_hist::samples 350747 +system.ruby.ST.miss_latency_hist::mean 62.242032 +system.ruby.ST.miss_latency_hist::gmean 40.314149 +system.ruby.ST.miss_latency_hist::stdev 71.440751 +system.ruby.ST.miss_latency_hist | 344926 98.34% 98.34% | 3768 1.07% 99.41% | 2002 0.57% 99.99% | 25 0.01% 99.99% | 25 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 350747 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 126602633 -system.ruby.IFETCH.latency_hist::mean 3.119985 -system.ruby.IFETCH.latency_hist::gmean 3.036795 -system.ruby.IFETCH.latency_hist::stdev 2.244898 -system.ruby.IFETCH.latency_hist | 126595894 99.99% 99.99% | 5742 0.00% 100.00% | 458 0.00% 100.00% | 336 0.00% 100.00% | 141 0.00% 100.00% | 58 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 126602633 +system.ruby.IFETCH.latency_hist::samples 127093109 +system.ruby.IFETCH.latency_hist::mean 3.119052 +system.ruby.IFETCH.latency_hist::gmean 3.036517 +system.ruby.IFETCH.latency_hist::stdev 2.234317 +system.ruby.IFETCH.latency_hist | 127086454 99.99% 99.99% | 5646 0.00% 100.00% | 489 0.00% 100.00% | 322 0.00% 100.00% | 142 0.00% 100.00% | 52 0.00% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 127093109 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 125784229 +system.ruby.IFETCH.hit_latency_hist::samples 126277648 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125784229 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 125784229 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126277648 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 126277648 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 818404 -system.ruby.IFETCH.miss_latency_hist::mean 21.561079 -system.ruby.IFETCH.miss_latency_hist::gmean 19.774643 -system.ruby.IFETCH.miss_latency_hist::stdev 20.911893 -system.ruby.IFETCH.miss_latency_hist | 811665 99.18% 99.18% | 5742 0.70% 99.88% | 458 0.06% 99.93% | 336 0.04% 99.98% | 141 0.02% 99.99% | 58 0.01% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 818404 +system.ruby.IFETCH.miss_latency_hist::samples 815461 +system.ruby.IFETCH.miss_latency_hist::mean 21.554760 +system.ruby.IFETCH.miss_latency_hist::gmean 19.772157 +system.ruby.IFETCH.miss_latency_hist::stdev 20.880175 +system.ruby.IFETCH.miss_latency_hist | 808806 99.18% 99.18% | 5646 0.69% 99.88% | 489 0.06% 99.94% | 322 0.04% 99.98% | 142 0.02% 99.99% | 52 0.01% 100.00% | 0 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 815461 system.ruby.RMW_Read.latency_hist::bucket_size 128 system.ruby.RMW_Read.latency_hist::max_bucket 1279 -system.ruby.RMW_Read.latency_hist::samples 494795 -system.ruby.RMW_Read.latency_hist::mean 6.019475 -system.ruby.RMW_Read.latency_hist::gmean 3.954538 -system.ruby.RMW_Read.latency_hist::stdev 10.125129 -system.ruby.RMW_Read.latency_hist | 494623 99.97% 99.97% | 131 0.03% 99.99% | 11 0.00% 99.99% | 18 0.00% 100.00% | 7 0.00% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 494795 +system.ruby.RMW_Read.latency_hist::samples 493321 +system.ruby.RMW_Read.latency_hist::mean 6.020581 +system.ruby.RMW_Read.latency_hist::gmean 3.953173 +system.ruby.RMW_Read.latency_hist::stdev 10.251314 +system.ruby.RMW_Read.latency_hist | 493148 99.96% 99.96% | 127 0.03% 99.99% | 17 0.00% 99.99% | 15 0.00% 100.00% | 9 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 493321 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 429248 +system.ruby.RMW_Read.hit_latency_hist::samples 428061 system.ruby.RMW_Read.hit_latency_hist::mean 3 system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 429248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 429248 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428061 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 428061 system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.RMW_Read.miss_latency_hist::samples 65547 -system.ruby.RMW_Read.miss_latency_hist::mean 25.793126 -system.ruby.RMW_Read.miss_latency_hist::gmean 24.141988 -system.ruby.RMW_Read.miss_latency_hist::stdev 17.977211 -system.ruby.RMW_Read.miss_latency_hist | 65375 99.74% 99.74% | 131 0.20% 99.94% | 11 0.02% 99.95% | 18 0.03% 99.98% | 7 0.01% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 65547 -system.ruby.Locked_RMW_Read.latency_hist::bucket_size 64 -system.ruby.Locked_RMW_Read.latency_hist::max_bucket 639 -system.ruby.Locked_RMW_Read.latency_hist::samples 339654 -system.ruby.Locked_RMW_Read.latency_hist::mean 5.341447 -system.ruby.Locked_RMW_Read.latency_hist::gmean 3.777860 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.189753 -system.ruby.Locked_RMW_Read.latency_hist | 339308 99.90% 99.90% | 89 0.03% 99.92% | 236 0.07% 99.99% | 2 0.00% 99.99% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 339654 +system.ruby.RMW_Read.miss_latency_hist::samples 65260 +system.ruby.RMW_Read.miss_latency_hist::mean 25.833527 +system.ruby.RMW_Read.miss_latency_hist::gmean 24.149766 +system.ruby.RMW_Read.miss_latency_hist::stdev 18.493474 +system.ruby.RMW_Read.miss_latency_hist | 65087 99.73% 99.73% | 127 0.19% 99.93% | 17 0.03% 99.96% | 15 0.02% 99.98% | 9 0.01% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 65260 +system.ruby.Locked_RMW_Read.latency_hist::bucket_size 128 +system.ruby.Locked_RMW_Read.latency_hist::max_bucket 1279 +system.ruby.Locked_RMW_Read.latency_hist::samples 339680 +system.ruby.Locked_RMW_Read.latency_hist::mean 5.345204 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.780937 +system.ruby.Locked_RMW_Read.latency_hist::stdev 8.076413 +system.ruby.Locked_RMW_Read.latency_hist | 339429 99.93% 99.93% | 234 0.07% 99.99% | 11 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 339680 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300671 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 300571 system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300671 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 300671 -system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 64 -system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 639 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38983 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.400739 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.361163 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.695962 -system.ruby.Locked_RMW_Read.miss_latency_hist | 38637 99.11% 99.11% | 89 0.23% 99.34% | 236 0.61% 99.95% | 2 0.01% 99.95% | 6 0.02% 99.97% | 3 0.01% 99.97% | 2 0.01% 99.98% | 3 0.01% 99.99% | 2 0.01% 99.99% | 3 0.01% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 38983 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 300571 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 300571 +system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 128 +system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 1279 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 39109 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 23.369199 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.378025 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.121215 +system.ruby.Locked_RMW_Read.miss_latency_hist | 38858 99.36% 99.36% | 234 0.60% 99.96% | 11 0.03% 99.98% | 3 0.01% 99.99% | 1 0.00% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 39109 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 339654 +system.ruby.Locked_RMW_Write.latency_hist::samples 339680 system.ruby.Locked_RMW_Write.latency_hist::mean 3 system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 339654 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339680 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 339680 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339654 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339680 system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 339654 -system.ruby.Directory_Controller.Fetch 178187 0.00% 0.00% -system.ruby.Directory_Controller.Data 97745 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 178657 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 142629 0.00% 0.00% -system.ruby.Directory_Controller.DMA_READ 815 0.00% 0.00% +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339680 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 339680 +system.ruby.Directory_Controller.Fetch 177916 0.00% 0.00% +system.ruby.Directory_Controller.Data 97855 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 178363 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 143156 0.00% 0.00% +system.ruby.Directory_Controller.DMA_READ 809 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 15738 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 178187 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 470 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 44884 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 470 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 44884 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 95548 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_READ 345 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 1852 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 15738 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 178187 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 95548 0.00% 0.00% -system.ruby.Directory_Controller.M_DRD.Data 345 0.00% 0.00% -system.ruby.Directory_Controller.M_DRDI.Memory_Ack 345 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 1852 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1852 0.00% 0.00% -system.ruby.DMA_Controller.ReadRequest | 815 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.ReadRequest::total 815 +system.ruby.Directory_Controller.CleanReplacement 15288 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 177916 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 447 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 45301 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 447 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 45301 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 96058 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 362 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 1435 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 15288 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 177916 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 96058 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 362 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 362 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 1435 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1435 0.00% 0.00% +system.ruby.DMA_Controller.ReadRequest | 809 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.ReadRequest::total 809 system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.WriteRequest::total 46736 -system.ruby.DMA_Controller.Data | 815 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.Data::total 815 +system.ruby.DMA_Controller.Data | 809 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.Data::total 809 system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.Ack::total 46736 -system.ruby.DMA_Controller.READY.ReadRequest | 815 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.READY.ReadRequest::total 815 +system.ruby.DMA_Controller.READY.ReadRequest | 809 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.READY.ReadRequest::total 809 system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.READY.WriteRequest::total 46736 -system.ruby.DMA_Controller.BUSY_RD.Data | 815 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.BUSY_RD.Data::total 815 +system.ruby.DMA_Controller.BUSY_RD.Data | 809 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.BUSY_RD.Data::total 809 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 6103954 40.89% 40.89% | 8824164 59.11% 100.00% -system.ruby.L1Cache_Controller.Load::total 14928118 -system.ruby.L1Cache_Controller.Ifetch | 67859054 53.60% 53.60% | 58743585 46.40% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 126602639 -system.ruby.L1Cache_Controller.Store | 5213279 48.82% 48.82% | 5465004 51.18% 100.00% -system.ruby.L1Cache_Controller.Store::total 10678283 -system.ruby.L1Cache_Controller.Inv | 16394 48.51% 48.51% | 17401 51.49% 100.00% -system.ruby.L1Cache_Controller.Inv::total 33795 -system.ruby.L1Cache_Controller.L1_Replacement | 832783 31.89% 31.89% | 1778531 68.11% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2611314 -system.ruby.L1Cache_Controller.Fwd_GETX | 12220 50.79% 50.79% | 11839 49.21% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 24059 -system.ruby.L1Cache_Controller.Fwd_GETS | 14364 56.68% 56.68% | 10979 43.32% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 25343 +system.ruby.L1Cache_Controller.Load | 6268725 41.74% 41.74% | 8749004 58.26% 100.00% +system.ruby.L1Cache_Controller.Load::total 15017729 +system.ruby.L1Cache_Controller.Ifetch | 68906101 54.22% 54.22% | 58187014 45.78% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 127093115 +system.ruby.L1Cache_Controller.Store | 5364359 50.02% 50.02% | 5359895 49.98% 100.00% +system.ruby.L1Cache_Controller.Store::total 10724254 +system.ruby.L1Cache_Controller.Inv | 15938 47.70% 47.70% | 17476 52.30% 100.00% +system.ruby.L1Cache_Controller.Inv::total 33414 +system.ruby.L1Cache_Controller.L1_Replacement | 827888 31.76% 31.76% | 1778547 68.24% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2606435 +system.ruby.L1Cache_Controller.Fwd_GETX | 12260 51.09% 51.09% | 11738 48.91% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 23998 +system.ruby.L1Cache_Controller.Fwd_GETS | 14169 56.03% 56.03% | 11118 43.97% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 25287 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 793 43.48% 43.48% | 1031 56.52% 100.00% -system.ruby.L1Cache_Controller.Data::total 1824 -system.ruby.L1Cache_Controller.Data_Exclusive | 253693 19.77% 19.77% | 1029417 80.23% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1283110 -system.ruby.L1Cache_Controller.DataS_fromL1 | 10979 43.31% 43.31% | 14368 56.69% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 25347 -system.ruby.L1Cache_Controller.Data_all_Acks | 582883 43.69% 43.69% | 751335 56.31% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1334218 -system.ruby.L1Cache_Controller.Ack | 12098 54.37% 54.37% | 10154 45.63% 100.00% -system.ruby.L1Cache_Controller.Ack::total 22252 -system.ruby.L1Cache_Controller.Ack_all | 12891 53.54% 53.54% | 11185 46.46% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 24076 -system.ruby.L1Cache_Controller.WB_Ack | 468087 27.72% 27.72% | 1220443 72.28% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1688530 -system.ruby.L1Cache_Controller.NP.Load | 281209 20.47% 20.47% | 1092251 79.53% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1373460 -system.ruby.L1Cache_Controller.NP.Ifetch | 328766 40.20% 40.20% | 488985 59.80% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 817751 -system.ruby.L1Cache_Controller.NP.Store | 223831 53.02% 53.02% | 198319 46.98% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 422150 -system.ruby.L1Cache_Controller.NP.Inv | 5086 54.54% 54.54% | 4239 45.46% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 9325 -system.ruby.L1Cache_Controller.I.Load | 8631 45.67% 45.67% | 10269 54.33% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 18900 -system.ruby.L1Cache_Controller.I.Ifetch | 106 16.23% 16.23% | 547 83.77% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 653 -system.ruby.L1Cache_Controller.I.Store | 5805 50.11% 50.11% | 5779 49.89% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 11584 -system.ruby.L1Cache_Controller.I.L1_Replacement | 8985 51.90% 51.90% | 8328 48.10% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 17313 -system.ruby.L1Cache_Controller.S.Load | 530372 50.22% 50.22% | 525759 49.78% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1056131 -system.ruby.L1Cache_Controller.S.Ifetch | 67530179 53.69% 53.69% | 58254050 46.31% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 125784229 -system.ruby.L1Cache_Controller.S.Store | 12098 54.37% 54.37% | 10155 45.63% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 22253 -system.ruby.L1Cache_Controller.S.Inv | 11044 46.05% 46.05% | 12940 53.95% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 23984 -system.ruby.L1Cache_Controller.S.L1_Replacement | 355711 39.28% 39.28% | 549760 60.72% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 905471 -system.ruby.L1Cache_Controller.E.Load | 1138534 29.37% 29.37% | 2737774 70.63% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3876308 -system.ruby.L1Cache_Controller.E.Store | 81127 48.65% 48.65% | 85645 51.35% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 166772 -system.ruby.L1Cache_Controller.E.Inv | 48 57.83% 57.83% | 35 42.17% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 83 -system.ruby.L1Cache_Controller.E.L1_Replacement | 171015 15.36% 15.36% | 942391 84.64% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1113406 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 278 59.40% 59.40% | 190 40.60% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 468 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 1045 48.60% 48.60% | 1105 51.40% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2150 -system.ruby.L1Cache_Controller.M.Load | 4145208 48.18% 48.18% | 4458111 51.82% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8603319 -system.ruby.L1Cache_Controller.M.Store | 4890418 48.63% 48.63% | 5165106 51.37% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10055524 -system.ruby.L1Cache_Controller.M.Inv | 216 53.73% 53.73% | 186 46.27% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 402 -system.ruby.L1Cache_Controller.M.L1_Replacement | 297072 51.65% 51.65% | 278052 48.35% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 575124 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 11941 50.62% 50.62% | 11649 49.38% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23590 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 13319 57.43% 57.43% | 9874 42.57% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23193 +system.ruby.L1Cache_Controller.Data | 828 44.64% 44.64% | 1027 55.36% 100.00% +system.ruby.L1Cache_Controller.Data::total 1855 +system.ruby.L1Cache_Controller.Data_Exclusive | 252860 19.71% 19.71% | 1029835 80.29% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1282695 +system.ruby.L1Cache_Controller.DataS_fromL1 | 11118 43.96% 43.96% | 14173 56.04% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 25291 +system.ruby.L1Cache_Controller.Data_all_Acks | 578454 43.51% 43.51% | 751132 56.49% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1329586 +system.ruby.L1Cache_Controller.Ack | 12149 54.85% 54.85% | 10001 45.15% 100.00% +system.ruby.L1Cache_Controller.Ack::total 22150 +system.ruby.L1Cache_Controller.Ack_all | 12977 54.06% 54.06% | 11028 45.94% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 24005 +system.ruby.L1Cache_Controller.WB_Ack | 469035 27.80% 27.80% | 1218348 72.20% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1687383 +system.ruby.L1Cache_Controller.NP.Load | 280457 20.44% 20.44% | 1091772 79.56% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1372229 +system.ruby.L1Cache_Controller.NP.Ifetch | 323032 39.65% 39.65% | 491723 60.35% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 814755 +system.ruby.L1Cache_Controller.NP.Store | 225423 53.48% 53.48% | 196076 46.52% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 421499 +system.ruby.L1Cache_Controller.NP.Inv | 4849 53.95% 53.95% | 4139 46.05% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 8988 +system.ruby.L1Cache_Controller.I.Load | 8492 45.24% 45.24% | 10279 54.76% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 18771 +system.ruby.L1Cache_Controller.I.Ifetch | 112 15.86% 15.86% | 594 84.14% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 706 +system.ruby.L1Cache_Controller.I.Store | 5744 50.09% 50.09% | 5723 49.91% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11467 +system.ruby.L1Cache_Controller.I.L1_Replacement | 9001 51.76% 51.76% | 8389 48.24% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 17390 +system.ruby.L1Cache_Controller.S.Load | 552961 51.86% 51.86% | 513218 48.14% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1066179 +system.ruby.L1Cache_Controller.S.Ifetch | 68582952 54.31% 54.31% | 57694696 45.69% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 126277648 +system.ruby.L1Cache_Controller.S.Store | 12149 54.85% 54.85% | 10001 45.15% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 22150 +system.ruby.L1Cache_Controller.S.Inv | 10866 45.32% 45.32% | 13108 54.68% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 23974 +system.ruby.L1Cache_Controller.S.L1_Replacement | 349852 38.80% 38.80% | 551810 61.20% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 901662 +system.ruby.L1Cache_Controller.E.Load | 1151502 29.73% 29.73% | 2721068 70.27% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3872570 +system.ruby.L1Cache_Controller.E.Store | 80746 48.37% 48.37% | 86187 51.63% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166933 +system.ruby.L1Cache_Controller.E.Inv | 47 57.32% 57.32% | 35 42.68% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 82 +system.ruby.L1Cache_Controller.E.L1_Replacement | 170526 15.32% 15.32% | 942229 84.68% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1112755 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 332 72.81% 72.81% | 124 27.19% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 456 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 992 45.23% 45.23% | 1201 54.77% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2193 +system.ruby.L1Cache_Controller.M.Load | 4275313 49.21% 49.21% | 4412667 50.79% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8687980 +system.ruby.L1Cache_Controller.M.Store | 5040297 49.89% 49.89% | 5061908 50.11% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10102205 +system.ruby.L1Cache_Controller.M.Inv | 176 47.57% 47.57% | 194 52.43% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 370 +system.ruby.L1Cache_Controller.M.L1_Replacement | 298509 51.95% 51.95% | 276119 48.05% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 574628 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 11928 50.67% 50.67% | 11614 49.33% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23542 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 13177 57.06% 57.06% | 9917 42.94% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23094 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 253693 19.77% 19.77% | 1029417 80.23% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1283110 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 10979 43.31% 43.31% | 14368 56.69% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25347 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 354040 39.24% 39.24% | 548267 60.76% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 902307 -system.ruby.L1Cache_Controller.IM.Data | 793 43.48% 43.48% | 1031 56.52% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 1824 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 228843 52.98% 52.98% | 203068 47.02% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431911 -system.ruby.L1Cache_Controller.SM.Inv | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.L1Cache_Controller.SM.Inv::total 1 -system.ruby.L1Cache_Controller.SM.Ack | 12098 54.37% 54.37% | 10154 45.63% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 22252 -system.ruby.L1Cache_Controller.SM.Ack_all | 12891 53.54% 53.54% | 11185 46.46% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 24076 -system.ruby.L1Cache_Controller.M_I.Ifetch | 3 50.00% 50.00% | 3 50.00% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252860 19.71% 19.71% | 1029835 80.29% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1282695 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11118 43.96% 43.96% | 14173 56.04% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25291 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348115 38.75% 38.75% | 550360 61.25% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 898475 +system.ruby.L1Cache_Controller.IM.Data | 828 44.64% 44.64% | 1027 55.36% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1855 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230339 53.43% 53.43% | 200772 46.57% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431111 +system.ruby.L1Cache_Controller.SM.Ack | 12149 54.85% 54.85% | 10001 45.15% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 22150 +system.ruby.L1Cache_Controller.SM.Ack_all | 12977 54.06% 54.06% | 11028 45.94% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 24005 +system.ruby.L1Cache_Controller.M_I.Ifetch | 5 83.33% 83.33% | 1 16.67% 100.00% system.ruby.L1Cache_Controller.M_I.Ifetch::total 6 -system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 468086 27.72% 27.72% | 1220443 72.28% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1688529 -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 1 -system.ruby.L2Cache_Controller.L1_GET_INSTR 818404 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1392538 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 433736 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 22253 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1688530 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 95493 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 15793 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 178187 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 113483 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 23599 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2150 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 1627 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 7690 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 25347 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1739097 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 4394 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16549 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 34274 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 127364 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 801825 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 83907 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 1933 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22252 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 275 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7330 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.MEM_Inv 2 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack | 469035 27.80% 27.80% | 1218348 72.20% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1687383 +system.ruby.L2Cache_Controller.L1_GET_INSTR 815461 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1391156 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 432966 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 22150 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1687383 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 95998 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 15348 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 177916 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 113143 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 23468 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2193 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1505 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 7534 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 25291 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1737811 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 3594 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16427 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 34220 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 127269 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799004 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 83018 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1958 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22150 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 257 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7192 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1248836 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 280379 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 95073 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8368 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 1950 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1248475 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 279741 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 95619 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8056 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 1564 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 25343 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 24059 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1688529 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 145 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 95 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.MEM_Inv 245 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 113483 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 1950 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 347 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 43 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.MEM_Inv 245 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 55 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 25287 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 23998 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1687383 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 122 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 100 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.MEM_Inv 230 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 113143 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 1564 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 310 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 42 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.MEM_Inv 230 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 60 0.00% 0.00% system.ruby.L2Cache_Controller.MCT_I.Ack_all 40 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 1351 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 7330 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 276 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 277 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.MEM_Inv 2 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 34274 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 16549 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 127364 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 131 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24185 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 47 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1714912 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23196 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2149 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 25345 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1245 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 7192 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 260 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 260 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 34220 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 16427 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 127269 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 115 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24108 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 41 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1713703 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23085 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2191 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 15 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 13 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 25276 0.00% 0.00% ---------- End Simulation Statistics ---------- |