diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | 3121 |
1 files changed, 1554 insertions, 1567 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index f26bf1c54..cf390c4d1 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,159 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137881 # Number of seconds simulated -sim_ticks 5137881357500 # Number of ticks simulated -final_tick 5137881357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133872 # Number of seconds simulated +sim_ticks 5133872107500 # Number of ticks simulated +final_tick 5133872107500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 401147 # Simulator instruction rate (inst/s) -host_op_rate 797370 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8430324111 # Simulator tick rate (ticks/s) -host_mem_usage 944704 # Number of bytes of host memory used -host_seconds 609.45 # Real time elapsed on the host -sim_insts 244480058 # Number of instructions simulated -sim_ops 485958826 # Number of ops (including micro ops) simulated +host_inst_rate 287663 # Simulator instruction rate (inst/s) +host_op_rate 571806 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6046720341 # Simulator tick rate (ticks/s) +host_mem_usage 1024224 # Number of bytes of host memory used +host_seconds 849.03 # Real time elapsed on the host +sim_insts 244235751 # Number of instructions simulated +sim_ops 485482573 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 396800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5697984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 149888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1826880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 430976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2905472 # Number of bytes read from this memory -system.physmem.bytes_read::total 11438656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 396800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 149888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 430976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6187584 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 396736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5572928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 164928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1639680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 412864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3220800 # Number of bytes read from this memory +system.physmem.bytes_read::total 11438848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 396736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 164928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 412864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 974528 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6205312 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9177664 # Number of bytes written to this memory +system.physmem.bytes_written::total 9195392 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6200 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 89031 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 28545 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 45398 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178729 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96681 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6199 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 87077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2577 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 25620 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 50325 # Number of read requests responded to by this memory +system.physmem.num_reads::total 178732 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96958 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143401 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 77230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1109014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 355571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 83882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 565500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2226337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 77230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29173 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 83882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 190285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1204307 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 581968 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1786274 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1204307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 587486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 77230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1109014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 355571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 83882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 565500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4012611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 83494 # Number of read requests accepted -system.physmem.writeReqs 76163 # Number of write requests accepted -system.physmem.readBursts 83494 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 76163 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5331584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue -system.physmem.bytesWritten 4872768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5343616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4874432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 143678 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 77278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1085521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 319385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 80420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 627363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2228113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 77278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 80420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 189823 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1208700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 582422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1791122 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1208700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 587945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 77278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1085521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 32125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 319385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 80420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 627363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4019235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 85451 # Number of read requests accepted +system.physmem.writeReqs 85019 # Number of write requests accepted +system.physmem.readBursts 85451 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 85019 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5457024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11840 # Total number of bytes read from write queue +system.physmem.bytesWritten 5440128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5468864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5441216 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 873 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4736 # Per bank write bursts -system.physmem.perBankRdBursts::1 4757 # Per bank write bursts -system.physmem.perBankRdBursts::2 5051 # Per bank write bursts -system.physmem.perBankRdBursts::3 5281 # Per bank write bursts -system.physmem.perBankRdBursts::4 5400 # Per bank write bursts -system.physmem.perBankRdBursts::5 4765 # Per bank write bursts -system.physmem.perBankRdBursts::6 4961 # Per bank write bursts -system.physmem.perBankRdBursts::7 5223 # Per bank write bursts -system.physmem.perBankRdBursts::8 5069 # Per bank write bursts -system.physmem.perBankRdBursts::9 5177 # Per bank write bursts -system.physmem.perBankRdBursts::10 4953 # Per bank write bursts -system.physmem.perBankRdBursts::11 4660 # Per bank write bursts -system.physmem.perBankRdBursts::12 5195 # Per bank write bursts -system.physmem.perBankRdBursts::13 6216 # Per bank write bursts -system.physmem.perBankRdBursts::14 6082 # Per bank write bursts -system.physmem.perBankRdBursts::15 5780 # Per bank write bursts -system.physmem.perBankWrBursts::0 4915 # Per bank write bursts -system.physmem.perBankWrBursts::1 4846 # Per bank write bursts -system.physmem.perBankWrBursts::2 4413 # Per bank write bursts -system.physmem.perBankWrBursts::3 4685 # Per bank write bursts -system.physmem.perBankWrBursts::4 5227 # Per bank write bursts -system.physmem.perBankWrBursts::5 4409 # Per bank write bursts -system.physmem.perBankWrBursts::6 4642 # Per bank write bursts -system.physmem.perBankWrBursts::7 4533 # Per bank write bursts -system.physmem.perBankWrBursts::8 4328 # Per bank write bursts -system.physmem.perBankWrBursts::9 4737 # Per bank write bursts -system.physmem.perBankWrBursts::10 4592 # Per bank write bursts -system.physmem.perBankWrBursts::11 4470 # Per bank write bursts -system.physmem.perBankWrBursts::12 4760 # Per bank write bursts -system.physmem.perBankWrBursts::13 5234 # Per bank write bursts -system.physmem.perBankWrBursts::14 5550 # Per bank write bursts -system.physmem.perBankWrBursts::15 4796 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 868 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5096 # Per bank write bursts +system.physmem.perBankRdBursts::1 5035 # Per bank write bursts +system.physmem.perBankRdBursts::2 5503 # Per bank write bursts +system.physmem.perBankRdBursts::3 5713 # Per bank write bursts +system.physmem.perBankRdBursts::4 5011 # Per bank write bursts +system.physmem.perBankRdBursts::5 4756 # Per bank write bursts +system.physmem.perBankRdBursts::6 4921 # Per bank write bursts +system.physmem.perBankRdBursts::7 5413 # Per bank write bursts +system.physmem.perBankRdBursts::8 5128 # Per bank write bursts +system.physmem.perBankRdBursts::9 4999 # Per bank write bursts +system.physmem.perBankRdBursts::10 4701 # Per bank write bursts +system.physmem.perBankRdBursts::11 5348 # Per bank write bursts +system.physmem.perBankRdBursts::12 5396 # Per bank write bursts +system.physmem.perBankRdBursts::13 6167 # Per bank write bursts +system.physmem.perBankRdBursts::14 6376 # Per bank write bursts +system.physmem.perBankRdBursts::15 5703 # Per bank write bursts +system.physmem.perBankWrBursts::0 5743 # Per bank write bursts +system.physmem.perBankWrBursts::1 5870 # Per bank write bursts +system.physmem.perBankWrBursts::2 5006 # Per bank write bursts +system.physmem.perBankWrBursts::3 5323 # Per bank write bursts +system.physmem.perBankWrBursts::4 4689 # Per bank write bursts +system.physmem.perBankWrBursts::5 4481 # Per bank write bursts +system.physmem.perBankWrBursts::6 5327 # Per bank write bursts +system.physmem.perBankWrBursts::7 5300 # Per bank write bursts +system.physmem.perBankWrBursts::8 5281 # Per bank write bursts +system.physmem.perBankWrBursts::9 5131 # Per bank write bursts +system.physmem.perBankWrBursts::10 5421 # Per bank write bursts +system.physmem.perBankWrBursts::11 5658 # Per bank write bursts +system.physmem.perBankWrBursts::12 5171 # Per bank write bursts +system.physmem.perBankWrBursts::13 5597 # Per bank write bursts +system.physmem.perBankWrBursts::14 5966 # Per bank write bursts +system.physmem.perBankWrBursts::15 5038 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5136881165000 # Total gap between requests +system.physmem.totGap 5132871981000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 83494 # Read request sizes (log2) +system.physmem.readPktSize::6 85451 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 76163 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 78715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see +system.physmem.writePktSize::6 85019 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 78990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -168,475 +164,469 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4484 # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15907 41.31% 41.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9655 25.07% 66.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3981 10.34% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2127 5.52% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1469 3.81% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1046 2.72% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 664 1.72% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 555 1.44% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3103 8.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38507 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3853 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.615365 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 121.265146 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 3842 99.71% 99.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 8 0.21% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 1 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-6911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3853 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3853 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.760446 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.599143 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.462049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 66 1.71% 1.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 8 0.21% 1.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 10 0.26% 2.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3269 84.84% 87.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 44 1.14% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 26 0.67% 88.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 135 3.50% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 114 2.96% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.08% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.36% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.21% 95.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.34% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.05% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.05% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.03% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 96 2.49% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.03% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.13% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.34% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.10% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.05% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.13% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 39962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 272.686252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.690614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.316153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16345 40.90% 40.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9834 24.61% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4112 10.29% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2230 5.58% 81.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1552 3.88% 85.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1069 2.68% 87.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 711 1.78% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 597 1.49% 91.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3512 8.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4105 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.770767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 117.592245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 4095 99.76% 99.76% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 7 0.17% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4105 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.706943 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.214534 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.616872 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 63 1.53% 1.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.17% 1.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.02% 1.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 4 0.10% 1.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3359 81.83% 83.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 49 1.19% 84.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.63% 85.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 173 4.21% 89.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 182 4.43% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 7 0.17% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 12 0.29% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.19% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.24% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.05% 95.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 157 3.82% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.24% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.17% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.05% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.05% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.12% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.19% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3853 # Writes before turning the bus around for reads -system.physmem.totQLat 942120750 # Total ticks spent queuing -system.physmem.totMemAccLat 2504108250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 416530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11309.16 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 4105 # Writes before turning the bus around for reads +system.physmem.totQLat 1041221500 # Total ticks spent queuing +system.physmem.totMemAccLat 2639959000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 426330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12211.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30059.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.04 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.04 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.95 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30961.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.06 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.45 # Average write queue length when enqueuing -system.physmem.readRowHits 65566 # Number of row buffer hits during reads -system.physmem.writeRowHits 55368 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.70 # Row buffer hit rate for writes -system.physmem.avgGap 32174481.33 # Average gap between requests -system.physmem.pageHitRate 75.84 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4942580735250 # Time in different power states -system.physmem.memoryStateTime::REF 171564900000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 6.94 # Average write queue length when enqueuing +system.physmem.readRowHits 67077 # Number of row buffer hits during reads +system.physmem.writeRowHits 63228 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.37 # Row buffer hit rate for writes +system.physmem.avgGap 30110118.97 # Average gap between requests +system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4938526642750 # Time in different power states +system.physmem.memoryStateTime::REF 171431260000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23734191750 # Time in different power states +system.physmem.memoryStateTime::ACT 23914099250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 5877722 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 425622 # Transaction distribution -system.membus.trans_dist::ReadResp 425619 # Transaction distribution -system.membus.trans_dist::WriteReq 7303 # Transaction distribution -system.membus.trans_dist::WriteResp 7303 # Transaction distribution -system.membus.trans_dist::Writeback 54691 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 21472 # Transaction distribution -system.membus.trans_dist::UpgradeReq 873 # Transaction distribution -system.membus.trans_dist::UpgradeResp 873 # Transaction distribution -system.membus.trans_dist::ReadExReq 56661 # Transaction distribution -system.membus.trans_dist::ReadExResp 56661 # Transaction distribution -system.membus.trans_dist::MessageReq 1005 # Transaction distribution -system.membus.trans_dist::MessageResp 1005 # Transaction distribution -system.membus.trans_dist::BadAddressError 3 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 2010 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 2010 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 313168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 222539 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 6 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1034159 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 44112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 44112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1080281 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 4020 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 4020 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160913 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996889 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8815488 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9973290 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 1402560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 1402560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 11379870 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 30180989 # Total data (bytes) -system.membus.snoop_data_through_bus 18048 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 165986000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 5056260 # Transaction distribution +system.membus.trans_dist::ReadResp 5056258 # Transaction distribution +system.membus.trans_dist::WriteReq 13754 # Transaction distribution +system.membus.trans_dist::WriteResp 13754 # Transaction distribution +system.membus.trans_dist::Writeback 96958 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1654 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1654 # Transaction distribution +system.membus.trans_dist::ReadExReq 129924 # Transaction distribution +system.membus.trans_dist::ReadExResp 129924 # Transaction distribution +system.membus.trans_dist::MessageReq 1664 # Transaction distribution +system.membus.trans_dist::MessageResp 1664 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7028524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3012958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456844 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10498330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10596613 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3520458 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6025913 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17615808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27162179 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3029056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30197891 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 297 # Total snoops (count) +system.membus.snoop_fanout::samples 324529 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 324529 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 324529 # Request fanout histogram +system.membus.reqLayer0.occupancy 165183000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315728000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315920500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2010000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1960000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 815495498 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 897247500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1005000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 980000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1662343876 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1679098885 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 28017243 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 35042997 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 105452 # number of replacements -system.l2c.tags.tagsinuse 64826.295665 # Cycle average of tags in use -system.l2c.tags.total_refs 3690842 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169644 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.756396 # Average number of references to valid blocks. +system.l2c.tags.replacements 105529 # number of replacements +system.l2c.tags.tagsinuse 64826.632454 # Cycle average of tags in use +system.l2c.tags.total_refs 3692969 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169653 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.767779 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50973.887089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131156 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1039.864675 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3857.355286 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 297.125354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1525.078899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.736641 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003210 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1792.530465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5328.582890 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.777800 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50921.041202 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134275 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1022.158767 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3887.538850 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 285.540185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1563.161522 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 13.370475 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1774.545144 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5359.142034 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.776993 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.015867 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058859 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004534 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023271 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.027352 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.081308 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64192 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 605 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7395 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52837 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979492 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33876235 # Number of tag accesses -system.l2c.tags.data_accesses 33876235 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20790 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10881 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 323642 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 493790 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 11848 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6379 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 159823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 243124 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 53625 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 12570 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 372046 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 571492 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2280010 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.015597 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.059319 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004357 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023852 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000204 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.027077 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.081774 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989176 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64124 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 541 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3271 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7391 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52860 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.978455 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33891981 # Number of tag accesses +system.l2c.tags.data_accesses 33891981 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 19672 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10574 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 322011 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 496358 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 11305 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6290 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 162787 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 241655 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 55032 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 13181 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 370296 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 572247 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2281408 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1547750 # number of Writeback hits -system.l2c.Writeback_hits::total 1547750 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 119 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 62 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 66 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 247 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 66599 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 37683 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 62729 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 167011 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 20790 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10883 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 323642 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 560389 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 11848 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6379 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 159823 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 280807 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 53625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 12570 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 372046 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 634221 # number of demand (read+write) hits -system.l2c.demand_hits::total 2447023 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 20790 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10883 # number of overall hits -system.l2c.overall_hits::cpu0.inst 323642 # number of overall hits -system.l2c.overall_hits::cpu0.data 560389 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 11848 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6379 # number of overall hits -system.l2c.overall_hits::cpu1.inst 159823 # number of overall hits -system.l2c.overall_hits::cpu1.data 280807 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 53625 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 12570 # number of overall hits -system.l2c.overall_hits::cpu2.inst 372046 # number of overall hits -system.l2c.overall_hits::cpu2.data 634221 # number of overall hits -system.l2c.overall_hits::total 2447023 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6200 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 15808 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2342 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4299 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 31 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 6737 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 12987 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48409 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 731 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 353 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 335 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1419 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 73318 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 24339 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 32507 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130164 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6200 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 89126 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2342 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 28638 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 31 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 6737 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 45494 # 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number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28199786500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30478398000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58678184500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 496533000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 763698500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1260231500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28696319500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31242096500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59938416000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015584 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018038 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000636 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017123 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.027147 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.012649 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862974 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.818548 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.422129 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.360695 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.355875 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.187795 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65657.766238 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61919.579534 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60870.660914 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -783,98 +758,98 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # 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Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000192639009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081570 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005098 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005098 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428643 # Number of tag accesses -system.iocache.tags.data_accesses 428643 # Number of data accesses +system.iocache.tags.tag_accesses 428634 # Number of tag accesses +system.iocache.tags.data_accesses 428634 # Number of data accesses system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 907 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses -system.iocache.demand_misses::total 907 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses -system.iocache.overall_misses::total 907 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132008537 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 132008537 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 132008537 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 132008537 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 132008537 # 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number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 906 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 906 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 906 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 906 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145544.142227 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 145544.142227 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 145544.142227 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145919.182119 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145919.182119 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145919.182119 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 725 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 725 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 21472 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 21472 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 94282037 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1310743323 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1310743323 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 94282037 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 94282037 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.799338 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.459589 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.459589 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.799338 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.799338 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 130044.188966 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61044.305281 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61044.305281 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 740 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 740 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28368 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 28368 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 740 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 740 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 740 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 740 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 93698779 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1718205368 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1718205368 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 93698779 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 93698779 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.816777 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.607192 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.607192 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.816777 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.816777 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 126619.971622 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60568.435138 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60568.435138 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -884,109 +859,121 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 53202678 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1873297 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1872762 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 7303 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 7303 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 935388 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 816 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 816 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 157258 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 157258 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1081926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3727147 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 42874 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 142768 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4994715 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34620672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 124341034 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 151600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 524032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 159637338 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 270199237 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 3149808 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5231949371 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadReq 7367165 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7366643 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13756 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13756 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1548978 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 28368 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1663 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1663 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296632 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296632 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740682 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14873990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 71302 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 198555 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16884529 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55700736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213654403 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 264160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 728920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270348219 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 69633 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4254339 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011195 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105211 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4206713 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47626 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 4254339 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5229007845 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 868500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 990000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2437443949 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2442789502 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4869271823 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4872933864 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23963155 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24776404 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 77561882 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 82986153 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1275815 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 151004 # Transaction distribution -system.iobus.trans_dist::ReadResp 151004 # Transaction distribution -system.iobus.trans_dist::WriteReq 27777 # Transaction distribution -system.iobus.trans_dist::WriteResp 27777 # Transaction distribution -system.iobus.trans_dist::MessageReq 1005 # Transaction distribution -system.iobus.trans_dist::MessageResp 1005 # Transaction distribution +system.iobus.trans_dist::ReadReq 3504325 # Transaction distribution +system.iobus.trans_dist::ReadResp 3504325 # Transaction distribution +system.iobus.trans_dist::WriteReq 57563 # Transaction distribution +system.iobus.trans_dist::WriteResp 39211 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 18352 # Transaction distribution +system.iobus.trans_dist::MessageReq 1664 # Transaction distribution +system.iobus.trans_dist::MessageResp 1664 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5602 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 50 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 594 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 142 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 16180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 6984892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27280 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 313168 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 44394 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 44394 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 2010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 2010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 359572 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 25 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143631 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1188 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 71 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 8090 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 160913 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1410472 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1410472 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 4020 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 4020 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1575405 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6554984 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2375600 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7028524 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7127104 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3492446 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 3520458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6554906 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2324808 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4638000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4502000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 42000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -994,11 +981,11 @@ system.iobus.reqLayer8.occupancy 18000 # La system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 143632000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 469000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 361000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12075000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11636000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -1008,431 +995,431 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 194319603 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 256433144 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 306863000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 306163000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 26743757 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33668003 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1005000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 980000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1069887436 # number of cpu cycles simulated +system.cpu0.numCycles 1069607129 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 70857782 # Number of instructions committed -system.cpu0.committedOps 144307609 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 132405898 # Number of integer alu accesses +system.cpu0.committedInsts 70538619 # Number of instructions committed +system.cpu0.committedOps 143755687 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 131850662 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 941314 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14024705 # number of instructions that are conditional controls -system.cpu0.num_int_insts 132405898 # number of integer instructions +system.cpu0.num_func_calls 928819 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13976393 # number of instructions that are conditional controls +system.cpu0.num_int_insts 131850662 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 243097330 # number of times the integer registers were read -system.cpu0.num_int_register_writes 113712565 # number of times the integer registers were written +system.cpu0.num_int_register_reads 241989475 # number of times the integer registers were read +system.cpu0.num_int_register_writes 113259644 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 82467233 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55021807 # number of times the CC registers were written -system.cpu0.num_mem_refs 13631596 # number of memory refs -system.cpu0.num_load_insts 10001277 # Number of load instructions -system.cpu0.num_store_insts 3630319 # Number of store instructions -system.cpu0.num_idle_cycles 1016044794.752217 # Number of idle cycles -system.cpu0.num_busy_cycles 53842641.247783 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050326 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949674 # Percentage of idle cycles -system.cpu0.Branches 15304700 # Number of branches fetched -system.cpu0.op_class::No_OpClass 96295 0.07% 0.07% # Class of executed instruction -system.cpu0.op_class::IntAlu 130472194 90.41% 90.48% # Class of executed instruction -system.cpu0.op_class::IntMult 58212 0.04% 90.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 49897 0.03% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::MemRead 10001277 6.93% 97.48% # Class of executed instruction -system.cpu0.op_class::MemWrite 3630319 2.52% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82136389 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 54810829 # number of times the CC registers were written +system.cpu0.num_mem_refs 13501731 # number of memory refs +system.cpu0.num_load_insts 9912408 # Number of load instructions +system.cpu0.num_store_insts 3589323 # Number of store instructions +system.cpu0.num_idle_cycles 1016224343.330366 # Number of idle cycles +system.cpu0.num_busy_cycles 53382785.669634 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049909 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950091 # Percentage of idle cycles +system.cpu0.Branches 15238819 # Number of branches fetched +system.cpu0.op_class::No_OpClass 94852 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 130054750 90.47% 90.53% # Class of executed instruction +system.cpu0.op_class::IntMult 56051 0.04% 90.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 48845 0.03% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::MemRead 9912408 6.90% 97.50% # Class of executed instruction +system.cpu0.op_class::MemWrite 3589323 2.50% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 144308194 # Class of executed instruction +system.cpu0.op_class::total 143756229 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 870298 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.224543 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 128999874 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 870810 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 148.137796 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147420132000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.471919 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.049993 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.702632 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.245062 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.267676 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.483794 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996532 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 869835 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.810026 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 128546541 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 870347 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 147.695736 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147420125000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.953257 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.567270 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.289498 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.246002 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.268686 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.482987 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997676 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 250 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 228 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 130765185 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 130765185 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 86225595 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39744393 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3029886 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 128999874 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 86225595 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39744393 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3029886 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 128999874 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 86225595 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39744393 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3029886 # number of overall hits -system.cpu0.icache.overall_hits::total 128999874 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 329843 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 162165 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 402482 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 894490 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 329843 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 162165 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 402482 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 894490 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 329843 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 162165 # 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Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1639978 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.971659 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.173145 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 234.203255 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 22.623054 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.498385 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.457428 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.044186 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.719707 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 235.128668 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 22.151075 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497499 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.459236 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.043264 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88359204 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88359204 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4868347 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2652392 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4007715 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11528454 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3486449 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1737919 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2850405 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8074773 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 17966 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 11989 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30798 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 60753 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8354796 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4390311 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6858120 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19603227 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8372762 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4402300 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6888918 # number of overall hits -system.cpu0.dcache.overall_hits::total 19663980 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 361221 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 171759 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 751040 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1284020 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 140767 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 64096 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 121973 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 326836 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148377 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 75751 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 181169 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 405297 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 501988 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 235855 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 873013 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1610856 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 650365 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 311606 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1054182 # number of overall misses -system.cpu0.dcache.overall_misses::total 2016153 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2368546750 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 11961749403 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14330296153 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2359034692 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3857271379 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6216306071 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4727581442 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 15819020782 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 20546602224 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4727581442 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 15819020782 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 20546602224 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5229568 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2824151 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4758755 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12812474 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3627216 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1802015 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2972378 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8401609 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 166343 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 87740 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 211967 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466050 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8856784 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4626166 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7731133 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21214083 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9023127 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4713906 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7943100 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21680133 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.069073 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060818 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.157823 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.100216 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038809 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035569 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041035 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038902 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.891994 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.863358 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.854704 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.869643 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.056678 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050983 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.112922 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.075933 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.072078 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.066104 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.132717 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092995 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13789.942594 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15926.913883 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11160.492946 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36804.709998 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31623.977265 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19019.649216 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20044.440194 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18120.028891 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12755.083151 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 15171.663710 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15005.967453 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 10190.993553 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 128848 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 88291742 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88291742 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4780114 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2623103 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4098065 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11501282 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3444198 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1705247 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2919966 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8069411 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 17741 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 11962 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 31134 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 60837 # number of SoftPFReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8224312 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4328350 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 7018031 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19570693 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8242053 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4340312 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 7049165 # number of overall hits +system.cpu0.dcache.overall_hits::total 19631530 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 360631 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 14602.266020 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15987.586490 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 10656.437768 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 138914 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 26365 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 26241 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.887085 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5.293777 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1547750 # number of writebacks -system.cpu0.dcache.writebacks::total 1547750 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 72 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 345273 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 345345 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1671 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 26387 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 28058 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1743 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 371660 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 373403 # 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number of SoftPFReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 234112 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 501353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 735465 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 309848 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 680115 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 989963 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2023850750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5632729880 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7656580630 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2144841050 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3093501359 # 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number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30657477000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33314384500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63971861500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 501111500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 893222000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394333500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31158588500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34207606500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65366195000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060792 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085267 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045070 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034642 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032158 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018807 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.863187 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.843348 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.546074 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050606 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.064849 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034669 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065731 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085623 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.045662 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11788.025593 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13881.685499 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13259.204421 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34358.687225 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32363.540257 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33151.757846 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12993.932872 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15072.458106 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14453.910270 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17806.399501 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17405.363564 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17533.020659 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16630.090561 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16792.180727 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16741.448211 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1548978 # number of writebacks +system.cpu0.dcache.writebacks::total 1548978 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 70 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 359132 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 359202 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1638 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 26497 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 28135 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1708 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 385629 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 387337 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1708 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 385629 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 387337 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 171029 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 408794 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 579823 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 59295 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 97205 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 156500 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 75065 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 179480 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 254545 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 230324 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 505999 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 736323 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 305389 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 685479 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 990868 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2019901500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5830950588 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7850852088 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1912820354 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3255992760 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5168813114 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 995266500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2770573261 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3765839761 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3932721854 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9086943348 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13019665202 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4927988354 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11857516609 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16785504963 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30674705000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33246369000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63921074000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534053500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 811227000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345280500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31208758500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34057596000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65266354500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.061209 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084010 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045295 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033572 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031937 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018640 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.862400 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.842514 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.545962 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050505 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.063972 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034738 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065711 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.084391 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045740 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11810.286560 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14263.787110 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13540.083936 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32259.387031 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33496.144849 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33027.559834 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13258.729101 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15436.668492 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.396908 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17074.737561 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17958.421554 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17682.002602 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16136.757886 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17298.147148 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16940.202896 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1443,376 +1430,376 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606024060 # number of cpu cycles simulated +system.cpu1.numCycles 2604021576 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35944624 # Number of instructions committed -system.cpu1.committedOps 69816061 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64937038 # Number of integer alu accesses +system.cpu1.committedInsts 35901808 # Number of instructions committed +system.cpu1.committedOps 69778761 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64893692 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 484528 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6597164 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64937038 # number of integer instructions +system.cpu1.num_func_calls 487874 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6598396 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64893692 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 120144832 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55989327 # number of times the integer registers were written +system.cpu1.num_int_register_reads 119938204 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55974127 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36928761 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27400948 # number of times the CC registers were written -system.cpu1.num_mem_refs 4904439 # number of memory refs -system.cpu1.num_load_insts 3100845 # Number of load instructions -system.cpu1.num_store_insts 1803594 # Number of store instructions -system.cpu1.num_idle_cycles 2475176569.081452 # Number of idle cycles -system.cpu1.num_busy_cycles 130847490.918548 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050210 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949790 # Percentage of idle cycles -system.cpu1.Branches 7263647 # Number of branches fetched -system.cpu1.op_class::No_OpClass 35052 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64819822 92.84% 92.89% # Class of executed instruction -system.cpu1.op_class::IntMult 29822 0.04% 92.94% # Class of executed instruction -system.cpu1.op_class::IntDiv 27277 0.04% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::MemRead 3100845 4.44% 97.42% # Class of executed instruction -system.cpu1.op_class::MemWrite 1803594 2.58% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36929560 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27415142 # number of times the CC registers were written +system.cpu1.num_mem_refs 4838216 # number of memory refs +system.cpu1.num_load_insts 3070311 # Number of load instructions +system.cpu1.num_store_insts 1767905 # Number of store instructions +system.cpu1.num_idle_cycles 2474835372.874957 # Number of idle cycles +system.cpu1.num_busy_cycles 129186203.125043 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049610 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950390 # Percentage of idle cycles +system.cpu1.Branches 7267731 # Number of branches fetched +system.cpu1.op_class::No_OpClass 34873 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64849393 92.94% 92.99% # Class of executed instruction +system.cpu1.op_class::IntMult 30804 0.04% 93.03% # Class of executed instruction +system.cpu1.op_class::IntDiv 25762 0.04% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::MemRead 3070311 4.40% 97.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 1767905 2.53% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69816412 # Class of executed instruction +system.cpu1.op_class::total 69779048 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29512659 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29512659 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 322904 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26886254 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 26249300 # Number of BTB hits +system.cpu2.branchPred.lookups 29537500 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29537500 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 323734 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26929505 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 26224950 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.630931 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 591365 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 64668 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155365551 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.383706 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 595117 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63666 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155672620 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10587640 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 145508462 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29512659 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26840665 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 143230873 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 673912 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 95091 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 7931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 8903 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 52631 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 2801 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3432374 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 167414 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3341 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 154322486 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.857387 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.033367 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10607285 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 145694636 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29537500 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26820067 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 143529975 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 676631 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 97153 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 5039 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8049 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 56841 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 4424 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3472431 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 167012 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3661 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154646852 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.855079 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.032629 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 98410042 63.77% 63.77% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 833989 0.54% 64.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 24035117 15.57% 79.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 597750 0.39% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 798628 0.52% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 859445 0.56% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 568143 0.37% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 716402 0.46% 82.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27502970 17.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 98720699 63.84% 63.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 840447 0.54% 64.38% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23990695 15.51% 79.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 599923 0.39% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 812589 0.53% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 861055 0.56% 81.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 574182 0.37% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 718315 0.46% 82.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27528947 17.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 154322486 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189956 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.936556 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10280285 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 95091051 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 22517334 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5911995 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 337607 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 283677190 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 337607 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12887048 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76613528 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4915145 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 25582017 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 13802994 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 282449598 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 208301 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 6363616 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 49211 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4861555 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 337331977 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 615247721 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 378014471 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 38 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 325050122 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12281853 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 158846 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 160455 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 28628976 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6469632 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3638513 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 420201 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 343826 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 280493266 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 428842 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278404006 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 102314 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8748691 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13528194 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 64074 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 154322486 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.804040 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.401684 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154646852 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189741 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.935904 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10277789 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95381782 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 22559618 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5904125 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 338966 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283871353 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 338966 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12885148 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76664692 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4829048 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 25619792 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14124701 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 282624473 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 211024 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 6375709 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 73879 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 5159969 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 337473501 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 616062521 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 378507156 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 50 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 325128635 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12344864 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 162095 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 163797 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 28599466 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6606628 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3716011 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 425441 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 346966 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 280674873 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 430305 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 278581977 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 102725 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8814114 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 13599788 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 65362 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154646852 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.801407 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.400759 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 91177599 59.08% 59.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5361636 3.47% 62.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3887403 2.52% 65.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4108764 2.66% 67.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 21799190 14.13% 81.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 3056480 1.98% 83.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24267786 15.73% 99.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 453628 0.29% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 210000 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 91425932 59.12% 59.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5392264 3.49% 62.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3912324 2.53% 65.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4126244 2.67% 67.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 21795400 14.09% 81.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 3071037 1.99% 83.88% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 24235245 15.67% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 469170 0.30% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 219236 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 154322486 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154646852 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 2321368 89.34% 89.34% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 246 0.01% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 217075 8.35% 97.70% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 59662 2.30% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2310389 89.01% 89.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 246 0.01% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 223101 8.59% 97.61% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 62004 2.39% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 72561 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 268083598 96.29% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 57882 0.02% 96.34% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 47134 0.02% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6794594 2.44% 98.80% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3348237 1.20% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 76436 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 268041478 96.22% 96.24% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 58746 0.02% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 49744 0.02% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6933130 2.49% 98.77% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3422443 1.23% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278404006 # Type of FU issued -system.cpu2.iq.rate 1.791929 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2598351 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.009333 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 713831099 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 289675272 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 276815941 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 63 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes +system.cpu2.iq.FU_type_0::total 278581977 # Type of FU issued +system.cpu2.iq.rate 1.789537 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2595740 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.009318 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 714509188 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 289923619 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 276984093 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 82 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 280929766 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 30 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 708692 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 281101244 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 37 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 733638 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1202973 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6613 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5162 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 660777 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1227908 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6601 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5025 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 667461 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 754641 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 21520 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 754863 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 24022 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 337607 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 71713264 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1590839 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 280922108 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 41019 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6469632 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3638513 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 247100 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 199459 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1088059 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5162 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 186556 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 187873 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 374429 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 277824668 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6659327 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 530499 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 338966 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 71689555 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1628683 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 281105178 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 39439 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6606628 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3716011 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 250069 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 194031 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1131651 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5025 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 186633 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 188127 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 374760 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 278001109 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6795315 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 530943 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9922055 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28210243 # Number of branches executed -system.cpu2.iew.exec_stores 3262728 # Number of stores executed -system.cpu2.iew.exec_rate 1.788200 # Inst execution rate -system.cpu2.iew.wb_sent 277637651 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 276815959 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 215923076 # num instructions producing a value -system.cpu2.iew.wb_consumers 354065892 # num instructions consuming a value +system.cpu2.iew.exec_refs 10133053 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28226522 # Number of branches executed +system.cpu2.iew.exec_stores 3337738 # Number of stores executed +system.cpu2.iew.exec_rate 1.785806 # Inst execution rate +system.cpu2.iew.wb_sent 277806882 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 276984111 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 215977189 # num instructions producing a value +system.cpu2.iew.wb_consumers 354208085 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.781707 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609839 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.779273 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609747 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9085200 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 364768 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 325355 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152966387 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.777091 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.654040 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9156375 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 364943 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 326343 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 153280377 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.774187 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.653000 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 95002675 62.11% 62.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4175839 2.73% 64.84% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1266091 0.83% 65.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24954040 16.31% 81.98% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 981729 0.64% 82.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 650164 0.43% 83.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 435006 0.28% 83.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23529501 15.38% 98.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1971342 1.29% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 95267512 62.15% 62.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4211429 2.75% 64.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1288351 0.84% 65.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24928908 16.26% 82.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 992667 0.65% 82.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 656859 0.43% 83.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 436979 0.29% 83.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23484943 15.32% 98.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2012729 1.31% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152966387 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 137677652 # Number of instructions committed -system.cpu2.commit.committedOps 271835156 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 153280377 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137795324 # Number of instructions committed +system.cpu2.commit.committedOps 271948125 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8244394 # Number of memory references committed -system.cpu2.commit.loads 5266658 # Number of loads committed -system.cpu2.commit.membars 166791 # Number of memory barriers committed -system.cpu2.commit.branches 27802655 # Number of branches committed +system.cpu2.commit.refs 8427269 # Number of memory references committed +system.cpu2.commit.loads 5378719 # Number of loads committed +system.cpu2.commit.membars 165391 # Number of memory barriers committed +system.cpu2.commit.branches 27813078 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 248203210 # Number of committed integer instructions. -system.cpu2.commit.function_calls 440588 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 43200 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 263446464 96.91% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 55564 0.02% 96.95% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 45534 0.02% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5266658 1.94% 98.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2977736 1.10% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 248363308 # Number of committed integer instructions. +system.cpu2.commit.function_calls 444774 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 44974 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 263371453 96.85% 96.86% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 56553 0.02% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 47876 0.02% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5378719 1.98% 98.88% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3048550 1.12% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 271835156 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1971342 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 271948125 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2012729 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 431889681 # The number of ROB reads -system.cpu2.rob.rob_writes 563202973 # The number of ROB writes -system.cpu2.timesIdled 114782 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1043065 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4908353341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 137677652 # Number of Instructions Simulated -system.cpu2.committedOps 271835156 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.128473 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.128473 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.886153 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.886153 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 369541594 # number of integer regfile reads -system.cpu2.int_regfile_writes 221773447 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72930 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 140769340 # number of cc regfile reads -system.cpu2.cc_regfile_writes 108468562 # number of cc regfile writes -system.cpu2.misc_regfile_reads 90221682 # number of misc regfile reads -system.cpu2.misc_regfile_writes 135530 # number of misc regfile writes +system.cpu2.rob.rob_reads 432344700 # The number of ROB reads +system.cpu2.rob.rob_writes 563581737 # The number of ROB writes +system.cpu2.timesIdled 114304 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1025768 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4904031691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137795324 # Number of Instructions Simulated +system.cpu2.committedOps 271948125 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.129738 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.129738 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.885161 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.885161 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 370036745 # number of integer regfile reads +system.cpu2.int_regfile_writes 221903617 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72874 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes +system.cpu2.cc_regfile_reads 140867740 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108480868 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90412070 # number of misc regfile reads +system.cpu2.misc_regfile_writes 138782 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |