diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-10 18:06:43 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-10 18:06:43 -0600 |
commit | e76442e203bd4ce18e897658a17756a3d00bdeb8 (patch) | |
tree | 93af3959085146bd965f4f7e8ad8e1dad142ce3d /tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | |
parent | 7bb65dd4345401f40eccb5c23b563558dfd9e854 (diff) | |
download | gem5-e76442e203bd4ce18e897658a17756a3d00bdeb8.tar.xz |
stats: changes due to recent changesets.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt | 3109 |
1 files changed, 1543 insertions, 1566 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 767b8b8bc..5315d8c71 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.142213 # Number of seconds simulated -sim_ticks 5142212861500 # Number of ticks simulated -final_tick 5142212861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.144107 # Number of seconds simulated +sim_ticks 5144107123500 # Number of ticks simulated +final_tick 5144107123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 316771 # Simulator instruction rate (inst/s) -host_op_rate 629731 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6695034949 # Simulator tick rate (ticks/s) -host_mem_usage 960996 # Number of bytes of host memory used -host_seconds 768.06 # Real time elapsed on the host -sim_insts 243300298 # Number of instructions simulated -sim_ops 483673350 # Number of ops (including micro ops) simulated +host_inst_rate 180241 # Simulator instruction rate (inst/s) +host_op_rate 358324 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3805676977 # Simulator tick rate (ticks/s) +host_mem_usage 1000324 # Number of bytes of host memory used +host_seconds 1351.69 # Real time elapsed on the host +sim_insts 243630211 # Number of instructions simulated +sim_ops 484343866 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 424320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5246720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 435328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5271168 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 163840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2163392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 379584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2979328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 167488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2239424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 369088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2863936 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11387840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 424320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 163840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 379584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 967744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9172160 # Number of bytes written to this memory -system.physmem.bytes_written::total 9172160 # Number of bytes written to this memory +system.physmem.bytes_read::total 11377408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 435328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 167488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 369088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 971904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9177088 # Number of bytes written to this memory +system.physmem.bytes_written::total 9177088 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6630 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 81980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 82362 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2560 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 33803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5931 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 46552 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 36 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5767 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 44749 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 177935 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143315 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143315 # Number of write requests responded to by this memory +system.physmem.num_reads::total 177772 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143392 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143392 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 82517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1020323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 84627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1024700 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 31862 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 420712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 73817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 579386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2214580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 31862 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 73817 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 188196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1783699 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1783699 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1783699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 435338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 71750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 556741 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2211736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 84627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32559 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 71750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1784000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1784000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1784000 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 82517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1020323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 84627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1024700 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 31862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 420712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 73817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 579386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3998279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 88878 # Number of read requests accepted -system.physmem.writeReqs 113942 # Number of write requests accepted -system.physmem.readBursts 88878 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 113942 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5683264 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4928 # Total number of bytes read from write queue -system.physmem.bytesWritten 7207296 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5688192 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7292288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 77 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1310 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 940 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5243 # Per bank write bursts -system.physmem.perBankRdBursts::1 4719 # Per bank write bursts -system.physmem.perBankRdBursts::2 5104 # Per bank write bursts -system.physmem.perBankRdBursts::3 5729 # Per bank write bursts -system.physmem.perBankRdBursts::4 5898 # Per bank write bursts -system.physmem.perBankRdBursts::5 5027 # Per bank write bursts -system.physmem.perBankRdBursts::6 5470 # Per bank write bursts -system.physmem.perBankRdBursts::7 5567 # Per bank write bursts -system.physmem.perBankRdBursts::8 5651 # Per bank write bursts -system.physmem.perBankRdBursts::9 5723 # Per bank write bursts -system.physmem.perBankRdBursts::10 5167 # Per bank write bursts -system.physmem.perBankRdBursts::11 5483 # Per bank write bursts -system.physmem.perBankRdBursts::12 5886 # Per bank write bursts -system.physmem.perBankRdBursts::13 6693 # Per bank write bursts -system.physmem.perBankRdBursts::14 5960 # Per bank write bursts -system.physmem.perBankRdBursts::15 5481 # Per bank write bursts -system.physmem.perBankWrBursts::0 7238 # Per bank write bursts -system.physmem.perBankWrBursts::1 6716 # Per bank write bursts -system.physmem.perBankWrBursts::2 7069 # Per bank write bursts -system.physmem.perBankWrBursts::3 6723 # Per bank write bursts -system.physmem.perBankWrBursts::4 7013 # Per bank write bursts -system.physmem.perBankWrBursts::5 6703 # Per bank write bursts -system.physmem.perBankWrBursts::6 6619 # Per bank write bursts -system.physmem.perBankWrBursts::7 7556 # Per bank write bursts -system.physmem.perBankWrBursts::8 6486 # Per bank write bursts -system.physmem.perBankWrBursts::9 6985 # Per bank write bursts -system.physmem.perBankWrBursts::10 6508 # Per bank write bursts -system.physmem.perBankWrBursts::11 6763 # Per bank write bursts -system.physmem.perBankWrBursts::12 7496 # Per bank write bursts -system.physmem.perBankWrBursts::13 7338 # Per bank write bursts -system.physmem.perBankWrBursts::14 7696 # Per bank write bursts -system.physmem.perBankWrBursts::15 7705 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 32559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 435338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 71750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 556741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3995736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 88604 # Number of read requests accepted +system.physmem.writeReqs 101715 # Number of write requests accepted +system.physmem.readBursts 88604 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 101715 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5666496 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4160 # Total number of bytes read from write queue +system.physmem.bytesWritten 6448384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5670656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6509760 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 65 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 959 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 894 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5172 # Per bank write bursts +system.physmem.perBankRdBursts::1 4675 # Per bank write bursts +system.physmem.perBankRdBursts::2 4614 # Per bank write bursts +system.physmem.perBankRdBursts::3 5517 # Per bank write bursts +system.physmem.perBankRdBursts::4 6171 # Per bank write bursts +system.physmem.perBankRdBursts::5 5192 # Per bank write bursts +system.physmem.perBankRdBursts::6 5194 # Per bank write bursts +system.physmem.perBankRdBursts::7 5097 # Per bank write bursts +system.physmem.perBankRdBursts::8 5481 # Per bank write bursts +system.physmem.perBankRdBursts::9 5563 # Per bank write bursts +system.physmem.perBankRdBursts::10 5214 # Per bank write bursts +system.physmem.perBankRdBursts::11 5694 # Per bank write bursts +system.physmem.perBankRdBursts::12 5834 # Per bank write bursts +system.physmem.perBankRdBursts::13 6887 # Per bank write bursts +system.physmem.perBankRdBursts::14 6277 # Per bank write bursts +system.physmem.perBankRdBursts::15 5957 # Per bank write bursts +system.physmem.perBankWrBursts::0 6561 # Per bank write bursts +system.physmem.perBankWrBursts::1 6098 # Per bank write bursts +system.physmem.perBankWrBursts::2 5964 # Per bank write bursts +system.physmem.perBankWrBursts::3 5948 # Per bank write bursts +system.physmem.perBankWrBursts::4 7233 # Per bank write bursts +system.physmem.perBankWrBursts::5 6043 # Per bank write bursts +system.physmem.perBankWrBursts::6 6495 # Per bank write bursts +system.physmem.perBankWrBursts::7 6502 # Per bank write bursts +system.physmem.perBankWrBursts::8 5629 # Per bank write bursts +system.physmem.perBankWrBursts::9 6174 # Per bank write bursts +system.physmem.perBankWrBursts::10 5473 # Per bank write bursts +system.physmem.perBankWrBursts::11 6467 # Per bank write bursts +system.physmem.perBankWrBursts::12 6126 # Per bank write bursts +system.physmem.perBankWrBursts::13 6747 # Per bank write bursts +system.physmem.perBankWrBursts::14 6614 # Per bank write bursts +system.physmem.perBankWrBursts::15 6682 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5141212728000 # Total gap between requests +system.physmem.totGap 5140299284500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 88878 # Read request sizes (log2) +system.physmem.readPktSize::6 88604 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 113942 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 84289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 101715 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 84282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -165,479 +165,455 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 68 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 62 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 60 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 41455 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.951538 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.940976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.089751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16126 38.90% 38.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9571 23.09% 61.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4083 9.85% 71.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2278 5.50% 77.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1502 3.62% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1068 2.58% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 718 1.73% 85.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 598 1.44% 86.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5511 13.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 41455 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4333 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.493423 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 181.058580 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4330 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 40184 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 301.485168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.308895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.181387 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15726 39.13% 39.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9443 23.50% 62.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4063 10.11% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2232 5.55% 78.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1531 3.81% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1042 2.59% 84.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 702 1.75% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 613 1.53% 87.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4832 12.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40184 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.412092 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 185.359125 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4132 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4333 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4333 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.989845 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.182522 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 26.410005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 65 1.50% 1.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 6 0.14% 1.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.02% 1.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 7 0.16% 1.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3364 77.64% 79.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 26 0.60% 80.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 23 0.53% 80.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 179 4.13% 84.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 85 1.96% 86.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 35 0.81% 87.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 25 0.58% 88.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 23 0.53% 88.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 117 2.70% 91.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.16% 91.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.09% 91.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.09% 91.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 14 0.32% 91.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.21% 92.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.23% 92.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 35 0.81% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 78 1.80% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.05% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.09% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 7 0.16% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 92 2.12% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 7 0.16% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 24 0.55% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.07% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 4 0.09% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.32% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.09% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.12% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.16% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 6 0.14% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.07% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.07% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.07% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.05% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.07% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.05% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.05% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4333 # Writes before turning the bus around for reads -system.physmem.totQLat 976769250 # Total ticks spent queuing -system.physmem.totMemAccLat 2641788000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 444005000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10999.53 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4135 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4135 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.366626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.429404 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.022185 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 69 1.67% 1.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 9 0.22% 1.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 3347 80.94% 82.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 165 3.99% 86.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 114 2.76% 89.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 31 0.75% 90.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 101 2.44% 92.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 11 0.27% 93.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 26 0.63% 93.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 40 0.97% 94.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 54 1.31% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 10 0.24% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 75 1.81% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 8 0.19% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 18 0.44% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 7 0.17% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 15 0.36% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 4 0.10% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 12 0.29% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 5 0.12% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 2 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 4 0.10% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4135 # Writes before turning the bus around for reads +system.physmem.totQLat 956383499 # Total ticks spent queuing +system.physmem.totMemAccLat 2616489749 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 442695000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10801.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29749.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.42 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29551.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.25 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.10 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.27 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.09 # Average write queue length when enqueuing -system.physmem.readRowHits 70835 # Number of row buffer hits during reads -system.physmem.writeRowHits 89124 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.77 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.13 # Row buffer hit rate for writes -system.physmem.avgGap 25348647.71 # Average gap between requests -system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153097560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 83370375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 333504600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 360527760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250475462640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 95043085920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2239708824000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2586157872855 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.947189 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3689335375500 # Time in different power states -system.physmem_0.memoryStateTime::REF 128054940000 # Time in different power states +system.physmem.avgWrQLen 11.42 # Average write queue length when enqueuing +system.physmem.readRowHits 70796 # Number of row buffer hits during reads +system.physmem.writeRowHits 78315 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.73 # Row buffer hit rate for writes +system.physmem.avgGap 27008860.31 # Average gap between requests +system.physmem.pageHitRate 78.77 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 147178080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 80086875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 324729600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 329469120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250566494880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94792163085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2243751115500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2589991237140 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.838461 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3691094925500 # Time in different power states +system.physmem_0.memoryStateTime::REF 128101480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 17909174750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17513749500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 160302240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 87313875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 359135400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 369210960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250475462640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95555045385 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2233887892500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2580894363000 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.132718 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3688582993750 # Time in different power states -system.physmem_1.memoryStateTime::REF 128054940000 # Time in different power states +system.physmem_1.actEnergy 156612960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 85300875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 365874600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 323429760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250566494880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95660983305 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2237004864750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2584163561130 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.053818 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3689804823000 # Time in different power states +system.physmem_1.memoryStateTime::REF 128101480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18657353000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18778765250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 905515045 # number of cpu cycles simulated +system.cpu0.numCycles 906748886 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71354866 # Number of instructions committed -system.cpu0.committedOps 145718889 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 133579753 # Number of integer alu accesses +system.cpu0.committedInsts 71802590 # Number of instructions committed +system.cpu0.committedOps 146381299 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134255761 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 936391 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14189595 # number of instructions that are conditional controls -system.cpu0.num_int_insts 133579753 # number of integer instructions +system.cpu0.num_func_calls 943296 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14239563 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134255761 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 244625676 # number of times the integer registers were read -system.cpu0.num_int_register_writes 114972528 # number of times the integer registers were written +system.cpu0.num_int_register_reads 246209877 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115427878 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83222516 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55621681 # number of times the CC registers were written -system.cpu0.num_mem_refs 13385296 # number of memory refs -system.cpu0.num_load_insts 10015665 # Number of load instructions -system.cpu0.num_store_insts 3369631 # Number of store instructions -system.cpu0.num_idle_cycles 858514977.989050 # Number of idle cycles -system.cpu0.num_busy_cycles 47000067.010950 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051904 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948096 # Percentage of idle cycles -system.cpu0.Branches 15470512 # Number of branches fetched -system.cpu0.op_class::No_OpClass 89016 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 132139784 90.68% 90.74% # Class of executed instruction -system.cpu0.op_class::IntMult 57056 0.04% 90.78% # Class of executed instruction -system.cpu0.op_class::IntDiv 49774 0.03% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.82% # Class of executed instruction -system.cpu0.op_class::MemRead 10013957 6.87% 97.69% # Class of executed instruction -system.cpu0.op_class::MemWrite 3369631 2.31% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83592437 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55838323 # number of times the CC registers were written +system.cpu0.num_mem_refs 13658115 # number of memory refs +system.cpu0.num_load_insts 10127652 # Number of load instructions +system.cpu0.num_store_insts 3530463 # Number of store instructions +system.cpu0.num_idle_cycles 859556134.264708 # Number of idle cycles +system.cpu0.num_busy_cycles 47192751.735292 # Number of busy cycles +system.cpu0.not_idle_fraction 0.052046 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.947954 # Percentage of idle cycles +system.cpu0.Branches 15533640 # Number of branches fetched +system.cpu0.op_class::No_OpClass 89870 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 132527069 90.54% 90.60% # Class of executed instruction +system.cpu0.op_class::IntMult 58535 0.04% 90.64% # Class of executed instruction +system.cpu0.op_class::IntDiv 49919 0.03% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.67% # Class of executed instruction +system.cpu0.op_class::MemRead 10125945 6.92% 97.59% # Class of executed instruction +system.cpu0.op_class::MemWrite 3530463 2.41% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 145719218 # Class of executed instruction +system.cpu0.op_class::total 146381801 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1638885 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999440 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19690308 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1639397 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.010701 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1639020 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999449 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19713831 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1639532 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 12.024060 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 129.361524 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 276.707159 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 105.930757 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.252659 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.540444 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.206896 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 129.995226 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 275.897813 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 106.106411 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.253897 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.538863 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.207239 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 235 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88564731 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88564731 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4814748 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2752692 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 3969504 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11536944 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3244156 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1918293 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2929310 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8091759 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19629 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10883 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29286 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 59798 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8058904 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4670985 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6898814 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19628703 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8078533 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4681868 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6928100 # number of overall hits -system.cpu0.dcache.overall_hits::total 19688501 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 357538 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 167572 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 785074 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1310184 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 120756 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 69485 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 135769 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 326010 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148495 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 65341 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 192799 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406635 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 478294 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 237057 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 920843 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1636194 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 626789 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 302398 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1113642 # number of overall misses -system.cpu0.dcache.overall_misses::total 2042829 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2347978500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12373504263 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14721482763 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2672090343 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4159812296 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6831902639 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5020068843 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 16533316559 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 21553385402 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5020068843 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 16533316559 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 21553385402 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5172286 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2920264 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4754578 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12847128 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3364912 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1987778 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3065079 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8417769 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 168124 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76224 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 222085 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466433 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8537198 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4908042 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7819657 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21264897 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8705322 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4984266 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8041742 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21731330 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.069126 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057382 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.165120 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.101983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.035887 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034956 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.044295 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038729 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.883247 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.857223 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.868132 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871797 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.056025 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.048300 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.117760 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.076943 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.072001 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.060671 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.138483 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.094004 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14011.759124 # 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average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15387.725082 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10962.238275 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38788.715315 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31884.062956 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20749.601827 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21481.612786 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17664.681189 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12922.068629 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16813.711817 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14587.515660 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 10337.830415 # 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number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2415923500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5732417941 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8148341441 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2415923500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5732417941 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8148341441 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 87642602 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39761377 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3473903 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 130877882 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 87642602 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39761377 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3473903 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 130877882 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 87642602 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39761377 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3473903 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 130877882 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003570 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004338 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117351 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006824 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003570 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004338 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117351 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006824 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003570 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004338 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117351 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006824 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14007.546109 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14061.589641 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9124.089859 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14007.546109 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14061.589641 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9124.089859 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14007.546109 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14061.589641 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9124.089859 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4572 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 6 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.970954 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 6 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22841 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 22841 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 22841 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 22841 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 22841 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 22841 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 175554 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376344 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 551898 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 175554 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 376344 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 551898 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 175554 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 376344 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 551898 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2103717250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4645372892 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6749090142 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2103717250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4645372892 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6749090142 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2103717250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4645372892 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6749090142 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004220 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004220 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004220 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.872259 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.872259 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.872259 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23039 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23039 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23039 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23039 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23039 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23039 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 172473 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 384626 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 557099 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 172473 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 384626 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 557099 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 172473 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 384626 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 557099 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2070011500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4726513433 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6796524933 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2070011500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4726513433 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6796524933 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2070011500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4726513433 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6796524933 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004257 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004257 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004257 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12199.851253 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12199.851253 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12199.851253 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608019043 # number of cpu cycles simulated +system.cpu1.numCycles 2608020264 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 36458068 # Number of instructions committed -system.cpu1.committedOps 70720299 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 65779411 # Number of integer alu accesses +system.cpu1.committedInsts 35983855 # Number of instructions committed +system.cpu1.committedOps 69821911 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64889046 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 521390 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6639276 # number of instructions that are conditional controls -system.cpu1.num_int_insts 65779411 # number of integer instructions +system.cpu1.num_func_calls 503439 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6569343 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64889046 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 122190876 # number of times the integer registers were read -system.cpu1.num_int_register_writes 56554100 # number of times the integer registers were written +system.cpu1.num_int_register_reads 120388172 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55814326 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 37054979 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27544073 # number of times the CC registers were written -system.cpu1.num_mem_refs 5171486 # number of memory refs -system.cpu1.num_load_insts 3182631 # Number of load instructions -system.cpu1.num_store_insts 1988855 # Number of store instructions -system.cpu1.num_idle_cycles 2476913850.669656 # Number of idle cycles -system.cpu1.num_busy_cycles 131105192.330343 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050270 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949730 # Percentage of idle cycles -system.cpu1.Branches 7356329 # Number of branches fetched -system.cpu1.op_class::No_OpClass 36814 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 65455015 92.55% 92.61% # Class of executed instruction -system.cpu1.op_class::IntMult 34008 0.05% 92.65% # Class of executed instruction -system.cpu1.op_class::IntDiv 24962 0.04% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.69% # Class of executed instruction -system.cpu1.op_class::MemRead 3181010 4.50% 97.19% # Class of executed instruction -system.cpu1.op_class::MemWrite 1988855 2.81% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36581725 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27247591 # number of times the CC registers were written +system.cpu1.num_mem_refs 4980693 # number of memory refs +system.cpu1.num_load_insts 3049501 # Number of load instructions +system.cpu1.num_store_insts 1931192 # Number of store instructions +system.cpu1.num_idle_cycles 2477411639.002949 # Number of idle cycles +system.cpu1.num_busy_cycles 130608624.997051 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050080 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949920 # Percentage of idle cycles +system.cpu1.Branches 7257729 # Number of branches fetched +system.cpu1.op_class::No_OpClass 34768 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64752658 92.74% 92.79% # Class of executed instruction +system.cpu1.op_class::IntMult 32117 0.05% 92.84% # Class of executed instruction +system.cpu1.op_class::IntDiv 23661 0.03% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.87% # Class of executed instruction +system.cpu1.op_class::MemRead 3047883 4.37% 97.23% # Class of executed instruction +system.cpu1.op_class::MemWrite 1931192 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 70720664 # Class of executed instruction +system.cpu1.op_class::total 69822279 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28980045 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28980045 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 316258 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26301179 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25662962 # Number of BTB hits +system.cpu2.branchPred.lookups 29145274 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29145274 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 322260 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26440523 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25789579 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.573428 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 575120 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 62760 # Number of incorrect RAS predictions. -system.cpu2.numCycles 153675594 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.538082 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 584080 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63924 # Number of incorrect RAS predictions. +system.cpu2.numCycles 153878746 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10522056 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142983634 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28980045 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26238082 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 141648223 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 664532 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 102750 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 5712 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 8254 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 65359 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 18 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 587 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3403920 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 164909 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3818 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 152684574 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.843447 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.027165 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10764874 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 143615831 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29145274 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26373659 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 141609884 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 675175 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 95795 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 6373 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7380 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 61565 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 20 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 458 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3473911 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 167436 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3564 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 152883285 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.850280 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.030640 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 97834881 64.08% 64.08% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 827461 0.54% 64.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23508780 15.40% 80.02% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 590429 0.39% 80.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 809590 0.53% 80.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 824910 0.54% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 565945 0.37% 81.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 689592 0.45% 82.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27032986 17.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 97765346 63.95% 63.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 837203 0.55% 64.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23601513 15.44% 79.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 591420 0.39% 80.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 819374 0.54% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 838216 0.55% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 577391 0.38% 81.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 693159 0.45% 82.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27159663 17.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 152684574 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.188579 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.930425 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9666714 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93465476 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23018277 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4894255 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 332917 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278595760 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 332917 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11754676 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 75764311 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4472306 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 25597731 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 13455764 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277400530 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 224282 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5843297 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 52985 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 5514893 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 331330378 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 605053013 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371514373 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 36 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 319639627 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11690749 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 161038 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 162632 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24003573 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6435164 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3706636 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 363903 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 318629 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275503234 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 421288 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273595538 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 103309 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8356083 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12887842 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 64640 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 152684574 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.791900 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.394187 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 152883285 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189404 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.933305 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9834703 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 93251994 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 21466938 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4884733 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 338239 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 279965546 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 338239 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11923429 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 75993663 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4610925 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 24032799 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12877614 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 278749384 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 221936 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5866894 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 51314 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4911660 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 333127303 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 607942521 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 373256279 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 196 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320819170 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12308133 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 159156 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 160655 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 23900033 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6505190 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3599973 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 377004 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 316512 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 276808275 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 423236 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 274695170 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 101004 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8754938 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 13676659 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 65243 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 152883285 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.796764 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.395757 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 90392452 59.20% 59.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5451363 3.57% 62.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3935423 2.58% 65.35% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3565723 2.34% 67.69% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22424664 14.69% 82.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2492768 1.63% 84.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23751475 15.56% 99.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 460834 0.30% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 209872 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 90394017 59.13% 59.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5385946 3.52% 62.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3961954 2.59% 65.24% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3603407 2.36% 67.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22510778 14.72% 82.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2513602 1.64% 83.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23841558 15.59% 99.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 461559 0.30% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 210464 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 152684574 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 152883285 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1676714 85.59% 85.59% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 85.59% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 168 0.01% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 221197 11.29% 96.89% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 60976 3.11% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1679391 85.86% 85.86% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 6 0.00% 85.86% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 133 0.01% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.87% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 216471 11.07% 96.93% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 59961 3.07% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 82248 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 263185371 96.20% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 54901 0.02% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 48803 0.02% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6793041 2.48% 98.75% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3431174 1.25% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 81534 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264357889 96.24% 96.27% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 55368 0.02% 96.29% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50253 0.02% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 68 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6828846 2.49% 98.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3321212 1.21% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273595538 # Type of FU issued -system.cpu2.iq.rate 1.780345 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1959055 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007160 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 701937961 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 284284863 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272009603 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 52 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 275472321 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 24 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 698574 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 274695170 # Type of FU issued +system.cpu2.iq.rate 1.785140 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1955962 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007120 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 704330322 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 285990572 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 273107568 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 269 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 106 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 276569466 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 132 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 697735 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1169867 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6207 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4815 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 637978 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1221587 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6074 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4844 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 639616 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 755628 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 24889 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 755983 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 21219 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 332917 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70606528 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1760004 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 275924522 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 40123 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6435186 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3706636 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 246888 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 186471 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1275738 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4815 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 176824 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 191426 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 368250 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273027006 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6657386 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 516016 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 338239 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 70808815 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1780684 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 277231511 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 42116 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6505190 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3599973 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 246009 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 189602 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1292389 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4844 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 181953 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 192646 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 374599 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 274123146 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6692505 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 521898 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10001726 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27723980 # Number of branches executed -system.cpu2.iew.exec_stores 3344340 # Number of stores executed -system.cpu2.iew.exec_rate 1.776645 # Inst execution rate -system.cpu2.iew.wb_sent 272834661 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272009615 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 211997747 # num instructions producing a value -system.cpu2.iew.wb_consumers 347754146 # num instructions consuming a value +system.cpu2.iew.exec_refs 9929733 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27833627 # Number of branches executed +system.cpu2.iew.exec_stores 3237228 # Number of stores executed +system.cpu2.iew.exec_rate 1.781423 # Inst execution rate +system.cpu2.iew.wb_sent 273932637 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 273107674 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 213006118 # num instructions producing a value +system.cpu2.iew.wb_consumers 349346589 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.770025 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609620 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.774824 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609727 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8688913 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356648 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 319605 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 151378980 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.765332 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.647504 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9088854 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357993 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 325291 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 151524726 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.769617 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.649272 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94244642 62.26% 62.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4276340 2.82% 65.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1271564 0.84% 65.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24442364 16.15% 82.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1016704 0.67% 82.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 679552 0.45% 83.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 473445 0.31% 83.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23012596 15.20% 98.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1961773 1.30% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 94238602 62.19% 62.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4221946 2.79% 64.98% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1274040 0.84% 65.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24556134 16.21% 82.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1017367 0.67% 82.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 681486 0.45% 83.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 477034 0.31% 83.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23101810 15.25% 98.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1956307 1.29% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 151378980 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135487364 # Number of instructions committed -system.cpu2.commit.committedOps 267234162 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 151524726 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135843766 # Number of instructions committed +system.cpu2.commit.committedOps 268140656 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8333976 # Number of memory references committed -system.cpu2.commit.loads 5265318 # Number of loads committed -system.cpu2.commit.membars 160044 # Number of memory barriers committed -system.cpu2.commit.branches 27319158 # Number of branches committed -system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244126615 # Number of committed integer instructions. -system.cpu2.commit.function_calls 428007 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 46777 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 258753265 96.83% 96.84% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 52699 0.02% 96.86% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 47480 0.02% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5265283 1.97% 98.85% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3068658 1.15% 100.00% # Class of committed instruction +system.cpu2.commit.refs 8243960 # Number of memory references committed +system.cpu2.commit.loads 5283603 # Number of loads committed +system.cpu2.commit.membars 162116 # Number of memory barriers committed +system.cpu2.commit.branches 27422801 # Number of branches committed +system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 244944567 # Number of committed integer instructions. +system.cpu2.commit.function_calls 433353 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 47848 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 259747107 96.87% 96.89% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 53065 0.02% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 48699 0.02% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5283564 1.97% 98.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2960357 1.10% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 267234162 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1961773 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 268140656 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1956307 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 425310506 # The number of ROB reads -system.cpu2.rob.rob_writes 553158006 # The number of ROB writes -system.cpu2.timesIdled 113704 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 991020 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4914719574 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135487364 # Number of Instructions Simulated -system.cpu2.committedOps 267234162 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.134243 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.134243 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.881645 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.881645 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 363574277 # number of integer regfile reads -system.cpu2.int_regfile_writes 217910153 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72980 # number of floating regfile reads +system.cpu2.rob.rob_reads 426769551 # The number of ROB reads +system.cpu2.rob.rob_writes 555823820 # The number of ROB writes +system.cpu2.timesIdled 116899 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 995461 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4917307163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135843766 # Number of Instructions Simulated +system.cpu2.committedOps 268140656 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.132763 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.132763 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.882797 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.882797 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 364780652 # number of integer regfile reads +system.cpu2.int_regfile_writes 218921020 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73130 # number of floating regfile reads system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138812774 # number of cc regfile reads -system.cpu2.cc_regfile_writes 106705933 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88766274 # number of misc regfile reads -system.cpu2.misc_regfile_writes 139734 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3554581 # Transaction distribution -system.iobus.trans_dist::ReadResp 3554581 # Transaction distribution -system.iobus.trans_dist::WriteReq 57732 # Transaction distribution -system.iobus.trans_dist::WriteResp 11012 # Transaction distribution +system.cpu2.cc_regfile_reads 139296056 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107100465 # number of cc regfile writes +system.cpu2.misc_regfile_reads 89036481 # number of misc regfile reads +system.cpu2.misc_regfile_writes 137201 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3554570 # Transaction distribution +system.iobus.trans_dist::ReadResp 3554570 # Transaction distribution +system.iobus.trans_dist::WriteReq 57725 # Transaction distribution +system.iobus.trans_dist::WriteResp 11005 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1688 # Transaction distribution -system.iobus.trans_dist::MessageResp 1688 # Transaction distribution +system.iobus.trans_dist::MessageReq 1681 # Transaction distribution +system.iobus.trans_dist::MessageResp 1681 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27896 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7129380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3376 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3376 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7228002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7129348 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3362 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3362 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7227952 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13955 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13948 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3570850 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6605370 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2500128 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3570873 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027752 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027752 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6724 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6724 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6605349 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2588568 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3583000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4563000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -1230,64 +1207,64 @@ system.iobus.reqLayer8.occupancy 18000 # La system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 318000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 404000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10022000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10340000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 273258249 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 221126240 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 301483000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 302697000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 28884002 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 28304753 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1044000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1088000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47568 # number of replacements -system.iocache.tags.tagsinuse 0.106184 # Cycle average of tags in use +system.iocache.tags.replacements 47566 # number of replacements +system.iocache.tags.tagsinuse 0.112009 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47582 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000571396009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.106184 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006636 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006636 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000571390009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112009 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007001 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007001 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428607 # Number of tag accesses -system.iocache.tags.data_accesses 428607 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses -system.iocache.ReadReq_misses::total 903 # number of ReadReq misses +system.iocache.tags.tag_accesses 428589 # Number of tag accesses +system.iocache.tags.data_accesses 428589 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 901 # number of ReadReq misses +system.iocache.ReadReq_misses::total 901 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses -system.iocache.demand_misses::total 903 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses -system.iocache.overall_misses::total 903 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 21110907 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21110907 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 7547175340 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 7547175340 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 21110907 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21110907 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 21110907 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21110907 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 901 # number of demand (read+write) misses +system.iocache.demand_misses::total 901 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 901 # number of overall misses +system.iocache.overall_misses::total 901 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132764027 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 132764027 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 6059046460 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6059046460 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 132764027 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 132764027 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 132764027 # number of overall miss cycles +system.iocache.overall_miss_latency::total 132764027 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 901 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 901 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 901 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 901 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 901 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 901 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1296,325 +1273,325 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 23378.634551 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 161540.568065 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 161540.568065 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 23378.634551 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 23378.634551 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 42516 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 147351.861265 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 129688.494435 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 129688.494435 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 147351.861265 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 147351.861265 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34598 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5560 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4497 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.646763 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.693573 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 186 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 186 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28512 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 28512 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 186 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 186 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 186 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 186 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11438907 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6064547344 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6064547344 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 11438907 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 11438907 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.205980 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.610274 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.610274 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.205980 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.205980 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 61499.500000 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212701.576319 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212701.576319 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 61499.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 61499.500000 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 738 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 23008 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 23008 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 738 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 738 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 738 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 94361527 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 4862624466 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4862624466 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 94361527 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 94361527 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.819090 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.492466 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.492466 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.819090 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.819090 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127861.147696 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 211344.943759 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 211344.943759 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 127861.147696 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 127861.147696 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104912 # number of replacements -system.l2c.tags.tagsinuse 64826.396555 # Cycle average of tags in use -system.l2c.tags.total_refs 3699624 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169121 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.875604 # Average number of references to valid blocks. +system.l2c.tags.replacements 104970 # number of replacements +system.l2c.tags.tagsinuse 64826.298792 # Cycle average of tags in use +system.l2c.tags.total_refs 3700737 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169148 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.878692 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51247.277585 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131369 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1719.764589 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5034.334216 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003270 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 365.232722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1988.868841 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.547985 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 847.123033 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3617.112946 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.781971 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51221.575879 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131319 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1714.525389 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5051.845543 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003637 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 364.783966 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1988.075845 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.500719 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 853.175626 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3622.680869 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.781579 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.026242 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076818 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.026162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.077085 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005573 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.030348 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000100 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.012926 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.055193 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989172 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64209 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 571 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3164 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7713 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52703 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979752 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33891817 # Number of tag accesses -system.l2c.tags.data_accesses 33891817 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20180 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10473 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 308266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 489820 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 12327 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6781 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 172994 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 227559 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 57791 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13812 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 370398 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 597307 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2287708 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.005566 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.030336 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000145 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.013018 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.055278 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64178 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2747 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6462 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54646 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.979279 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33928519 # Number of tag accesses +system.l2c.tags.data_accesses 33928519 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 20269 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10932 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 306104 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 491683 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 12164 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6423 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 169856 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 227750 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 59393 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 13568 # 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average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1758,70 +1735,70 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5122016 # Transaction distribution -system.membus.trans_dist::ReadResp 5122015 # Transaction distribution -system.membus.trans_dist::WriteReq 13950 # Transaction distribution -system.membus.trans_dist::WriteResp 13950 # Transaction distribution -system.membus.trans_dist::Writeback 143315 # Transaction distribution +system.membus.trans_dist::ReadReq 5122083 # Transaction distribution +system.membus.trans_dist::ReadResp 5122081 # Transaction distribution +system.membus.trans_dist::WriteReq 13936 # Transaction distribution +system.membus.trans_dist::WriteResp 13936 # Transaction distribution +system.membus.trans_dist::Writeback 143392 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1630 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1630 # Transaction distribution -system.membus.trans_dist::ReadExReq 130173 # Transaction distribution -system.membus.trans_dist::ReadExResp 130173 # Transaction distribution -system.membus.trans_dist::MessageReq 1688 # Transaction distribution -system.membus.trans_dist::MessageResp 1688 # Transaction distribution -system.membus.trans_dist::BadAddressError 1 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3376 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3376 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129380 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044798 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455864 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10630044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141727 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141727 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10775147 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570850 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6089593 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17566400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27226843 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6022656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6022656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33256251 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 522 # Total snoops (count) -system.membus.snoop_fanout::samples 370715 # Request fanout histogram +system.membus.trans_dist::UpgradeReq 1613 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1613 # Transaction distribution +system.membus.trans_dist::ReadExReq 129914 # Transaction distribution +system.membus.trans_dist::ReadExResp 129914 # Transaction distribution +system.membus.trans_dist::MessageReq 1681 # Transaction distribution +system.membus.trans_dist::MessageResp 1681 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3362 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3362 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044744 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10629668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141614 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141614 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10774644 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570873 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6089485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17560128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27220486 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6015552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33242762 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 642 # Total snoops (count) +system.membus.snoop_fanout::samples 370612 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 370715 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 370612 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 370715 # Request fanout histogram -system.membus.reqLayer0.occupancy 161293000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 370612 # Request fanout histogram +system.membus.reqLayer0.occupancy 162893500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314500500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 314579500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2088000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2176000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1165884999 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1055146498 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1044000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1088000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1714039312 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1708813357 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 30187998 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 29666247 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1831,52 +1808,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7445356 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7445355 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13952 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13952 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1548383 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 28512 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1653 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1653 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291909 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291909 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1733601 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15004877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73054 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 211316 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17022848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55474752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213691163 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 265608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 747576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270179099 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 79089 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4261601 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011175 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105119 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7441673 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7441143 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13938 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13938 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1548363 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 23008 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1618 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1618 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291446 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291446 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15004999 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72834 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 207249 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17025096 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55679680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213700038 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 269360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 773664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270422742 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 67345 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4256875 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011187 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105175 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4213978 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47623 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4209254 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47621 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4261601 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5362619847 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4256875 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5306720328 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 837000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2486663092 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2510055059 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4974743955 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4923615960 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 27294890 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 25531897 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 94899067 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 85751327 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |