diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-12-05 00:11:25 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-12-05 00:11:25 +0000 |
| commit | bbcbe028fe904ec3f48b39e02c4a8fbc6f438699 (patch) | |
| tree | 2e3c780f3c56f844d4fb36b438c3691af198a02b /tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full | |
| parent | 78275c9d2f918d245902c3c00a9486b4af8e8099 (diff) | |
| download | gem5-bbcbe028fe904ec3f48b39e02c4a8fbc6f438699.tar.xz | |
stats: Update to reflect changes to PCI handling
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full')
6 files changed, 1787 insertions, 1778 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index d7ee3e6f6..bf97d6d87 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -28,8 +28,9 @@ mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -139,6 +140,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -155,6 +157,7 @@ system=system tags=system.cpu0.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.slave[1] @@ -189,6 +192,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -205,6 +209,7 @@ system=system tags=system.cpu0.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.slave[0] @@ -267,7 +272,7 @@ dtb=system.cpu1.dtb eventq_index=0 function_trace=false function_trace_start=0 -interrupts=Null +interrupts= isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 @@ -363,7 +368,7 @@ iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -interrupts=Null +interrupts= isa=system.cpu2.isa issueToExecuteDelay=1 issueWidth=8 @@ -1215,8 +1220,8 @@ frontend_latency=2 response_latency=2 use_default_range=false width=16 -default=system.pc.pciconfig.pio -master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side +default=system.pc.pci_host.pio +master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master [system.iocache] @@ -1225,6 +1230,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=false @@ -1241,7 +1247,8 @@ system=system tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 -cpu_side=system.iobus.master[19] +writeback_clean=false +cpu_side=system.iobus.master[18] mem_side=system.membus.slave[4] [system.iocache.tags] @@ -1260,6 +1267,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 forward_snoops=true @@ -1276,6 +1284,7 @@ system=system tags=system.l2c.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] @@ -1326,7 +1335,7 @@ pio=system.membus.default [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge eventq_index=0 intrctrl=system.intrctrl system=system @@ -1347,7 +1356,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[13] +pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 @@ -1359,7 +1368,7 @@ pio_latency=100000 platform=system.pc system=system terminal=system.pc.com_1.terminal -pio=system.iobus.master[14] +pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal @@ -1385,7 +1394,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[15] +pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake @@ -1403,7 +1412,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[16] +pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake @@ -1421,7 +1430,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[17] +pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake @@ -1439,7 +1448,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[18] +pio=system.iobus.master[17] [system.pc.i_dont_exist1] type=IsaFake @@ -1457,7 +1466,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[11] +pio=system.iobus.master[10] [system.pc.i_dont_exist2] type=IsaFake @@ -1475,17 +1484,19 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[12] +pio=system.iobus.master[11] -[system.pc.pciconfig] -type=PciConfigAll -bus=0 +[system.pc.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=13835058055282163712 +conf_device_bits=8 +conf_size=16777216 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=9223372036854775808 platform=system.pc -size=16777216 system=system pio=system.iobus.default @@ -1608,14 +1619,13 @@ config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 eventq_index=0 +host=system.pc.pci_host io_shift=0 pci_bus=0 pci_dev=4 pci_func=0 pio_latency=30000 -platform=system.pc system=system -config=system.iobus.master[4] dma=system.iobus.slave[1] pio=system.iobus.master[3] @@ -1639,7 +1649,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/work/gem5/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1662,7 +1672,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/work/gem5/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1767,7 +1777,7 @@ pio_addr=4273995776 pio_latency=100000 system=system int_master=system.iobus.slave[2] -pio=system.iobus.master[10] +pio=system.iobus.master[9] [system.pc.south_bridge.keyboard] type=I8042 @@ -1781,7 +1791,7 @@ mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=100000 system=system -pio=system.iobus.master[5] +pio=system.iobus.master[4] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin @@ -1802,7 +1812,7 @@ pio_addr=9223372036854775840 pio_latency=100000 slave=system.pc.south_bridge.pic2 system=system -pio=system.iobus.master[6] +pio=system.iobus.master[5] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin @@ -1819,7 +1829,7 @@ pio_addr=9223372036854775968 pio_latency=100000 slave=Null system=system -pio=system.iobus.master[7] +pio=system.iobus.master[6] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin @@ -1834,7 +1844,7 @@ int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 system=system -pio=system.iobus.master[8] +pio=system.iobus.master[7] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin @@ -1848,7 +1858,7 @@ i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[8] [system.physmem] type=DRAMCtrl @@ -1952,12 +1962,13 @@ version= [system.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 response_latency=1 -snoop_filter=Null +snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -1965,6 +1976,13 @@ width=32 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port +[system.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.voltage_domain] type=VoltageDomain eventq_index=0 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json index 6cc193075..aed66fce8 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json @@ -2,7 +2,7 @@ "name": null, "sim_quantum": 0, "system": { - "kernel": "/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9", + "kernel": "/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9", "mmap_using_noreserve": false, "kernel_addr_check": true, "bridge": { @@ -40,7 +40,7 @@ }, "name": "iobus", "default": { - "peer": "system.pc.pciconfig.pio", + "peer": "system.pc.pci_host.pio", "role": "MASTER" }, "forward_latency": 1, @@ -53,7 +53,6 @@ "system.pc.south_bridge.cmos.pio", "system.pc.south_bridge.dma1.pio", "system.pc.south_bridge.ide.pio", - "system.pc.south_bridge.ide.config", "system.pc.south_bridge.keyboard.pio", "system.pc.south_bridge.pic1.pio", "system.pc.south_bridge.pic2.pio", @@ -107,6 +106,7 @@ "peer": "system.toL2Bus.master[0]", "role": "SLAVE" }, + "clusivity": "mostly_incl", "prefetcher": null, "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, @@ -133,11 +133,12 @@ "peer": "system.membus.slave[2]", "role": "MASTER" }, - "mshrs": 20, + "type": "Cache", "forward_snoops": true, + "writeback_clean": false, "hit_latency": 20, - "demand_mshr_reserve": 1, "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, "addr_ranges": [ "0:18446744073709551615" ], @@ -145,11 +146,11 @@ "prefetch_on_access": false, "path": "system.l2c", "name": "l2c", - "type": "Cache", + "mshrs": 20, "sequential_access": false, "assoc": 8 }, - "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", + "readfile": "/work/gem5/outgoing/gem5_2/tests/halt.sh", "intel_mp_table": { "oem_table_addr": 0, "name": "intel_mp_table", @@ -631,9 +632,10 @@ "load_offset": 0, "iocache": { "cpu_side": { - "peer": "system.iobus.master[19]", + "peer": "system.iobus.master[18]", "role": "SLAVE" }, + "clusivity": "mostly_incl", "prefetcher": null, "clk_domain": "system.clk_domain", "write_buffers": 8, @@ -660,11 +662,12 @@ "peer": "system.membus.slave[4]", "role": "MASTER" }, - "mshrs": 20, + "type": "Cache", "forward_snoops": false, + "writeback_clean": false, "hit_latency": 50, - "demand_mshr_reserve": 1, "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, "addr_ranges": [ "0:134217727" ], @@ -672,7 +675,7 @@ "prefetch_on_access": false, "path": "system.iocache", "name": "iocache", - "type": "Cache", + "mshrs": 20, "sequential_access": false, "assoc": 8 }, @@ -798,7 +801,7 @@ "name": "fake_com_4", "warn_access": "", "pio": { - "peer": "system.iobus.master[17]", + "peer": "system.iobus.master[16]", "role": "SLAVE" }, "ret_bad_addr": false, @@ -816,31 +819,13 @@ "type": "IsaFake", "ret_data16": 65535 }, - "pciconfig": { - "name": "pciconfig", - "pio": { - "peer": "system.iobus.default", - "role": "SLAVE" - }, - "bus": 0, - "pio_latency": 30000, - "clk_domain": "system.clk_domain", - "system": "system", - "platform": "system.pc", - "eventq_index": 0, - "cxx_class": "PciConfigAll", - "path": "system.pc.pciconfig", - "pio_addr": 0, - "type": "PciConfigAll", - "size": 16777216 - }, "fake_com_2": { "system": "system", "ret_data8": 255, "name": "fake_com_2", "warn_access": "", "pio": { - "peer": "system.iobus.master[15]", + "peer": "system.iobus.master[14]", "role": "SLAVE" }, "ret_bad_addr": false, @@ -985,7 +970,7 @@ "speaker": { "name": "speaker", "pio": { - "peer": "system.iobus.master[9]", + "peer": "system.iobus.master[8]", "role": "SLAVE" }, "pio_latency": 100000, @@ -1003,7 +988,7 @@ "command_port": 9223372036854775908, "name": "keyboard", "pio": { - "peer": "system.iobus.master[5]", + "peer": "system.iobus.master[4]", "role": "SLAVE" }, "mouse_int_pin": { @@ -1032,7 +1017,7 @@ "pit": { "name": "pit", "pio": { - "peer": "system.iobus.master[8]", + "peer": "system.iobus.master[7]", "role": "SLAVE" }, "pio_latency": 100000, @@ -1058,7 +1043,7 @@ }, "name": "io_apic", "pio": { - "peer": "system.iobus.master[10]", + "peer": "system.iobus.master[9]", "role": "SLAVE" }, "pio_latency": 100000, @@ -1084,7 +1069,7 @@ "cxx_class": "X86ISA::IntSourcePin" }, "pio": { - "peer": "system.iobus.master[6]", + "peer": "system.iobus.master[5]", "role": "SLAVE" }, "pio_latency": 100000, @@ -1108,7 +1093,7 @@ "cxx_class": "X86ISA::IntSourcePin" }, "pio": { - "peer": "system.iobus.master[7]", + "peer": "system.iobus.master[6]", "role": "SLAVE" }, "pio_latency": 100000, @@ -1151,7 +1136,6 @@ "Revision": 0, "LegacyIOBase": 9223372036854775808, "pio_latency": 30000, - "platform": "system.pc", "PXCAPLinkCap": 0, "CapabilityPtr": 0, "MSIXCAPBaseOffset": 0, @@ -1183,7 +1167,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks0.image.child", - "image_file": "/scratch/nilay/GEM5/system/disks/linux-x86.img", + "image_file": "/work/gem5/dist/disks/linux-x86.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks0.image", @@ -1211,7 +1195,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks1.image.child", - "image_file": "/scratch/nilay/GEM5/system/disks/linux-bigswap2.img", + "image_file": "/work/gem5/dist/disks/linux-bigswap2.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks1.image", @@ -1242,6 +1226,7 @@ "PXCAPDevCap2": 0, "PXCAPDevCtrl": 0, "MSICAPMaskBits": 0, + "host": "system.pc.pci_host", "Command": 0, "SubClassCode": 1, "pci_func": 0, @@ -1285,10 +1270,6 @@ "clk_domain": "system.clk_domain", "SubsystemVendorID": 0, "PMCAPBaseOffset": 0, - "config": { - "peer": "system.iobus.master[4]", - "role": "SLAVE" - }, "MSICAPPendingBits": 0, "MSIXTableOffset": 0, "MSICAPMsgUpperAddr": 0, @@ -1330,7 +1311,7 @@ "name": "fake_floppy", "warn_access": "", "pio": { - "peer": "system.iobus.master[18]", + "peer": "system.iobus.master[17]", "role": "SLAVE" }, "ret_bad_addr": false, @@ -1354,7 +1335,7 @@ "name": "i_dont_exist2", "warn_access": "", "pio": { - "peer": "system.iobus.master[12]", + "peer": "system.iobus.master[11]", "role": "SLAVE" }, "ret_bad_addr": false, @@ -1379,7 +1360,7 @@ "name": "i_dont_exist1", "warn_access": "", "pio": { - "peer": "system.iobus.master[11]", + "peer": "system.iobus.master[10]", "role": "SLAVE" }, "ret_bad_addr": false, @@ -1401,7 +1382,7 @@ "com_1": { "name": "com_1", "pio": { - "peer": "system.iobus.master[14]", + "peer": "system.iobus.master[13]", "role": "SLAVE" }, "pio_latency": 100000, @@ -1425,6 +1406,26 @@ "pio_addr": 9223372036854776824, "type": "Uart8250" }, + "pci_host": { + "conf_size": 16777216, + "name": "pci_host", + "conf_device_bits": 8, + "pio": { + "peer": "system.iobus.default", + "role": "SLAVE" + }, + "conf_base": 13835058055282163712, + "clk_domain": "system.clk_domain", + "system": "system", + "pci_dma_base": 0, + "platform": "system.pc", + "eventq_index": 0, + "cxx_class": "GenericPciHost", + "path": "system.pc.pci_host", + "pci_pio_base": 9223372036854775808, + "type": "GenericPciHost", + "pci_mem_base": 0 + }, "eventq_index": 0, "cxx_class": "Pc", "path": "system.pc", @@ -1434,7 +1435,7 @@ "name": "behind_pci", "warn_access": "", "pio": { - "peer": "system.iobus.master[13]", + "peer": "system.iobus.master[12]", "role": "SLAVE" }, "ret_bad_addr": false, @@ -1459,7 +1460,7 @@ "name": "fake_com_3", "warn_access": "", "pio": { - "peer": "system.iobus.master[16]", + "peer": "system.iobus.master[15]", "role": "SLAVE" }, "ret_bad_addr": false, @@ -1704,7 +1705,16 @@ "role": "SLAVE" }, "name": "toL2Bus", - "snoop_filter": null, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, "forward_latency": 0, "clk_domain": "system.cpu_clk_domain", "system": "system", @@ -1793,6 +1803,7 @@ "peer": "system.cpu0.icache_port", "role": "SLAVE" }, + "clusivity": "mostly_incl", "prefetcher": null, "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, @@ -1819,11 +1830,12 @@ "peer": "system.toL2Bus.slave[0]", "role": "MASTER" }, - "mshrs": 4, + "type": "Cache", "forward_snoops": true, + "writeback_clean": true, "hit_latency": 2, - "demand_mshr_reserve": 1, "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, "addr_ranges": [ "0:18446744073709551615" ], @@ -1831,34 +1843,36 @@ "prefetch_on_access": false, "path": "system.cpu0.icache", "name": "icache", - "type": "Cache", + "mshrs": 4, "sequential_access": false, "assoc": 1 }, - "interrupts": { - "int_master": { - "peer": "system.membus.slave[3]", - "role": "MASTER" - }, - "name": "interrupts", - "pio": { - "peer": "system.membus.master[1]", - "role": "SLAVE" - }, - "int_slave": { - "peer": "system.membus.master[2]", - "role": "SLAVE" - }, - "pio_latency": 100000, - "clk_domain": "system.cpu0.apic_clk_domain", - "system": "system", - "int_latency": 1000, - "eventq_index": 0, - "cxx_class": "X86ISA::Interrupts", - "path": "system.cpu0.interrupts", - "pio_addr": 2305843009213693952, - "type": "X86LocalApic" - }, + "interrupts": [ + { + "int_master": { + "peer": "system.membus.slave[3]", + "role": "MASTER" + }, + "name": "interrupts", + "pio": { + "peer": "system.membus.master[1]", + "role": "SLAVE" + }, + "int_slave": { + "peer": "system.membus.master[2]", + "role": "SLAVE" + }, + "pio_latency": 100000, + "clk_domain": "system.cpu0.apic_clk_domain", + "system": "system", + "int_latency": 1000, + "eventq_index": 0, + "cxx_class": "X86ISA::Interrupts", + "path": "system.cpu0.interrupts", + "pio_addr": 2305843009213693952, + "type": "X86LocalApic" + } + ], "dcache_port": { "peer": "system.cpu0.dcache.cpu_side", "role": "MASTER" @@ -1902,6 +1916,7 @@ "peer": "system.cpu0.dcache_port", "role": "SLAVE" }, + "clusivity": "mostly_incl", "prefetcher": null, "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, @@ -1928,11 +1943,12 @@ "peer": "system.toL2Bus.slave[1]", "role": "MASTER" }, - "mshrs": 4, + "type": "Cache", "forward_snoops": true, + "writeback_clean": false, "hit_latency": 2, - "demand_mshr_reserve": 1, "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, "addr_ranges": [ "0:18446744073709551615" ], @@ -1940,7 +1956,7 @@ "prefetch_on_access": false, "path": "system.cpu0.dcache", "name": "dcache", - "type": "Cache", + "mshrs": 4, "sequential_access": false, "assoc": 4 }, @@ -1995,7 +2011,7 @@ "do_quiesce": true, "type": "TimingSimpleCPU", "profile": 0, - "interrupts": null, + "interrupts": [], "socket_id": 0, "max_insts_all_threads": 0, "path": "system.cpu1", @@ -2593,7 +2609,7 @@ "eventq_index": 0, "type": "DerivO3CPU", "wbWidth": 8, - "interrupts": null, + "interrupts": [], "smtCommitPolicy": "RoundRobin", "issueToExecuteDelay": 1, "dtb": { @@ -2644,6 +2660,7 @@ "path": "system.intrctrl", "type": "IntrControl" }, + "multi_thread": false, "work_begin_ckpt_count": 0, "work_begin_cpu_id_exit": -1, "work_item_id": -1, diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index fb8fdc7fa..30a665fe2 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -3,17 +3,9 @@ warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. -warn: x86 cpuid: unknown family 0xbacc -warn: x86 cpuid: unknown family 0xbacc WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 -warn: x86 cpuid: unknown family 0x8086 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -25,17 +17,7 @@ Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 7191, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +Command: 0, Timestamp: 9400, Bank: 5 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -43,33 +25,31 @@ Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 6675, Bank: 2 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +Command: 0, Timestamp: 6996, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 12287, Bank: 1 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 6767, Bank: 1 +Command: 0, Timestamp: 6448, Bank: 4 WARNING: Bank is already active! -Command: 0, Timestamp: 6921, Bank: 6 -WARNING: Bank is already active! -Command: 0, Timestamp: 11289, Bank: 4 -WARNING: Bank is already active! -Command: 0, Timestamp: 7232, Bank: 3 -WARNING: Bank is already active! -Command: 0, Timestamp: 11338, Bank: 4 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +Command: 0, Timestamp: 7603, Bank: 3 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 10369, Bank: 4 +WARNING: Bank is already active! +Command: 0, Timestamp: 9709, Bank: 5 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 7701, Bank: 2 +WARNING: Bank is already active! +Command: 0, Timestamp: 11369, Bank: 1 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -89,17 +69,19 @@ Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: Tried to clear PCI interrupt 14 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 8909, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 6789, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 8215, Bank: 1 +WARNING: Bank is already active! +Command: 0, Timestamp: 8557, Bank: 5 +WARNING: Bank is already active! +Command: 0, Timestamp: 11226, Bank: 4 warn: Unknown mouse command 0xe1. warn: instruction 'wbinvd' unimplemented -WARNING: Bank is already active! -Command: 0, Timestamp: 7075, Bank: 7 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 6474, Bank: 4 -WARNING: Bank is already active! -Command: 0, Timestamp: 6837, Bank: 6 +Command: 0, Timestamp: 7944, Bank: 0 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index 88f772da2..73370e2b3 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 6 2015 14:29:04 -gem5 started Jul 7 2015 09:32:35 -gem5 executing on e104799-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full +gem5 compiled Dec 4 2015 15:10:31 +gem5 started Dec 4 2015 16:03:32 +gem5 executing on e104799-lin, pid 2775 +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index cc30b102c..df59304a0 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.140310 # Number of seconds simulated -sim_ticks 5140310077000 # Number of ticks simulated -final_tick 5140310077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.142345 # Number of seconds simulated +sim_ticks 5142345332000 # Number of ticks simulated +final_tick 5142345332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 193642 # Simulator instruction rate (inst/s) -host_op_rate 384932 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4095276555 # Simulator tick rate (ticks/s) -host_mem_usage 1038092 # Number of bytes of host memory used -host_seconds 1255.18 # Real time elapsed on the host -sim_insts 243055842 # Number of instructions simulated -sim_ops 483158927 # Number of ops (including micro ops) simulated +host_inst_rate 328643 # Simulator instruction rate (inst/s) +host_op_rate 653294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6944434004 # Simulator tick rate (ticks/s) +host_mem_usage 993680 # Number of bytes of host memory used +host_seconds 740.50 # Real time elapsed on the host +sim_insts 243359937 # Number of instructions simulated +sim_ops 483763631 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 444160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5333440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 157504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1822656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 355968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3200064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 463872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5043712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 148160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2254656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 338432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3039936 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11344576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 444160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 157504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 355968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 957632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9154432 # Number of bytes written to this memory -system.physmem.bytes_written::total 9154432 # Number of bytes written to this memory +system.physmem.bytes_read::total 11319616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 463872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 148160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 338432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 950464 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9139904 # Number of bytes written to this memory +system.physmem.bytes_written::total 9139904 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6940 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 83335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2461 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 28479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 33 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5562 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 50001 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7248 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 78808 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2315 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 35229 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 34 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5288 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 47499 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 177259 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143038 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143038 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176869 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142811 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142811 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 86407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1037572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 30641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 354581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 69250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 622543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2206983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 86407 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 30641 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 69250 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 186298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1780910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1780910 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1780910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 90206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 980819 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 28812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 438449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 65813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 591157 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2201256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 90206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 28812 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 65813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 184831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1777380 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1777380 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1777380 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 86407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1037572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 30641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 354581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 69250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 622543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3987893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 86979 # Number of read requests accepted -system.physmem.writeReqs 83143 # Number of write requests accepted -system.physmem.readBursts 86979 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83143 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5559296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 5321152 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5566656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5321152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 90206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 980819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 28812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 438449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 65813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 591157 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3978636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 90808 # Number of read requests accepted +system.physmem.writeReqs 80864 # Number of write requests accepted +system.physmem.readBursts 90808 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 80864 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5799936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11776 # Total number of bytes read from write queue +system.physmem.bytesWritten 5173504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5811712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5175296 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 184 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 33940 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5203 # Per bank write bursts -system.physmem.perBankRdBursts::1 4657 # Per bank write bursts -system.physmem.perBankRdBursts::2 5413 # Per bank write bursts -system.physmem.perBankRdBursts::3 5303 # Per bank write bursts -system.physmem.perBankRdBursts::4 5134 # Per bank write bursts -system.physmem.perBankRdBursts::5 4786 # Per bank write bursts -system.physmem.perBankRdBursts::6 5593 # Per bank write bursts -system.physmem.perBankRdBursts::7 5448 # Per bank write bursts -system.physmem.perBankRdBursts::8 5260 # Per bank write bursts -system.physmem.perBankRdBursts::9 4897 # Per bank write bursts -system.physmem.perBankRdBursts::10 5208 # Per bank write bursts -system.physmem.perBankRdBursts::11 5207 # Per bank write bursts -system.physmem.perBankRdBursts::12 5484 # Per bank write bursts -system.physmem.perBankRdBursts::13 6574 # Per bank write bursts -system.physmem.perBankRdBursts::14 6603 # Per bank write bursts -system.physmem.perBankRdBursts::15 6094 # Per bank write bursts -system.physmem.perBankWrBursts::0 5594 # Per bank write bursts -system.physmem.perBankWrBursts::1 5124 # Per bank write bursts -system.physmem.perBankWrBursts::2 5270 # Per bank write bursts -system.physmem.perBankWrBursts::3 4838 # Per bank write bursts -system.physmem.perBankWrBursts::4 5433 # Per bank write bursts -system.physmem.perBankWrBursts::5 5211 # Per bank write bursts -system.physmem.perBankWrBursts::6 5102 # Per bank write bursts -system.physmem.perBankWrBursts::7 5101 # Per bank write bursts -system.physmem.perBankWrBursts::8 5096 # Per bank write bursts -system.physmem.perBankWrBursts::9 5186 # Per bank write bursts -system.physmem.perBankWrBursts::10 5320 # Per bank write bursts -system.physmem.perBankWrBursts::11 5088 # Per bank write bursts -system.physmem.perBankWrBursts::12 4612 # Per bank write bursts -system.physmem.perBankWrBursts::13 5363 # Per bank write bursts -system.physmem.perBankWrBursts::14 5353 # Per bank write bursts -system.physmem.perBankWrBursts::15 5452 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 28946 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5471 # Per bank write bursts +system.physmem.perBankRdBursts::1 4964 # Per bank write bursts +system.physmem.perBankRdBursts::2 5622 # Per bank write bursts +system.physmem.perBankRdBursts::3 5619 # Per bank write bursts +system.physmem.perBankRdBursts::4 5375 # Per bank write bursts +system.physmem.perBankRdBursts::5 4811 # Per bank write bursts +system.physmem.perBankRdBursts::6 5429 # Per bank write bursts +system.physmem.perBankRdBursts::7 5659 # Per bank write bursts +system.physmem.perBankRdBursts::8 5571 # Per bank write bursts +system.physmem.perBankRdBursts::9 5234 # Per bank write bursts +system.physmem.perBankRdBursts::10 5583 # Per bank write bursts +system.physmem.perBankRdBursts::11 5583 # Per bank write bursts +system.physmem.perBankRdBursts::12 6015 # Per bank write bursts +system.physmem.perBankRdBursts::13 6427 # Per bank write bursts +system.physmem.perBankRdBursts::14 6843 # Per bank write bursts +system.physmem.perBankRdBursts::15 6418 # Per bank write bursts +system.physmem.perBankWrBursts::0 5328 # Per bank write bursts +system.physmem.perBankWrBursts::1 5179 # Per bank write bursts +system.physmem.perBankWrBursts::2 4756 # Per bank write bursts +system.physmem.perBankWrBursts::3 4771 # Per bank write bursts +system.physmem.perBankWrBursts::4 5274 # Per bank write bursts +system.physmem.perBankWrBursts::5 4797 # Per bank write bursts +system.physmem.perBankWrBursts::6 4981 # Per bank write bursts +system.physmem.perBankWrBursts::7 4962 # Per bank write bursts +system.physmem.perBankWrBursts::8 4826 # Per bank write bursts +system.physmem.perBankWrBursts::9 4673 # Per bank write bursts +system.physmem.perBankWrBursts::10 4967 # Per bank write bursts +system.physmem.perBankWrBursts::11 4883 # Per bank write bursts +system.physmem.perBankWrBursts::12 5134 # Per bank write bursts +system.physmem.perBankWrBursts::13 5204 # Per bank write bursts +system.physmem.perBankWrBursts::14 5383 # Per bank write bursts +system.physmem.perBankWrBursts::15 5718 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 5136428721000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 5141345197000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 86979 # Read request sizes (log2) +system.physmem.readPktSize::6 90808 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83143 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 81214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 80864 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see @@ -161,1117 +161,1109 @@ system.physmem.rdQLenPdf::28 0 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39730 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 273.859753 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.661250 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 301.445638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16103 40.53% 40.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9824 24.73% 65.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4113 10.35% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2266 5.70% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1547 3.89% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1072 2.70% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 721 1.81% 89.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 578 1.45% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3506 8.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39730 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.613337 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 232.441160 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4016 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 69 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40174 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 273.144621 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.560811 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 297.725081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16113 40.11% 40.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9912 24.67% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4303 10.71% 75.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2413 6.01% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1642 4.09% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1065 2.65% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 735 1.83% 90.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 648 1.61% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3343 8.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40174 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4096 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.121094 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 231.669266 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4094 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.687484 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.141176 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.818199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 66 1.64% 1.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 4 0.10% 1.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.02% 1.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.12% 1.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3291 81.89% 83.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 104 2.59% 86.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 32 0.80% 87.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 108 2.69% 89.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 15 0.37% 90.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 105 2.61% 92.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 59 1.47% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 4 0.10% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 14 0.35% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 20 0.50% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.05% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.10% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 144 3.58% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.10% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 15 0.37% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.07% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.25% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads -system.physmem.totQLat 1059562475 # Total ticks spent queuing -system.physmem.totMemAccLat 2688262475 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 434320000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12197.95 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4096 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4096 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.735352 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.630791 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.122766 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 68 1.66% 1.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 3 0.07% 1.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.02% 1.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.12% 1.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3465 84.59% 86.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 91 2.22% 88.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 32 0.78% 89.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 114 2.78% 92.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 13 0.32% 92.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 74 1.81% 94.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 48 1.17% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.07% 95.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.32% 95.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.24% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.17% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.05% 96.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 111 2.71% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.10% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.05% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 16 0.39% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.07% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.15% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4096 # Writes before turning the bus around for reads +system.physmem.totQLat 1084591495 # Total ticks spent queuing +system.physmem.totMemAccLat 2783791495 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 453120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11968.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30947.95 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.08 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.08 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30718.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.13 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 6.40 # Average write queue length when enqueuing -system.physmem.readRowHits 68770 # Number of row buffer hits during reads -system.physmem.writeRowHits 61507 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.98 # Row buffer hit rate for writes -system.physmem.avgGap 30192618.95 # Average gap between requests -system.physmem.pageHitRate 76.63 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 145673640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 79307250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 323988600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 270041040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96324881400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2240107908000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2587635213210 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.890753 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3686018034728 # Time in different power states -system.physmem_0.memoryStateTime::REF 128007880000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 7.79 # Average write queue length when enqueuing +system.physmem.readRowHits 72353 # Number of row buffer hits during reads +system.physmem.writeRowHits 58932 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.88 # Row buffer hit rate for writes +system.physmem.avgGap 29948653.23 # Average gap between requests +system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 144214560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 78573000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 335010000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 259511040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250484108160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96378538635 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2237986517250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2585666472645 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.978665 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3687486057488 # Time in different power states +system.physmem_0.memoryStateTime::REF 128059360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 19864390272 # Time in different power states +system.physmem_0.memoryStateTime::ACT 19884905262 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 154685160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 84187125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 353550600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 268725600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96580278450 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2233317414750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2581142254965 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.102097 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3685663172228 # Time in different power states -system.physmem_1.memoryStateTime::REF 128007880000 # Time in different power states +system.physmem_1.actEnergy 159500880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 86876625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 371841600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 264306240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250484108160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 97163933940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2232534954750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2581065522195 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.160201 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3686335779224 # Time in different power states +system.physmem_1.memoryStateTime::REF 128059360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 20186348022 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21009267026 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1072285093 # number of cpu cycles simulated +system.cpu0.numCycles 1088115959 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.committedInsts 71949472 # Number of instructions committed -system.cpu0.committedOps 146629560 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134558000 # Number of integer alu accesses +system.cpu0.committedInsts 71651877 # Number of instructions committed +system.cpu0.committedOps 146177129 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134125177 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 963710 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14252688 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134558000 # number of integer instructions +system.cpu0.num_func_calls 958449 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14231951 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134125177 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 246915381 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115616486 # number of times the integer registers were written +system.cpu0.num_int_register_reads 245781224 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115362346 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83804950 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55920138 # number of times the CC registers were written -system.cpu0.num_mem_refs 13826864 # number of memory refs -system.cpu0.num_load_insts 10217566 # Number of load instructions -system.cpu0.num_store_insts 3609298 # Number of store instructions -system.cpu0.num_idle_cycles 1017808343.518800 # Number of idle cycles -system.cpu0.num_busy_cycles 54476749.481200 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050804 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949196 # Percentage of idle cycles -system.cpu0.Branches 15573120 # Number of branches fetched -system.cpu0.op_class::No_OpClass 93861 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 132602488 90.43% 90.50% # Class of executed instruction -system.cpu0.op_class::IntMult 58992 0.04% 90.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 49734 0.03% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.57% # Class of executed instruction -system.cpu0.op_class::MemRead 10215736 6.97% 97.54% # Class of executed instruction -system.cpu0.op_class::MemWrite 3609298 2.46% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83627387 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55829285 # number of times the CC registers were written +system.cpu0.num_mem_refs 13623500 # number of memory refs +system.cpu0.num_load_insts 10168797 # Number of load instructions +system.cpu0.num_store_insts 3454703 # Number of store instructions +system.cpu0.num_idle_cycles 1031530406.657702 # Number of idle cycles +system.cpu0.num_busy_cycles 56585552.342298 # Number of busy cycles +system.cpu0.not_idle_fraction 0.052003 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.947997 # Percentage of idle cycles +system.cpu0.Branches 15545637 # Number of branches fetched +system.cpu0.op_class::No_OpClass 91075 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 132356346 90.54% 90.61% # Class of executed instruction +system.cpu0.op_class::IntMult 58823 0.04% 90.65% # Class of executed instruction +system.cpu0.op_class::IntDiv 49650 0.03% 90.68% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.68% # Class of executed instruction +system.cpu0.op_class::MemRead 10166974 6.96% 97.64% # Class of executed instruction +system.cpu0.op_class::MemWrite 3454703 2.36% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146630109 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1637608 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999082 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19599059 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1638120 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.964361 # Average number of references to valid blocks. +system.cpu0.op_class::total 146177571 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1639042 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999458 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19611882 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1639554 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.961718 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.195835 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 211.604713 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 116.198534 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.359757 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.413290 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.226950 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999998 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 186.987910 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 208.755532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 116.256017 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.365211 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.407726 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.227063 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 241 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 250 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 215 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88196204 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88196204 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4977443 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2399002 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4079601 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11456046 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3466928 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1632244 # 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number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 53517 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99664 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 153181 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58722 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 186898 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 245620 # number of SoftPFReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 206874 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 521102 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 727976 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 265596 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 708000 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 973596 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 176326 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 193522 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 369848 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3494 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2876 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 6370 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 179820 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 196398 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 376218 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2091939500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 6052493500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8144433000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3446784995 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5707366401 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9154151396 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 1012257500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2960769500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3973027000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 5538724495 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11759859901 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 17298584396 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6550981995 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 14720629401 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 21271611396 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30675451000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32998770000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63674221000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 673827500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 612008500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1285836000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31349278500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33610778500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64960057000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060083 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086629 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045028 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031715 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031989 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018218 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.857969 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.855498 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.527019 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048793 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065297 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034382 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061648 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086352 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.044992 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13640.978240 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14361.527674 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14169.282962 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 64405.422483 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57266.078032 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59760.357982 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17238.130513 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15841.632869 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16175.502809 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26773.420029 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22567.289899 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23762.575134 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24665.213313 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20791.849436 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21848.499168 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173970.095165 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170516.892136 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172163.215699 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192852.747567 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212798.504868 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201858.084772 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174336.995329 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171136.052811 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172665.999500 # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 358190 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 358260 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1746 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 33668 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 35414 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1816 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 391858 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 393674 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1816 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 391858 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 393674 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 158773 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 421604 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 580377 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62735 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 103680 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 166415 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 59778 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 188477 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 248255 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 221508 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 525284 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 746792 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 281286 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 713761 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 995047 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 176153 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 193877 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 370030 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3295 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 3452 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 6747 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 179448 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 197329 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 376777 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2163130500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5958622500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8121753000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4375430996 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5531064377 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9906495373 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 1034307500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2977676500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 4011984000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6538561496 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11489686877 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 18028248373 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7572868996 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 14467363377 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 22040232373 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30638632000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33033633500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63672265500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 639710000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 711714500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1351424500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31278342000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33745348000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65023690000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059966 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087419 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045438 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034238 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.033163 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019789 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.859324 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.856344 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.532877 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.049443 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.066080 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.035255 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061827 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087372 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045964 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13624.045020 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14133.220985 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13993.926362 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 69744.656029 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53347.457340 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59528.860818 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17302.477500 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15798.619991 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16160.737951 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 29518.398866 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21873.285455 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24140.923273 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26922.310374 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20269.198481 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22149.941031 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173931.934171 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170384.488619 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172073.252169 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 194145.675266 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 206174.536501 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200300.059286 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174303.096162 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171010.586381 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172578.713669 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 862096 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.743965 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129388053 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 862608 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 149.996352 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149036221500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.474426 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 126.886783 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 237.382757 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.286083 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.247826 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.463638 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997547 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 863213 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.772348 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129563028 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 863725 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13958.951644 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13915.111257 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 863213 # number of writebacks +system.cpu0.icache.writebacks::total 863213 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 25359 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 25359 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 25359 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 25359 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 25359 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 25359 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 169918 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 389608 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 559526 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 169918 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 389608 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 559526 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 169918 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 389608 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 559526 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2318697500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5380005477 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7698702977 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2318697500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5380005477 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7698702977 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2318697500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5380005477 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7698702977 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004307 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114860 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004289 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004307 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114860 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004289 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004307 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114860 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004289 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13645.979237 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13808.765418 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13759.330178 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13645.979237 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13808.765418 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13759.330178 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13645.979237 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13808.765418 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13759.330178 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606017773 # number of cpu cycles simulated +system.cpu1.numCycles 2608019031 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 35434857 # Number of instructions committed -system.cpu1.committedOps 68967174 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 63950727 # Number of integer alu accesses +system.cpu1.committedInsts 35872545 # Number of instructions committed +system.cpu1.committedOps 69699402 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64677814 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 471160 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6540311 # number of instructions that are conditional controls -system.cpu1.num_int_insts 63950727 # number of integer instructions +system.cpu1.num_func_calls 478121 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6602854 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64677814 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 118144335 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55187205 # number of times the integer registers were written +system.cpu1.num_int_register_reads 119785728 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55703367 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36132607 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26987111 # number of times the CC registers were written -system.cpu1.num_mem_refs 4484202 # number of memory refs -system.cpu1.num_load_insts 2795233 # Number of load instructions -system.cpu1.num_store_insts 1688969 # Number of store instructions -system.cpu1.num_idle_cycles 2475079638.158952 # Number of idle cycles -system.cpu1.num_busy_cycles 130938134.841048 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050245 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949755 # Percentage of idle cycles -system.cpu1.Branches 7181922 # Number of branches fetched -system.cpu1.op_class::No_OpClass 31577 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64399053 93.38% 93.42% # Class of executed instruction -system.cpu1.op_class::IntMult 30119 0.04% 93.47% # Class of executed instruction -system.cpu1.op_class::IntDiv 23752 0.03% 93.50% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::MemRead 2793873 4.05% 97.55% # Class of executed instruction -system.cpu1.op_class::MemWrite 1688969 2.45% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36592003 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27221835 # number of times the CC registers were written +system.cpu1.num_mem_refs 4725252 # number of memory refs +system.cpu1.num_load_insts 2891470 # Number of load instructions +system.cpu1.num_store_insts 1833782 # Number of store instructions +system.cpu1.num_idle_cycles 2475574417.457654 # Number of idle cycles +system.cpu1.num_busy_cycles 132444613.542345 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050784 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949216 # Percentage of idle cycles +system.cpu1.Branches 7256649 # Number of branches fetched +system.cpu1.op_class::No_OpClass 36799 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64882747 93.09% 93.14% # Class of executed instruction +system.cpu1.op_class::IntMult 30615 0.04% 93.19% # Class of executed instruction +system.cpu1.op_class::IntDiv 25662 0.04% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.22% # Class of executed instruction +system.cpu1.op_class::MemRead 2890134 4.15% 97.37% # Class of executed instruction +system.cpu1.op_class::MemWrite 1833782 2.63% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 68967343 # Class of executed instruction -system.cpu2.branchPred.lookups 28923833 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28923833 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 299320 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26177104 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25594852 # Number of BTB hits +system.cpu1.op_class::total 69699739 # Class of executed instruction +system.cpu2.branchPred.lookups 28904699 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28904699 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 301799 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26182960 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25618019 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.775720 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 576883 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63148 # Number of incorrect RAS predictions. -system.cpu2.numCycles 157005173 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.842333 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 577766 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 65377 # Number of incorrect RAS predictions. +system.cpu2.numCycles 157028917 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10541640 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142873863 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28923833 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26171735 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 144747848 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 631807 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 102981 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10810 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 7821 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 69710 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 26 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1766 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3423471 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 155018 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2920 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 155797854 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.805083 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.007319 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10756065 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142934226 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28904699 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26195785 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 144559167 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 634442 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 102497 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 11445 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 9293 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 61170 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 12 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1572 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3392030 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 159049 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2822 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 155817791 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.805701 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.007704 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 100986987 64.82% 64.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 876917 0.56% 65.38% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23450339 15.05% 80.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 581596 0.37% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 798015 0.51% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 839359 0.54% 81.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 536249 0.34% 82.20% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 727748 0.47% 82.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27000644 17.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 100969926 64.80% 64.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 864181 0.55% 65.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23515186 15.09% 80.45% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 574321 0.37% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 784323 0.50% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 832797 0.53% 81.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 526849 0.34% 82.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 721182 0.46% 82.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27029026 17.35% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 155797854 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.184222 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.909995 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9166837 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 95859954 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 22256485 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 3994112 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 316555 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278482972 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 316555 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10781931 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 77376747 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5125883 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 24368379 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 13624506 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277324695 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 194123 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5339465 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 70652 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 6671965 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 331399724 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 605057293 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371622887 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 206 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 320041085 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11358639 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 162877 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 164126 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 19798687 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6564509 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3714734 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 445796 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 396085 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275510749 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 407738 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273563069 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 95252 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8356294 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12697185 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 62746 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 155797854 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.755885 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.385565 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 155817791 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.184072 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.910241 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9372643 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95636804 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 20963245 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4000269 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 317872 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278646605 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 317872 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10991831 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77276692 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5181011 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 23079329 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 13444163 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277492076 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 194116 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5314185 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 68849 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 6513408 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 331462631 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605120715 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 371802312 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 234 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320362920 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11099709 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 163935 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 165202 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 19836823 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6505105 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3734190 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 446981 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 391369 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275686580 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 411981 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273842853 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 94839 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8211456 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12322633 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 64605 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 155817791 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.757456 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.386043 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 93882941 60.26% 60.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5118927 3.29% 63.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3721264 2.39% 65.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3253797 2.09% 68.02% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 23197295 14.89% 82.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2207034 1.42% 84.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23724652 15.23% 99.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 467591 0.30% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 224353 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 93841974 60.23% 60.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5140662 3.30% 63.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3701702 2.38% 65.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3241767 2.08% 67.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 23231728 14.91% 82.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2206356 1.42% 84.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23779364 15.26% 99.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 455294 0.29% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 218944 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 155797854 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 155817791 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1207723 81.78% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 207267 14.03% 95.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 61876 4.19% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1209883 81.76% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.76% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 208644 14.10% 95.86% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 61248 4.14% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 77671 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 263072310 96.17% 96.19% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 56421 0.02% 96.21% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50248 0.02% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 74 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6863613 2.51% 98.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3442732 1.26% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 74059 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263387979 96.18% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 56208 0.02% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 48343 0.02% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 104 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6817856 2.49% 98.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3458304 1.26% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273563069 # Type of FU issued -system.cpu2.iq.rate 1.742383 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1476866 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.005399 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 704495801 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 284279079 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272064636 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 309 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274962115 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 149 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 723478 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 273842853 # Type of FU issued +system.cpu2.iq.rate 1.743901 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1479775 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.005404 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 705077754 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 284314372 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272343231 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 356 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 332 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 144 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 275248392 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 177 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 717023 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1134849 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 5659 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5111 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 595348 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1119882 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5658 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5248 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 603569 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 712058 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 23525 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 712184 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 25029 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 316555 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 69932049 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 4483827 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 275918487 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 35063 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6564509 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3714734 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 243249 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 162438 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4010481 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5111 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 167096 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 181001 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 348097 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273015158 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6728091 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 497866 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 317872 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 69999671 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 4334406 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 276098561 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 36227 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6505105 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3734190 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 245180 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 161697 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3862519 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5248 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 168896 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 180792 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 349688 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273296807 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6682967 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 496833 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10090158 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27708578 # Number of branches executed -system.cpu2.iew.exec_stores 3362067 # Number of stores executed -system.cpu2.iew.exec_rate 1.738893 # Inst execution rate -system.cpu2.iew.wb_sent 272843265 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272064754 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212267822 # num instructions producing a value -system.cpu2.iew.wb_consumers 348193993 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.732839 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609625 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 8353767 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 344992 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 303032 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 154549869 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.731235 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.636337 # Number of insts commited each cycle +system.cpu2.iew.exec_refs 10058933 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27720177 # Number of branches executed +system.cpu2.iew.exec_stores 3375966 # Number of stores executed +system.cpu2.iew.exec_rate 1.740423 # Inst execution rate +system.cpu2.iew.wb_sent 273120714 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272343375 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212424693 # num instructions producing a value +system.cpu2.iew.wb_consumers 348436865 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.734352 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609650 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 8207919 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 347376 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 304652 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 154587808 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.732912 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.636931 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 97453895 63.06% 63.06% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4255487 2.75% 65.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1275451 0.83% 66.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24388605 15.78% 82.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 953115 0.62% 83.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 708142 0.46% 83.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 433200 0.28% 83.77% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23018173 14.89% 98.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2063801 1.34% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 97422616 63.02% 63.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4263028 2.76% 65.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1258481 0.81% 66.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24441508 15.81% 82.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 948995 0.61% 83.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 702646 0.45% 83.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 422583 0.27% 83.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23085730 14.93% 98.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2042221 1.32% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 154549869 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135671513 # Number of instructions committed -system.cpu2.commit.committedOps 267562193 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 154587808 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135835515 # Number of instructions committed +system.cpu2.commit.committedOps 267887100 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8549046 # Number of memory references committed -system.cpu2.commit.loads 5429660 # Number of loads committed -system.cpu2.commit.membars 149565 # Number of memory barriers committed -system.cpu2.commit.branches 27339925 # Number of branches committed +system.cpu2.commit.refs 8515843 # Number of memory references committed +system.cpu2.commit.loads 5385222 # Number of loads committed +system.cpu2.commit.membars 151391 # Number of memory barriers committed +system.cpu2.commit.branches 27354284 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244518367 # Number of committed integer instructions. -system.cpu2.commit.function_calls 438140 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 46308 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 258864003 96.75% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 54521 0.02% 96.79% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 48349 0.02% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5429610 2.03% 98.83% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3119386 1.17% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 244770291 # Number of committed integer instructions. +system.cpu2.commit.function_calls 437535 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 44208 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 259226210 96.77% 96.78% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 54262 0.02% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 46624 0.02% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.82% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5385159 2.01% 98.83% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3130621 1.17% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 267562193 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2063801 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 428372162 # The number of ROB reads -system.cpu2.rob.rob_writes 553085882 # The number of ROB writes -system.cpu2.timesIdled 112358 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1207319 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4910585893 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135671513 # Number of Instructions Simulated -system.cpu2.committedOps 267562193 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.157245 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.157245 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.864121 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.864121 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 363757841 # number of integer regfile reads -system.cpu2.int_regfile_writes 218039219 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73086 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138801079 # number of cc regfile reads -system.cpu2.cc_regfile_writes 106740366 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88776769 # number of misc regfile reads -system.cpu2.misc_regfile_writes 143860 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3545348 # Transaction distribution -system.iobus.trans_dist::ReadResp 3545348 # Transaction distribution -system.iobus.trans_dist::WriteReq 57726 # Transaction distribution -system.iobus.trans_dist::WriteResp 57726 # Transaction distribution -system.iobus.trans_dist::MessageReq 1644 # Transaction distribution -system.iobus.trans_dist::MessageResp 1644 # Transaction distribution +system.cpu2.commit.op_class_0::total 267887100 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2042221 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 428611967 # The number of ROB reads +system.cpu2.rob.rob_writes 553425779 # The number of ROB writes +system.cpu2.timesIdled 117856 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1211126 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4911627157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135835515 # Number of Instructions Simulated +system.cpu2.committedOps 267887100 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.156023 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.156023 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.865035 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.865035 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 364164831 # number of integer regfile reads +system.cpu2.int_regfile_writes 218212592 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73112 # number of floating regfile reads +system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes +system.cpu2.cc_regfile_reads 138818129 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106823368 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88818544 # number of misc regfile reads +system.cpu2.misc_regfile_writes 142989 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3545369 # Transaction distribution +system.iobus.trans_dist::ReadResp 3545369 # Transaction distribution +system.iobus.trans_dist::WriteReq 57733 # Transaction distribution +system.iobus.trans_dist::WriteResp 57733 # Transaction distribution +system.iobus.trans_dist::MessageReq 1667 # Transaction distribution +system.iobus.trans_dist::MessageResp 1667 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7066648 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7066646 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1182 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27866 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7110880 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7209436 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7110938 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3334 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3334 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7209538 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3533324 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3533323 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2364 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13933 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3561720 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6596152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2378420 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 3561710 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6668 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6668 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6596226 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2386632 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 41000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 5416500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 6479000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 921000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 921000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 40500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 21000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 199976000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 199977500 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 478500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 507000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 170000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11026500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11054500 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 117264991 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 144387481 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1060500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1052000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 283491000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 284201000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 31080000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 25798000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 979000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 987000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47579 # number of replacements -system.iocache.tags.tagsinuse 0.099877 # Cycle average of tags in use +system.iocache.tags.replacements 47578 # number of replacements +system.iocache.tags.tagsinuse 0.106179 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47594 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000697713509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.099877 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006242 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006242 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000689447509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.106179 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006636 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006636 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428706 # Number of tag accesses -system.iocache.tags.data_accesses 428706 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses -system.iocache.ReadReq_misses::total 914 # number of ReadReq misses +system.iocache.tags.tag_accesses 428697 # Number of tag accesses +system.iocache.tags.data_accesses 428697 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 913 # number of ReadReq misses +system.iocache.ReadReq_misses::total 913 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses -system.iocache.demand_misses::total 914 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses -system.iocache.overall_misses::total 914 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126880776 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 126880776 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3631478705 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 3631478705 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 126880776 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 126880776 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 126880776 # number of overall miss cycles -system.iocache.overall_miss_latency::total 126880776 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 913 # number of demand (read+write) misses +system.iocache.demand_misses::total 913 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 913 # number of overall misses +system.iocache.overall_misses::total 913 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126475754 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 126475754 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2945894237 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2945894237 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 126475754 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 126475754 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 126475754 # number of overall miss cycles +system.iocache.overall_miss_latency::total 126475754 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 913 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 913 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 913 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 913 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 913 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1280,327 +1272,327 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138819.229759 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 138819.229759 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 77728.568172 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 77728.568172 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138819.229759 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 138819.229759 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138819.229759 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 138819.229759 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 769 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138527.660460 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 138527.660460 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 63054.243086 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 63054.243086 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138527.660460 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 138527.660460 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138527.660460 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 138527.660460 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 657 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 71 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 59 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.830986 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.135593 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 756 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 756 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 27936 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 27936 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 756 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 756 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 756 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 756 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89080776 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 89080776 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 2234678705 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2234678705 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 89080776 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 89080776 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 89080776 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 89080776 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.827133 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.597945 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.597945 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.827133 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.827133 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117831.714286 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79992.794423 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79992.794423 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 117831.714286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 117831.714286 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 755 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 755 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 22656 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 22656 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 755 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 755 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 755 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 755 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88725754 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88725754 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1813094237 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1813094237 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88725754 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 88725754 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88725754 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 88725754 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.826944 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.826944 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.484932 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.484932 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.826944 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.826944 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.826944 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.826944 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117517.554967 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 80027.111450 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80027.111450 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 117517.554967 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 117517.554967 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104623 # number of replacements -system.l2c.tags.tagsinuse 64807.193930 # Cycle average of tags in use -system.l2c.tags.total_refs 4639141 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168699 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 27.499517 # Average number of references to valid blocks. +system.l2c.tags.replacements 104233 # number of replacements +system.l2c.tags.tagsinuse 64807.184468 # Cycle average of tags in use +system.l2c.tags.total_refs 4648895 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168429 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.601512 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51005.580247 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.135096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1646.367272 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4933.030076 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 515.170725 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1886.196797 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.248761 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 884.127622 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3927.337333 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.778283 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50959.111320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.136263 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1606.978228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4944.954504 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 496.939087 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1891.921055 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.257150 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 951.270746 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3946.616114 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.777574 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.025122 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075272 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007861 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.028781 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.024521 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075454 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.007583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.028868 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.013491 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.059926 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.014515 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.060221 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.988879 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64076 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2840 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6926 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54004 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.977722 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 41427151 # Number of tag accesses -system.l2c.tags.data_accesses 41427151 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20684 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10937 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10806 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5737 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 57444 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 12625 # number of ReadReq hits -system.l2c.ReadReq_hits::total 118233 # number of ReadReq hits +system.l2c.tags.occ_task_id_blocks::1024 64196 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 668 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3069 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5065 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55320 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.979553 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 41479817 # Number of tag accesses +system.l2c.tags.data_accesses 41479817 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 19668 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10402 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 11752 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6500 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 59100 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 12594 # number of ReadReq hits +system.l2c.ReadReq_hits::total 120016 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.WritebackDirty_hits::writebacks 1548069 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 1548069 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 861756 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 861756 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 31 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 115 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 276 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 69082 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 29187 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 61537 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 159806 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 315648 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 161184 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 370798 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 847630 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 512537 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 207468 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 595557 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 1315562 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 20684 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10939 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 315648 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 581619 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10806 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5737 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 161184 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 236655 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 57444 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 12625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 370798 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 657094 # number of demand (read+write) hits -system.l2c.demand_hits::total 2441233 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 20684 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10939 # number of overall hits -system.l2c.overall_hits::cpu0.inst 315648 # number of overall hits -system.l2c.overall_hits::cpu0.data 581619 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10806 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5737 # number of overall hits -system.l2c.overall_hits::cpu1.inst 161184 # number of overall hits -system.l2c.overall_hits::cpu1.data 236655 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 57444 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 12625 # number of overall hits -system.l2c.overall_hits::cpu2.inst 370798 # number of overall hits -system.l2c.overall_hits::cpu2.data 657094 # number of overall hits -system.l2c.overall_hits::total 2441233 # number of overall hits +system.l2c.WritebackDirty_hits::writebacks 1549010 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1549010 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 862717 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 862717 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 97 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 74 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 95 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 266 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 60797 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 31555 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 67417 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 159769 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 296952 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 167603 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 384294 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 848849 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 505674 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 213822 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 597828 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 1317324 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 19668 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10404 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 296952 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 566471 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 11752 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6500 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 167603 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 245377 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 59100 # 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number of overall hits +system.l2c.overall_hits::cpu2.inst 384294 # number of overall hits +system.l2c.overall_hits::cpu2.data 665245 # number of overall hits +system.l2c.overall_hits::total 2445960 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 33 # number of ReadReq misses -system.l2c.ReadReq_misses::total 38 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 707 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 151 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 525 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1383 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 68319 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 24150 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 37538 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130007 # 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number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 467 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 809 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 30766 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 35749 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 66515 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2315 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5288 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 7603 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 4729 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 12206 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 16935 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2315 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 35495 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 34 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5288 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 47955 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 91087 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2315 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 35495 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 34 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5288 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 47955 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 91087 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 176153 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 193877 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 370030 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3295 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 3452 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 6747 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 179448 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 197329 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 376777 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 4679000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 4679000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 24153500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 33128000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 57281500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3613457000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4266576500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7880033500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 278830000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 668925000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 947755000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 575594000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1526186500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 2101780500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 278830000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4189051000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 4679000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 668925000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 5792763000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10934248000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 278830000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4189051000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 4679000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 668925000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 5792763000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10934248000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28436719000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30610149000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59046868000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 601817000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 671983500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1273800500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 29038536000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31282132500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60320668500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000575 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.822115 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.830961 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.479834 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.493670 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.346519 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.229774 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.013624 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.013573 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.008803 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021638 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.020009 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.012544 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.013624 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.126374 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000575 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013573 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.067239 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034722 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.013624 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.126374 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000575 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013573 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.067239 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034722 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 137617.647059 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 137617.647059 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70624.269006 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70937.901499 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70805.315204 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117449.684717 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119348.135612 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 118470.021800 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120444.924406 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126498.676248 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124655.399185 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121715.796151 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 125035.761101 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124108.680248 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120444.924406 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 118018.058882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 137617.647059 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126498.676248 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 120795.808571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 120041.806185 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120444.924406 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 118018.058882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 137617.647059 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126498.676248 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 120795.808571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 120041.806185 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161431.931332 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157884.375145 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159573.191363 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182645.523520 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 194664.976825 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 188795.094116 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161821.452454 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158527.801286 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 160096.472184 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5063565 # Transaction distribution -system.membus.trans_dist::ReadResp 5112237 # Transaction distribution -system.membus.trans_dist::WriteReq 13898 # Transaction distribution -system.membus.trans_dist::WriteResp 13898 # Transaction distribution -system.membus.trans_dist::WritebackDirty 143038 # Transaction distribution -system.membus.trans_dist::CleanEvict 8555 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1675 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1675 # Transaction distribution -system.membus.trans_dist::ReadExReq 129715 # Transaction distribution -system.membus.trans_dist::ReadExResp 129715 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 48672 # Transaction distribution -system.membus.trans_dist::MessageReq 1644 # Transaction distribution -system.membus.trans_dist::MessageResp 1644 # Transaction distribution +system.membus.trans_dist::ReadReq 5063475 # Transaction distribution +system.membus.trans_dist::ReadResp 5112044 # Transaction distribution +system.membus.trans_dist::WriteReq 13928 # Transaction distribution +system.membus.trans_dist::WriteResp 13928 # Transaction distribution +system.membus.trans_dist::WritebackDirty 142811 # Transaction distribution +system.membus.trans_dist::CleanEvict 8387 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1702 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1702 # Transaction distribution +system.membus.trans_dist::ReadExReq 129429 # Transaction distribution +system.membus.trans_dist::ReadExResp 129429 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 48569 # Transaction distribution +system.membus.trans_dist::MessageReq 1667 # Transaction distribution +system.membus.trans_dist::MessageResp 1667 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044046 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 462505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10617431 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10762706 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6088089 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17503808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27153617 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3334 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3334 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110938 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3043868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 461232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10616038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10761354 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6668 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6668 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561710 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6087733 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17454144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27103587 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025152 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3025152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30185345 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 665 # Total snoops (count) -system.membus.snoop_fanout::samples 5458032 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000301 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017353 # Request fanout histogram +system.membus.pkt_size::total 30135407 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 824 # Total snoops (count) +system.membus.snoop_fanout::samples 5457240 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000305 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017475 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5456388 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1644 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5455573 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1667 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5458032 # Request fanout histogram -system.membus.reqLayer0.occupancy 219245500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5457240 # Request fanout histogram +system.membus.reqLayer0.occupancy 220305500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 286800000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 286836500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2376580 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2385368 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 547442853 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 534782231 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1397580 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1398368 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1208317879 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1230215238 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 52360943 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 43264654 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -1820,60 +1812,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.snoop_filter.tot_requests 5045447 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2544703 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1173 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1173 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5045999 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2542699 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 716 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1209 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1209 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 5213999 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7425168 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13900 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13900 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1631215 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 861756 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 94957 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 289813 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 289813 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 862620 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1349075 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 979 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 27936 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2586983 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15072215 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 70159 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 206201 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17935558 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110359232 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213581393 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 258600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 748792 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 324948017 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 226396 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8918852 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.005051 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.070893 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5211020 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7425092 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13930 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13930 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1629876 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 862717 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 95523 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1686 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1686 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 289480 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 289480 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 863740 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1350844 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 987 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 22656 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2590172 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15076396 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 68863 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 204307 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17939738 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110491648 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213734051 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 254408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 750576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 325230683 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 223463 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8879878 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.004588 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.067577 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 8873800 99.49% 99.49% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 45052 0.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 8839140 99.54% 99.54% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 40738 0.46% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8918852 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3217820998 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8879878 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3300004999 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 406876 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 437354 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 810576399 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 839896281 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1832733252 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1865125250 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23881478 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24363482 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 87500568 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 87735122 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal index 898984ead..2e4dba06f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal @@ -29,7 +29,7 @@ Built 1 zonelists. Total pages: 30610 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 2000.005 MHz processor.
+time.c: Detected 2000.003 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@@ -46,7 +46,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812539
+result 7812530
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
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