summaryrefslogtreecommitdiff
path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full
diff options
context:
space:
mode:
authorNilay Vaish <nilay@cs.wisc.edu>2014-10-11 16:18:51 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2014-10-11 16:18:51 -0500
commit1efe42fa97ed03662666cafee1b9dec9dfe524e9 (patch)
treedd35dfa8f257445840ea3afe71ebdce4d8e4030e /tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full
parent8e07b36d2b6c1db8c4196336acc66d16e63f8ff3 (diff)
downloadgem5-1efe42fa97ed03662666cafee1b9dec9dfe524e9.tar.xz
stats: updates due to changes to x86, stale configs.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full')
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini126
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json1148
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt3082
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal12
4 files changed, 2333 insertions, 2035 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
index 925d90ad5..2c304759f 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
@@ -75,7 +75,7 @@ type=Bridge
clk_domain=system.clk_domain
delay=50000
eventq_index=0
-ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
+ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
req_size=16
resp_size=16
master=system.iobus.slave[0]
@@ -114,9 +114,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -353,6 +350,7 @@ do_statistics_insts=true
dtb=system.cpu2.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -405,7 +403,6 @@ switched_out=true
system=system
tracer=system.cpu2.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=
@@ -787,8 +784,8 @@ transition_latency=100000000
[system.e820_table]
type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+children=entries0 entries1 entries2 entries3 entries4
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
eventq_index=0
[system.e820_table.entries0]
@@ -814,6 +811,13 @@ size=133169152
[system.e820_table.entries3]
type=X86E820Entry
+addr=134217728
+eventq_index=0
+range_type=2
+size=3087007744
+
+[system.e820_table.entries4]
+type=X86E820Entry
addr=4294901760
eventq_index=0
range_type=2
@@ -862,13 +866,13 @@ version=17
[system.intel_mp_table.base_entries02]
type=X86IntelMPBus
bus_id=0
-bus_type=ISA
+bus_type=PCI
eventq_index=0
[system.intel_mp_table.base_entries03]
type=X86IntelMPBus
bus_id=1
-bus_type=PCI
+bus_type=ISA
eventq_index=0
[system.intel_mp_table.base_entries04]
@@ -878,7 +882,7 @@ dest_io_apic_intin=16
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=1
+source_bus_id=0
source_bus_irq=16
trigger=ConformTrigger
@@ -889,7 +893,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -900,7 +904,7 @@ dest_io_apic_intin=2
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=0
trigger=ConformTrigger
@@ -911,7 +915,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -922,7 +926,7 @@ dest_io_apic_intin=1
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=1
trigger=ConformTrigger
@@ -933,7 +937,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -944,7 +948,7 @@ dest_io_apic_intin=3
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=3
trigger=ConformTrigger
@@ -955,7 +959,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -966,7 +970,7 @@ dest_io_apic_intin=4
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=4
trigger=ConformTrigger
@@ -977,7 +981,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -988,7 +992,7 @@ dest_io_apic_intin=5
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=5
trigger=ConformTrigger
@@ -999,7 +1003,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -1010,7 +1014,7 @@ dest_io_apic_intin=6
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=6
trigger=ConformTrigger
@@ -1021,7 +1025,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -1032,7 +1036,7 @@ dest_io_apic_intin=7
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=7
trigger=ConformTrigger
@@ -1043,7 +1047,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -1054,7 +1058,7 @@ dest_io_apic_intin=8
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=8
trigger=ConformTrigger
@@ -1065,7 +1069,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -1076,7 +1080,7 @@ dest_io_apic_intin=9
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=9
trigger=ConformTrigger
@@ -1087,7 +1091,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -1098,7 +1102,7 @@ dest_io_apic_intin=10
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=10
trigger=ConformTrigger
@@ -1109,7 +1113,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -1120,7 +1124,7 @@ dest_io_apic_intin=11
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=11
trigger=ConformTrigger
@@ -1131,7 +1135,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -1142,7 +1146,7 @@ dest_io_apic_intin=12
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=12
trigger=ConformTrigger
@@ -1153,7 +1157,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -1164,7 +1168,7 @@ dest_io_apic_intin=13
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=13
trigger=ConformTrigger
@@ -1175,7 +1179,7 @@ dest_io_apic_intin=0
eventq_index=0
interrupt_type=ExtInt
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
@@ -1186,15 +1190,15 @@ dest_io_apic_intin=14
eventq_index=0
interrupt_type=INT
polarity=ConformPolarity
-source_bus_id=0
+source_bus_id=1
source_bus_irq=14
trigger=ConformTrigger
[system.intel_mp_table.ext_entries]
type=X86IntelMPBusHierarchy
-bus_id=0
+bus_id=1
eventq_index=0
-parent_bus=1
+parent_bus=0
subtractive_decode=true
[system.intrctrl]
@@ -1203,7 +1207,7 @@ eventq_index=0
sys=system
[system.iobus]
-type=NoncoherentBus
+type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
@@ -1284,11 +1288,12 @@ sequential_access=false
size=4194304
[system.membus]
-type=CoherentBus
+type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -1533,6 +1538,7 @@ HeaderType=0
InterruptLine=14
InterruptPin=1
LatencyTimer=0
+LegacyIOBase=9223372036854775808
MSICAPBaseOffset=0
MSICAPCapId=0
MSICAPMaskBits=0
@@ -1823,8 +1829,33 @@ pio=system.iobus.master[9]
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -1833,6 +1864,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -1846,19 +1878,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
@@ -1888,10 +1927,11 @@ vendor=
version=
[system.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
index b8b06f12b..3c9f7ff5e 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
@@ -2,39 +2,20 @@
"name": null,
"sim_quantum": 0,
"system": {
- "bridge": {
- "slave": {
- "peer": "system.membus.master[0]",
- "role": "SLAVE"
- },
- "name": "bridge",
- "req_size": 16,
- "delay": 5.0000000000000004e-08,
- "eventq_index": 0,
- "master": {
- "peer": "system.iobus.slave[0]",
- "role": "MASTER"
- },
- "cxx_class": "Bridge",
- "path": "system.bridge",
- "resp_size": 16,
- "type": "Bridge"
- },
+ "kernel": "/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9",
"l2c": {
- "assoc": 8,
- "mem_side": {
- "peer": "system.membus.slave[2]",
- "role": "MASTER"
- },
- "cpu_side": {
- "peer": "system.toL2Bus.master[0]",
- "role": "SLAVE"
- },
- "name": "l2c",
+ "is_top_level": false,
+ "prefetcher": null,
+ "clk_domain": "system.cpu_clk_domain",
+ "write_buffers": 8,
+ "response_latency": 20,
+ "cxx_class": "BaseCache",
+ "size": 4194304,
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 20,
+ "clk_domain": "system.cpu_clk_domain",
"sequential_access": false,
"assoc": 8,
"cxx_class": "LRU",
@@ -43,77 +24,56 @@
"type": "LRU",
"size": 4194304
},
- "hit_latency": 20,
- "mshrs": 20,
- "response_latency": 20,
- "is_top_level": false,
- "tgts_per_mshr": 12,
- "sequential_access": false,
+ "system": "system",
"max_miss_count": 0,
"eventq_index": 0,
+ "mem_side": {
+ "peer": "system.membus.slave[2]",
+ "role": "MASTER"
+ },
+ "mshrs": 20,
+ "forward_snoops": true,
+ "hit_latency": 20,
+ "tgts_per_mshr": 12,
+ "addr_ranges": [
+ "0:18446744073709551615"
+ ],
+ "assoc": 8,
"prefetch_on_access": false,
- "cxx_class": "BaseCache",
"path": "system.l2c",
- "write_buffers": 8,
- "two_queue": false,
+ "name": "l2c",
"type": "BaseCache",
- "forward_snoops": true,
- "size": 4194304
+ "sequential_access": false,
+ "cpu_side": {
+ "peer": "system.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
+ "two_queue": false
},
"kernel_addr_check": true,
- "membus": {
+ "bridge": {
+ "ranges": [
+ "3221225472:4294901760",
+ "9223372036854775808:11529215046068469759",
+ "13835058055282163712:18446744073709551615"
+ ],
"slave": {
- "peer": [
- "system.apicbridge.master",
- "system.system_port",
- "system.l2c.mem_side",
- "system.cpu0.interrupts.int_master",
- "system.iocache.mem_side"
- ],
+ "peer": "system.membus.master[0]",
"role": "SLAVE"
},
- "name": "membus",
- "badaddr_responder": {
- "ret_data8": 255,
- "name": "badaddr_responder",
- "pio": {
- "peer": "system.membus.default",
- "role": "SLAVE"
- },
- "ret_bad_addr": true,
- "pio_latency": 1.0000000000000001e-07,
- "fake_mem": false,
- "pio_size": 8,
- "ret_data32": 4294967295,
- "eventq_index": 0,
- "update_data": false,
- "ret_data64": 18446744073709551615,
- "cxx_class": "IsaFake",
- "path": "system.membus.badaddr_responder",
- "pio_addr": 0,
- "type": "IsaFake",
- "ret_data16": 65535
- },
- "default": {
- "peer": "system.membus.badaddr_responder.pio",
- "role": "MASTER"
- },
- "header_cycles": 1,
- "width": 8,
+ "name": "bridge",
+ "req_size": 16,
+ "clk_domain": "system.clk_domain",
+ "delay": 50000,
"eventq_index": 0,
"master": {
- "peer": [
- "system.bridge.slave",
- "system.cpu0.interrupts.pio",
- "system.cpu0.interrupts.int_slave",
- "system.physmem.port"
- ],
+ "peer": "system.iobus.slave[0]",
"role": "MASTER"
},
- "cxx_class": "CoherentBus",
- "path": "system.membus",
- "type": "CoherentBus",
- "use_default_range": false
+ "cxx_class": "Bridge",
+ "path": "system.bridge",
+ "resp_size": 16,
+ "type": "Bridge"
},
"iobus": {
"slave": {
@@ -129,6 +89,7 @@
"peer": "system.pc.pciconfig.pio",
"role": "MASTER"
},
+ "clk_domain": "system.clk_domain",
"header_cycles": 1,
"width": 8,
"eventq_index": 0,
@@ -156,68 +117,23 @@
],
"role": "MASTER"
},
- "cxx_class": "NoncoherentBus",
+ "cxx_class": "NoncoherentXBar",
"path": "system.iobus",
- "type": "NoncoherentBus",
+ "type": "NoncoherentXBar",
"use_default_range": false
},
- "physmem": [
- {
- "static_frontend_latency": 1e-08,
- "tRFC": 2.6e-07,
- "activation_limit": 4,
- "tWTR": 7.500000000000001e-09,
- "write_low_thresh_perc": 50,
- "channels": 1,
- "write_buffer_size": 64,
- "device_bus_width": 8,
- "write_high_thresh_perc": 85,
- "cxx_class": "DRAMCtrl",
- "null": false,
- "port": {
- "peer": "system.membus.master[3]",
- "role": "SLAVE"
- },
- "in_addr_map": true,
- "tRRD": 6.000000000000001e-09,
- "tRTW": 2.5e-09,
- "max_accesses_per_row": 16,
- "burst_length": 8,
- "tRTP": 7.500000000000001e-09,
- "tWR": 1.5000000000000002e-08,
- "eventq_index": 0,
- "static_backend_latency": 1e-08,
- "banks_per_rank": 8,
- "addr_mapping": "RoRaBaChCo",
- "tRCD": 1.375e-08,
- "type": "DRAMCtrl",
- "min_writes_per_switch": 16,
- "ranks_per_channel": 2,
- "page_policy": "open_adaptive",
- "tCL": 1.375e-08,
- "read_buffer_size": 32,
- "conf_table_reported": true,
- "tCK": 1.25e-09,
- "tRAS": 3.5e-08,
- "tBURST": 5e-09,
- "path": "system.physmem",
- "devices_per_rank": 8,
- "name": "physmem",
- "tXAW": 3.0000000000000004e-08,
- "tREFI": 7.8e-06,
- "mem_sched_policy": "frfcfs",
- "tRP": 1.375e-08,
- "device_rowbuffer_size": 1024
- }
- ],
"apicbridge": {
+ "ranges": [
+ "11529215046068469760:11529215046068473855"
+ ],
"slave": {
"peer": "system.iobus.master[0]",
"role": "SLAVE"
},
"name": "apicbridge",
"req_size": 16,
- "delay": 5.0000000000000004e-08,
+ "clk_domain": "system.clk_domain",
+ "delay": 50000,
"eventq_index": 0,
"master": {
"peer": "system.membus.slave[0]",
@@ -228,23 +144,26 @@
"resp_size": 16,
"type": "Bridge"
},
+ "symbolfile": "",
+ "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh",
"intel_mp_table": {
"oem_table_addr": 0,
"name": "intel_mp_table",
"ext_entries": [
{
- "parent_bus": 1,
+ "parent_bus": 0,
"name": "ext_entries",
"type": "X86IntelMPBusHierarchy",
"subtractive_decode": true,
"eventq_index": 0,
"cxx_class": "X86ISA::IntelMP::BusHierarchy",
"path": "system.intel_mp_table.ext_entries",
- "bus_id": 0
+ "bus_id": 1
}
],
- "spec_rev": 4,
+ "oem_id": "",
"eventq_index": 0,
+ "spec_rev": 4,
"base_entries": [
{
"enable": true,
@@ -273,6 +192,7 @@
"id": 1
},
{
+ "bus_type": "PCI",
"name": "base_entries02",
"type": "X86IntelMPBus",
"eventq_index": 0,
@@ -281,6 +201,7 @@
"bus_id": 0
},
{
+ "bus_type": "ISA",
"name": "base_entries03",
"type": "X86IntelMPBus",
"eventq_index": 0,
@@ -295,7 +216,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 1,
+ "source_bus_id": 0,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 16,
"path": "system.intel_mp_table.base_entries04",
@@ -309,7 +230,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries05",
@@ -323,7 +244,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 2,
"path": "system.intel_mp_table.base_entries06",
@@ -337,7 +258,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries07",
@@ -351,7 +272,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 1,
"path": "system.intel_mp_table.base_entries08",
@@ -365,7 +286,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries09",
@@ -379,7 +300,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 3,
"path": "system.intel_mp_table.base_entries10",
@@ -393,7 +314,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries11",
@@ -407,7 +328,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 4,
"path": "system.intel_mp_table.base_entries12",
@@ -421,7 +342,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries13",
@@ -435,7 +356,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 5,
"path": "system.intel_mp_table.base_entries14",
@@ -449,7 +370,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries15",
@@ -463,7 +384,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 6,
"path": "system.intel_mp_table.base_entries16",
@@ -477,7 +398,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries17",
@@ -491,7 +412,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 7,
"path": "system.intel_mp_table.base_entries18",
@@ -505,7 +426,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries19",
@@ -519,7 +440,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 8,
"path": "system.intel_mp_table.base_entries20",
@@ -533,7 +454,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries21",
@@ -547,7 +468,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 9,
"path": "system.intel_mp_table.base_entries22",
@@ -561,7 +482,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries23",
@@ -575,7 +496,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 10,
"path": "system.intel_mp_table.base_entries24",
@@ -589,7 +510,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries25",
@@ -603,7 +524,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 11,
"path": "system.intel_mp_table.base_entries26",
@@ -617,7 +538,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries27",
@@ -631,7 +552,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 12,
"path": "system.intel_mp_table.base_entries28",
@@ -645,7 +566,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries29",
@@ -659,7 +580,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 13,
"path": "system.intel_mp_table.base_entries30",
@@ -673,7 +594,7 @@
"interrupt_type": "ExtInt",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 0,
"path": "system.intel_mp_table.base_entries31",
@@ -687,7 +608,7 @@
"interrupt_type": "INT",
"trigger": "ConformTrigger",
"eventq_index": 0,
- "source_bus_id": 0,
+ "source_bus_id": 1,
"cxx_class": "X86ISA::IntelMP::IOIntAssignment",
"dest_io_apic_intin": 14,
"path": "system.intel_mp_table.base_entries32",
@@ -699,55 +620,183 @@
"path": "system.intel_mp_table",
"type": "X86IntelMPConfigTable",
"local_apic": 4276092928,
- "oem_table_size": 0
+ "oem_table_size": 0,
+ "product_id": ""
},
"cxx_class": "LinuxX86System",
"load_offset": 0,
- "work_end_ckpt_count": 0,
- "smbios_table": {
- "name": "smbios_table",
- "structures": [
- {
- "major": 0,
- "name": "structures",
- "emb_cont_firmware_major": 0,
- "rom_size": 0,
- "starting_addr_segment": 0,
- "emb_cont_firmware_minor": 0,
- "eventq_index": 0,
- "cxx_class": "X86ISA::SMBios::BiosInformation",
- "path": "system.smbios_table.structures",
- "type": "X86SMBiosBiosInformation",
- "minor": 0
- }
+ "iocache": {
+ "is_top_level": true,
+ "prefetcher": null,
+ "clk_domain": "system.clk_domain",
+ "write_buffers": 8,
+ "response_latency": 50,
+ "cxx_class": "BaseCache",
+ "size": 1024,
+ "tags": {
+ "name": "tags",
+ "eventq_index": 0,
+ "hit_latency": 50,
+ "clk_domain": "system.clk_domain",
+ "sequential_access": false,
+ "assoc": 8,
+ "cxx_class": "LRU",
+ "path": "system.iocache.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "size": 1024
+ },
+ "system": "system",
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "mem_side": {
+ "peer": "system.membus.slave[4]",
+ "role": "MASTER"
+ },
+ "mshrs": 20,
+ "forward_snoops": false,
+ "hit_latency": 50,
+ "tgts_per_mshr": 12,
+ "addr_ranges": [
+ "0:134217727"
],
- "major_version": 2,
- "minor_version": 5,
+ "assoc": 8,
+ "prefetch_on_access": false,
+ "path": "system.iocache",
+ "name": "iocache",
+ "type": "BaseCache",
+ "sequential_access": false,
+ "cpu_side": {
+ "peer": "system.iobus.master[18]",
+ "role": "SLAVE"
+ },
+ "two_queue": false
+ },
+ "intel_mp_pointer": {
+ "imcr_present": true,
+ "name": "intel_mp_pointer",
+ "spec_rev": 4,
"eventq_index": 0,
- "cxx_class": "X86ISA::SMBios::SMBiosTable",
- "path": "system.smbios_table",
- "type": "X86SMBiosSMBiosTable"
+ "cxx_class": "X86ISA::IntelMP::FloatingPointer",
+ "path": "system.intel_mp_pointer",
+ "type": "X86IntelMPFloatingPointer",
+ "default_config": 0
+ },
+ "memories": [
+ "system.physmem"
+ ],
+ "acpi_description_table_pointer": {
+ "name": "acpi_description_table_pointer",
+ "cxx_class": "X86ISA::ACPI::RSDP",
+ "xsdt": {
+ "oem_table_id": "",
+ "name": "xsdt",
+ "entries": [],
+ "creator_revision": 0,
+ "creator_id": "",
+ "oem_id": "",
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::ACPI::XSDT",
+ "path": "system.acpi_description_table_pointer.xsdt",
+ "oem_revision": 0,
+ "type": "X86ACPIXSDT"
+ },
+ "rsdt": null,
+ "eventq_index": 0,
+ "oem_id": "",
+ "path": "system.acpi_description_table_pointer",
+ "type": "X86ACPIRSDP",
+ "revision": 2
},
- "work_begin_ckpt_count": 0,
"clk_domain": {
"name": "clk_domain",
+ "clock": [
+ 1000
+ ],
"init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.clk_domain",
"type": "SrcClockDomain",
"domain_id": -1
},
+ "mem_ranges": [
+ "0:134217727"
+ ],
+ "membus": {
+ "default": {
+ "peer": "system.membus.badaddr_responder.pio",
+ "role": "MASTER"
+ },
+ "slave": {
+ "peer": [
+ "system.apicbridge.master",
+ "system.system_port",
+ "system.l2c.mem_side",
+ "system.cpu0.interrupts.int_master",
+ "system.iocache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "name": "membus",
+ "badaddr_responder": {
+ "system": "system",
+ "ret_data8": 255,
+ "name": "badaddr_responder",
+ "warn_access": "",
+ "pio": {
+ "peer": "system.membus.default",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": true,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": false,
+ "ret_data64": 18446744073709551615,
+ "cxx_class": "IsaFake",
+ "path": "system.membus.badaddr_responder",
+ "pio_addr": 0,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "snoop_filter": null,
+ "clk_domain": "system.clk_domain",
+ "header_cycles": 1,
+ "system": "system",
+ "width": 8,
+ "eventq_index": 0,
+ "master": {
+ "peer": [
+ "system.bridge.slave",
+ "system.cpu0.interrupts.pio",
+ "system.cpu0.interrupts.int_slave",
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "cxx_class": "CoherentXBar",
+ "path": "system.membus",
+ "type": "CoherentXBar",
+ "use_default_range": false
+ },
"pc": {
"fake_com_4": {
+ "system": "system",
"ret_data8": 255,
"name": "fake_com_4",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[16]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
@@ -767,7 +816,10 @@
"role": "SLAVE"
},
"bus": 0,
- "pio_latency": 3.0000000000000004e-08,
+ "pio_latency": 30000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
+ "platform": "system.pc",
"eventq_index": 0,
"cxx_class": "PciConfigAll",
"path": "system.pc.pciconfig",
@@ -776,14 +828,17 @@
"size": 16777216
},
"fake_com_2": {
+ "system": "system",
"ret_data8": 255,
"name": "fake_com_2",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[14]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
@@ -801,12 +856,14 @@
"int_lines": [
{
"name": "int_lines0",
+ "source": "system.pc.south_bridge.pic1.output",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 0,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.io_apic",
"path": "system.pc.south_bridge.int_lines0.sink",
"type": "X86IntSinkPin"
},
@@ -816,12 +873,14 @@
},
{
"name": "int_lines1",
+ "source": "system.pc.south_bridge.pic2.output",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 2,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.pic1",
"path": "system.pc.south_bridge.int_lines1.sink",
"type": "X86IntSinkPin"
},
@@ -831,12 +890,14 @@
},
{
"name": "int_lines2",
+ "source": "system.pc.south_bridge.cmos.int_pin",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 0,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.pic2",
"path": "system.pc.south_bridge.int_lines2.sink",
"type": "X86IntSinkPin"
},
@@ -846,12 +907,14 @@
},
{
"name": "int_lines3",
+ "source": "system.pc.south_bridge.pit.int_pin",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 0,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.pic1",
"path": "system.pc.south_bridge.int_lines3.sink",
"type": "X86IntSinkPin"
},
@@ -861,12 +924,14 @@
},
{
"name": "int_lines4",
+ "source": "system.pc.south_bridge.pit.int_pin",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 2,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.io_apic",
"path": "system.pc.south_bridge.int_lines4.sink",
"type": "X86IntSinkPin"
},
@@ -876,12 +941,14 @@
},
{
"name": "int_lines5",
+ "source": "system.pc.south_bridge.keyboard.keyboard_int_pin",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 1,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.io_apic",
"path": "system.pc.south_bridge.int_lines5.sink",
"type": "X86IntSinkPin"
},
@@ -891,12 +958,14 @@
},
{
"name": "int_lines6",
+ "source": "system.pc.south_bridge.keyboard.mouse_int_pin",
"eventq_index": 0,
"sink": {
"name": "sink",
"number": 12,
"eventq_index": 0,
"cxx_class": "X86ISA::IntSinkPin",
+ "device": "system.pc.south_bridge.io_apic",
"path": "system.pc.south_bridge.int_lines6.sink",
"type": "X86IntSinkPin"
},
@@ -912,14 +981,18 @@
"peer": "system.iobus.master[9]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Speaker",
"path": "system.pc.south_bridge.speaker",
"pio_addr": 9223372036854775905,
- "type": "PcSpeaker"
+ "type": "PcSpeaker",
+ "i8254": "system.pc.south_bridge.pit"
},
"keyboard": {
+ "system": "system",
"command_port": 9223372036854775908,
"name": "keyboard",
"pio": {
@@ -933,7 +1006,8 @@
"name": "mouse_int_pin",
"cxx_class": "X86ISA::IntSourcePin"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"keyboard_int_pin": {
"eventq_index": 0,
"path": "system.pc.south_bridge.keyboard.keyboard_int_pin",
@@ -954,6 +1028,7 @@
"peer": "system.iobus.master[8]",
"role": "SLAVE"
},
+ "pio_latency": 100000,
"int_pin": {
"eventq_index": 0,
"path": "system.pc.south_bridge.pit.int_pin",
@@ -961,7 +1036,8 @@
"name": "int_pin",
"cxx_class": "X86ISA::IntSourcePin"
},
- "pio_latency": 1.0000000000000001e-07,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::I8254",
"path": "system.pc.south_bridge.pit",
@@ -978,9 +1054,12 @@
"peer": "system.iobus.master[10]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "external_int_pic": "system.pc.south_bridge.pic1",
+ "system": "system",
"apic_id": 1,
- "int_latency": 1e-09,
+ "int_latency": 1000,
"eventq_index": 0,
"cxx_class": "X86ISA::I82094AA",
"path": "system.pc.south_bridge.io_apic",
@@ -988,6 +1067,7 @@
"type": "I82094AA"
},
"pic1": {
+ "slave": "system.pc.south_bridge.pic2",
"name": "pic1",
"output": {
"eventq_index": 0,
@@ -1000,7 +1080,9 @@
"peer": "system.iobus.master[6]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"mode": "I8259Master",
"cxx_class": "X86ISA::I8259",
@@ -1009,6 +1091,7 @@
"type": "I8259"
},
"pic2": {
+ "slave": null,
"name": "pic2",
"output": {
"eventq_index": 0,
@@ -1021,7 +1104,9 @@
"peer": "system.iobus.master[7]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"mode": "I8259Slave",
"cxx_class": "X86ISA::I8259",
@@ -1029,13 +1114,16 @@
"pio_addr": 9223372036854775968,
"type": "I8259"
},
+ "platform": "system.pc",
"dma1": {
"name": "dma1",
"pio": {
"peer": "system.iobus.master[2]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::I8237",
"path": "system.pc.south_bridge.dma1",
@@ -1054,7 +1142,9 @@
"MSIXCAPNextCapability": 0,
"PXCAPLinkCtrl": 0,
"Revision": 0,
- "pio_latency": 3.0000000000000004e-08,
+ "LegacyIOBase": 9223372036854775808,
+ "pio_latency": 30000,
+ "platform": "system.pc",
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
@@ -1078,21 +1168,23 @@
"image": {
"read_only": false,
"name": "image",
+ "cxx_class": "CowDiskImage",
+ "eventq_index": 0,
"child": {
"read_only": true,
"name": "child",
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.pc.south_bridge.ide.disks0.image.child",
+ "image_file": "/scratch/nilay/GEM5/system/disks/linux-x86.img",
"type": "RawDiskImage"
},
- "eventq_index": 0,
- "cxx_class": "CowDiskImage",
"path": "system.pc.south_bridge.ide.disks0.image",
- "table_size": 65536,
- "type": "CowDiskImage"
+ "image_file": "",
+ "type": "CowDiskImage",
+ "table_size": 65536
},
- "delay": 1e-06,
+ "delay": 1000000,
"eventq_index": 0,
"cxx_class": "IdeDisk",
"path": "system.pc.south_bridge.ide.disks0",
@@ -1104,21 +1196,23 @@
"image": {
"read_only": false,
"name": "image",
+ "cxx_class": "CowDiskImage",
+ "eventq_index": 0,
"child": {
"read_only": true,
"name": "child",
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.pc.south_bridge.ide.disks1.image.child",
+ "image_file": "/scratch/nilay/GEM5/system/disks/linux-bigswap2.img",
"type": "RawDiskImage"
},
- "eventq_index": 0,
- "cxx_class": "CowDiskImage",
"path": "system.pc.south_bridge.ide.disks1.image",
- "table_size": 65536,
- "type": "CowDiskImage"
+ "image_file": "",
+ "type": "CowDiskImage",
+ "table_size": 65536
},
- "delay": 1e-06,
+ "delay": 1000000,
"eventq_index": 0,
"cxx_class": "IdeDisk",
"path": "system.pc.south_bridge.ide.disks1",
@@ -1157,6 +1251,7 @@
"MinimumGrant": 0,
"Status": 640,
"BAR0Size": 8,
+ "system": "system",
"name": "ide",
"PXCAPNextCapability": 0,
"eventq_index": 0,
@@ -1171,7 +1266,7 @@
"role": "MASTER"
},
"PMCAPCapId": 0,
- "config_latency": 2e-08,
+ "config_latency": 20000,
"BAR1Size": 3,
"pio": {
"peer": "system.iobus.master[3]",
@@ -1180,6 +1275,7 @@
"pci_dev": 4,
"PMCAPCtrlStatus": 0,
"cxx_class": "IdeController",
+ "clk_domain": "system.clk_domain",
"SubsystemVendorID": 0,
"PMCAPBaseOffset": 0,
"config": {
@@ -1203,6 +1299,8 @@
"peer": "system.iobus.master[1]",
"role": "SLAVE"
},
+ "pio_latency": 100000,
+ "time": "Sun Jan 1 00:00:00 2012",
"int_pin": {
"eventq_index": 0,
"path": "system.pc.south_bridge.cmos.int_pin",
@@ -1210,8 +1308,8 @@
"name": "int_pin",
"cxx_class": "X86ISA::IntSourcePin"
},
- "time": "Sun Jan 1 00:00:00 2012",
- "pio_latency": 1.0000000000000001e-07,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Cmos",
"path": "system.pc.south_bridge.cmos",
@@ -1220,14 +1318,17 @@
}
},
"fake_floppy": {
+ "system": "system",
"ret_data8": 255,
"name": "fake_floppy",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[17]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 2,
"ret_data32": 4294967295,
@@ -1240,23 +1341,29 @@
"type": "IsaFake",
"ret_data16": 65535
},
+ "system": "system",
+ "intrctrl": "system.intrctrl",
"com_1": {
"name": "com_1",
"pio": {
"peer": "system.iobus.master[13]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
+ "system": "system",
"terminal": {
"name": "terminal",
"output": true,
"number": 0,
+ "intr_control": "system.intrctrl",
"eventq_index": 0,
"cxx_class": "Terminal",
"path": "system.pc.com_1.terminal",
"type": "Terminal",
"port": 3456
},
+ "platform": "system.pc",
"eventq_index": 0,
"cxx_class": "Uart8250",
"path": "system.pc.com_1",
@@ -1267,14 +1374,17 @@
"cxx_class": "Pc",
"path": "system.pc",
"behind_pci": {
+ "system": "system",
"ret_data8": 255,
"name": "behind_pci",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[12]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
@@ -1289,14 +1399,17 @@
},
"type": "Pc",
"i_dont_exist": {
+ "system": "system",
"ret_data8": 255,
"name": "i_dont_exist",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[11]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 1,
"ret_data32": 4294967295,
@@ -1310,14 +1423,17 @@
"ret_data16": 65535
},
"fake_com_3": {
+ "system": "system",
"ret_data8": 255,
"name": "fake_com_3",
+ "warn_access": "",
"pio": {
"peer": "system.iobus.master[15]",
"role": "SLAVE"
},
"ret_bad_addr": false,
- "pio_latency": 1.0000000000000001e-07,
+ "pio_latency": 100000,
+ "clk_domain": "system.clk_domain",
"fake_mem": false,
"pio_size": 8,
"ret_data32": 4294967295,
@@ -1368,71 +1484,177 @@
"name": "entries2"
},
{
- "addr": 4294901760,
+ "addr": 134217728,
"range_type": 2,
"eventq_index": 0,
"cxx_class": "X86ISA::E820Entry",
"path": "system.e820_table.entries3",
- "size": 65536,
+ "size": 3087007744,
"type": "X86E820Entry",
"name": "entries3"
+ },
+ {
+ "addr": 4294901760,
+ "range_type": 2,
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::E820Entry",
+ "path": "system.e820_table.entries4",
+ "size": 65536,
+ "type": "X86E820Entry",
+ "name": "entries4"
}
],
"path": "system.e820_table",
"type": "X86E820Table"
},
- "acpi_description_table_pointer": {
- "name": "acpi_description_table_pointer",
- "xsdt": {
- "name": "xsdt",
- "creator_revision": 0,
- "eventq_index": 0,
- "cxx_class": "X86ISA::ACPI::XSDT",
- "path": "system.acpi_description_table_pointer.xsdt",
- "oem_revision": 0,
- "type": "X86ACPIXSDT"
- },
+ "smbios_table": {
+ "name": "smbios_table",
+ "structures": [
+ {
+ "major": 0,
+ "vendor": "",
+ "name": "structures",
+ "characteristics": [],
+ "release_date": "06/08/2008",
+ "cxx_class": "X86ISA::SMBios::BiosInformation",
+ "emb_cont_firmware_major": 0,
+ "rom_size": 0,
+ "starting_addr_segment": 0,
+ "emb_cont_firmware_minor": 0,
+ "version": "",
+ "eventq_index": 0,
+ "characteristic_ext_bytes": [],
+ "path": "system.smbios_table.structures",
+ "type": "X86SMBiosBiosInformation",
+ "minor": 0
+ }
+ ],
+ "major_version": 2,
+ "minor_version": 5,
"eventq_index": 0,
- "cxx_class": "X86ISA::ACPI::RSDP",
- "path": "system.acpi_description_table_pointer",
- "type": "X86ACPIRSDP",
- "revision": 2
+ "cxx_class": "X86ISA::SMBios::SMBiosTable",
+ "path": "system.smbios_table",
+ "type": "X86SMBiosSMBiosTable"
},
"dvfs_handler": {
"enable": false,
"name": "dvfs_handler",
- "transition_latency": 9.999999999999999e-05,
+ "sys_clk_domain": "system.clk_domain",
+ "transition_latency": 100000000,
"eventq_index": 0,
"cxx_class": "DVFSHandler",
+ "domains": [],
"path": "system.dvfs_handler",
"type": "DVFSHandler"
},
"work_end_exit_count": 0,
"type": "LinuxX86System",
"voltage_domain": {
+ "name": "voltage_domain",
"eventq_index": 0,
+ "voltage": [
+ "1.0"
+ ],
+ "cxx_class": "VoltageDomain",
"path": "system.voltage_domain",
- "type": "VoltageDomain",
- "name": "voltage_domain",
- "cxx_class": "VoltageDomain"
+ "type": "VoltageDomain"
},
"cache_line_size": 64,
- "intel_mp_pointer": {
- "imcr_present": true,
- "name": "intel_mp_pointer",
- "spec_rev": 4,
- "eventq_index": 0,
- "cxx_class": "X86ISA::IntelMP::FloatingPointer",
- "path": "system.intel_mp_pointer",
- "type": "X86IntelMPFloatingPointer",
- "default_config": 0
- },
+ "boot_osflags": "earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1",
+ "physmem": [
+ {
+ "static_frontend_latency": 10000,
+ "tRFC": 260000,
+ "activation_limit": 4,
+ "in_addr_map": true,
+ "IDD3N2": "0.0",
+ "tWTR": 7500,
+ "IDD52": "0.0",
+ "clk_domain": "system.clk_domain",
+ "channels": 1,
+ "write_buffer_size": 64,
+ "device_bus_width": 8,
+ "VDD": "1.5",
+ "write_high_thresh_perc": 85,
+ "cxx_class": "DRAMCtrl",
+ "bank_groups_per_rank": 0,
+ "IDD2N2": "0.0",
+ "port": {
+ "peer": "system.membus.master[3]",
+ "role": "SLAVE"
+ },
+ "tCCD_L": 0,
+ "IDD2N": "0.05",
+ "null": false,
+ "IDD2P1": "0.0",
+ "eventq_index": 0,
+ "tRRD": 6000,
+ "tRTW": 2500,
+ "IDD4R": "0.187",
+ "burst_length": 8,
+ "tRTP": 7500,
+ "IDD4W": "0.165",
+ "tWR": 15000,
+ "banks_per_rank": 8,
+ "devices_per_rank": 8,
+ "IDD2P02": "0.0",
+ "IDD6": "0.0",
+ "IDD5": "0.22",
+ "tRCD": 13750,
+ "type": "DRAMCtrl",
+ "IDD3P02": "0.0",
+ "IDD0": "0.075",
+ "IDD62": "0.0",
+ "min_writes_per_switch": 16,
+ "mem_sched_policy": "frfcfs",
+ "IDD02": "0.0",
+ "IDD2P0": "0.0",
+ "ranks_per_channel": 2,
+ "page_policy": "open_adaptive",
+ "IDD4W2": "0.0",
+ "tCS": 2500,
+ "tCL": 13750,
+ "read_buffer_size": 32,
+ "conf_table_reported": true,
+ "tCK": 1250,
+ "tRAS": 35000,
+ "tRP": 13750,
+ "tBURST": 5000,
+ "path": "system.physmem",
+ "tXP": 0,
+ "tXS": 0,
+ "addr_mapping": "RoRaBaChCo",
+ "IDD3P0": "0.0",
+ "IDD3P1": "0.0",
+ "IDD3N": "0.057",
+ "name": "physmem",
+ "tXSDLL": 0,
+ "tXAW": 30000,
+ "dll": true,
+ "write_low_thresh_perc": 50,
+ "range": "0:134217727",
+ "VDD2": "0.0",
+ "IDD2P12": "0.0",
+ "tRRD_L": 0,
+ "tXPDLL": 0,
+ "IDD4R2": "0.0",
+ "device_rowbuffer_size": 1024,
+ "static_backend_latency": 10000,
+ "max_accesses_per_row": 16,
+ "IDD3P12": "0.0",
+ "tREFI": 7800000
+ }
+ ],
"work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0,
"path": "system",
"cpu_clk_domain": {
"name": "cpu_clk_domain",
+ "clock": [
+ 500
+ ],
"init_perf_level": 0,
+ "voltage_domain": "system.voltage_domain",
"eventq_index": 0,
"cxx_class": "SrcClockDomain",
"path": "system.cpu_clk_domain",
@@ -1450,7 +1672,10 @@
"role": "SLAVE"
},
"name": "toL2Bus",
+ "snoop_filter": null,
+ "clk_domain": "system.cpu_clk_domain",
"header_cycles": 1,
+ "system": "system",
"width": 8,
"eventq_index": 0,
"master": {
@@ -1459,51 +1684,12 @@
],
"role": "MASTER"
},
- "cxx_class": "CoherentBus",
+ "cxx_class": "CoherentXBar",
"path": "system.toL2Bus",
- "type": "CoherentBus",
+ "type": "CoherentXBar",
"use_default_range": false
},
- "iocache": {
- "assoc": 8,
- "mem_side": {
- "peer": "system.membus.slave[4]",
- "role": "MASTER"
- },
- "cpu_side": {
- "peer": "system.iobus.master[18]",
- "role": "SLAVE"
- },
- "name": "iocache",
- "tags": {
- "name": "tags",
- "eventq_index": 0,
- "hit_latency": 50,
- "sequential_access": false,
- "assoc": 8,
- "cxx_class": "LRU",
- "path": "system.iocache.tags",
- "block_size": 64,
- "type": "LRU",
- "size": 1024
- },
- "hit_latency": 50,
- "mshrs": 20,
- "response_latency": 50,
- "is_top_level": true,
- "tgts_per_mshr": 12,
- "sequential_access": false,
- "max_miss_count": 0,
- "eventq_index": 0,
- "prefetch_on_access": false,
- "cxx_class": "BaseCache",
- "path": "system.iocache",
- "write_buffers": 8,
- "two_queue": false,
- "type": "BaseCache",
- "forward_snoops": false,
- "size": 1024
- },
+ "work_end_ckpt_count": 0,
"mem_mode": "atomic",
"name": "system",
"init_param": 0,
@@ -1514,7 +1700,6 @@
"load_addr_mask": 18446744073709551615,
"cpu": [
{
- "simpoint_interval": 100000000,
"do_statistics_insts": true,
"numThreads": 1,
"itb": {
@@ -1523,6 +1708,8 @@
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu0.itb.walker",
@@ -1537,47 +1724,48 @@
"type": "X86TLB",
"size": 64
},
+ "simulate_data_stalls": false,
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "AtomicSimpleCPU",
"max_loads_all_threads": 0,
+ "system": "system",
"apic_clk_domain": {
"name": "apic_clk_domain",
+ "clk_domain": "system.cpu_clk_domain",
"eventq_index": 0,
"cxx_class": "DerivedClockDomain",
"path": "system.cpu0.apic_clk_domain",
"type": "DerivedClockDomain",
"clk_divider": 16
},
- "simpoint_profile": false,
- "simulate_data_stalls": false,
+ "clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
"width": 1,
+ "checker": null,
"eventq_index": 0,
"do_quiesce": true,
"type": "AtomicSimpleCPU",
"fastmem": false,
- "profile": 0.0,
+ "profile": 0,
"icache_port": {
"peer": "system.cpu0.icache.cpu_side",
"role": "MASTER"
},
"icache": {
- "assoc": 1,
- "mem_side": {
- "peer": "system.toL2Bus.slave[0]",
- "role": "MASTER"
- },
- "cpu_side": {
- "peer": "system.cpu0.icache_port",
- "role": "SLAVE"
- },
- "name": "icache",
+ "is_top_level": true,
+ "prefetcher": null,
+ "clk_domain": "system.cpu_clk_domain",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "BaseCache",
+ "size": 32768,
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 2,
+ "clk_domain": "system.cpu_clk_domain",
"sequential_access": false,
"assoc": 1,
"cxx_class": "LRU",
@@ -1586,22 +1774,31 @@
"type": "LRU",
"size": 32768
},
- "hit_latency": 2,
- "mshrs": 4,
- "response_latency": 2,
- "is_top_level": true,
- "tgts_per_mshr": 20,
- "sequential_access": false,
+ "system": "system",
"max_miss_count": 0,
"eventq_index": 0,
+ "mem_side": {
+ "peer": "system.toL2Bus.slave[0]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "forward_snoops": true,
+ "hit_latency": 2,
+ "tgts_per_mshr": 20,
+ "addr_ranges": [
+ "0:18446744073709551615"
+ ],
+ "assoc": 1,
"prefetch_on_access": false,
- "cxx_class": "BaseCache",
"path": "system.cpu0.icache",
- "write_buffers": 8,
- "two_queue": false,
+ "name": "icache",
"type": "BaseCache",
- "forward_snoops": true,
- "size": 32768
+ "sequential_access": false,
+ "cpu_side": {
+ "peer": "system.cpu0.icache_port",
+ "role": "SLAVE"
+ },
+ "two_queue": false
},
"interrupts": {
"int_master": {
@@ -1613,31 +1810,30 @@
"peer": "system.membus.master[1]",
"role": "SLAVE"
},
- "pio_latency": 1.0000000000000001e-07,
"int_slave": {
"peer": "system.membus.master[2]",
"role": "SLAVE"
},
- "int_latency": 1e-09,
+ "pio_latency": 100000,
+ "clk_domain": "system.cpu0.apic_clk_domain",
+ "system": "system",
+ "int_latency": 1000,
"eventq_index": 0,
"cxx_class": "X86ISA::Interrupts",
"path": "system.cpu0.interrupts",
"pio_addr": 2305843009213693952,
"type": "X86LocalApic"
},
+ "dcache_port": {
+ "peer": "system.cpu0.dcache.cpu_side",
+ "role": "MASTER"
+ },
"socket_id": 0,
"max_insts_all_threads": 0,
"path": "system.cpu0",
- "isa": [
- {
- "eventq_index": 0,
- "path": "system.cpu0.isa",
- "type": "X86ISA",
- "name": "isa",
- "cxx_class": "X86ISA::ISA"
- }
- ],
+ "max_loads_any_thread": 0,
"switched_out": false,
+ "workload": [],
"name": "cpu0",
"dtb": {
"name": "dtb",
@@ -1645,6 +1841,8 @@
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu0.dtb.walker",
@@ -1659,28 +1857,24 @@
"type": "X86TLB",
"size": 64
},
+ "simpoint_start_insts": [],
"max_insts_any_thread": 0,
"simulate_inst_stalls": false,
- "progress_interval": 0.0,
- "dcache_port": {
- "peer": "system.cpu0.dcache.cpu_side",
- "role": "MASTER"
- },
+ "progress_interval": 0,
+ "branchPred": null,
"dcache": {
- "assoc": 4,
- "mem_side": {
- "peer": "system.toL2Bus.slave[1]",
- "role": "MASTER"
- },
- "cpu_side": {
- "peer": "system.cpu0.dcache_port",
- "role": "SLAVE"
- },
- "name": "dcache",
+ "is_top_level": true,
+ "prefetcher": null,
+ "clk_domain": "system.cpu_clk_domain",
+ "write_buffers": 8,
+ "response_latency": 2,
+ "cxx_class": "BaseCache",
+ "size": 32768,
"tags": {
"name": "tags",
"eventq_index": 0,
"hit_latency": 2,
+ "clk_domain": "system.cpu_clk_domain",
"sequential_access": false,
"assoc": 4,
"cxx_class": "LRU",
@@ -1689,24 +1883,41 @@
"type": "LRU",
"size": 32768
},
- "hit_latency": 2,
- "mshrs": 4,
- "response_latency": 2,
- "is_top_level": true,
- "tgts_per_mshr": 20,
- "sequential_access": false,
+ "system": "system",
"max_miss_count": 0,
"eventq_index": 0,
+ "mem_side": {
+ "peer": "system.toL2Bus.slave[1]",
+ "role": "MASTER"
+ },
+ "mshrs": 4,
+ "forward_snoops": true,
+ "hit_latency": 2,
+ "tgts_per_mshr": 20,
+ "addr_ranges": [
+ "0:18446744073709551615"
+ ],
+ "assoc": 4,
"prefetch_on_access": false,
- "cxx_class": "BaseCache",
"path": "system.cpu0.dcache",
- "write_buffers": 8,
- "two_queue": false,
+ "name": "dcache",
"type": "BaseCache",
- "forward_snoops": true,
- "size": 32768
+ "sequential_access": false,
+ "cpu_side": {
+ "peer": "system.cpu0.dcache_port",
+ "role": "SLAVE"
+ },
+ "two_queue": false
},
- "max_loads_any_thread": 0,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu0.isa",
+ "type": "X86ISA",
+ "name": "isa",
+ "cxx_class": "X86ISA::ISA"
+ }
+ ],
"tracer": {
"eventq_index": 0,
"path": "system.cpu0.tracer",
@@ -1724,6 +1935,8 @@
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu1.itb.walker",
@@ -1734,29 +1947,26 @@
"type": "X86TLB",
"size": 64
},
+ "system": "system",
"function_trace": false,
"do_checkpoint_insts": true,
"cxx_class": "TimingSimpleCPU",
"max_loads_all_threads": 0,
+ "clk_domain": "system.cpu_clk_domain",
"function_trace_start": 0,
"cpu_id": 0,
+ "checker": null,
"eventq_index": 0,
"do_quiesce": true,
"type": "TimingSimpleCPU",
- "profile": 0.0,
+ "profile": 0,
+ "interrupts": null,
"socket_id": 0,
"max_insts_all_threads": 0,
"path": "system.cpu1",
- "isa": [
- {
- "eventq_index": 0,
- "path": "system.cpu1.isa",
- "type": "X86ISA",
- "name": "isa",
- "cxx_class": "X86ISA::ISA"
- }
- ],
+ "max_loads_any_thread": 0,
"switched_out": true,
+ "workload": [],
"name": "cpu1",
"dtb": {
"name": "dtb",
@@ -1764,6 +1974,8 @@
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu1.dtb.walker",
@@ -1774,9 +1986,19 @@
"type": "X86TLB",
"size": 64
},
+ "simpoint_start_insts": [],
"max_insts_any_thread": 0,
- "progress_interval": 0.0,
- "max_loads_any_thread": 0,
+ "progress_interval": 0,
+ "branchPred": null,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu1.isa",
+ "type": "X86ISA",
+ "name": "isa",
+ "cxx_class": "X86ISA::ISA"
+ }
+ ],
"tracer": {
"eventq_index": 0,
"path": "system.cpu1.tracer",
@@ -1788,8 +2010,7 @@
{
"SQEntries": 32,
"smtLSQThreshold": 100,
- "do_statistics_insts": true,
- "dispatchWidth": 8,
+ "fetchTrapLatency": 1,
"iewToRenameDelay": 1,
"itb": {
"name": "itb",
@@ -1797,6 +2018,8 @@
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu2.itb.walker",
@@ -1807,26 +2030,39 @@
"type": "X86TLB",
"size": 64
},
- "wbWidth": 8,
- "squashWidth": 8,
- "forwardComSize": 5,
- "function_trace": false,
- "do_checkpoint_insts": true,
"fetchWidth": 8,
- "cxx_class": "DerivO3CPU",
- "backComSize": 5,
- "switched_out": true,
"max_loads_all_threads": 0,
- "numROBEntries": 192,
- "commitToIEWDelay": 1,
- "commitToDecodeDelay": 1,
- "decodeToRenameDelay": 1,
+ "cpu_id": 0,
"fetchToDecodeDelay": 1,
- "issueWidth": 8,
- "LSQCheckLoads": true,
- "commitToRenameDelay": 1,
"renameToDecodeDelay": 1,
- "wbDepth": 1,
+ "do_quiesce": true,
+ "renameToROBDelay": 1,
+ "max_insts_all_threads": 0,
+ "decodeWidth": 8,
+ "commitToFetchDelay": 1,
+ "needsTSO": true,
+ "smtIQThreshold": 100,
+ "workload": [],
+ "name": "cpu2",
+ "SSITSize": 1024,
+ "activity": 0,
+ "max_loads_any_thread": 0,
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu2.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ },
+ "decodeToFetchDelay": 1,
+ "renameWidth": 8,
+ "numThreads": 1,
+ "squashWidth": 8,
+ "function_trace": false,
+ "backComSize": 5,
+ "decodeToRenameDelay": 1,
+ "store_set_clear_period": 250000,
+ "numPhysIntRegs": 256,
"fuPool": {
"name": "fuPool",
"FUList": [
@@ -2266,33 +2502,17 @@
"path": "system.cpu2.fuPool",
"type": "FUPool"
},
- "cachePorts": 200,
- "function_trace_start": 0,
- "cpu_id": 0,
- "store_set_clear_period": 250000,
- "numPhysFloatRegs": 256,
- "eventq_index": 0,
- "smtNumFetchingThreads": 1,
- "numThreads": 1,
- "numPhysIntRegs": 256,
- "do_quiesce": true,
- "type": "DerivO3CPU",
- "isa": [
- {
- "eventq_index": 0,
- "path": "system.cpu2.isa",
- "type": "X86ISA",
- "name": "isa",
- "cxx_class": "X86ISA::ISA"
- }
- ],
+ "socket_id": 0,
+ "renameToFetchDelay": 1,
+ "path": "system.cpu2",
+ "numRobs": 1,
+ "switched_out": true,
+ "smtLSQPolicy": "Partitioned",
+ "fetchBufferSize": 64,
+ "simpoint_start_insts": [],
+ "max_insts_any_thread": 0,
"smtROBThreshold": 100,
- "profile": 0.0,
- "renameToROBDelay": 1,
- "commitToFetchDelay": 1,
- "fetchTrapLatency": 1,
- "progress_interval": 0.0,
- "commitWidth": 8,
+ "numIQEntries": 64,
"branchPred": {
"choiceCtrBits": 2,
"name": "branchPred",
@@ -2309,32 +2529,47 @@
"path": "system.cpu2.branchPred",
"localPredictorSize": 2048,
"type": "BranchPredictor",
+ "predType": "tournament",
"RASSize": 16,
"globalPredictorSize": 8192
},
- "socket_id": 0,
- "numPhysCCRegs": 1280,
- "renameToFetchDelay": 1,
- "LSQDepCheckShift": 4,
- "decodeWidth": 8,
- "trapLatency": 13,
- "needsTSO": true,
- "renameWidth": 8,
- "path": "system.cpu2",
- "max_insts_all_threads": 0,
- "max_loads_any_thread": 0,
- "numRobs": 1,
- "iewToDecodeDelay": 1,
- "max_insts_any_thread": 0,
+ "LFSTSize": 1024,
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu2.isa",
+ "type": "X86ISA",
+ "name": "isa",
+ "cxx_class": "X86ISA::ISA"
+ }
+ ],
+ "smtROBPolicy": "Partitioned",
+ "iewToFetchDelay": 1,
+ "do_statistics_insts": true,
+ "dispatchWidth": 8,
+ "commitToDecodeDelay": 1,
+ "smtIQPolicy": "Partitioned",
+ "issueWidth": 8,
+ "LSQCheckLoads": true,
+ "commitToRenameDelay": 1,
+ "cachePorts": 200,
+ "system": "system",
+ "checker": null,
+ "numPhysFloatRegs": 256,
+ "eventq_index": 0,
+ "type": "DerivO3CPU",
+ "wbWidth": 8,
+ "interrupts": null,
+ "smtCommitPolicy": "RoundRobin",
"issueToExecuteDelay": 1,
- "name": "cpu2",
- "fetchBufferSize": 64,
"dtb": {
"name": "dtb",
"eventq_index": 0,
"cxx_class": "X86ISA::TLB",
"walker": {
"name": "walker",
+ "clk_domain": "system.cpu_clk_domain",
+ "system": "system",
"eventq_index": 0,
"cxx_class": "X86ISA::Walker",
"path": "system.cpu2.dtb.walker",
@@ -2345,39 +2580,44 @@
"type": "X86TLB",
"size": 64
},
- "SSITSize": 1024,
- "LQEntries": 32,
- "numIQEntries": 64,
- "activity": 0,
- "LFSTSize": 1024,
+ "numROBEntries": 192,
+ "fetchQueueSize": 32,
"iewToCommitDelay": 1,
+ "smtNumFetchingThreads": 1,
+ "forwardComSize": 5,
+ "do_checkpoint_insts": true,
+ "cxx_class": "DerivO3CPU",
+ "commitToIEWDelay": 1,
+ "commitWidth": 8,
+ "clk_domain": "system.cpu_clk_domain",
+ "function_trace_start": 0,
+ "smtFetchPolicy": "SingleThread",
+ "profile": 0,
+ "LSQDepCheckShift": 4,
+ "trapLatency": 13,
+ "iewToDecodeDelay": 1,
+ "numPhysCCRegs": 1280,
"renameToIEWDelay": 2,
- "iewToFetchDelay": 1,
- "tracer": {
- "eventq_index": 0,
- "path": "system.cpu2.tracer",
- "type": "ExeTracer",
- "name": "tracer",
- "cxx_class": "Trace::ExeTracer"
- },
- "decodeToFetchDelay": 1,
- "smtIQThreshold": 100
+ "progress_interval": 0,
+ "LQEntries": 32
}
],
"intrctrl": {
+ "name": "intrctrl",
+ "sys": "system",
"eventq_index": 0,
+ "cxx_class": "IntrControl",
"path": "system.intrctrl",
- "type": "IntrControl",
- "name": "intrctrl",
- "cxx_class": "IntrControl"
+ "type": "IntrControl"
},
- "num_work_ids": 16,
+ "work_begin_ckpt_count": 0,
+ "work_begin_cpu_id_exit": -1,
"work_item_id": -1,
- "work_begin_cpu_id_exit": -1
+ "num_work_ids": 16
},
- "time_sync_period": 0.1,
+ "time_sync_period": 100000000000,
"eventq_index": 0,
- "time_sync_spin_threshold": 9.999999999999999e-05,
+ "time_sync_spin_threshold": 100000000,
"cxx_class": "Root",
"path": "root",
"time_sync_enable": false,
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 9fd6d97ff..e53b3f285 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,150 +1,154 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.133872 # Number of seconds simulated
-sim_ticks 5133872107500 # Number of ticks simulated
-final_tick 5133872107500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.137752 # Number of seconds simulated
+sim_ticks 5137751757500 # Number of ticks simulated
+final_tick 5137751757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 332026 # Simulator instruction rate (inst/s)
-host_op_rate 659988 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6979227984 # Simulator tick rate (ticks/s)
-host_mem_usage 973372 # Number of bytes of host memory used
-host_seconds 735.59 # Real time elapsed on the host
-sim_insts 244235751 # Number of instructions simulated
-sim_ops 485482573 # Number of ops (including micro ops) simulated
+host_inst_rate 205879 # Simulator instruction rate (inst/s)
+host_op_rate 409313 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4343855741 # Simulator tick rate (ticks/s)
+host_mem_usage 976756 # Number of bytes of host memory used
+host_seconds 1182.76 # Real time elapsed on the host
+sim_insts 243506025 # Number of instructions simulated
+sim_ops 484120527 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 396736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5572928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 164928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1639680 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 412864 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 3220800 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11438848 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 396736 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 164928 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 412864 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 974528 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6205312 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 475328 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 5564736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 130048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2113344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 2688 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 362880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2752000 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11429696 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 475328 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 130048 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 362880 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 968256 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6180416 # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9195392 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9170496 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6199 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 87077 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2577 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 25620 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 6451 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 50325 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 178732 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 96958 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 7427 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 86949 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2032 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 33021 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 42 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 5670 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 43000 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 178589 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 96569 # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 143678 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 77278 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1085521 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 32125 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 319385 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 80420 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 627363 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2228113 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 77278 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 32125 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 80420 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 189823 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1208700 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 582422 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1791122 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1208700 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 587945 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 77278 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1085521 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 32125 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 319385 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 80420 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 627363 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4019235 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 85451 # Number of read requests accepted
-system.physmem.writeReqs 85019 # Number of write requests accepted
-system.physmem.readBursts 85451 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 85019 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 5457024 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 11840 # Total number of bytes read from write queue
-system.physmem.bytesWritten 5440128 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 5468864 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 5441216 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_writes::total 143289 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 92517 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1083107 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 25312 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 411336 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 523 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 70630 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 535643 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2224649 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 92517 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 25312 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 70630 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 188459 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1202942 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 581982 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1784924 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1202942 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 587501 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 92517 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1083107 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 25312 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 411336 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 523 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 70630 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 535643 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4009573 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 84209 # Number of read requests accepted
+system.physmem.writeReqs 74716 # Number of write requests accepted
+system.physmem.readBursts 84209 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 74716 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 5376960 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 12416 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4781824 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 5389376 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 4781824 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 868 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 5096 # Per bank write bursts
-system.physmem.perBankRdBursts::1 5035 # Per bank write bursts
-system.physmem.perBankRdBursts::2 5503 # Per bank write bursts
-system.physmem.perBankRdBursts::3 5713 # Per bank write bursts
-system.physmem.perBankRdBursts::4 5011 # Per bank write bursts
-system.physmem.perBankRdBursts::5 4756 # Per bank write bursts
-system.physmem.perBankRdBursts::6 4921 # Per bank write bursts
-system.physmem.perBankRdBursts::7 5413 # Per bank write bursts
-system.physmem.perBankRdBursts::8 5128 # Per bank write bursts
-system.physmem.perBankRdBursts::9 4999 # Per bank write bursts
-system.physmem.perBankRdBursts::10 4701 # Per bank write bursts
-system.physmem.perBankRdBursts::11 5348 # Per bank write bursts
-system.physmem.perBankRdBursts::12 5396 # Per bank write bursts
-system.physmem.perBankRdBursts::13 6167 # Per bank write bursts
-system.physmem.perBankRdBursts::14 6376 # Per bank write bursts
-system.physmem.perBankRdBursts::15 5703 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5743 # Per bank write bursts
-system.physmem.perBankWrBursts::1 5870 # Per bank write bursts
-system.physmem.perBankWrBursts::2 5006 # Per bank write bursts
-system.physmem.perBankWrBursts::3 5323 # Per bank write bursts
-system.physmem.perBankWrBursts::4 4689 # Per bank write bursts
-system.physmem.perBankWrBursts::5 4481 # Per bank write bursts
-system.physmem.perBankWrBursts::6 5327 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5300 # Per bank write bursts
-system.physmem.perBankWrBursts::8 5281 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5131 # Per bank write bursts
-system.physmem.perBankWrBursts::10 5421 # Per bank write bursts
-system.physmem.perBankWrBursts::11 5658 # Per bank write bursts
-system.physmem.perBankWrBursts::12 5171 # Per bank write bursts
-system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
-system.physmem.perBankWrBursts::14 5966 # Per bank write bursts
-system.physmem.perBankWrBursts::15 5038 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 805 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 5309 # Per bank write bursts
+system.physmem.perBankRdBursts::1 4164 # Per bank write bursts
+system.physmem.perBankRdBursts::2 4421 # Per bank write bursts
+system.physmem.perBankRdBursts::3 5747 # Per bank write bursts
+system.physmem.perBankRdBursts::4 5625 # Per bank write bursts
+system.physmem.perBankRdBursts::5 4848 # Per bank write bursts
+system.physmem.perBankRdBursts::6 4889 # Per bank write bursts
+system.physmem.perBankRdBursts::7 4803 # Per bank write bursts
+system.physmem.perBankRdBursts::8 5153 # Per bank write bursts
+system.physmem.perBankRdBursts::9 5288 # Per bank write bursts
+system.physmem.perBankRdBursts::10 4847 # Per bank write bursts
+system.physmem.perBankRdBursts::11 5280 # Per bank write bursts
+system.physmem.perBankRdBursts::12 5573 # Per bank write bursts
+system.physmem.perBankRdBursts::13 6540 # Per bank write bursts
+system.physmem.perBankRdBursts::14 6055 # Per bank write bursts
+system.physmem.perBankRdBursts::15 5473 # Per bank write bursts
+system.physmem.perBankWrBursts::0 4689 # Per bank write bursts
+system.physmem.perBankWrBursts::1 3818 # Per bank write bursts
+system.physmem.perBankWrBursts::2 3922 # Per bank write bursts
+system.physmem.perBankWrBursts::3 4862 # Per bank write bursts
+system.physmem.perBankWrBursts::4 4936 # Per bank write bursts
+system.physmem.perBankWrBursts::5 4229 # Per bank write bursts
+system.physmem.perBankWrBursts::6 4848 # Per bank write bursts
+system.physmem.perBankWrBursts::7 4482 # Per bank write bursts
+system.physmem.perBankWrBursts::8 4577 # Per bank write bursts
+system.physmem.perBankWrBursts::9 4853 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4451 # Per bank write bursts
+system.physmem.perBankWrBursts::11 4689 # Per bank write bursts
+system.physmem.perBankWrBursts::12 4903 # Per bank write bursts
+system.physmem.perBankWrBursts::13 5464 # Per bank write bursts
+system.physmem.perBankWrBursts::14 5149 # Per bank write bursts
+system.physmem.perBankWrBursts::15 4844 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 5132871981000 # Total gap between requests
+system.physmem.totGap 5136577016500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 85451 # Read request sizes (log2)
+system.physmem.readPktSize::6 84209 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 85019 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 78990 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4833 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 949 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 171 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 74716 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 79815 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 3315 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 133 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
@@ -164,487 +168,497 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 124 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 64 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 61 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 59 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 59 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 58 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 53 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1895 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4053 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4329 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4808 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5006 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5424 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5828 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6499 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 5996 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 5563 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 5052 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 4932 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 4301 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 4152 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 4194 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 4105 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 131 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 121 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 127 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 123 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 103 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 115 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 87 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 91 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 86 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 73 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 60 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 40 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 34 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 123 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 68 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 62 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 58 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 56 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 56 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 54 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1333 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1661 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 3664 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3841 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 3881 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4252 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4400 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4751 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5087 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 5589 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 5179 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 4864 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4484 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 4396 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 3849 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 3706 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 3707 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 3671 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 72 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 82 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 86 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 101 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 80 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 73 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 65 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 63 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 81 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 54 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 24 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 39962 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 272.686252 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 163.690614 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 301.316153 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 16345 40.90% 40.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 9834 24.61% 65.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4112 10.29% 75.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2230 5.58% 81.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1552 3.88% 85.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1069 2.68% 87.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 711 1.78% 89.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 597 1.49% 91.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 3512 8.79% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 39962 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 4105 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 20.770767 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 117.592245 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255 4095 99.76% 99.76% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511 7 0.17% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 4105 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 4105 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.706943 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.214534 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 13.616872 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3 63 1.53% 1.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7 7 0.17% 1.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11 1 0.02% 1.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 4 0.10% 1.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 3359 81.83% 83.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 49 1.19% 84.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 26 0.63% 85.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 173 4.21% 89.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 182 4.43% 94.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 7 0.17% 94.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 12 0.29% 94.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 8 0.19% 94.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 10 0.24% 95.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 2 0.05% 95.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 1 0.02% 95.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.02% 95.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 157 3.82% 98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 1 0.02% 98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 3 0.07% 99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 10 0.24% 99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.02% 99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 7 0.17% 99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 2 0.05% 99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 2 0.05% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 5 0.12% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 2 0.05% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 8 0.19% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 2 0.05% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 4105 # Writes before turning the bus around for reads
-system.physmem.totQLat 1041221500 # Total ticks spent queuing
-system.physmem.totMemAccLat 2639959000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 426330000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12211.45 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 37237 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 272.814244 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 163.615678 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 301.614315 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 15278 41.03% 41.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 9118 24.49% 65.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 3769 10.12% 75.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2135 5.73% 81.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1492 4.01% 85.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 936 2.51% 87.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 657 1.76% 89.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 562 1.51% 91.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 3290 8.84% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 37237 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 3726 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.548309 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 194.901220 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 3723 99.92% 99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023 1 0.03% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::5632-6143 1 0.03% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 3726 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 3726 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.052603 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.849959 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 12.299765 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 61 1.64% 1.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 9 0.24% 1.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 1 0.03% 1.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 4 0.11% 2.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 3105 83.33% 85.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 37 0.99% 86.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 24 0.64% 86.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 154 4.13% 91.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 145 3.89% 95.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 6 0.16% 95.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 11 0.30% 95.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 2 0.05% 95.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 14 0.38% 95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 4 0.11% 96.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 1 0.03% 96.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 119 3.19% 99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 5 0.13% 99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 1 0.03% 99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 1 0.03% 99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 6 0.16% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 4 0.11% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.03% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 1 0.03% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 9 0.24% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.03% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 3726 # Writes before turning the bus around for reads
+system.physmem.totQLat 920887750 # Total ticks spent queuing
+system.physmem.totMemAccLat 2496169000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 420075000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10960.99 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30961.45 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.07 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.06 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29710.99 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.93 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.93 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 6.94 # Average write queue length when enqueuing
-system.physmem.readRowHits 67077 # Number of row buffer hits during reads
-system.physmem.writeRowHits 63228 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 78.67 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.37 # Row buffer hit rate for writes
-system.physmem.avgGap 30110118.97 # Average gap between requests
-system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 4938526642750 # Time in different power states
-system.physmem.memoryStateTime::REF 171431260000 # Time in different power states
+system.physmem.avgWrQLen 12.74 # Average write queue length when enqueuing
+system.physmem.readRowHits 66918 # Number of row buffer hits during reads
+system.physmem.writeRowHits 54576 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 79.65 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.04 # Row buffer hit rate for writes
+system.physmem.avgGap 32320761.47 # Average gap between requests
+system.physmem.pageHitRate 76.54 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 4942660463000 # Time in different power states
+system.physmem.memoryStateTime::REF 171560740000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 23914099250 # Time in different power states
+system.physmem.memoryStateTime::ACT 23528333250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 145575360 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 156537360 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 79431000 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 85412250 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 323294400 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 341772600 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 270468720 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 280344240 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 335319544560 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 335319544560 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 122941148535 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 123404461065 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 2972480080500 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 2972073666000 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 3431559543075 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 3431661738075 # Total energy per rank (pJ)
-system.physmem.averagePower::0 668.415487 # Core power per rank (mW)
-system.physmem.averagePower::1 668.435393 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 5056260 # Transaction distribution
-system.membus.trans_dist::ReadResp 5056258 # Transaction distribution
-system.membus.trans_dist::WriteReq 13754 # Transaction distribution
-system.membus.trans_dist::WriteResp 13754 # Transaction distribution
-system.membus.trans_dist::Writeback 96958 # Transaction distribution
+system.physmem.actEnergy::0 135618840 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 145892880 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 73998375 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 79604250 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 310486800 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 344830200 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 231893280 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 252266400 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 335572807440 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 335572807440 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 122729524065 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 123386936985 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 2974992236250 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 2974415558250 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 3434046565050 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 3434197896405 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.395092 # Core power per rank (mW)
+system.physmem.averagePower::1 668.424547 # Core power per rank (mW)
+system.membus.trans_dist::ReadReq 5119571 # Transaction distribution
+system.membus.trans_dist::ReadResp 5119569 # Transaction distribution
+system.membus.trans_dist::WriteReq 13900 # Transaction distribution
+system.membus.trans_dist::WriteResp 13900 # Transaction distribution
+system.membus.trans_dist::Writeback 96569 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 1654 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1654 # Transaction distribution
-system.membus.trans_dist::ReadExReq 129924 # Transaction distribution
-system.membus.trans_dist::ReadExResp 129924 # Transaction distribution
-system.membus.trans_dist::MessageReq 1664 # Transaction distribution
-system.membus.trans_dist::MessageResp 1664 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 1658 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1658 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130179 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130179 # Transaction distribution
+system.membus.trans_dist::MessageReq 1687 # Transaction distribution
+system.membus.trans_dist::MessageResp 1687 # Transaction distribution
system.membus.trans_dist::BadAddressError 2 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7028524 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3012958 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456844 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3374 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3374 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129206 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3039990 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456177 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 10498330 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94955 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 94955 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 10596613 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6656 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6656 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3520458 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6025913 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17615808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 27162179 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029056 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 3029056 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 30197891 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 297 # Total snoops (count)
-system.membus.snoop_fanout::samples 324529 # Request fanout histogram
+system.membus.pkt_count_system.l2c.mem_side::total 10625377 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94957 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 94957 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 10723708 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6748 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6748 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6079977 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17581760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 27232497 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 3029312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30268557 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 291 # Total snoops (count)
+system.membus.snoop_fanout::samples 323999 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 324529 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 323999 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 324529 # Request fanout histogram
-system.membus.reqLayer0.occupancy 165183000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 323999 # Request fanout histogram
+system.membus.reqLayer0.occupancy 162958500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 315920500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 314938500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1960000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 2254000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 897247500 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 804193000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 980000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 1127000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1679098885 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1664243698 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer4.occupancy 35042997 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 28678745 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 105529 # number of replacements
-system.l2c.tags.tagsinuse 64826.632454 # Cycle average of tags in use
-system.l2c.tags.total_refs 3692969 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 169653 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 21.767779 # Average number of references to valid blocks.
+system.l2c.tags.replacements 104648 # number of replacements
+system.l2c.tags.tagsinuse 64825.327064 # Cycle average of tags in use
+system.l2c.tags.total_refs 3691316 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 168821 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 21.865266 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 50921.041202 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134275 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 1022.158767 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3887.538850 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 285.540185 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 1563.161522 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 13.370475 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 1774.545144 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 5359.142034 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.776993 # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks 51329.060133 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131449 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 1735.761730 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 4946.132925 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003182 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 379.214744 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 1982.386911 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.162749 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 878.696468 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 3562.776774 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.783219 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.015597 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.059319 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.004357 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.023852 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000204 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.027077 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.081774 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.989176 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 64124 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 541 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 3271 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 7391 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 52860 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.978455 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 33891981 # Number of tag accesses
-system.l2c.tags.data_accesses 33891981 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 19672 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 10574 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 322011 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 496358 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 11305 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 6290 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 162787 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 241655 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker 55032 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker 13181 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 370296 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 572247 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2281408 # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst 0.026486 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.075472 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.005786 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.030249 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000170 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.013408 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.054364 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.989156 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024 64173 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 3770 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 7642 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 52446 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024 0.979202 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 33857298 # Number of tag accesses
+system.l2c.tags.data_accesses 33857298 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker 21885 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 11413 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 321088 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 497388 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 12632 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 6595 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 160077 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 224317 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker 53710 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker 12539 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst 370609 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data 592462 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 2284715 # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks 1548978 # number of Writeback hits
-system.l2c.Writeback_hits::total 1548978 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 124 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data 90 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 261 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 66428 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 37696 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data 62332 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 166456 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 19672 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 10576 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 322011 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 562786 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 11305 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 6290 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 162787 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 279351 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker 55032 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker 13181 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 370296 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 634579 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2447866 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 19672 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 10576 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 322011 # number of overall hits
-system.l2c.overall_hits::cpu0.data 562786 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 11305 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 6290 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 162787 # number of overall hits
-system.l2c.overall_hits::cpu1.data 279351 # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker 55032 # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker 13181 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 370296 # number of overall hits
-system.l2c.overall_hits::cpu2.data 634579 # number of overall hits
-system.l2c.overall_hits::total 2447866 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 6199 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 12693 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 2577 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 4439 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker 35 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 6453 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 15968 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 48369 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 700 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 296 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 406 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1402 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 74470 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 21268 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 34438 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 130176 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 6199 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 87163 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 2577 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 25707 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker 35 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 6453 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 50406 # number of demand (read+write) misses
-system.l2c.demand_misses::total 178545 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 6199 # number of overall misses
-system.l2c.overall_misses::cpu0.data 87163 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 2577 # number of overall misses
-system.l2c.overall_misses::cpu1.data 25707 # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker 35 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 6453 # number of overall misses
-system.l2c.overall_misses::cpu2.data 50406 # number of overall misses
-system.l2c.overall_misses::total 178545 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst 188438000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 344143000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2792750 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 504402750 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data 1264657500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 2304434000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 3069868 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data 4534805 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 7604673 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 1465791412 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 2496772674 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 3962564086 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 188438000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 1809934412 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker 2792750 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 504402750 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 3761430174 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 6266998086 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 188438000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 1809934412 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker 2792750 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 504402750 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 3761430174 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 6266998086 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 19672 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 10579 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 328210 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 509051 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 11305 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 6290 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 165364 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 246094 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker 55067 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker 13181 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 376749 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 588215 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2329777 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_hits::writebacks 1547592 # number of Writeback hits
+system.l2c.Writeback_hits::total 1547592 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 126 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 49 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data 89 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 264 # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 63533 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 34910 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data 62567 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 161010 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 21885 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 11415 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 321088 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 560921 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 12632 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 6595 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 160077 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 259227 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker 53710 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker 12539 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 370609 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 655029 # number of demand (read+write) hits
+system.l2c.demand_hits::total 2445727 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 21885 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 11415 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 321088 # number of overall hits
+system.l2c.overall_hits::cpu0.data 560921 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 12632 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 6595 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 160077 # number of overall hits
+system.l2c.overall_hits::cpu1.data 259227 # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker 53710 # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker 12539 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 370609 # number of overall hits
+system.l2c.overall_hits::cpu2.data 655029 # number of overall hits
+system.l2c.overall_hits::total 2445727 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 7427 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 17501 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 2032 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 4808 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker 42 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst 5670 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data 10484 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 47969 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 766 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 250 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data 384 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 1400 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 69535 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 28299 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 32603 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 130437 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 7427 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 87036 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 2032 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 33107 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker 42 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 5670 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 43087 # number of demand (read+write) misses
+system.l2c.demand_misses::total 178406 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 7427 # number of overall misses
+system.l2c.overall_misses::cpu0.data 87036 # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 2032 # number of overall misses
+system.l2c.overall_misses::cpu1.data 33107 # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker 42 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 5670 # number of overall misses
+system.l2c.overall_misses::cpu2.data 43087 # number of overall misses
+system.l2c.overall_misses::total 178406 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 150329750 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 367685500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3647250 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 442043250 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data 814497000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1778277250 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 2652136 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data 4441809 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 7093945 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 1942003664 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 2343046915 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 4285050579 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 150329750 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 2309689164 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker 3647250 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 442043250 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 3157543915 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 6063327829 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 150329750 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 2309689164 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker 3647250 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 442043250 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 3157543915 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 6063327829 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 21885 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 11417 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 328515 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 514889 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 12632 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 6596 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 162109 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 229125 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker 53752 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker 12539 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 376279 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data 602946 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2332684 # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 1548978 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1548978 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 824 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 343 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 496 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1663 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 140898 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 58964 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 96770 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 296632 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 19672 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 10581 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 328210 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 649949 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 11305 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 6290 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 165364 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 305058 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker 55067 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker 13181 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 376749 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 684985 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2626411 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 19672 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 10581 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 328210 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 649949 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 11305 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 6290 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 165364 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 305058 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker 55067 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker 13181 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 376749 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 684985 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2626411 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000473 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.018887 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.024935 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.015584 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.018038 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000636 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.017128 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.027147 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.020761 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.849515 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.862974 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 0.818548 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.843055 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.528538 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.360695 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 0.355875 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.438847 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000473 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.018887 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.134107 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.015584 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.084269 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000636 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.017128 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.073587 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.067981 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000473 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.018887 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.134107 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.015584 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.084269 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000636 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.017128 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.073587 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.067981 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73123.011253 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 77527.145754 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 79792.857143 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78165.620642 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 79199.492735 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 47642.787736 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10371.175676 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11169.470443 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 5424.160485 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68920.040060 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 72500.513212 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 30440.051054 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 73123.011253 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 70406.286692 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 79792.857143 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 78165.620642 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 74622.667421 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 35100.384138 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 73123.011253 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 70406.286692 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 79792.857143 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 78165.620642 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 74622.667421 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 35100.384138 # average overall miss latency
+system.l2c.Writeback_accesses::writebacks 1547592 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 1547592 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 892 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 299 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data 473 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 1664 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 133068 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 63209 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 95170 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 291447 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 21885 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 11419 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 328515 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 647957 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 12632 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 6596 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 162109 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 292334 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker 53752 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker 12539 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 376279 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 698116 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2624133 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 21885 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 11419 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 328515 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 647957 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 12632 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 6596 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 162109 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 292334 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker 53752 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker 12539 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 376279 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 698116 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2624133 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000350 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.022608 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.033990 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000152 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.012535 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.020984 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000781 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst 0.015069 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data 0.017388 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.020564 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.858744 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836120 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data 0.811839 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.841346 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.522552 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.447705 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 0.342576 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.447550 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000350 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.022608 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.134324 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.000152 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.012535 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.113251 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000781 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.015069 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.061719 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.067987 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000350 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.022608 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.134324 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.000152 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.012535 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.113251 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000781 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.015069 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.061719 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.067987 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73981.176181 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 76473.689684 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 86839.285714 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77961.772487 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 77689.526898 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 37071.384644 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10608.544000 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11567.210938 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 5067.103571 # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68624.462490 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71865.991320 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 32851.495964 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 73981.176181 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 69764.375026 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 86839.285714 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 77961.772487 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 73282.983615 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 33986.120585 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 73981.176181 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 69764.375026 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 86839.285714 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 77961.772487 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 73282.983615 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 33986.120585 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -653,119 +667,125 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 96958 # number of writebacks
-system.l2c.writebacks::total 96958 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.inst 2577 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 4439 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 35 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst 6451 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data 15968 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 29470 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 296 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data 406 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 702 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 21268 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 34438 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 55706 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 2577 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 25707 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker 35 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 6451 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 50406 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 85176 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 2577 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 25707 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker 35 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 6451 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 50406 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 85176 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 155734000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 288607000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2363250 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 423558250 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1065933000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1936195500 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2960296 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 4096905 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 7057201 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1193338588 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2055185326 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 3248523914 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 155734000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 1481945588 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2363250 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 423558250 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 3121118326 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 5184719414 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 155734000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 1481945588 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2363250 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 423558250 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 3121118326 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 5184719414 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28199786500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30478398000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 58678184500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 496533000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 763698500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 1260231500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28696319500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31242096500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 59938416000 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015584 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018038 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000636 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017123 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.027147 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.012649 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.862974 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.818548 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.422129 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.360695 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.355875 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.187795 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015584 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.084269 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000636 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017123 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.073587 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.032431 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015584 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.084269 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000636 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017123 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.073587 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.032431 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60432.285603 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65016.219869 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65657.766238 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66754.321142 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 65700.559891 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10090.899015 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.992877 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56109.581907 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59677.836285 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 58315.512045 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60432.285603 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57647.550784 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65657.766238 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61919.579534 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 60870.660914 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60432.285603 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57647.550784 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65657.766238 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61919.579534 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 60870.660914 # average overall mshr miss latency
+system.l2c.writebacks::writebacks 96569 # number of writebacks
+system.l2c.writebacks::total 96569 # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 2032 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 4808 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 42 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst 5670 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data 10484 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 23037 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 250 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data 384 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 634 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 28299 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data 32603 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 60902 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 2032 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 33107 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker 42 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst 5670 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data 43087 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 83939 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 2032 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 33107 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker 42 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst 5670 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data 43087 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 83939 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 124575250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 307568500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3127250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 371081250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data 683718500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1490133250 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2500500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3860881 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 6361381 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1578314336 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1925294585 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 3503608921 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 124575250 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 1885882836 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3127250 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 371081250 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 2609013085 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 4993742171 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 124575250 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 1885882836 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3127250 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 371081250 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 2609013085 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 4993742171 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27997217000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30232738500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 58229955500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 537806500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 646167500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 1183974000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28535023500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30878906000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 59413929500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020984 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017388 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.009876 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836120 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.811839 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.381010 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.447705 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.342576 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.208964 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.113251 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.061719 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.031987 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000152 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012535 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.113251 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000781 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015069 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.061719 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.031987 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63970.153910 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65215.423502 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 64684.344750 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10054.377604 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.723975 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55772.795364 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59052.681808 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 57528.634872 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56963.265654 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60552.210295 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59492.514457 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61306.717520 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56963.265654 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74458.333333 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65446.428571 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60552.210295 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59492.514457 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -776,54 +796,54 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.tags.replacements 47571 # number of replacements
-system.iocache.tags.tagsinuse 0.081570 # Cycle average of tags in use
+system.iocache.tags.replacements 47569 # number of replacements
+system.iocache.tags.tagsinuse 0.092434 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 5000192639009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081570 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005098 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.005098 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 5000571333009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092434 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005777 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.005777 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428634 # Number of tag accesses
-system.iocache.tags.data_accesses 428634 # Number of data accesses
+system.iocache.tags.tag_accesses 428616 # Number of tag accesses
+system.iocache.tags.data_accesses 428616 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 906 # number of ReadReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 906 # number of demand (read+write) misses
-system.iocache.demand_misses::total 906 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 906 # number of overall misses
-system.iocache.overall_misses::total 906 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132202779 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 132202779 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 132202779 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 132202779 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 132202779 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 132202779 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
+system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses
+system.iocache.demand_misses::total 904 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses
+system.iocache.overall_misses::total 904 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131931527 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 131931527 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 131931527 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 131931527 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 131931527 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 131931527 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 906 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 906 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 906 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 906 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 145919.182119 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 145919.182119 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 145919.182119 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 145941.954646 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 145941.954646 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145941.954646 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 145941.954646 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked
@@ -832,38 +852,38 @@ system.iocache.avg_blocked_cycles::no_mshrs 12.076923 #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 46720 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 740 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 740 # number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28368 # number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 28368 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 740 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 740 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 740 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 740 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 93698779 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1718205368 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1718205368 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 93698779 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 93698779 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 0.816777 # mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.607192 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.607192 # mshr miss rate for WriteInvalidateReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 0.816777 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 0.816777 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 126619.971622 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60568.435138 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60568.435138 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 734 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 22056 # number of WriteInvalidateReq MSHR misses
+system.iocache.WriteInvalidateReq_mshr_misses::total 22056 # number of WriteInvalidateReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 734 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 734 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 734 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 93740027 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1329860248 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1329860248 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 93740027 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93740027 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 93740027 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 0.811947 # mshr miss rate for ReadReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.472089 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.472089 # mshr miss rate for WriteInvalidateReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 0.811947 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.811947 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 0.811947 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 127711.208447 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60294.715633 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60294.715633 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127711.208447 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 127711.208447 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
@@ -877,567 +897,563 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 7367165 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 7366643 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 13756 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 13756 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 1548978 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 28368 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 1663 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 1663 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 296632 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 296632 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 7431790 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 7431262 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 13902 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 13902 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1547592 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 22056 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 1664 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1664 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 291447 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 291447 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740682 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14873990 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 71302 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 198555 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 16884529 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55700736 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213654403 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 264160 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 728920 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 270348219 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 69633 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 4254339 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.011195 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.105211 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1733856 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14997138 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72735 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 201275 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 17005004 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55482624 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213567857 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 271280 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 749120 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 270070881 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 66934 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 4248687 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.011209 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.105278 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 4206713 98.88% 98.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 47626 1.12% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 4201063 98.88% 98.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 47624 1.12% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4254339 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 5229007845 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 4248687 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 5247340592 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 990000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2442789502 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 2425844552 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4872933864 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4872344858 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 24776404 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 24091410 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 82986153 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 80681637 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 3504325 # Transaction distribution
-system.iobus.trans_dist::ReadResp 3504325 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57563 # Transaction distribution
-system.iobus.trans_dist::WriteResp 39211 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 18352 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1664 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1664 # Transaction distribution
+system.iobus.trans_dist::ReadReq 3554542 # Transaction distribution
+system.iobus.trans_dist::ReadResp 3554542 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57685 # Transaction distribution
+system.iobus.trans_dist::WriteResp 33021 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 24664 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1687 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1687 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 6984892 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27280 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27782 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 7028524 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3328 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3328 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 7127104 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 7129206 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3374 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3374 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 7227828 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3492446 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13640 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13891 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 3520458 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6656 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6656 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 6554906 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 2324808 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 3570760 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6748 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6748 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 6605284 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 2693792 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 4502000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 4846000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy 25000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 143632000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 361000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy 333000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 11636000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy 10264000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 256433144 # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy 199614020 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 306163000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 303080000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 33668003 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 27344255 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 980000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1127000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 1069607129 # number of cpu cycles simulated
+system.cpu0.numCycles 818767223 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 70538619 # Number of instructions committed
-system.cpu0.committedOps 143755687 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 131850662 # Number of integer alu accesses
+system.cpu0.committedInsts 72040073 # Number of instructions committed
+system.cpu0.committedOps 146798683 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 134677148 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 928819 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 13976393 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 131850662 # number of integer instructions
+system.cpu0.num_func_calls 957492 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 14259376 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 134677148 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 241989475 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 113259644 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 247199145 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 115729599 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 82136389 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 54810829 # number of times the CC registers were written
-system.cpu0.num_mem_refs 13501731 # number of memory refs
-system.cpu0.num_load_insts 9912408 # Number of load instructions
-system.cpu0.num_store_insts 3589323 # Number of store instructions
-system.cpu0.num_idle_cycles 1016224343.330366 # Number of idle cycles
-system.cpu0.num_busy_cycles 53382785.669634 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.049909 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.950091 # Percentage of idle cycles
-system.cpu0.Branches 15238819 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 94852 0.07% 0.07% # Class of executed instruction
-system.cpu0.op_class::IntAlu 130054750 90.47% 90.53% # Class of executed instruction
-system.cpu0.op_class::IntMult 56051 0.04% 90.57% # Class of executed instruction
-system.cpu0.op_class::IntDiv 48845 0.03% 90.61% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.61% # Class of executed instruction
-system.cpu0.op_class::MemRead 9912408 6.90% 97.50% # Class of executed instruction
-system.cpu0.op_class::MemWrite 3589323 2.50% 100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads 83822967 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 55940767 # number of times the CC registers were written
+system.cpu0.num_mem_refs 13836630 # number of memory refs
+system.cpu0.num_load_insts 10218166 # Number of load instructions
+system.cpu0.num_store_insts 3618464 # Number of store instructions
+system.cpu0.num_idle_cycles 776544159.837226 # Number of idle cycles
+system.cpu0.num_busy_cycles 42223063.162775 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.051569 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.948431 # Percentage of idle cycles
+system.cpu0.Branches 15573109 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 95028 0.06% 0.06% # Class of executed instruction
+system.cpu0.op_class::IntAlu 132757091 90.43% 90.50% # Class of executed instruction
+system.cpu0.op_class::IntMult 59427 0.04% 90.54% # Class of executed instruction
+system.cpu0.op_class::IntDiv 51115 0.03% 90.57% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.57% # Class of executed instruction
+system.cpu0.op_class::MemRead 10218166 6.96% 97.54% # Class of executed instruction
+system.cpu0.op_class::MemWrite 3618464 2.46% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 143756229 # Class of executed instruction
+system.cpu0.op_class::total 146799291 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 869835 # number of replacements
-system.cpu0.icache.tags.tagsinuse 510.810026 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 128546541 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 870347 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 147.695736 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 147420125000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.953257 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.567270 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.289498 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.246002 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.268686 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst 0.482987 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.997676 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 866413 # number of replacements
+system.cpu0.icache.tags.tagsinuse 510.840210 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 130156159 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 866925 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 150.135432 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 149014386250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 138.994027 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 266.522548 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst 105.323634 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.271473 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.520552 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst 0.205710 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.997735 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 228 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 130310898 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 130310898 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 85798477 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 39676062 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 3072002 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 128546541 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 85798477 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 39676062 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 3072002 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 128546541 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 85798477 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 39676062 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 3072002 # number of overall hits
-system.cpu0.icache.overall_hits::total 128546541 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 328211 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 165364 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 400424 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 893999 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 328211 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 165364 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 400424 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 893999 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 328211 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 165364 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 400424 # number of overall misses
-system.cpu0.icache.overall_misses::total 893999 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2321256000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5686834829 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 8008090829 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 2321256000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 5686834829 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 8008090829 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 2321256000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 5686834829 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 8008090829 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 86126688 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 39841426 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 3472426 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 129440540 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 86126688 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 39841426 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 3472426 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 129440540 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 86126688 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 39841426 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 3472426 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 129440540 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003811 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004151 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.115315 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.006907 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003811 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004151 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115315 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.006907 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003811 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004151 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.115315 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.006907 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14037.251155 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14202.032918 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 8957.606025 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14037.251155 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14202.032918 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 8957.606025 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14037.251155 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14202.032918 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 8957.606025 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 4468 # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses 131912504 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 131912504 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 87639896 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 39531787 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst 2984476 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 130156159 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 87639896 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 39531787 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst 2984476 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 130156159 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 87639896 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 39531787 # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst 2984476 # number of overall hits
+system.cpu0.icache.overall_hits::total 130156159 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 328528 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 162109 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst 398768 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 889405 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 328528 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 162109 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst 398768 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 889405 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 328528 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 162109 # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst 398768 # number of overall misses
+system.cpu0.icache.overall_misses::total 889405 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2245844750 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5606326194 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 7852170944 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 2245844750 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst 5606326194 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 7852170944 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 2245844750 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst 5606326194 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 7852170944 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 87968424 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 39693896 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst 3383244 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 131045564 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 87968424 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 39693896 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst 3383244 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 131045564 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 87968424 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 39693896 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst 3383244 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 131045564 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003735 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004084 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117866 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.006787 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003735 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004084 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117866 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.006787 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003735 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004084 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117866 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.006787 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.917734 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14059.117567 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 8828.566226 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.917734 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14059.117567 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 8828.566226 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.917734 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14059.117567 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 8828.566226 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 4938 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 254 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 262 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.590551 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.847328 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23641 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 23641 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst 23641 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 23641 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst 23641 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 23641 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 165364 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376783 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 542147 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 165364 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 376783 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 542147 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 165364 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 376783 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 542147 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1989596000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4688278233 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 6677874233 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1989596000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4688278233 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 6677874233 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1989596000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4688278233 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 6677874233 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004151 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108507 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004188 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004151 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108507 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.004188 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004151 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108507 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.004188 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12031.615104 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12442.913383 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12317.460454 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12031.615104 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12442.913383 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12317.460454 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12031.615104 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12442.913383 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12317.460454 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22465 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 22465 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst 22465 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 22465 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst 22465 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 22465 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 162109 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376303 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 538412 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 162109 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 376303 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 538412 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 162109 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst 376303 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 538412 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1920905250 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4627637688 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 6548542938 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1920905250 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4627637688 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 6548542938 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1920905250 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4627637688 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 6548542938 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004109 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.004109 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004084 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.111225 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.004109 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12162.698710 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11849.467025 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12297.636979 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12162.698710 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 1639466 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.999450 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 19633257 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1639978 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 11.971659 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements 1637866 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.999423 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 19673585 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 1638378 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 12.007965 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.719707 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 235.128668 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data 22.151075 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497499 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.459236 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data 0.043264 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 126.297276 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 280.648639 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data 105.053508 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.246674 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.548142 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data 0.205183 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 270 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 88291742 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 88291742 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 4780114 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 2623103 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 4098065 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 11501282 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3444198 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 1705247 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 2919966 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 8069411 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 17741 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data 11962 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data 31134 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 60837 # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 8224312 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 4328350 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 7018031 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 19570693 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 8242053 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 4340312 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data 7049165 # number of overall hits
-system.cpu0.dcache.overall_hits::total 19631530 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 360631 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 171099 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 767926 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1299656 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 141722 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 60933 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data 123702 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 326357 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148420 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data 75080 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data 181895 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 405395 # number of SoftPFReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 502353 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 232032 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data 891628 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1626013 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 650773 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 307112 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data 1073523 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2031408 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2363215000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 13135142401 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 15498357401 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2121316122 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4027899410 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 6149215532 # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 4484531122 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 17163041811 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 21647572933 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 4484531122 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 17163041811 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 21647572933 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 5140745 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 2794202 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data 4865991 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 12800938 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 3585920 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 1766180 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data 3043668 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 8395768 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 166161 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 87042 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 213029 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 466232 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 8726665 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 4560382 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data 7909659 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 21196706 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 8892826 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 4647424 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data 8122688 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 21662938 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.070152 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.061234 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.157815 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.101528 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.039522 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034500 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.040642 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.038872 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.893230 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.862572 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.853851 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.869513 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.057565 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050880 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data 0.112726 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.076711 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.073180 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.066082 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data 0.132164 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.093773 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13811.974354 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17104.698110 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11924.968916 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34813.912363 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32561.311943 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18841.990618 # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19327.209704 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 19249.105917 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13313.284047 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 14602.266020 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15987.586490 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 10656.437768 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 138914 # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses 88453877 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 88453877 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 5010669 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 2623262 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data 3898583 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 11532514 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3480346 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 1810737 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data 2788314 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 8079397 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 20263 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10587 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29029 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 59879 # number of SoftPFReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 8491015 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 4433999 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data 6686897 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 19611911 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 8511278 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 4444586 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data 6715926 # number of overall hits
+system.cpu0.dcache.overall_hits::total 19671790 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 362952 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 164891 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data 772037 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1299880 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 133960 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 65129 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data 126515 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 325604 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 151937 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data 64294 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data 190363 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 406594 # number of SoftPFReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 496912 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 230020 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data 898552 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1625484 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 648849 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 294314 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data 1088915 # number of overall misses
+system.cpu0.dcache.overall_misses::total 2032078 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2296036750 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 11919855793 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 14215892543 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2581335822 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3855689962 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 6437025784 # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 4877372572 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 15775545755 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 20652918327 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 4877372572 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 15775545755 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 20652918327 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 5373621 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 2788153 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data 4670620 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 12832394 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 3614306 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 1875866 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data 2914829 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 8405001 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 172200 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 74881 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 219392 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 466473 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 8987927 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 4664019 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data 7585449 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 21237395 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 9160127 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 4738900 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data 7804841 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 21703868 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067543 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.059140 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.165296 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.101297 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037064 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034719 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.043404 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.038739 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.882329 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.858616 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.867684 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871635 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055287 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.049318 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118457 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.076539 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070834 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.062106 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.139518 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.093627 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13924.572900 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15439.487736 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10936.311462 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39634.200157 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30476.148773 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 19769.492340 # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21204.123867 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17556.630841 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 12705.703856 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16572.003275 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14487.398700 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 10163.447627 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 128010 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 26241 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 27734 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5.293777 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.615634 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 1548978 # number of writebacks
-system.cpu0.dcache.writebacks::total 1548978 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 70 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 359132 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 359202 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1638 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 26497 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 28135 # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data 1708 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data 385629 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 387337 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data 1708 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data 385629 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 387337 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 171029 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 408794 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 579823 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 59295 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 97205 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 156500 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 75065 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 179480 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 254545 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 230324 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data 505999 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 736323 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 305389 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data 685479 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 990868 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2019901500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5830950588 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7850852088 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1912820354 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3255992760 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5168813114 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 995266500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2770573261 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3765839761 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3932721854 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9086943348 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 13019665202 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4927988354 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11857516609 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 16785504963 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30674705000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33246369000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63921074000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534053500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 811227000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345280500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31208758500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34057596000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65266354500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.061209 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084010 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045295 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033572 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031937 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018640 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.862400 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.842514 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.545962 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050505 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.063972 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.034738 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065711 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.084391 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.045740 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11810.286560 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14263.787110 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13540.083936 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32259.387031 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33496.144849 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33027.559834 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13258.729101 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15436.668492 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.396908 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17074.737561 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17958.421554 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17682.002602 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16136.757886 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17298.147148 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16940.202896 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 1547592 # number of writebacks
+system.cpu0.dcache.writebacks::total 1547592 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 59 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 355847 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 355906 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1633 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 30941 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 32574 # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data 1692 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 386788 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 388480 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data 1692 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 386788 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 388480 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 164832 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 416190 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 581022 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 63496 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95574 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 159070 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64293 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 186824 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 251117 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 228328 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 511764 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 740092 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 292621 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 698588 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 991209 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1964999750 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5660700319 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7625700069 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2364352650 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3101755528 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5466108178 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 883443250 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2757990753 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3641434003 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4329352400 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 8762455847 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 13091808247 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5212795650 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11520446600 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 16733242250 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30452050000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32985877000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63437927000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 577982500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 687759500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1265742000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31030032500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33673636500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64703669000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059119 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.089108 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045278 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033849 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032789 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018926 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.858602 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.851553 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.538331 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048955 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.067467 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.034849 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061749 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.089507 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.045670 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.227371 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13601.240585 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13124.632233 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37236.245590 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32453.967899 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34362.910530 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13740.893254 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14762.507777 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14500.945786 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18961.110333 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17122.063777 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17689.433539 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17814.154316 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16491.045652 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16881.648825 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -1448,376 +1464,376 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 2604021576 # number of cpu cycles simulated
+system.cpu1.numCycles 2606022983 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 35901808 # Number of instructions committed
-system.cpu1.committedOps 69778761 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 64893692 # Number of integer alu accesses
+system.cpu1.committedInsts 35939339 # Number of instructions committed
+system.cpu1.committedOps 69774923 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 64844483 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 487874 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 6598396 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 64893692 # number of integer instructions
+system.cpu1.num_func_calls 499287 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 6580388 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 64844483 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 119938204 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 55974127 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 120226227 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 55826198 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 36929560 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 27415142 # number of times the CC registers were written
-system.cpu1.num_mem_refs 4838216 # number of memory refs
-system.cpu1.num_load_insts 3070311 # Number of load instructions
-system.cpu1.num_store_insts 1767905 # Number of store instructions
-system.cpu1.num_idle_cycles 2474835372.874957 # Number of idle cycles
-system.cpu1.num_busy_cycles 129186203.125043 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.049610 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.950390 # Percentage of idle cycles
-system.cpu1.Branches 7267731 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 34873 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 64849393 92.94% 92.99% # Class of executed instruction
-system.cpu1.op_class::IntMult 30804 0.04% 93.03% # Class of executed instruction
-system.cpu1.op_class::IntDiv 25762 0.04% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.07% # Class of executed instruction
-system.cpu1.op_class::MemRead 3070311 4.40% 97.47% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1767905 2.53% 100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads 36586824 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 27309791 # number of times the CC registers were written
+system.cpu1.num_mem_refs 4927873 # number of memory refs
+system.cpu1.num_load_insts 3050339 # Number of load instructions
+system.cpu1.num_store_insts 1877534 # Number of store instructions
+system.cpu1.num_idle_cycles 2477290986.248718 # Number of idle cycles
+system.cpu1.num_busy_cycles 128731996.751282 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.049398 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.950602 # Percentage of idle cycles
+system.cpu1.Branches 7259898 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 35461 0.05% 0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu 64754697 92.80% 92.86% # Class of executed instruction
+system.cpu1.op_class::IntMult 31756 0.05% 92.90% # Class of executed instruction
+system.cpu1.op_class::IntDiv 25505 0.04% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.94% # Class of executed instruction
+system.cpu1.op_class::MemRead 3050339 4.37% 97.31% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1877534 2.69% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 69779048 # Class of executed instruction
+system.cpu1.op_class::total 69775292 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 29537500 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 29537500 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 323734 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 26929505 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 26224950 # Number of BTB hits
+system.cpu2.branchPred.lookups 29000272 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 29000272 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 311632 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 26370508 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 25723888 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 97.383706 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 595117 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 63666 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 155672620 # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct 97.547943 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 573459 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 63282 # Number of incorrect RAS predictions.
+system.cpu2.numCycles 153009050 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 10607285 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 145694636 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 29537500 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 26820067 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 143529975 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 676631 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 97153 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 5039 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 8049 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 56841 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 4424 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 3472431 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 167012 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 3661 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 154646852 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.855079 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 3.032629 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 10521285 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 142969715 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 29000272 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 26297347 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 141031314 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 650011 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 92984 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles 4408 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 9006 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 47091 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 2529 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 579 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 3383247 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 163781 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 3234 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 152033550 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.852472 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 3.031588 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 98720699 63.84% 63.84% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 840447 0.54% 64.38% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 23990695 15.51% 79.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 599923 0.39% 80.28% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 812589 0.53% 80.81% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 861055 0.56% 81.36% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 574182 0.37% 81.73% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 718315 0.46% 82.20% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 27528947 17.80% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 97124192 63.88% 63.88% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 819598 0.54% 64.42% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 23594190 15.52% 79.94% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 577537 0.38% 80.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 790978 0.52% 80.84% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 823076 0.54% 81.38% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 560198 0.37% 81.75% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 693420 0.46% 82.21% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 27050361 17.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 154646852 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.189741 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.935904 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 10277789 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 95381782 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 22559618 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 5904125 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 338966 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 283871353 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 338966 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 12885148 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 76664692 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 4829048 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 25619792 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 14124701 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 282624473 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 211024 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 6375709 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 73879 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 5159969 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 337473501 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 616062521 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 378507156 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 50 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 325128635 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 12344864 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 162095 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 163797 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 28599466 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6606628 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3716011 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 425441 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 346966 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 280674873 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 430305 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 278581977 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 102725 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 8814114 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 13599788 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 65362 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 154646852 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.801407 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 2.400759 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 152033550 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.189533 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.934387 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 9712542 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 92934302 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 23280371 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 5017317 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 325657 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 278875678 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 325657 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 11857648 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 75889768 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 4419845 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 25919685 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 12857653 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 277706863 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 221466 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 5888159 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 42783 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 4808995 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 331833488 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 605194394 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 371618079 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 36 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 320107208 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 11726280 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 151218 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 152719 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 24489304 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6338862 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3553328 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 367719 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 319565 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 275826769 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 413139 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 273878584 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 98557 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 8364175 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 12972199 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 61453 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 152033550 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.801435 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 2.398557 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 91425932 59.12% 59.12% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 5392264 3.49% 62.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 3912324 2.53% 65.14% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 4126244 2.67% 67.80% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 21795400 14.09% 81.90% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 3071037 1.99% 83.88% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 24235245 15.67% 99.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 469170 0.30% 99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 219236 0.14% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 89826062 59.08% 59.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 5325607 3.50% 62.59% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 3883778 2.55% 65.14% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 3618974 2.38% 67.52% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 22318323 14.68% 82.20% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 2568868 1.69% 83.89% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 23837030 15.68% 99.57% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 450577 0.30% 99.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 204331 0.13% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 154646852 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 152033550 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 2310389 89.01% 89.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 246 0.01% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.02% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 223101 8.59% 97.61% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 62004 2.39% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 1765790 86.71% 86.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 6 0.00% 86.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 95 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.72% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 213483 10.48% 97.20% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 57008 2.80% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 76436 0.03% 0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 268041478 96.22% 96.24% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 58746 0.02% 96.26% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 49744 0.02% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 6933130 2.49% 98.77% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3422443 1.23% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 75484 0.03% 0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 263736524 96.30% 96.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 54819 0.02% 96.34% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 47031 0.02% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.36% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 6686249 2.44% 98.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3278477 1.20% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 278581977 # Type of FU issued
-system.cpu2.iq.rate 1.789537 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 2595740 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.009318 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 714509188 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 289923619 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 276984093 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 82 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 281101244 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 37 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 733638 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 273878584 # Type of FU issued
+system.cpu2.iq.rate 1.789950 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 2036382 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.007435 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 701925596 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 284608270 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 272313229 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 61 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 275839453 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 29 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 685704 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1227908 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 6601 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 5025 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 667461 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1161006 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 6104 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 4803 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 634153 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 754863 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 24022 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 755552 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 21313 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 338966 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 71689555 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 1628683 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 281105178 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 39439 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6606628 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3716011 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 250069 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 194031 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 1131651 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 5025 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 186633 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 188127 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 374760 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 278001109 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 6795315 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 530943 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 325657 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 70767994 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 1741893 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 276239908 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 40444 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6338884 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3553328 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 236248 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 194416 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 1250638 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 4803 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 177191 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 184398 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 361589 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 273320009 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 6554812 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 510377 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
-system.cpu2.iew.exec_refs 10133053 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 28226522 # Number of branches executed
-system.cpu2.iew.exec_stores 3337738 # Number of stores executed
-system.cpu2.iew.exec_rate 1.785806 # Inst execution rate
-system.cpu2.iew.wb_sent 277806882 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 276984111 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 215977189 # num instructions producing a value
-system.cpu2.iew.wb_consumers 354208085 # num instructions consuming a value
+system.cpu2.iew.exec_refs 9748811 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 27755327 # Number of branches executed
+system.cpu2.iew.exec_stores 3193999 # Number of stores executed
+system.cpu2.iew.exec_rate 1.786300 # Inst execution rate
+system.cpu2.iew.wb_sent 273134840 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 272313245 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 212432379 # num instructions producing a value
+system.cpu2.iew.wb_consumers 348339663 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.779273 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.609747 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.779720 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.609843 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 9156375 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 364943 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 326343 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 153280377 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.774187 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.653000 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 8691419 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 351686 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 314047 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 150733678 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.774964 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.652543 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 95267512 62.15% 62.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4211429 2.75% 64.90% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1288351 0.84% 65.74% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 24928908 16.26% 82.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 992667 0.65% 82.65% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 656859 0.43% 83.08% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 436979 0.29% 83.37% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 23484943 15.32% 98.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 2012729 1.31% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 93656646 62.13% 62.13% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4148238 2.75% 64.89% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1235888 0.82% 65.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 24514613 16.26% 81.97% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1002757 0.67% 82.63% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 665638 0.44% 83.08% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 467092 0.31% 83.39% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 23101150 15.33% 98.71% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1941656 1.29% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 153280377 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 137795324 # Number of instructions committed
-system.cpu2.commit.committedOps 271948125 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 150733678 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 135526613 # Number of instructions committed
+system.cpu2.commit.committedOps 267546921 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8427269 # Number of memory references committed
-system.cpu2.commit.loads 5378719 # Number of loads committed
-system.cpu2.commit.membars 165391 # Number of memory barriers committed
-system.cpu2.commit.branches 27813078 # Number of branches committed
+system.cpu2.commit.refs 8097053 # Number of memory references committed
+system.cpu2.commit.loads 5177878 # Number of loads committed
+system.cpu2.commit.membars 162019 # Number of memory barriers committed
+system.cpu2.commit.branches 27358633 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 248363308 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 444774 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 44974 0.02% 0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 263371453 96.85% 96.86% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 56553 0.02% 96.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 47876 0.02% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 5378719 1.98% 98.88% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 3048550 1.12% 100.00% # Class of committed instruction
+system.cpu2.commit.int_insts 244351653 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 425746 # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass 44568 0.02% 0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 259307312 96.92% 96.94% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 52493 0.02% 96.96% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 45495 0.02% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.97% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 5177878 1.94% 98.91% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 2919175 1.09% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 271948125 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 2012729 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 267546921 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 1941656 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 432344700 # The number of ROB reads
-system.cpu2.rob.rob_writes 563581737 # The number of ROB writes
-system.cpu2.timesIdled 114304 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1025768 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 4904031691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 137795324 # Number of Instructions Simulated
-system.cpu2.committedOps 271948125 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.129738 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.129738 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.885161 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.885161 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 370036745 # number of integer regfile reads
-system.cpu2.int_regfile_writes 221903617 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 72874 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 140867740 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 108480868 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 90412070 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 138782 # number of misc regfile writes
+system.cpu2.rob.rob_reads 425004820 # The number of ROB reads
+system.cpu2.rob.rob_writes 553782312 # The number of ROB writes
+system.cpu2.timesIdled 113608 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 975500 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 4910108147 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 135526613 # Number of Instructions Simulated
+system.cpu2.committedOps 267546921 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.128996 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.128996 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.885742 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.885742 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 363608614 # number of integer regfile reads
+system.cpu2.int_regfile_writes 218247524 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 72984 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes
+system.cpu2.cc_regfile_reads 138904210 # number of cc regfile reads
+system.cpu2.cc_regfile_writes 106846664 # number of cc regfile writes
+system.cpu2.misc_regfile_reads 88678814 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 129757 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
index 72fbd3738..2c13ee133 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
@@ -4,6 +4,7 @@ BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
+ BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)
BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
end_pfn_map = 1048576
kernel direct mapping tables up to 100000000 @ 8000-d000
@@ -23,18 +24,18 @@ Setting APIC routing to flat
Processors: 1
swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000
swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000
-Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
-Built 1 zonelists. Total pages: 30612
+Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)
+Built 1 zonelists. Total pages: 30610
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 1999.986 MHz processor.
+time.c: Detected 2000.002 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
Checking aperture...
-Memory: 122184k/131072k available (3742k kernel code, 8464k reserved, 1874k data, 232k init)
+Memory: 122176k/131072k available (3742k kernel code, 8472k reserved, 1874k data, 232k init)
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
@@ -44,7 +45,7 @@ ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812464
+result 7812527
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
@@ -56,6 +57,7 @@ usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
PCI: Probing PCI hardware
+PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16
PCI-GART: No AMD northbridge found.
NET: Registered protocol family 2
Time: tsc clocksource has been installed.
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 09:05:50 +0000