diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
---|---|---|
committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full | |
parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full')
5 files changed, 1527 insertions, 1504 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 42bed7716..bf000969d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,14 +20,14 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 load_offset=0 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -readfile=/z/stever/hg/gem5/tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -1597,7 +1597,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1620,7 +1620,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index 246bb0fe6..56f83c534 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -3,6 +3,7 @@ warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0xbacc +warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unimplemented function 8 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index ad22be7e5..6a57a8844 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 12 2014 12:50:47 -gem5 started May 12 2014 15:35:34 -gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /z/stever/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full +gem5 compiled Jun 21 2014 11:13:07 +gem5 started Jun 21 2014 22:18:32 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 80c9b1902..307acd090 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,156 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133875 # Number of seconds simulated -sim_ticks 5133874673500 # Number of ticks simulated -final_tick 5133874673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.135764 # Number of seconds simulated +sim_ticks 5135763847500 # Number of ticks simulated +final_tick 5135763847500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236000 # Simulator instruction rate (inst/s) -host_op_rate 469116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4968557721 # Simulator tick rate (ticks/s) -host_mem_usage 928744 # Number of bytes of host memory used -host_seconds 1033.27 # Real time elapsed on the host -sim_insts 243852609 # Number of instructions simulated -sim_ops 484724493 # Number of ops (including micro ops) simulated +host_inst_rate 259782 # Simulator instruction rate (inst/s) +host_op_rate 516376 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5470381356 # Simulator tick rate (ticks/s) +host_mem_usage 959692 # Number of bytes of host memory used +host_seconds 938.83 # Real time elapsed on the host +sim_insts 243891279 # Number of instructions simulated +sim_ops 484789360 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2445440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 500480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5911104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 139776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1689280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 309696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2752128 # Number of bytes read from this memory -system.physmem.bytes_read::total 13749568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 500480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 139776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 309696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 949952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9083392 # Number of bytes written to this memory -system.physmem.bytes_written::total 9083392 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38210 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7820 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 92361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2184 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 26395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4839 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 43002 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214837 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141928 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141928 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 476334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 97486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1151392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 27226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 329046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 60324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 536072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2678205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 97486 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 27226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 60324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 185036 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1769305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1769305 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1769305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 476334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 97486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1151392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 27226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 329046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 60324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 536072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4447510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 96612 # Number of read requests accepted -system.physmem.writeReqs 73475 # Number of write requests accepted -system.physmem.readBursts 96612 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 73475 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6177024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 4701248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6183168 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4702400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::pc.south_bridge.ide 2442432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 470912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6169536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 114240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1582592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 379456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2632640 # Number of bytes read from this memory +system.physmem.bytes_read::total 13794368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 470912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 114240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 379456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9131520 # Number of bytes written to this memory +system.physmem.bytes_written::total 9131520 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7358 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 96399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1785 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24728 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41135 # Number of read requests responded to by this memory +system.physmem.num_reads::total 215537 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142680 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142680 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 475573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 91693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1201289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 22244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 308151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 512609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2685943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 91693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 22244 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73885 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 187822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1778026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1778026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1778026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 475573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 91693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1201289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 22244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 308151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 512609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4463968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 94056 # Number of read requests accepted +system.physmem.writeReqs 72760 # Number of write requests accepted +system.physmem.readBursts 94056 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 72760 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6015488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4096 # Total number of bytes read from write queue +system.physmem.bytesWritten 4656640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6019584 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4656640 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 64 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 831 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5404 # Per bank write bursts -system.physmem.perBankRdBursts::1 5964 # Per bank write bursts -system.physmem.perBankRdBursts::2 6149 # Per bank write bursts -system.physmem.perBankRdBursts::3 6338 # Per bank write bursts -system.physmem.perBankRdBursts::4 5414 # Per bank write bursts -system.physmem.perBankRdBursts::5 6001 # Per bank write bursts -system.physmem.perBankRdBursts::6 5201 # Per bank write bursts -system.physmem.perBankRdBursts::7 6053 # Per bank write bursts -system.physmem.perBankRdBursts::8 5779 # Per bank write bursts -system.physmem.perBankRdBursts::9 5783 # Per bank write bursts -system.physmem.perBankRdBursts::10 5919 # Per bank write bursts -system.physmem.perBankRdBursts::11 5801 # Per bank write bursts -system.physmem.perBankRdBursts::12 6766 # Per bank write bursts -system.physmem.perBankRdBursts::13 6809 # Per bank write bursts -system.physmem.perBankRdBursts::14 6844 # Per bank write bursts -system.physmem.perBankRdBursts::15 6291 # Per bank write bursts -system.physmem.perBankWrBursts::0 4307 # Per bank write bursts -system.physmem.perBankWrBursts::1 4604 # Per bank write bursts -system.physmem.perBankWrBursts::2 4694 # Per bank write bursts -system.physmem.perBankWrBursts::3 4750 # Per bank write bursts -system.physmem.perBankWrBursts::4 4088 # Per bank write bursts -system.physmem.perBankWrBursts::5 4371 # Per bank write bursts -system.physmem.perBankWrBursts::6 3767 # Per bank write bursts -system.physmem.perBankWrBursts::7 4522 # Per bank write bursts -system.physmem.perBankWrBursts::8 4168 # Per bank write bursts -system.physmem.perBankWrBursts::9 4368 # Per bank write bursts -system.physmem.perBankWrBursts::10 4606 # Per bank write bursts -system.physmem.perBankWrBursts::11 4444 # Per bank write bursts -system.physmem.perBankWrBursts::12 5448 # Per bank write bursts -system.physmem.perBankWrBursts::13 5248 # Per bank write bursts -system.physmem.perBankWrBursts::14 5481 # Per bank write bursts -system.physmem.perBankWrBursts::15 4591 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 766 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5609 # Per bank write bursts +system.physmem.perBankRdBursts::1 5668 # Per bank write bursts +system.physmem.perBankRdBursts::2 5585 # Per bank write bursts +system.physmem.perBankRdBursts::3 5594 # Per bank write bursts +system.physmem.perBankRdBursts::4 6037 # Per bank write bursts +system.physmem.perBankRdBursts::5 6612 # Per bank write bursts +system.physmem.perBankRdBursts::6 5733 # Per bank write bursts +system.physmem.perBankRdBursts::7 5990 # Per bank write bursts +system.physmem.perBankRdBursts::8 5523 # Per bank write bursts +system.physmem.perBankRdBursts::9 5460 # Per bank write bursts +system.physmem.perBankRdBursts::10 5647 # Per bank write bursts +system.physmem.perBankRdBursts::11 6128 # Per bank write bursts +system.physmem.perBankRdBursts::12 6059 # Per bank write bursts +system.physmem.perBankRdBursts::13 6267 # Per bank write bursts +system.physmem.perBankRdBursts::14 6194 # Per bank write bursts +system.physmem.perBankRdBursts::15 5886 # Per bank write bursts +system.physmem.perBankWrBursts::0 4545 # Per bank write bursts +system.physmem.perBankWrBursts::1 4402 # Per bank write bursts +system.physmem.perBankWrBursts::2 4127 # Per bank write bursts +system.physmem.perBankWrBursts::3 4299 # Per bank write bursts +system.physmem.perBankWrBursts::4 4675 # Per bank write bursts +system.physmem.perBankWrBursts::5 5126 # Per bank write bursts +system.physmem.perBankWrBursts::6 4327 # Per bank write bursts +system.physmem.perBankWrBursts::7 4679 # Per bank write bursts +system.physmem.perBankWrBursts::8 4360 # Per bank write bursts +system.physmem.perBankWrBursts::9 4207 # Per bank write bursts +system.physmem.perBankWrBursts::10 4528 # Per bank write bursts +system.physmem.perBankWrBursts::11 4822 # Per bank write bursts +system.physmem.perBankWrBursts::12 4836 # Per bank write bursts +system.physmem.perBankWrBursts::13 4641 # Per bank write bursts +system.physmem.perBankWrBursts::14 4944 # Per bank write bursts +system.physmem.perBankWrBursts::15 4242 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5132874544500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 5131947184500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 96612 # Read request sizes (log2) +system.physmem.readPktSize::6 94056 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 73475 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 73469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1283 # What read queue length does an incoming req see +system.physmem.writePktSize::6 72760 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71094 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1622 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 587 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -161,464 +165,474 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 3779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.633118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.344584 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.042030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13828 38.72% 38.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8395 23.51% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3582 10.03% 72.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1962 5.49% 77.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1409 3.95% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 988 2.77% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 701 1.96% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 566 1.59% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4278 11.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35709 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4100 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.539756 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 117.618727 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 4089 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 8 0.20% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4100 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4100 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.916341 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.808533 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.372443 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-1 61 1.49% 1.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2-3 8 0.20% 1.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-5 2 0.05% 1.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6-7 3 0.07% 1.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-9 1 0.02% 1.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10-11 1 0.02% 1.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-13 1 0.02% 1.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14-15 5 0.12% 2.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2769 67.54% 69.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 821 20.02% 89.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 36 0.88% 90.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 38 0.93% 91.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 31 0.76% 92.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 30 0.73% 92.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 54 1.32% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 53 1.29% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 24 0.59% 96.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 28 0.68% 96.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 12 0.29% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 22 0.54% 97.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 34 0.83% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 16 0.39% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 10 0.24% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 6 0.15% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 8 0.20% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 2 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 4 0.10% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 5 0.12% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 2 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 2 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 8 0.20% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::66-67 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4100 # Writes before turning the bus around for reads -system.physmem.totQLat 2438372750 # Total ticks spent queuing -system.physmem.totMemAccLat 4248047750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 482580000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25263.92 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::25 4031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 35723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.746690 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.799684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.095227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14318 40.08% 40.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8282 23.18% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3507 9.82% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1954 5.47% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1307 3.66% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 922 2.58% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 623 1.74% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 530 1.48% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4280 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 35723 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3978 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.627954 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 119.433357 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 3969 99.77% 99.77% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 7 0.18% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6656-6911 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3978 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3978 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.290598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.208175 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.685696 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-1 45 1.13% 1.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2-3 5 0.13% 1.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-5 3 0.08% 1.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6-7 4 0.10% 1.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10-11 1 0.03% 1.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14-15 5 0.13% 1.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2627 66.04% 67.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 818 20.56% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 28 0.70% 88.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 32 0.80% 89.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 32 0.80% 90.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 35 0.88% 91.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 65 1.63% 93.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 48 1.21% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 35 0.88% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 29 0.73% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 29 0.73% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 26 0.65% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 31 0.78% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 18 0.45% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 10 0.25% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 17 0.43% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 8 0.20% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 6 0.15% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 2 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 2 0.05% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 7 0.18% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 3 0.08% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 4 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3978 # Writes before turning the bus around for reads +system.physmem.totQLat 2424873249 # Total ticks spent queuing +system.physmem.totMemAccLat 4187223249 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 469960000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25798.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44013.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44548.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.91 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.46 # Average write queue length when enqueuing -system.physmem.readRowHits 79177 # Number of row buffer hits during reads -system.physmem.writeRowHits 55086 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.97 # Row buffer hit rate for writes -system.physmem.avgGap 30177935.67 # Average gap between requests -system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4939989054000 # Time in different power states -system.physmem.memoryStateTime::REF 171431260000 # Time in different power states +system.physmem.avgWrQLen 6.97 # Average write queue length when enqueuing +system.physmem.readRowHits 76538 # Number of row buffer hits during reads +system.physmem.writeRowHits 54491 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.89 # Row buffer hit rate for writes +system.physmem.avgGap 30764118.46 # Average gap between requests +system.physmem.pageHitRate 78.58 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4942425043001 # Time in different power states +system.physmem.memoryStateTime::REF 171494180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22454242000 # Time in different power states +system.physmem.memoryStateTime::ACT 21844559499 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6437004 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 422289 # Transaction distribution -system.membus.trans_dist::ReadResp 422287 # Transaction distribution -system.membus.trans_dist::WriteReq 6118 # Transaction distribution -system.membus.trans_dist::WriteResp 6118 # Transaction distribution -system.membus.trans_dist::Writeback 73475 # Transaction distribution -system.membus.trans_dist::UpgradeReq 843 # Transaction distribution -system.membus.trans_dist::UpgradeResp 843 # Transaction distribution -system.membus.trans_dist::ReadExReq 76388 # Transaction distribution -system.membus.trans_dist::ReadExResp 76388 # Transaction distribution -system.membus.trans_dist::MessageReq 850 # Transaction distribution -system.membus.trans_dist::MessageResp 850 # Transaction distribution +system.membus.throughput 6452408 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 421921 # Transaction distribution +system.membus.trans_dist::ReadResp 421919 # Transaction distribution +system.membus.trans_dist::WriteReq 5915 # Transaction distribution +system.membus.trans_dist::WriteResp 5915 # Transaction distribution +system.membus.trans_dist::Writeback 72760 # Transaction distribution +system.membus.trans_dist::UpgradeReq 778 # Transaction distribution +system.membus.trans_dist::UpgradeResp 778 # Transaction distribution +system.membus.trans_dist::ReadExReq 75224 # Transaction distribution +system.membus.trans_dist::ReadExResp 75224 # Transaction distribution +system.membus.trans_dist::MessageReq 825 # Transaction distribution +system.membus.trans_dist::MessageResp 825 # Transaction distribution system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 204215 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308134 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 196326 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1010391 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 69253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 69253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1081344 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158115 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995025 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8047552 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9200692 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2838016 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2838016 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 12042108 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32720690 # Total data (bytes) -system.membus.snoop_data_through_bus 326080 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 162128500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::total 1002050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1075932 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3300 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3300 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 157715 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995169 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7734720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 8887604 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2941504 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2941504 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 11832408 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32744958 # Total data (bytes) +system.membus.snoop_data_through_bus 393088 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 161596500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315102000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315113000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1650000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 806327999 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 794070497 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 850000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 825000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1598914090 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1569908183 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 224687998 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 236956000 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 103794 # number of replacements -system.l2c.tags.tagsinuse 64810.608353 # Cycle average of tags in use -system.l2c.tags.total_refs 3657966 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167984 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.775681 # Average number of references to valid blocks. +system.l2c.tags.replacements 104346 # number of replacements +system.l2c.tags.tagsinuse 64811.945905 # Cycle average of tags in use +system.l2c.tags.total_refs 3669840 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168730 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.749778 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51486.278563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.125055 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1295.377972 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4270.696448 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 302.542141 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1483.932036 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.824361 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1349.140567 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4614.691210 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.785618 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51276.768453 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121941 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1221.298902 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4234.138382 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002961 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 249.507225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1581.676468 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.253356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1493.843089 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4747.335130 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.782421 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019766 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.065166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004616 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022643 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020586 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.070415 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.988931 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64190 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3206 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7166 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53256 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979462 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33587388 # Number of tag accesses -system.l2c.tags.data_accesses 33587388 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20605 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 11266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 339595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 520668 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 10906 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6430 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 151391 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 219548 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 53731 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 8985 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 345046 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 563659 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2251830 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.018636 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064608 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003807 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.024134 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000111 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.022794 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.072439 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.988952 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64384 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2861 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7799 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53379 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.982422 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33692585 # Number of tag accesses +system.l2c.tags.data_accesses 33692585 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 19944 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10836 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 348846 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 522725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9533 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5021 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 144714 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 221166 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 56163 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 10079 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 347465 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 563204 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2259696 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1542066 # number of Writeback hits -system.l2c.Writeback_hits::total 1542066 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 52 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 72 # number of UpgradeReq hits +system.l2c.Writeback_hits::writebacks 1546042 # number of Writeback hits +system.l2c.Writeback_hits::total 1546042 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 139 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 73 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 259 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 66169 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 39322 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 60638 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166129 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 20605 # 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number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 130701291 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6017123258 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6017123258 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6147824549 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6147824549 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6147824549 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6147824549 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47628 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47628 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47628 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47628 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -796,60 +816,60 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 144535.209890 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 144535.209890 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 124665.724658 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 124665.724658 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125045.343208 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 125045.343208 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125045.343208 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 88795 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 143944.153084 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 143944.153084 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 128791.165625 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 128791.165625 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 129080.048480 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129080.048480 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 129080.048480 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129080.048480 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 86048 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8200 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7909 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.828659 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.879757 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 733 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 24176 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 24176 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 24909 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 24909 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 24909 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 24909 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93385041 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 93385041 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4566242660 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4566242660 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4659627701 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4659627701 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4659627701 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.805495 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.805495 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.517466 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.517466 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.522969 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.522969 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.522969 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127401.147340 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127401.147340 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 188875.027300 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 188875.027300 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 187066.028383 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 187066.028383 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 735 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 735 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 25536 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 25536 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 26271 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 26271 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 26271 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 26271 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92456791 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 92456791 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4688241758 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4688241758 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4780698549 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4780698549 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.809471 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.809471 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.546575 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.546575 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.551587 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.551587 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125791.552381 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 125791.552381 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 183593.427240 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 183593.427240 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -859,510 +879,511 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52260442 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1795853 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1795321 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6118 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6118 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 903975 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 804 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 804 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 176511 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 152342 # Transaction distribution +system.toL2Bus.throughput 52407719 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1793633 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1793101 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 5915 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 5915 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 899960 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 730 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 730 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 172146 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 146613 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1006951 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3618137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34540 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 139444 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4799072 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32221504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120018356 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 123320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 517264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 152880444 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268161042 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 137520 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5048228823 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 999818 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3602290 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 141650 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4778107 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31993152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119401652 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 525848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 152041460 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 269011854 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 141816 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5025953302 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2267749080 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2251918114 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4703679799 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4677619434 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 19140467 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 19272449 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 74891774 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 76057203 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1277477 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 149797 # Transaction distribution -system.iobus.trans_dist::ReadResp 149797 # Transaction distribution -system.iobus.trans_dist::WriteReq 29441 # Transaction distribution -system.iobus.trans_dist::WriteResp 29441 # Transaction distribution -system.iobus.trans_dist::MessageReq 850 # Transaction distribution -system.iobus.trans_dist::MessageResp 850 # Transaction distribution +system.iobus.throughput 1276582 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 149714 # Transaction distribution +system.iobus.trans_dist::ReadResp 149714 # Transaction distribution +system.iobus.trans_dist::WriteReq 30624 # Transaction distribution +system.iobus.trans_dist::WriteResp 30624 # Transaction distribution +system.iobus.trans_dist::MessageReq 825 # Transaction distribution +system.iobus.trans_dist::MessageResp 825 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4890 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 558 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 38 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 588 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287110 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 224 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287208 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 156 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 308658 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 49818 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 49818 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 360176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 308134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 52542 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 52542 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 362326 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2760 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 279 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 19 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 294 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 12 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143555 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143604 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 312 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6513 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 158115 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1583592 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1583592 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3400 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1745107 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6558405 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2044244 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 157715 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1670648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1670648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3300 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1831663 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6556225 # Total data (bytes) +system.iobus.reqLayer0.occupancy 1987954 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4518000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4046000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 367000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 387000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 33000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143556000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143605000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 178000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 124000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9750000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9774000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 220209699 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 232428549 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303393000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 303046000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30099002 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 31488000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 850000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 825000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1160444400 # number of cpu cycles simulated +system.cpu0.numCycles 1167096017 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72635405 # Number of instructions committed -system.cpu0.committedOps 147758080 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 135731001 # Number of integer alu accesses +system.cpu0.committedInsts 72932334 # Number of instructions committed +system.cpu0.committedOps 148186849 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 136173063 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1010341 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14309822 # number of instructions that are conditional controls -system.cpu0.num_int_insts 135731001 # number of integer instructions +system.cpu0.num_func_calls 1014433 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14332221 # number of instructions that are conditional controls +system.cpu0.num_int_insts 136173063 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 249546871 # number of times the integer registers were read -system.cpu0.num_int_register_writes 116495894 # number of times the integer registers were written +system.cpu0.num_int_register_reads 250637191 # number of times the integer registers were read +system.cpu0.num_int_register_writes 116800630 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 84252648 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 56217158 # number of times the CC registers were written -system.cpu0.num_mem_refs 14168966 # number of memory refs -system.cpu0.num_load_insts 10366088 # Number of load instructions -system.cpu0.num_store_insts 3802878 # Number of store instructions -system.cpu0.num_idle_cycles 1101978015.213226 # Number of idle cycles -system.cpu0.num_busy_cycles 58466384.786774 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050383 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949617 # Percentage of idle cycles -system.cpu0.Branches 15683494 # Number of branches fetched -system.cpu0.op_class::No_OpClass 100234 0.07% 0.07% # Class of executed instruction -system.cpu0.op_class::IntAlu 133376064 90.27% 90.33% # Class of executed instruction -system.cpu0.op_class::IntMult 62929 0.04% 90.38% # Class of executed instruction -system.cpu0.op_class::IntDiv 50413 0.03% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.41% # Class of executed instruction -system.cpu0.op_class::MemRead 10366088 7.02% 97.43% # Class of executed instruction -system.cpu0.op_class::MemWrite 3802878 2.57% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 84487712 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 56367816 # number of times the CC registers were written +system.cpu0.num_mem_refs 14369378 # number of memory refs +system.cpu0.num_load_insts 10451844 # Number of load instructions +system.cpu0.num_store_insts 3917534 # Number of store instructions +system.cpu0.num_idle_cycles 1108227141.183960 # Number of idle cycles +system.cpu0.num_busy_cycles 58868875.816040 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050440 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949560 # Percentage of idle cycles +system.cpu0.Branches 15712912 # Number of branches fetched +system.cpu0.op_class::No_OpClass 100385 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 133601927 90.16% 90.23% # Class of executed instruction +system.cpu0.op_class::IntMult 62763 0.04% 90.27% # Class of executed instruction +system.cpu0.op_class::IntDiv 53014 0.04% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.30% # Class of executed instruction +system.cpu0.op_class::MemRead 10451844 7.05% 97.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 3917534 2.64% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 147758606 # Class of executed instruction +system.cpu0.op_class::total 148187467 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 850385 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.795763 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129494152 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 850897 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 152.185461 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147465545000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 306.120317 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.033154 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 67.642292 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.597891 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.267643 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.132114 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997648 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 855609 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.820181 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129797062 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856121 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 151.610651 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147456803500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 296.387192 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 131.510981 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 82.922008 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.578881 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.256857 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.161957 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997696 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131214879 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131214879 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 88330268 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38415630 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2748254 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129494152 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 88330268 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38415630 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2748254 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129494152 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 88330268 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38415630 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2748254 # number of overall hits -system.cpu0.icache.overall_hits::total 129494152 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 347417 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 153575 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 368828 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 869820 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 347417 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 153575 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 368828 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 869820 # 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number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086110 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118022 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060483 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036684 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031302 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.044084 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.066595 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085705 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.044084 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12226.941776 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14498.870423 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13864.444455 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32691.740066 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31637.185858 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32065.350310 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16678.143000 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16831.518813 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16785.568777 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1546042 # number of writebacks +system.cpu0.dcache.writebacks::total 1546042 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 343252 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 343252 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 17347 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 17347 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 360599 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 360599 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 360599 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 360599 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 225418 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 575479 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 800897 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62696 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 84608 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 147304 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 288114 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 660087 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 948201 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 288114 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 660087 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 948201 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2768607746 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8066658535 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 10835266281 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1923226701 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2756691504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4679918205 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4691834447 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 10823350039 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15515184486 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4691834447 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10823350039 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15515184486 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30492689000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33165040000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63657729000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 394150500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 725206000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1119356500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30886839500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33890246000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64777085500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087511 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118564 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060350 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037581 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030000 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017533 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.043751 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.043751 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12282.105892 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14017.294350 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13528.913557 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30675.429070 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32581.924924 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31770.476056 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1373,376 +1394,377 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606021866 # number of cpu cycles simulated +system.cpu1.numCycles 2604023259 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34914129 # Number of instructions committed -system.cpu1.committedOps 67869828 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 62995297 # Number of integer alu accesses +system.cpu1.committedInsts 34762499 # Number of instructions committed +system.cpu1.committedOps 67606793 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 62736553 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 438942 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6428622 # number of instructions that are conditional controls -system.cpu1.num_int_insts 62995297 # number of integer instructions +system.cpu1.num_func_calls 437056 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6403696 # number of instructions that are conditional controls +system.cpu1.num_int_insts 62736553 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 116271710 # number of times the integer registers were read -system.cpu1.num_int_register_writes 54373007 # number of times the integer registers were written +system.cpu1.num_int_register_reads 115724590 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54164636 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35773638 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26686136 # number of times the CC registers were written -system.cpu1.num_mem_refs 4480512 # number of memory refs -system.cpu1.num_load_insts 2784989 # Number of load instructions -system.cpu1.num_store_insts 1695523 # Number of store instructions -system.cpu1.num_idle_cycles 2483027076.334052 # Number of idle cycles -system.cpu1.num_busy_cycles 122994789.665948 # Number of busy cycles -system.cpu1.not_idle_fraction 0.047196 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.952804 # Percentage of idle cycles -system.cpu1.Branches 7029914 # Number of branches fetched -system.cpu1.op_class::No_OpClass 31008 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 63308003 93.28% 93.32% # Class of executed instruction -system.cpu1.op_class::IntMult 28040 0.04% 93.37% # Class of executed instruction -system.cpu1.op_class::IntDiv 22580 0.03% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.40% # Class of executed instruction -system.cpu1.op_class::MemRead 2784989 4.10% 97.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 1695523 2.50% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 35537675 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26584960 # number of times the CC registers were written +system.cpu1.num_mem_refs 4433444 # number of memory refs +system.cpu1.num_load_insts 2764122 # Number of load instructions +system.cpu1.num_store_insts 1669322 # Number of store instructions +system.cpu1.num_idle_cycles 2476870816.288117 # Number of idle cycles +system.cpu1.num_busy_cycles 127152442.711883 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048829 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951171 # Percentage of idle cycles +system.cpu1.Branches 7001569 # Number of branches fetched +system.cpu1.op_class::No_OpClass 28648 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 63095899 93.33% 93.37% # Class of executed instruction +system.cpu1.op_class::IntMult 28577 0.04% 93.41% # Class of executed instruction +system.cpu1.op_class::IntDiv 20525 0.03% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.44% # Class of executed instruction +system.cpu1.op_class::MemRead 2764122 4.09% 97.53% # Class of executed instruction +system.cpu1.op_class::MemWrite 1669322 2.47% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 67870143 # Class of executed instruction +system.cpu1.op_class::total 67607093 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28758894 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28758894 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 306803 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26351534 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25737629 # Number of BTB hits +system.cpu2.branchPred.lookups 28894520 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28894520 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 314484 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26386768 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25807983 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.670325 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 530881 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 61512 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154845080 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.806533 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 541788 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 61672 # Number of incorrect RAS predictions. +system.cpu2.numCycles 154118891 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9460785 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141747704 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28758894 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26268510 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54302787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1434244 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 58972 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 24471854 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 4161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6545 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 20028 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3117082 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 139514 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1749 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 89437217 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.124405 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.409858 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9526926 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142222809 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28894520 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26349771 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54464711 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1558370 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 64917 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 23183087 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6096 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 25004 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 241 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3179586 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 151181 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1925 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 88503258 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.167922 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.413230 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 35270123 39.44% 39.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 589507 0.66% 40.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23704151 26.50% 66.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 307246 0.34% 66.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 603965 0.68% 67.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 802586 0.90% 68.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 334965 0.37% 68.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 517417 0.58% 69.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27307257 30.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 34173678 38.61% 38.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 596420 0.67% 39.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23721602 26.80% 66.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 320974 0.36% 66.45% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 619988 0.70% 67.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 815233 0.92% 68.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 353145 0.40% 68.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 523827 0.59% 69.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27378391 30.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 89437217 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.185727 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.915416 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10926187 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 23367960 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 31523393 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1298286 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1115198 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278635226 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 49 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1115198 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11921655 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 13834152 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4411879 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 31656208 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5292001 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277656292 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 6764 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2483668 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2130930 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 331880087 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 604361998 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371268132 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 6 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321920244 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 9959841 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 147988 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 148926 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11485411 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6218482 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3410117 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 341148 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 274139 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276004640 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 412430 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 274449569 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 59781 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7023554 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10820295 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 55045 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 89437217 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.068628 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.396853 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 88503258 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.187482 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.922812 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10770329 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 22316529 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 33210052 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 993418 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1230628 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 279539625 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 15 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1230628 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11632631 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 11620518 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4366536 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 33251587 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 6419117 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 278526444 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 145793 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2942087 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 39888 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 2722851 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 332982462 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 606515542 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 372413837 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 321866415 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11116047 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 145000 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 146469 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 9034946 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6263244 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3375371 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 381006 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 309187 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 276743563 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 411647 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 274777165 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 83308 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7862427 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12385425 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 57804 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 88503258 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.104712 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.400001 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 26098480 29.18% 29.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6131096 6.86% 36.04% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3936751 4.40% 40.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2730796 3.05% 43.49% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25025448 27.98% 71.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1337810 1.50% 72.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23830586 26.65% 99.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 291775 0.33% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 54475 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 25772149 29.12% 29.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5479119 6.19% 35.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3780646 4.27% 39.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2658058 3.00% 42.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25098242 28.36% 70.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1415095 1.60% 72.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23897363 27.00% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 310729 0.35% 99.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 91857 0.10% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 89437217 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 88503258 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 125312 33.75% 33.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 120 0.03% 33.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 109 0.03% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 191005 51.44% 85.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 54802 14.76% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 130084 34.74% 34.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 34.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 103 0.03% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 34.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 196279 52.42% 87.18% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 48005 12.82% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 76601 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264560846 96.40% 96.42% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 54414 0.02% 96.44% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50942 0.02% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6508971 2.37% 98.83% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3197795 1.17% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 79957 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 264964709 96.43% 96.46% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 54296 0.02% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50937 0.02% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.50% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6495012 2.36% 98.86% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3132254 1.14% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274449569 # Type of FU issued -system.cpu2.iq.rate 1.772414 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 371348 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001353 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 638809448 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 283444416 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273102485 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 12 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274744310 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 6 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 641561 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 274777165 # Type of FU issued +system.cpu2.iq.rate 1.782891 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 374471 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001363 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 638559252 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 285021199 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 273394851 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 14 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 275071659 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 20 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 655974 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 993516 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6753 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4280 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 500329 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1102337 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6308 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4079 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 550460 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656426 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10045 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656385 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 7890 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1115198 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9119918 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 823405 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 276417070 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 70631 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6218482 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3410117 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 233790 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 637954 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3900 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4280 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 173413 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 173644 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 347057 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273959168 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6398525 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 490400 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1230628 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 6003858 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 2680102 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 277155210 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 55656 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6263266 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3375371 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 233323 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 631738 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1840063 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4079 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 177700 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 182074 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 359774 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 274266101 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6377623 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 511064 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9531292 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27864904 # Number of branches executed -system.cpu2.iew.exec_stores 3132767 # Number of stores executed -system.cpu2.iew.exec_rate 1.769247 # Inst execution rate -system.cpu2.iew.wb_sent 273810478 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273102491 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212979431 # num instructions producing a value -system.cpu2.iew.wb_consumers 348314367 # num instructions consuming a value +system.cpu2.iew.exec_refs 9440682 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27899539 # Number of branches executed +system.cpu2.iew.exec_stores 3063059 # Number of stores executed +system.cpu2.iew.exec_rate 1.779575 # Inst execution rate +system.cpu2.iew.wb_sent 274107922 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 273394865 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 213810949 # num instructions producing a value +system.cpu2.iew.wb_consumers 349940477 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.763714 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611457 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.773922 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.610992 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7316358 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357385 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 309115 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 88322018 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.046767 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.870309 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8157845 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 353843 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 317282 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 87272630 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.082246 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.874009 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 30852434 34.93% 34.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4395307 4.98% 39.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1238857 1.40% 41.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24650858 27.91% 69.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 865215 0.98% 70.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 585749 0.66% 70.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 347954 0.39% 71.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23291491 26.37% 97.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2094153 2.37% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 30201439 34.61% 34.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4017102 4.60% 39.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1154677 1.32% 40.53% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24628965 28.22% 68.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 905267 1.04% 69.79% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 589610 0.68% 70.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 344278 0.39% 70.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23302755 26.70% 97.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2128537 2.44% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 88322018 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136303075 # Number of instructions committed -system.cpu2.commit.committedOps 269096585 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 87272630 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 136196446 # Number of instructions committed +system.cpu2.commit.committedOps 268995718 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8134753 # Number of memory references committed -system.cpu2.commit.loads 5224965 # Number of loads committed -system.cpu2.commit.membars 164376 # Number of memory barriers committed -system.cpu2.commit.branches 27532187 # Number of branches committed +system.cpu2.commit.refs 7985840 # Number of memory references committed +system.cpu2.commit.loads 5160929 # Number of loads committed +system.cpu2.commit.membars 163767 # Number of memory barriers committed +system.cpu2.commit.branches 27540439 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245708361 # Number of committed integer instructions. -system.cpu2.commit.function_calls 429087 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 43848 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 260815603 96.92% 96.94% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 52558 0.02% 96.96% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 49823 0.02% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.98% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5224965 1.94% 98.92% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2909788 1.08% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 245590309 # Number of committed integer instructions. +system.cpu2.commit.function_calls 428081 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 46387 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 260861796 96.98% 96.99% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 52266 0.02% 97.01% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 49429 0.02% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.03% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5160929 1.92% 98.95% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2824911 1.05% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 269096585 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2094153 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 268995718 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2128537 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 362613065 # The number of ROB reads -system.cpu2.rob.rob_writes 553944877 # The number of ROB writes -system.cpu2.timesIdled 473034 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65407863 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4900873955 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136303075 # Number of Instructions Simulated -system.cpu2.committedOps 269096585 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.136035 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.136035 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.880254 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.880254 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364552649 # number of integer regfile reads -system.cpu2.int_regfile_writes 218803003 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72918 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139316304 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107298284 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88761943 # number of misc regfile reads -system.cpu2.misc_regfile_writes 132629 # number of misc regfile writes +system.cpu2.rob.rob_reads 362270810 # The number of ROB reads +system.cpu2.rob.rob_writes 555542201 # The number of ROB writes +system.cpu2.timesIdled 475518 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65615633 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4908375985 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 136196446 # Number of Instructions Simulated +system.cpu2.committedOps 268995718 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.131593 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.131593 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.883710 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.883710 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 364616127 # number of integer regfile reads +system.cpu2.int_regfile_writes 219111496 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72926 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes +system.cpu2.cc_regfile_reads 139466740 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107376389 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88828545 # number of misc regfile reads +system.cpu2.misc_regfile_writes 129118 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal index 08dac49a9..72fbd3738 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal @@ -44,7 +44,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812444
+result 7812464
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
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