diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/long/fs/10.linux-boot/ref/x86/linux | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/x86/linux')
7 files changed, 2927 insertions, 2957 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 4b49caa69..15805fa4d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -29,7 +29,7 @@ mem_ranges=0:134217727 memories=system.physmem mmap_using_noreserve=false num_work_ids=16 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -202,7 +202,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -252,7 +252,7 @@ system=system port=system.cpu.dtb_walker_cache.cpu_side [system.cpu.dtb_walker_cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -594,7 +594,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -660,7 +660,7 @@ system=system port=system.cpu.itb_walker_cache.cpu_side [system.cpu.itb_walker_cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -695,7 +695,7 @@ sequential_access=false size=1024 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -1202,7 +1202,7 @@ master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_b slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 @@ -1586,7 +1586,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1609,7 +1609,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index ce7843f5c..264f4c629 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.154115 # Number of seconds simulated -sim_ticks 5154115247000 # Number of ticks simulated -final_tick 5154115247000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.126140 # Number of seconds simulated +sim_ticks 5126139641000 # Number of ticks simulated +final_tick 5126139641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128017 # Simulator instruction rate (inst/s) -host_op_rate 253040 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1617614851 # Simulator tick rate (ticks/s) -host_mem_usage 806232 # Number of bytes of host memory used -host_seconds 3186.24 # Real time elapsed on the host -sim_insts 407894468 # Number of instructions simulated -sim_ops 806246903 # Number of ops (including micro ops) simulated +host_inst_rate 128755 # Simulator instruction rate (inst/s) +host_op_rate 254500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1618610313 # Simulator tick rate (ticks/s) +host_mem_usage 809248 # Number of bytes of host memory used +host_seconds 3167.00 # Real time elapsed on the host +sim_insts 407767906 # Number of instructions simulated +sim_ops 806002026 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 4480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1047104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10813376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1038720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10766272 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11893632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1047104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1047104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9584064 # Number of bytes written to this memory -system.physmem.bytes_written::total 9584064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 70 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168959 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11837632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1038720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1038720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9565696 # Number of bytes written to this memory +system.physmem.bytes_written::total 9565696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16230 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168223 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185838 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149751 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149751 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 203159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2098008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2307599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 203159 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 203159 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1859497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1859497 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1859497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 203159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2098008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4167097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185838 # Number of read requests accepted -system.physmem.writeReqs 149751 # Number of write requests accepted -system.physmem.readBursts 185838 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 149751 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11883456 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 9582144 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11893632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9584064 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 184963 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149464 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149464 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 202632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2100269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2309268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 202632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 202632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1866062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1866062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1866062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 202632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2100269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4175331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 184963 # Number of read requests accepted +system.physmem.writeReqs 149464 # Number of write requests accepted +system.physmem.readBursts 184963 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149464 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11826048 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11584 # Total number of bytes read from write queue +system.physmem.bytesWritten 9564672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11837632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9565696 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 181 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11738 # Per bank write bursts -system.physmem.perBankRdBursts::1 11323 # Per bank write bursts -system.physmem.perBankRdBursts::2 11916 # Per bank write bursts -system.physmem.perBankRdBursts::3 11912 # Per bank write bursts -system.physmem.perBankRdBursts::4 12271 # Per bank write bursts -system.physmem.perBankRdBursts::5 11705 # Per bank write bursts -system.physmem.perBankRdBursts::6 10605 # Per bank write bursts -system.physmem.perBankRdBursts::7 10992 # Per bank write bursts -system.physmem.perBankRdBursts::8 11596 # Per bank write bursts -system.physmem.perBankRdBursts::9 11415 # Per bank write bursts -system.physmem.perBankRdBursts::10 11752 # Per bank write bursts -system.physmem.perBankRdBursts::11 11610 # Per bank write bursts -system.physmem.perBankRdBursts::12 11474 # Per bank write bursts -system.physmem.perBankRdBursts::13 12022 # Per bank write bursts -system.physmem.perBankRdBursts::14 11655 # Per bank write bursts -system.physmem.perBankRdBursts::15 11693 # Per bank write bursts -system.physmem.perBankWrBursts::0 10141 # Per bank write bursts -system.physmem.perBankWrBursts::1 9357 # Per bank write bursts -system.physmem.perBankWrBursts::2 8826 # Per bank write bursts -system.physmem.perBankWrBursts::3 8882 # Per bank write bursts -system.physmem.perBankWrBursts::4 9347 # Per bank write bursts -system.physmem.perBankWrBursts::5 9205 # Per bank write bursts -system.physmem.perBankWrBursts::6 8767 # Per bank write bursts -system.physmem.perBankWrBursts::7 8936 # Per bank write bursts -system.physmem.perBankWrBursts::8 9149 # Per bank write bursts -system.physmem.perBankWrBursts::9 9192 # Per bank write bursts -system.physmem.perBankWrBursts::10 10057 # Per bank write bursts -system.physmem.perBankWrBursts::11 9346 # Per bank write bursts -system.physmem.perBankWrBursts::12 9689 # Per bank write bursts -system.physmem.perBankWrBursts::13 9578 # Per bank write bursts -system.physmem.perBankWrBursts::14 9663 # Per bank write bursts -system.physmem.perBankWrBursts::15 9586 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48781 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12059 # Per bank write bursts +system.physmem.perBankRdBursts::1 11374 # Per bank write bursts +system.physmem.perBankRdBursts::2 11651 # Per bank write bursts +system.physmem.perBankRdBursts::3 11200 # Per bank write bursts +system.physmem.perBankRdBursts::4 11713 # Per bank write bursts +system.physmem.perBankRdBursts::5 11071 # Per bank write bursts +system.physmem.perBankRdBursts::6 11625 # Per bank write bursts +system.physmem.perBankRdBursts::7 11816 # Per bank write bursts +system.physmem.perBankRdBursts::8 11540 # Per bank write bursts +system.physmem.perBankRdBursts::9 11598 # Per bank write bursts +system.physmem.perBankRdBursts::10 11427 # Per bank write bursts +system.physmem.perBankRdBursts::11 11449 # Per bank write bursts +system.physmem.perBankRdBursts::12 11382 # Per bank write bursts +system.physmem.perBankRdBursts::13 12463 # Per bank write bursts +system.physmem.perBankRdBursts::14 11321 # Per bank write bursts +system.physmem.perBankRdBursts::15 11093 # Per bank write bursts +system.physmem.perBankWrBursts::0 10213 # Per bank write bursts +system.physmem.perBankWrBursts::1 9339 # Per bank write bursts +system.physmem.perBankWrBursts::2 9470 # Per bank write bursts +system.physmem.perBankWrBursts::3 9072 # Per bank write bursts +system.physmem.perBankWrBursts::4 9457 # Per bank write bursts +system.physmem.perBankWrBursts::5 9178 # Per bank write bursts +system.physmem.perBankWrBursts::6 9173 # Per bank write bursts +system.physmem.perBankWrBursts::7 8997 # Per bank write bursts +system.physmem.perBankWrBursts::8 8928 # Per bank write bursts +system.physmem.perBankWrBursts::9 9204 # Per bank write bursts +system.physmem.perBankWrBursts::10 9473 # Per bank write bursts +system.physmem.perBankWrBursts::11 8827 # Per bank write bursts +system.physmem.perBankWrBursts::12 9527 # Per bank write bursts +system.physmem.perBankWrBursts::13 9857 # Per bank write bursts +system.physmem.perBankWrBursts::14 9294 # Per bank write bursts +system.physmem.perBankWrBursts::15 9439 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 5154115197500 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 5126139591500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185838 # Read request sizes (log2) +system.physmem.readPktSize::6 184963 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149751 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 171307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149464 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,418 +156,418 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7827 # What write queue length does an incoming req see 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queue length does an incoming req see +system.physmem.wrQLenPdf::33 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 72428 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.370685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.530831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.820481 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27904 38.53% 38.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17658 24.38% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7456 10.29% 73.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4108 5.67% 78.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2731 3.77% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1986 2.74% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1581 2.18% 87.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1174 1.62% 89.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7830 10.81% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 72428 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7352 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.252992 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 561.335686 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7351 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 71880 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.588425 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.048684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 320.988013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27629 38.44% 38.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17400 24.21% 62.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7428 10.33% 72.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4118 5.73% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2845 3.96% 82.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1999 2.78% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1307 1.82% 87.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1141 1.59% 88.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8013 11.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 71880 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7347 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.150402 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 560.379075 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7346 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7352 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7352 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.364663 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.601623 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.168660 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6294 85.61% 85.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 82 1.12% 86.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 194 2.64% 89.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 86 1.17% 90.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 99 1.35% 91.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 218 2.97% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 33 0.45% 95.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.15% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.20% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.08% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.04% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.04% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 253 3.44% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 7 0.10% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.05% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.20% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7347 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.341364 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.592949 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.054942 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6299 85.74% 85.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 77 1.05% 86.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 192 2.61% 89.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 82 1.12% 90.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 130 1.77% 92.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 203 2.76% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 23 0.31% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.10% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 7 0.10% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.11% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.05% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.08% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 243 3.31% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.10% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.12% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 11 0.15% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 7 0.10% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.22% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7352 # Writes before turning the bus around for reads -system.physmem.totQLat 2003475850 # Total ticks spent queuing -system.physmem.totMemAccLat 5484957100 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 928395000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10790.00 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7347 # Writes before turning the bus around for reads +system.physmem.totQLat 1972823732 # Total ticks spent queuing +system.physmem.totMemAccLat 5437486232 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 923910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10676.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29540.00 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29426.49 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.16 # Average write queue length when enqueuing -system.physmem.readRowHits 152313 # Number of row buffer hits during reads -system.physmem.writeRowHits 110658 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.89 # Row buffer hit rate for writes -system.physmem.avgGap 15358415.20 # Average gap between requests -system.physmem.pageHitRate 78.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 270738720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 147724500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 721203600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 476027280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 336641292000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 130240416060 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2978219081250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3446716483410 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.731853 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4954469478230 # Time in different power states -system.physmem_0.memoryStateTime::REF 172107000000 # Time in different power states +system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.70 # Average write queue length when enqueuing +system.physmem.readRowHits 152120 # Number of row buffer hits during reads +system.physmem.writeRowHits 110229 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.75 # Row buffer hit rate for writes +system.physmem.avgGap 15328127.19 # Average gap between requests +system.physmem.pageHitRate 78.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 270149040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 147402750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 721570200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 485345520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 129415070025 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2962157471250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3428011044705 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.732438 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4927750166228 # Time in different power states +system.physmem_0.memoryStateTime::REF 171172820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27531969270 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27209465022 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 276816960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 151041000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 727084800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 494164800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 336641292000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 130162900905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2978287085250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3446740385715 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.736489 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4954592740478 # Time in different power states -system.physmem_1.memoryStateTime::REF 172107000000 # Time in different power states +system.physmem_1.actEnergy 273263760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 149102250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 719721600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 483077520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 334814035920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129328302060 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2962233583500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3428001086610 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.730496 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4927884080230 # Time in different power states +system.physmem_1.memoryStateTime::REF 171172820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27415396022 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27082630770 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86789700 # Number of BP lookups -system.cpu.branchPred.condPredicted 86789700 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 894071 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80040540 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78122239 # Number of BTB hits +system.cpu.branchPred.lookups 86515320 # Number of BP lookups +system.cpu.branchPred.condPredicted 86515320 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 846562 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79887008 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77941063 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.603338 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1558682 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180590 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.564128 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1538368 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 179519 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449504376 # number of cpu cycles simulated +system.cpu.numCycles 448780162 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27485279 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 428718572 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86789700 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79680921 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 418030666 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1875632 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 150798 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 59488 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 208856 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 90 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 672 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9123295 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 449746 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4755 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 446873665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.892893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.051645 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27109366 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 427484272 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86515320 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79479431 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 417767954 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1778202 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 144572 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 59542 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 198505 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8932158 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 424030 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4890 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 446169387 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.890848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.050446 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281625965 63.02% 63.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2138685 0.48% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72155487 16.15% 79.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1568927 0.35% 80.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2122343 0.47% 80.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2325830 0.52% 80.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1507660 0.34% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1867139 0.42% 81.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81561629 18.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281281763 63.04% 63.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2130107 0.48% 63.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72126905 16.17% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1545484 0.35% 80.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2095217 0.47% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2290541 0.51% 81.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1479828 0.33% 81.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1850907 0.41% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81368635 18.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 446873665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193079 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.953758 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 22890187 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264923803 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150702566 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7419293 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 937816 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 837865741 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 937816 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25728184 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 222903682 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12889746 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154594835 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29819402 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834359795 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 448369 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12212745 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 141423 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14773604 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 996662587 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1812180036 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114009606 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 309 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964181963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32480622 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 461875 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 465908 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 38538990 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17255328 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10136845 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1286418 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1053742 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 828858399 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1188333 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823669123 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 243637 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23799824 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 35821203 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 147900 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 446873665 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.843181 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418517 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 446169387 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192779 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.952547 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23013230 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 265986736 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 147854773 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8425547 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 889101 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 835878661 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 889101 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 26336765 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 222825660 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12982234 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 152266315 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 30869312 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 832551989 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 449261 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12787861 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 146326 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14734321 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 994655089 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1807638707 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1111268111 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963888503 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30766581 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 460676 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 463553 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43190500 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17070475 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10019861 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1311535 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1113253 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 827301854 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1181846 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 822527972 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 224018 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22481665 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33938360 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 142118 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 446169387 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.843533 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.419200 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262902763 58.83% 58.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13828746 3.09% 61.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9781500 2.19% 64.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7055144 1.58% 65.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74339132 16.64% 82.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4387820 0.98% 83.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72808347 16.29% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1195469 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 574744 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262457891 58.82% 58.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13818111 3.10% 61.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9771246 2.19% 64.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7528828 1.69% 65.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 73243364 16.42% 82.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4832116 1.08% 83.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72756563 16.31% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1182673 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 578595 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 446873665 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 446169387 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1974081 71.95% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 2 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 609151 22.20% 94.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160307 5.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2475977 76.35% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 605774 18.68% 95.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 161247 4.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 285084 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795424559 96.57% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150449 0.02% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 127671 0.02% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 84 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18333357 2.23% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9347919 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 283294 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 794512938 96.59% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150315 0.02% 96.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 126079 0.02% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 84 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18183253 2.21% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9272009 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823669123 # Type of FU issued -system.cpu.iq.rate 1.832394 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2743541 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2097198642 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 853858757 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819128971 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 446 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 432 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 155 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 826127364 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 216 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1863869 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 822527972 # Type of FU issued +system.cpu.iq.rate 1.832808 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3242998 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003943 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2094691886 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 850977244 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818130626 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 165 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 825487451 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 225 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1857982 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3260732 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15309 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14369 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1707925 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3083761 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14419 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13953 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1600409 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2207612 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 70919 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2207227 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 67958 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 937816 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 204799790 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10007204 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 830046732 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 155850 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17255344 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10136845 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 698572 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 395239 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8760495 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14369 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 514805 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 529588 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1044393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822053660 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17935902 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1483234 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 889101 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 204671978 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10002497 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 828483700 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 158761 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17070475 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10019861 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 692471 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 393140 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8758574 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13953 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 479614 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 507057 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 986671 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821011839 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17813350 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1389357 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27057833 # number of memory reference insts executed -system.cpu.iew.exec_branches 83242296 # Number of branches executed -system.cpu.iew.exec_stores 9121931 # Number of stores executed -system.cpu.iew.exec_rate 1.828800 # Inst execution rate -system.cpu.iew.wb_sent 821550761 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819129126 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640649566 # num instructions producing a value -system.cpu.iew.wb_consumers 1049893259 # num instructions consuming a value +system.cpu.iew.exec_refs 26873346 # number of memory reference insts executed +system.cpu.iew.exec_branches 83150160 # Number of branches executed +system.cpu.iew.exec_stores 9059996 # Number of stores executed +system.cpu.iew.exec_rate 1.829430 # Inst execution rate +system.cpu.iew.wb_sent 820539763 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818130791 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639922411 # num instructions producing a value +system.cpu.iew.wb_consumers 1048802840 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.822294 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610204 # average fanout of values written-back +system.cpu.iew.wb_rate 1.823010 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610146 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23669936 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1040433 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 905908 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443311497 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.818692 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.674309 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22357422 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1039727 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 857347 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 442798070 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.820247 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.674846 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272449194 61.46% 61.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11181690 2.52% 63.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3605884 0.81% 64.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74618286 16.83% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2464935 0.56% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1628465 0.37% 82.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 954634 0.22% 82.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70998554 16.02% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5409855 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272013186 61.43% 61.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11121974 2.51% 63.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3639430 0.82% 64.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74586618 16.84% 81.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2447768 0.55% 82.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1626880 0.37% 82.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1002961 0.23% 82.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70975924 16.03% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5383329 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443311497 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407894468 # Number of instructions committed -system.cpu.commit.committedOps 806246903 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 442798070 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407767906 # Number of instructions committed +system.cpu.commit.committedOps 806002026 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22423531 # Number of memory references committed -system.cpu.commit.loads 13994611 # Number of loads committed -system.cpu.commit.membars 468283 # Number of memory barriers committed -system.cpu.commit.branches 82184111 # Number of branches committed +system.cpu.commit.refs 22406164 # Number of memory references committed +system.cpu.commit.loads 13986712 # Number of loads committed +system.cpu.commit.membars 468149 # Number of memory barriers committed +system.cpu.commit.branches 82157432 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735078702 # Number of committed integer instructions. -system.cpu.commit.function_calls 1156217 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171842 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783387641 97.16% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 145035 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121422 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 734850257 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155439 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171613 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783160302 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144896 0.02% 97.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121618 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -594,230 +594,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13992027 1.74% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8428920 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13984129 1.73% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8419452 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806246903 # Class of committed instruction -system.cpu.commit.bw_lim_events 5409855 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1267740043 # The number of ROB reads -system.cpu.rob.rob_writes 1663415417 # The number of ROB writes -system.cpu.timesIdled 288487 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2630711 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9858723524 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407894468 # Number of Instructions Simulated -system.cpu.committedOps 806246903 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.102011 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.102011 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907432 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907432 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1091775121 # number of integer regfile reads -system.cpu.int_regfile_writes 655663425 # number of integer regfile writes -system.cpu.fp_regfile_reads 155 # number of floating regfile reads -system.cpu.cc_regfile_reads 416039105 # number of cc regfile reads -system.cpu.cc_regfile_writes 321913343 # number of cc regfile writes -system.cpu.misc_regfile_reads 265322894 # number of misc regfile reads -system.cpu.misc_regfile_writes 400562 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1662098 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.990156 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19068760 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1662610 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.469172 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 806002026 # Class of committed instruction +system.cpu.commit.bw_lim_events 5383329 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1265696040 # The number of ROB reads +system.cpu.rob.rob_writes 1660107630 # The number of ROB writes +system.cpu.timesIdled 283975 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2610775 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9803496536 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407767906 # Number of Instructions Simulated +system.cpu.committedOps 806002026 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.100577 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.100577 # CPI: Total CPI of All Threads +system.cpu.ipc 0.908614 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.908614 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1090426394 # number of integer regfile reads +system.cpu.int_regfile_writes 654841654 # number of integer regfile writes +system.cpu.fp_regfile_reads 165 # number of floating regfile reads +system.cpu.cc_regfile_reads 415713185 # number of cc regfile reads +system.cpu.cc_regfile_writes 321659378 # number of cc regfile writes +system.cpu.misc_regfile_reads 264880270 # number of misc regfile reads +system.cpu.misc_regfile_writes 399890 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1655948 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.995019 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18959511 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1656460 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.445801 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 40620500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.990156 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999981 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999981 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995019 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 204 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 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SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.863559 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.101659 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.101659 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118242 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118242 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14896.112554 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14896.112554 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41378.667932 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41378.667932 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19017.197849 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19017.197849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15994.353969 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15994.353969 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 467851 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 84 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 51332 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 87653092 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87653092 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10818266 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10818266 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8075018 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8075018 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63136 # number of 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cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12619706 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12619706 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8409813 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8409813 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 469636 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 469636 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21029519 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21029519 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21499155 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21499155 # number of overall (read+write) accesses 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-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.301831 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188325.642314 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188325.642314 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162796.306744 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162796.306744 # average overall mshr uncacheable latency +system.cpu.dcache.writebacks::writebacks 1557810 # number of writebacks +system.cpu.dcache.writebacks::total 1557810 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 835579 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 835579 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44644 # number of WriteReq MSHR hits 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+system.cpu.dcache.overall_mshr_miss_latency::total 31717679239 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97793653500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97793653500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2614977500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2614977500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100408631000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100408631000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076536 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076536 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034501 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034501 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858148 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858148 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059726 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077167 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077167 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.399556 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.399556 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42725.860807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42725.860807 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15000.728257 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15000.728257 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20439.399257 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20439.399257 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19118.218692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19118.218692 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.505766 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.505766 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188494.017156 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188494.017156 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.791394 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.791394 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 73546 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 14.805379 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 113695 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 73561 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.545588 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5097093086500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.805379 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.925336 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.925336 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 71018 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.855051 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 110090 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 71033 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.549843 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 197734009500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.855051 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.990941 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.990941 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 451096 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 451096 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 113711 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 113711 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 113711 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 113711 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 113711 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 113711 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74558 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 74558 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74558 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 74558 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74558 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 74558 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 932190000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 932190000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 932190000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 932190000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 932190000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 932190000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 188269 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 188269 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 188269 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 188269 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 188269 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 188269 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.396018 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.396018 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.396018 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.396018 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.396018 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.396018 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12502.883661 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12502.883661 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12502.883661 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12502.883661 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12502.883661 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12502.883661 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 436469 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 436469 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 110104 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 110104 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 110104 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 110104 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 110104 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 110104 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 72087 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 72087 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 72087 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 72087 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 72087 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 72087 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 888705500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 888705500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 888705500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 888705500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 888705500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 888705500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 182191 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 182191 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 182191 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 182191 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 182191 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 182191 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395667 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395667 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395667 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395667 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395667 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395667 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12328.235327 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12328.235327 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12328.235327 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12328.235327 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12328.235327 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12328.235327 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -826,180 +827,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 13222 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 13222 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74558 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74558 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74558 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 74558 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74558 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 74558 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 857632000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 857632000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 857632000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 857632000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 857632000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 857632000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.396018 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.396018 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.396018 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.396018 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.396018 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.396018 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11502.883661 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11502.883661 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11502.883661 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 17880 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 17880 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 72087 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 72087 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 72087 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 72087 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 72087 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 72087 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 816618500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 816618500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 816618500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 816618500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 816618500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 816618500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395667 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395667 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395667 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395667 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11328.235327 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11328.235327 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11328.235327 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 993321 # number of replacements -system.cpu.icache.tags.tagsinuse 508.961085 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8058871 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 993832 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.108887 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147914027500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.961085 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994065 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994065 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10117194 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10117194 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8058871 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8058871 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8058871 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8058871 # number of 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14809433489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14809433489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14809433489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9123291 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9123291 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9123291 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9123291 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9123291 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9123291 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116671 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.116671 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.116671 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.116671 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.116671 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.116671 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13913.148465 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13913.148465 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13913.148465 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13913.148465 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13913.148465 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13913.148465 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6712 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 16 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 348 # number of cycles access was blocked +system.cpu.icache.tags.replacements 972475 # number of replacements +system.cpu.icache.tags.tagsinuse 509.589862 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7892622 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 972987 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.111745 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147937650500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.589862 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995293 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995293 # Average percentage of cache occupancy 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14506630997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14506630997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8932155 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8932155 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8932155 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8932155 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8932155 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8932155 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116381 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116381 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116381 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.116381 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.116381 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.116381 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13954.949960 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13954.949960 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13954.949960 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13954.949960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13954.949960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13954.949960 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6454 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 314 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.287356 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 16 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.554140 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70517 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70517 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70517 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70517 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70517 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70517 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 993903 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 993903 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 993903 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 993903 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 993903 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 993903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13139309991 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13139309991 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13139309991 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13139309991 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13139309991 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13139309991 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108941 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108941 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108941 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108941 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108941 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108941 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13219.911793 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13219.911793 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13219.911793 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13219.911793 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13219.911793 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13219.911793 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66166 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 66166 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 66166 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 66166 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 66166 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 66166 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 973367 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 973367 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 973367 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 973367 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 973367 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 973367 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12880264497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12880264497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12880264497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12880264497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12880264497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12880264497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108973 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108973 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108973 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108973 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13232.690750 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13232.690750 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13232.690750 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13232.690750 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13232.690750 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13232.690750 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 13951 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.067078 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 26495 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 13966 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.897107 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5104644726500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.067078 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.379192 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.379192 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 97508 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 97508 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26495 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26495 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 13962 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.017494 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 24005 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 13975 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.717710 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5100174829000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.017494 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376093 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.376093 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 92555 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 92555 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24014 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 24014 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26497 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26497 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26497 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26497 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14838 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 14838 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14838 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14838 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14838 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14838 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176788000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176788000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176788000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 176788000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176788000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 176788000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41333 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41333 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24016 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 24016 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24016 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 24016 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14841 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 14841 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14841 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 14841 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14841 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 14841 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 170100000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 170100000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 170100000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 170100000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 170100000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 170100000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38855 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 38855 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41335 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41335 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41335 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41335 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.358987 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.358987 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358969 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.358969 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358969 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.358969 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11914.543739 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11914.543739 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11914.543739 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11914.543739 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11914.543739 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11914.543739 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38857 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38857 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38857 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38857 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.381959 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.381959 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.381939 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.381939 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.381939 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.381939 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11461.491813 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11461.491813 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11461.491813 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11461.491813 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11461.491813 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11461.491813 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1008,183 +1009,183 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1499 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1499 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14838 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14838 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14838 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 14838 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14838 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 14838 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 161950000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 161950000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 161950000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 161950000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 161950000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 161950000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.358987 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.358987 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358969 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358969 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358969 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358969 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10914.543739 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10914.543739 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10914.543739 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10914.543739 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10914.543739 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10914.543739 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2319 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2319 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14841 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14841 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14841 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 14841 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14841 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 14841 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 155259000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 155259000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 155259000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 155259000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 155259000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 155259000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.381959 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381959 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381939 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381939 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381939 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10461.491813 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10461.491813 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10461.491813 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10461.491813 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112938 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64810.238427 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4946164 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176935 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.954695 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 112328 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64826.279220 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4884469 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176125 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.732968 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50458.579366 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 20.514879 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139418 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3172.056588 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11158.948175 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.769937 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000313 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50541.510277 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.632944 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.140332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3105.306836 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.688831 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.771202 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000208 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048402 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170272 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.988926 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63997 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3372 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5567 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54302 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.976517 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43925036 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43925036 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1577768 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1577768 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 153927 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 153927 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 977435 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 977435 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 69221 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12891 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1338249 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1420361 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 69221 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12891 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 977435 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1492176 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2551723 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 69221 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12891 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 977435 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1492176 # number of overall hits -system.cpu.l2cache.overall_hits::total 2551723 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1505 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1505 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134154 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134154 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 16363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 70 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35783 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 35858 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 70 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16363 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169937 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 186375 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 70 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16363 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169937 # number of overall misses -system.cpu.l2cache.overall_misses::total 186375 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23274500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 23274500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10328890000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10328890000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1358981500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1358981500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 6541000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 429500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3085479000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3092449500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6541000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 429500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1358981500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13414369000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14780321000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6541000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 429500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1358981500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13414369000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14780321000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 1577768 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1577768 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1814 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1814 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 288081 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 288081 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 993798 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 993798 # number of ReadCleanReq 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of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11643093000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12834592000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5219000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 453000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1185827000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11643093000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12834592000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90257448500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90257448500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2455427500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2455427500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 92712876000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 92712876000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.829658 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.829658 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.465682 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.465682 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016463 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016463 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.001010 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000388 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026039 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024621 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001010 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000388 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016463 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102239 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.068065 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001010 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000388 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016463 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102239 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.068065 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21326.910299 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21326.910299 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66992.784412 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66992.784412 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73054.275411 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73054.275411 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 75900 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76270.829257 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76284.779941 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73054.275411 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68946.255289 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69312.522469 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73054.275411 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68946.255289 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69312.522469 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.288562 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.288562 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176824.996412 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176824.996412 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150318.867998 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150318.867998 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.847651 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.847651 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463964 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463964 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026098 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024742 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102180 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068536 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000930 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016682 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102180 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068536 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21184.770437 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21184.770437 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66967.446512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66967.446512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73063.894023 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73063.894023 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 75500 # average ReadSharedReq mshr miss latency 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latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73063.894023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68815.046633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69192.532252 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.497472 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.497472 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176993.260290 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176993.260290 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.259287 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.259287 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 602920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3061153 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1727529 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1124352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 288090 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288090 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 993903 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1464872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 602896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3032324 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13873 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13873 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1727482 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1093519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2562 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2562 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 973367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1456602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1641 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2979851 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6223737 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 32716 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 177236 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9413540 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63603072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208211079 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 921280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5280832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278016263 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 218468 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6317764 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.033210 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179185 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917513 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6205490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31703 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168231 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9322937 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62267648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207474745 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 922624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5343616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 276008633 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 220316 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6258702 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.033424 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.179742 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 6107951 96.68% 96.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 209813 3.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6049509 96.66% 96.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 209193 3.34% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6317764 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4638715490 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6258702 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4609709481 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 577500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1492354491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1461362367 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3105124685 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3096027096 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 22263487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 22269484 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 111892387 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 108175907 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 222126 # Transaction distribution -system.iobus.trans_dist::ReadResp 222126 # Transaction distribution -system.iobus.trans_dist::WriteReq 57753 # Transaction distribution -system.iobus.trans_dist::WriteResp 57753 # Transaction distribution -system.iobus.trans_dist::MessageReq 1650 # Transaction distribution -system.iobus.trans_dist::MessageResp 1650 # Transaction distribution +system.iobus.trans_dist::ReadReq 222102 # Transaction distribution +system.iobus.trans_dist::ReadResp 222102 # Transaction distribution +system.iobus.trans_dist::WriteReq 57708 # Transaction distribution +system.iobus.trans_dist::WriteResp 57708 # Transaction distribution +system.iobus.trans_dist::MessageReq 1641 # Transaction distribution +system.iobus.trans_dist::MessageResp 1641 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -1383,15 +1384,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 464488 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 464350 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95270 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95270 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3300 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 563058 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3282 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3282 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 562902 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -1407,19 +1408,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 238530 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 238452 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027864 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6600 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6600 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3272994 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3933000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3272880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3911656 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1449,25 +1450,25 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 242643106 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 242679087 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 453455000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 453362000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 50182000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1650000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1641000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47580 # number of replacements -system.iocache.tags.tagsinuse 0.177808 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.091366 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47596 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4993210705000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.177808 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.011113 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.011113 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4993241946000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091366 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005710 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005710 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1481,14 +1482,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 915 system.iocache.demand_misses::total 915 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 915 # number of overall misses system.iocache.overall_misses::total 915 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142818702 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 142818702 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5513453404 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5513453404 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 142818702 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 142818702 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 142818702 # number of overall miss cycles -system.iocache.overall_miss_latency::total 142818702 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143595677 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 143595677 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5513463410 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5513463410 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 143595677 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 143595677 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 143595677 # number of overall miss cycles +system.iocache.overall_miss_latency::total 143595677 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) @@ -1505,19 +1506,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156086.013115 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 156086.013115 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.560873 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118010.560873 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156086.013115 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 156086.013115 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156086.013115 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 156086.013115 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 218 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 156935.166120 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.775043 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118010.775043 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 156935.166120 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156935.166120 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 156935.166120 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 18 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.111111 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1531,14 +1532,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 915 system.iocache.demand_mshr_misses::total 915 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 915 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 915 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97068702 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 97068702 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3177453404 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3177453404 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97068702 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 97068702 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97068702 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 97068702 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 97845677 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3177463410 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3177463410 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 97845677 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97845677 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 97845677 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1547,81 +1548,81 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 106086.013115 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.560873 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.560873 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 106086.013115 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 106086.013115 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 106935.166120 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.775043 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.775043 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 106935.166120 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 602920 # Transaction distribution -system.membus.trans_dist::ReadResp 656038 # Transaction distribution -system.membus.trans_dist::WriteReq 13934 # Transaction distribution -system.membus.trans_dist::WriteResp 13934 # Transaction distribution -system.membus.trans_dist::Writeback 149751 # Transaction distribution -system.membus.trans_dist::CleanEvict 10203 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2209 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1791 # Transaction distribution -system.membus.trans_dist::ReadExReq 133869 # Transaction distribution -system.membus.trans_dist::ReadExResp 133868 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 53130 # Transaction distribution -system.membus.trans_dist::MessageReq 1650 # Transaction distribution -system.membus.trans_dist::MessageResp 1650 # Transaction distribution -system.membus.trans_dist::BadAddressError 12 # Transaction distribution +system.membus.trans_dist::ReadReq 602896 # Transaction distribution +system.membus.trans_dist::ReadResp 655806 # Transaction distribution +system.membus.trans_dist::WriteReq 13873 # Transaction distribution +system.membus.trans_dist::WriteResp 13873 # Transaction distribution +system.membus.trans_dist::Writeback 149464 # Transaction distribution +system.membus.trans_dist::CleanEvict 9883 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2535 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2080 # Transaction distribution +system.membus.trans_dist::ReadExReq 133195 # Transaction distribution +system.membus.trans_dist::ReadExResp 133194 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 52918 # Transaction distribution +system.membus.trans_dist::MessageReq 1641 # Transaction distribution +system.membus.trans_dist::MessageResp 1641 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464488 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 488383 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 24 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1722115 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1867232 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238530 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538437 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18462656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20239623 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3282 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3282 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464350 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 486631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1720185 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1865287 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6564 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6564 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238452 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538373 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18388288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20165113 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23261263 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1586 # Total snoops (count) -system.membus.snoop_fanout::samples 1014957 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001626 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.040287 # Request fanout histogram +system.membus.pkt_size::total 23186717 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1616 # Total snoops (count) +system.membus.snoop_fanout::samples 1013692 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001619 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.040202 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1013307 99.84% 99.84% # Request fanout histogram -system.membus.snoop_fanout::2 1650 0.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 1012051 99.84% 99.84% # Request fanout histogram +system.membus.snoop_fanout::2 1641 0.16% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 1014957 # Request fanout histogram -system.membus.reqLayer0.occupancy 355040500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1013692 # Request fanout histogram +system.membus.reqLayer0.occupancy 354973500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 388549500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 388325000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3300000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3282000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1018755770 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1016908044 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1650000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1641000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2209187226 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2204699193 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 86115345 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 86072153 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index bea975397..d7ee3e6f6 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -29,7 +29,7 @@ mem_ranges=0:134217727 memories=system.physmem mmap_using_noreserve=false num_work_ids=16 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -134,7 +134,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -184,7 +184,7 @@ system=system port=system.toL2Bus.slave[3] [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -1220,7 +1220,7 @@ master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_b slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 @@ -1255,7 +1255,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -1639,7 +1639,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1662,7 +1662,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json index 6fe40cc4f..6cc193075 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json @@ -2,7 +2,7 @@ "name": null, "sim_quantum": 0, "system": { - "kernel": "/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9", + "kernel": "/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9", "mmap_using_noreserve": false, "kernel_addr_check": true, "bridge": { @@ -111,7 +111,7 @@ "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, "response_latency": 20, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 4194304, "tags": { "name": "tags", @@ -145,11 +145,11 @@ "prefetch_on_access": false, "path": "system.l2c", "name": "l2c", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 8 }, - "readfile": "/work/gem5/outgoing/gem5/tests/halt.sh", + "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", "intel_mp_table": { "oem_table_addr": 0, "name": "intel_mp_table", @@ -638,7 +638,7 @@ "clk_domain": "system.clk_domain", "write_buffers": 8, "response_latency": 50, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 1024, "tags": { "name": "tags", @@ -672,7 +672,7 @@ "prefetch_on_access": false, "path": "system.iocache", "name": "iocache", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 8 }, @@ -1183,7 +1183,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks0.image.child", - "image_file": "/work/gem5/dist/disks/linux-x86.img", + "image_file": "/scratch/nilay/GEM5/system/disks/linux-x86.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks0.image", @@ -1211,7 +1211,7 @@ "eventq_index": 0, "cxx_class": "RawDiskImage", "path": "system.pc.south_bridge.ide.disks1.image.child", - "image_file": "/work/gem5/dist/disks/linux-bigswap2.img", + "image_file": "/scratch/nilay/GEM5/system/disks/linux-bigswap2.img", "type": "RawDiskImage" }, "path": "system.pc.south_bridge.ide.disks1.image", @@ -1797,7 +1797,7 @@ "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, "response_latency": 2, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", @@ -1831,7 +1831,7 @@ "prefetch_on_access": false, "path": "system.cpu0.icache", "name": "icache", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 1 }, @@ -1906,7 +1906,7 @@ "clk_domain": "system.cpu_clk_domain", "write_buffers": 8, "response_latency": 2, - "cxx_class": "BaseCache", + "cxx_class": "Cache", "size": 32768, "tags": { "name": "tags", @@ -1940,7 +1940,7 @@ "prefetch_on_access": false, "path": "system.cpu0.dcache", "name": "dcache", - "type": "BaseCache", + "type": "Cache", "sequential_access": false, "assoc": 4 }, diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index 69801740a..fb8fdc7fa 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -4,6 +4,7 @@ warn: Sockets disabled, not accepting gdb connections warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. warn: x86 cpuid: unknown family 0xbacc +warn: x86 cpuid: unknown family 0xbacc WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -21,24 +22,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 6 -WARNING: Bank is already active! -Command: 0, Timestamp: 7107, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 12359, Bank: 3 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 10565, Bank: 5 -WARNING: Bank is already active! -Command: 0, Timestamp: 7170, Bank: 1 +Command: 0, Timestamp: 7191, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 2 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -52,7 +43,7 @@ Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 7090, Bank: 1 +Command: 0, Timestamp: 6675, Bank: 2 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -61,6 +52,20 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 6767, Bank: 1 +WARNING: Bank is already active! +Command: 0, Timestamp: 6921, Bank: 6 +WARNING: Bank is already active! +Command: 0, Timestamp: 11289, Bank: 4 +WARNING: Bank is already active! +Command: 0, Timestamp: 7232, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 11338, Bank: 4 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -77,26 +82,24 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: Tried to clear PCI interrupt 14 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: Unknown mouse command 0xe1. WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: instruction 'wbinvd' unimplemented +warn: Tried to clear PCI interrupt 14 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: Unknown mouse command 0xe1. +warn: instruction 'wbinvd' unimplemented WARNING: Bank is already active! -Command: 0, Timestamp: 10421, Bank: 2 -WARNING: Bank is already active! -Command: 0, Timestamp: 9326, Bank: 7 +Command: 0, Timestamp: 7075, Bank: 7 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 6448, Bank: 0 +Command: 0, Timestamp: 6474, Bank: 4 WARNING: Bank is already active! -Command: 0, Timestamp: 6590, Bank: 6 +Command: 0, Timestamp: 6837, Bank: 6 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index ba1f8e728..494bbffd2 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,156 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.141168 # Number of seconds simulated -sim_ticks 5141168437500 # Number of ticks simulated -final_tick 5141168437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137726 # Number of seconds simulated +sim_ticks 5137726358500 # Number of ticks simulated +final_tick 5137726358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195369 # Simulator instruction rate (inst/s) -host_op_rate 388397 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4114294038 # Simulator tick rate (ticks/s) -host_mem_usage 1021404 # Number of bytes of host memory used -host_seconds 1249.59 # Real time elapsed on the host -sim_insts 244131065 # Number of instructions simulated -sim_ops 485336254 # Number of ops (including micro ops) simulated +host_inst_rate 193743 # Simulator instruction rate (inst/s) +host_op_rate 385165 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4079424438 # Simulator tick rate (ticks/s) +host_mem_usage 1056160 # Number of bytes of host memory used +host_seconds 1259.42 # Real time elapsed on the host +sim_insts 244004222 # Number of instructions simulated +sim_ops 485086710 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 377472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4958144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 201472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2034880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 383296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3456256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 380096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4972288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 215232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2058496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 369024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3382272 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11442624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 377472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 201472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 383296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 962240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9198208 # Number of bytes written to this memory -system.physmem.bytes_written::total 9198208 # Number of bytes written to this memory +system.physmem.bytes_read::total 11408192 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 380096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 215232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 369024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9193728 # Number of bytes written to this memory +system.physmem.bytes_written::total 9193728 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 5898 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 77471 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3148 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 31795 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 37 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 54004 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 5939 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 77692 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 32164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 33 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5766 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 52848 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178791 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143722 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143722 # Number of write requests responded to by this memory +system.physmem.num_reads::total 178253 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143652 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143652 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 73421 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 964400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 39188 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 395801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 74554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 672271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2225685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 73421 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 39188 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 74554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1789128 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1789128 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1789128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 73981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 967799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 41892 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 400663 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 71826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 658321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2220475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 73981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 41892 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 71826 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 187700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1789455 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1789455 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1789455 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 73421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 964400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 39188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 395801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 74554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 672271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4014813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 95417 # Number of read requests accepted -system.physmem.writeReqs 81462 # Number of write requests accepted -system.physmem.readBursts 95417 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 81462 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6099840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue -system.physmem.bytesWritten 5213440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6106688 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5213568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 73981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 967799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 41892 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 400663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 71826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 658321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4009929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 94617 # Number of read requests accepted +system.physmem.writeReqs 88760 # Number of write requests accepted +system.physmem.readBursts 94617 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 88760 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6047936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 5680640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6055488 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5680640 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 21330 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6364 # Per bank write bursts -system.physmem.perBankRdBursts::1 5596 # Per bank write bursts -system.physmem.perBankRdBursts::2 5691 # Per bank write bursts -system.physmem.perBankRdBursts::3 5690 # Per bank write bursts -system.physmem.perBankRdBursts::4 6222 # Per bank write bursts -system.physmem.perBankRdBursts::5 5617 # Per bank write bursts -system.physmem.perBankRdBursts::6 5512 # Per bank write bursts -system.physmem.perBankRdBursts::7 5018 # Per bank write bursts -system.physmem.perBankRdBursts::8 6455 # Per bank write bursts -system.physmem.perBankRdBursts::9 6386 # Per bank write bursts -system.physmem.perBankRdBursts::10 5929 # Per bank write bursts -system.physmem.perBankRdBursts::11 5798 # Per bank write bursts -system.physmem.perBankRdBursts::12 5744 # Per bank write bursts -system.physmem.perBankRdBursts::13 6558 # Per bank write bursts -system.physmem.perBankRdBursts::14 6049 # Per bank write bursts -system.physmem.perBankRdBursts::15 6681 # Per bank write bursts -system.physmem.perBankWrBursts::0 5937 # Per bank write bursts -system.physmem.perBankWrBursts::1 5551 # Per bank write bursts -system.physmem.perBankWrBursts::2 4927 # Per bank write bursts -system.physmem.perBankWrBursts::3 4762 # Per bank write bursts -system.physmem.perBankWrBursts::4 5737 # Per bank write bursts -system.physmem.perBankWrBursts::5 5264 # Per bank write bursts -system.physmem.perBankWrBursts::6 5028 # Per bank write bursts -system.physmem.perBankWrBursts::7 4496 # Per bank write bursts -system.physmem.perBankWrBursts::8 4483 # Per bank write bursts -system.physmem.perBankWrBursts::9 4823 # Per bank write bursts -system.physmem.perBankWrBursts::10 4660 # Per bank write bursts -system.physmem.perBankWrBursts::11 4592 # Per bank write bursts -system.physmem.perBankWrBursts::12 4759 # Per bank write bursts -system.physmem.perBankWrBursts::13 5475 # Per bank write bursts -system.physmem.perBankWrBursts::14 5045 # Per bank write bursts -system.physmem.perBankWrBursts::15 5921 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 28899 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6147 # Per bank write bursts +system.physmem.perBankRdBursts::1 5269 # Per bank write bursts +system.physmem.perBankRdBursts::2 5685 # Per bank write bursts +system.physmem.perBankRdBursts::3 5978 # Per bank write bursts +system.physmem.perBankRdBursts::4 5788 # Per bank write bursts +system.physmem.perBankRdBursts::5 5231 # Per bank write bursts +system.physmem.perBankRdBursts::6 5218 # Per bank write bursts +system.physmem.perBankRdBursts::7 5097 # Per bank write bursts +system.physmem.perBankRdBursts::8 6282 # Per bank write bursts +system.physmem.perBankRdBursts::9 6366 # Per bank write bursts +system.physmem.perBankRdBursts::10 6408 # Per bank write bursts +system.physmem.perBankRdBursts::11 6175 # Per bank write bursts +system.physmem.perBankRdBursts::12 5716 # Per bank write bursts +system.physmem.perBankRdBursts::13 6642 # Per bank write bursts +system.physmem.perBankRdBursts::14 6153 # Per bank write bursts +system.physmem.perBankRdBursts::15 6344 # Per bank write bursts +system.physmem.perBankWrBursts::0 6191 # Per bank write bursts +system.physmem.perBankWrBursts::1 5213 # Per bank write bursts +system.physmem.perBankWrBursts::2 6082 # Per bank write bursts +system.physmem.perBankWrBursts::3 5966 # Per bank write bursts +system.physmem.perBankWrBursts::4 5232 # Per bank write bursts +system.physmem.perBankWrBursts::5 5147 # Per bank write bursts +system.physmem.perBankWrBursts::6 4857 # Per bank write bursts +system.physmem.perBankWrBursts::7 4466 # Per bank write bursts +system.physmem.perBankWrBursts::8 5491 # Per bank write bursts +system.physmem.perBankWrBursts::9 5559 # Per bank write bursts +system.physmem.perBankWrBursts::10 5838 # Per bank write bursts +system.physmem.perBankWrBursts::11 5586 # Per bank write bursts +system.physmem.perBankWrBursts::12 5717 # Per bank write bursts +system.physmem.perBankWrBursts::13 5929 # Per bank write bursts +system.physmem.perBankWrBursts::14 5787 # Per bank write bursts +system.physmem.perBankWrBursts::15 5699 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 5140168291000 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 5136593386000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 95417 # Read request sizes (log2) +system.physmem.readPktSize::6 94617 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 81462 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 89319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 88760 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 87985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -165,989 +161,996 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 70 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 53 # 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What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 41697 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 281.270307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.374177 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.197981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16587 39.78% 39.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10275 24.64% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4266 10.23% 74.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2445 5.86% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1622 3.89% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1132 2.71% 87.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 786 1.89% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 680 1.63% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3904 9.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 41697 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4370 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.624485 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 178.940609 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4367 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4254 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4254 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.149036 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.343940 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.936401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 69 1.62% 1.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.16% 1.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.02% 1.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 8 0.19% 2.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3652 85.85% 87.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 58 1.36% 89.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 99 2.33% 91.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 64 1.50% 93.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 41 0.96% 94.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 93 2.19% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 12 0.28% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.19% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 11 0.26% 96.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.09% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.14% 97.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.05% 97.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 101 2.37% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.07% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.14% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4254 # Writes before turning the bus around for reads -system.physmem.totQLat 1082376548 # Total ticks spent queuing -system.physmem.totMemAccLat 2869439048 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 476550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11356.38 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4370 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4370 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.311213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.106663 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.785732 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 51 1.17% 1.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 5 0.11% 1.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.02% 1.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 8 0.18% 1.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3654 83.62% 85.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 60 1.37% 86.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 119 2.72% 89.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 59 1.35% 90.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 85 1.95% 92.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 116 2.65% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.30% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.11% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.21% 95.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.07% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.05% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.09% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 133 3.04% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.09% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.14% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.07% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.07% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.23% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4370 # Writes before turning the bus around for reads +system.physmem.totQLat 1101479246 # Total ticks spent queuing +system.physmem.totMemAccLat 2873335496 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 472495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11655.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30106.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30405.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.18 # Average write queue length when enqueuing -system.physmem.readRowHits 76603 # Number of row buffer hits during reads -system.physmem.writeRowHits 58733 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.10 # Row buffer hit rate for writes -system.physmem.avgGap 29060364.94 # Average gap between requests -system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 152447400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82937250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 356538000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 270228960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250406807040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 95253368040 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2241273741750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2587796068440 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.867367 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3687953773966 # Time in different power states -system.physmem_0.memoryStateTime::REF 128019840000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.15 # Average write queue length when enqueuing +system.physmem.readRowHits 75876 # Number of row buffer hits during reads +system.physmem.writeRowHits 65681 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes +system.physmem.avgGap 28011110.37 # Average gap between requests +system.physmem.pageHitRate 77.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 153536040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 83535375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 346421400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 279618480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250238982240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94990329855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2239672524000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2585764947390 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.869445 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3685813216724 # Time in different power states +system.physmem_0.memoryStateTime::REF 127934040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18290517534 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17956780776 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 160786080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 87503625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 386872200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 257631840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250406807040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95642577720 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2237948975250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2584891153755 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.974840 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3687413088990 # Time in different power states -system.physmem_1.memoryStateTime::REF 128019840000 # Time in different power states +system.physmem_1.actEnergy 161655480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 87978000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 390663000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 295410240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250238982240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95244065640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2234394426750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2580813181350 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.044329 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3685435461238 # Time in different power states +system.physmem_1.memoryStateTime::REF 127934040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18838516010 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18309070012 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 818622179 # number of cpu cycles simulated +system.cpu0.numCycles 810473886 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 70465386 # Number of instructions committed -system.cpu0.committedOps 143948929 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 131896754 # Number of integer alu accesses +system.cpu0.committedInsts 70312072 # Number of instructions committed +system.cpu0.committedOps 143658243 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 131612768 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 904463 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13997547 # number of instructions that are conditional controls -system.cpu0.num_int_insts 131896754 # number of integer instructions +system.cpu0.num_func_calls 897074 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13988759 # number of instructions that are conditional controls +system.cpu0.num_int_insts 131612768 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 241558700 # number of times the integer registers were read -system.cpu0.num_int_register_writes 113520418 # number of times the integer registers were written +system.cpu0.num_int_register_reads 240911367 # number of times the integer registers were read +system.cpu0.num_int_register_writes 113282572 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 82096977 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 54912679 # number of times the CC registers were written -system.cpu0.num_mem_refs 13231012 # number of memory refs -system.cpu0.num_load_insts 9870869 # Number of load instructions -system.cpu0.num_store_insts 3360143 # Number of store instructions -system.cpu0.num_idle_cycles 776995348.800534 # Number of idle cycles -system.cpu0.num_busy_cycles 41626830.199466 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050850 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949150 # Percentage of idle cycles -system.cpu0.Branches 15238298 # Number of branches fetched -system.cpu0.op_class::No_OpClass 84207 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 130532761 90.68% 90.74% # Class of executed instruction -system.cpu0.op_class::IntMult 57038 0.04% 90.78% # Class of executed instruction -system.cpu0.op_class::IntDiv 45915 0.03% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.81% # Class of executed instruction -system.cpu0.op_class::MemRead 9869228 6.86% 97.67% # Class of executed instruction -system.cpu0.op_class::MemWrite 3360143 2.33% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82064957 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 54880945 # number of times the CC registers were written +system.cpu0.num_mem_refs 13139441 # number of memory refs +system.cpu0.num_load_insts 9809284 # Number of load instructions +system.cpu0.num_store_insts 3330157 # Number of store instructions +system.cpu0.num_idle_cycles 769348747.137634 # Number of idle cycles +system.cpu0.num_busy_cycles 41125138.862366 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050742 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949258 # Percentage of idle cycles +system.cpu0.Branches 15218344 # Number of branches fetched +system.cpu0.op_class::No_OpClass 83498 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 130336285 90.73% 90.78% # Class of executed instruction +system.cpu0.op_class::IntMult 55624 0.04% 90.82% # Class of executed instruction +system.cpu0.op_class::IntDiv 45353 0.03% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.85% # Class of executed instruction +system.cpu0.op_class::MemRead 9807642 6.83% 97.68% # Class of executed instruction +system.cpu0.op_class::MemWrite 3330157 2.32% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143949292 # Class of executed instruction +system.cpu0.op_class::total 143658559 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1638295 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999362 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19673231 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1638807 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.004605 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1637472 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999430 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19610556 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1637984 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.972373 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 232.517984 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 254.861534 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 24.619844 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.454137 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.497776 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.048086 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 233.382237 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 253.425972 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 25.191221 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.455825 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.494973 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.049202 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88575778 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88575778 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4693238 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2575592 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4254114 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11522944 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3236162 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1812970 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3039112 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8088244 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19748 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10138 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30323 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 60209 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7929400 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4388562 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7293226 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19611188 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7949148 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4398700 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7323549 # number of overall hits -system.cpu0.dcache.overall_hits::total 19671397 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 340869 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 165985 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 824524 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1331378 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 120523 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 67710 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 137190 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 325423 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 143877 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 63954 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 198209 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406040 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 461392 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 233695 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 961714 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1656801 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 605269 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 297649 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1159923 # number of overall misses -system.cpu0.dcache.overall_misses::total 2062841 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2308605500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12073522500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14382128000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2733996493 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4762162878 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7496159371 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5042601993 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 16835685378 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 21878287371 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5042601993 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 16835685378 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 21878287371 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5034107 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2741577 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 5078638 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12854322 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3356685 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1880680 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3176302 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8413667 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 163625 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 74092 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 228532 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466249 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8390792 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4622257 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 8254940 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21267989 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8554417 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4696349 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8483472 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21734238 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067712 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060544 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.162351 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.103574 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.035905 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.036003 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.043192 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038678 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.879309 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.863170 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.867314 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.870865 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.054988 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050559 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116502 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.077901 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070755 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063379 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.136727 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.094912 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13908.518842 # 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average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14951.447648 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10957.118282 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40077.926340 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 34179.028942 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 22816.612756 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21674.898218 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17683.706409 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13292.174846 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16930.170830 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14674.165734 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 10671.398817 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 195153 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 23048 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 22760 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.591678 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.574385 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1547778 # number of writebacks -system.cpu0.dcache.writebacks::total 1547778 # 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average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14564.900232 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20354.485766 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18370.866933 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18963.748409 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19163.136607 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17344.086440 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17864.262635 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164538.245286 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 162011.647080 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163213.720165 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177659.963986 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200289.863734 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 190256.220892 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164769.126780 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162777.138213 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163723.644922 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 1547245 # number of writebacks +system.cpu0.dcache.writebacks::total 1547245 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 49 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 383157 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 383206 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1554 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32300 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 33854 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1603 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 415457 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 417060 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1603 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 415457 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 417060 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 163145 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 438935 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 602080 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 67710 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 103870 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 171580 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 65147 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 193119 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 258266 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 230855 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 542805 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 773660 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 296002 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 735924 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1031926 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 186313 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 204652 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 390965 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3641 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 3691 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 7332 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 189954 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 208343 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 398297 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2099080000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5941231000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8040311000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2625649990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3973863872 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6599513862 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 969909500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2805652000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3775561500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4724729990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9915094872 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14639824862 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5694639490 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12720746872 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 18415386362 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30666876000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33145024000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63811900000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 650679500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 751025500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1401705000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31317555500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33896049500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65213605000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060310 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085775 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.047056 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036227 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032336 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.020407 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.868291 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.849390 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.553932 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050470 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065167 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.036489 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063668 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086004 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.047622 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12866.345889 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13535.559935 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13354.223691 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38777.876089 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38258.052104 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38463.188379 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14888.014797 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14528.099255 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14618.887116 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20466.223344 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18266.402984 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18922.814753 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19238.516936 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17285.408374 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17845.646260 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164598.691449 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 161957.977445 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163216.400445 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178709.008514 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 203474.803576 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 191176.350245 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 164869.155164 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162693.488622 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163731.097648 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 878679 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.838296 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 128369666 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 879191 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 146.008849 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149037485500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 260.884696 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 143.250304 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 106.703296 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.509540 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.279786 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.208405 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997731 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 865313 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.808042 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 127930489 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 865825 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 147.755596 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 149027837500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 256.241174 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 140.482462 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 114.084406 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.500471 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.274380 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.222821 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997672 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 130155694 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 130155694 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 85680859 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39485533 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3203274 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 128369666 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 85680859 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39485533 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3203274 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 128369666 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 85680859 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39485533 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3203274 # number of overall hits -system.cpu0.icache.overall_hits::total 128369666 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 290083 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 179832 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 436911 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 906826 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 290083 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 179832 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 436911 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 906826 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 290083 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 179832 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 436911 # number of overall misses -system.cpu0.icache.overall_misses::total 906826 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2559612500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6034803488 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8594415988 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2559612500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 6034803488 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8594415988 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2559612500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 6034803488 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8594415988 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 85970942 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39665365 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3640185 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 129276492 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 85970942 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39665365 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3640185 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 129276492 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 85970942 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39665365 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3640185 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 129276492 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003374 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004534 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.120024 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.007015 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003374 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004534 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.120024 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.007015 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003374 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004534 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.120024 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.007015 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.353908 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.432024 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9477.469755 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14233.353908 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.432024 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9477.469755 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14233.353908 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.432024 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9477.469755 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5682 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 129687214 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 129687214 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 85494784 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 39252405 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3183300 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 127930489 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 85494784 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 39252405 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3183300 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 127930489 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 85494784 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 39252405 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3183300 # number of overall hits +system.cpu0.icache.overall_hits::total 127930489 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 295547 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 174112 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 421231 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 890890 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 295547 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 174112 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 421231 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 890890 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 295547 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 174112 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 421231 # number of overall misses +system.cpu0.icache.overall_misses::total 890890 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2498575500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5836919481 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8335494981 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2498575500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5836919481 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8335494981 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2498575500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5836919481 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8335494981 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 85790331 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39426517 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3604531 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 128821379 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 85790331 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39426517 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3604531 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 128821379 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 85790331 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39426517 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3604531 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 128821379 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003445 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004416 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116862 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006916 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003445 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004416 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116862 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006916 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003445 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004416 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116862 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006916 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14350.392276 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13856.813675 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9356.368329 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14350.392276 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13856.813675 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9356.368329 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14350.392276 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13856.813675 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9356.368329 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4826 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 315 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 303 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.038095 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.927393 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 27624 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 27624 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 27624 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 27624 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 27624 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 27624 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 179832 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 409287 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 589119 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 179832 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 409287 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 589119 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 179832 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 409287 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 589119 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2379780500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5367751488 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7747531988 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2379780500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5367751488 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7747531988 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2379780500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5367751488 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7747531988 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004534 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.112436 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004557 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004534 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.112436 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004557 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004534 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.112436 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004557 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13233.353908 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13114.883903 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13151.047561 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13233.353908 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13114.883903 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13151.047561 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13233.353908 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13114.883903 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13151.047561 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 25055 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 25055 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 25055 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 25055 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 25055 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 25055 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 174112 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 396176 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 570288 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 174112 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 396176 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 570288 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 174112 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 396176 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 570288 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2324463500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5197379983 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7521843483 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2324463500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5197379983 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7521843483 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2324463500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5197379983 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7521843483 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004416 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.109911 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004427 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004416 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.109911 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004427 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004416 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.109911 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004427 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13350.392276 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13118.866320 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13189.552442 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13350.392276 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13118.866320 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13189.552442 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13350.392276 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13118.866320 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13189.552442 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2607160707 # number of cpu cycles simulated +system.cpu1.numCycles 2606018119 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35907928 # Number of instructions committed -system.cpu1.committedOps 69695660 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64757843 # Number of integer alu accesses +system.cpu1.committedInsts 35722790 # Number of instructions committed +system.cpu1.committedOps 69377917 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64437935 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 501298 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6590213 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64757843 # number of integer instructions +system.cpu1.num_func_calls 498036 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6548156 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64437935 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 119979371 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55719008 # number of times the integer registers were written +system.cpu1.num_int_register_reads 119381439 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55453390 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36729292 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27266794 # number of times the CC registers were written -system.cpu1.num_mem_refs 4880817 # number of memory refs -system.cpu1.num_load_insts 2999293 # Number of load instructions -system.cpu1.num_store_insts 1881524 # Number of store instructions -system.cpu1.num_idle_cycles 2477690884.667310 # Number of idle cycles -system.cpu1.num_busy_cycles 129469822.332690 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049659 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950341 # Percentage of idle cycles -system.cpu1.Branches 7272679 # Number of branches fetched -system.cpu1.op_class::No_OpClass 37847 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64724112 92.87% 92.92% # Class of executed instruction -system.cpu1.op_class::IntMult 30276 0.04% 92.96% # Class of executed instruction -system.cpu1.op_class::IntDiv 24690 0.04% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.00% # Class of executed instruction -system.cpu1.op_class::MemRead 2997578 4.30% 97.30% # Class of executed instruction -system.cpu1.op_class::MemWrite 1881524 2.70% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36402445 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27104510 # number of times the CC registers were written +system.cpu1.num_mem_refs 4834095 # number of memory refs +system.cpu1.num_load_insts 2964009 # Number of load instructions +system.cpu1.num_store_insts 1870086 # Number of store instructions +system.cpu1.num_idle_cycles 2478102522.985643 # Number of idle cycles +system.cpu1.num_busy_cycles 127915596.014357 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049085 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950915 # Percentage of idle cycles +system.cpu1.Branches 7225753 # Number of branches fetched +system.cpu1.op_class::No_OpClass 35671 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64456455 92.91% 92.96% # Class of executed instruction +system.cpu1.op_class::IntMult 31131 0.04% 93.00% # Class of executed instruction +system.cpu1.op_class::IntDiv 22623 0.03% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.03% # Class of executed instruction +system.cpu1.op_class::MemRead 2962280 4.27% 97.30% # Class of executed instruction +system.cpu1.op_class::MemWrite 1870086 2.70% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69696027 # Class of executed instruction +system.cpu1.op_class::total 69378246 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29601973 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29601973 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 343203 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26791839 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 26086008 # Number of BTB hits +system.cpu2.branchPred.lookups 29560975 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29560975 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 321330 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26625449 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 26036610 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.365500 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 612615 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 69103 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155854675 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.788435 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 603794 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 66654 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155113045 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 11239570 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 145909603 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29601973 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26698623 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 143043279 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 717621 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 104333 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 8734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9529 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 59780 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 573 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3640195 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 178301 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3755 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 154823972 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.854554 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.033337 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 11047280 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 145686023 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29560975 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26640404 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 142542790 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 677515 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 104928 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 5475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8867 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 68985 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 22 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 511 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3604542 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 166149 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3283 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154116964 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.860489 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.036370 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 98922650 63.89% 63.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 904691 0.58% 64.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23796776 15.37% 79.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 606779 0.39% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 848220 0.55% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 866864 0.56% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 584872 0.38% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 770506 0.50% 82.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27522614 17.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 98277439 63.77% 63.77% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 921613 0.60% 64.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23771065 15.42% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 603849 0.39% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 843324 0.55% 80.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 864608 0.56% 81.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 573617 0.37% 81.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 772001 0.50% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27489448 17.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 154823972 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189933 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.936190 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10345115 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 94152716 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23674012 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5064791 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 359462 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 284127567 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 359462 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12498058 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76923279 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4647064 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 26307426 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12860875 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 282811276 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 202798 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5895071 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 49763 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4757971 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 337796416 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 617680837 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 379222279 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 178 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 324911571 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12884845 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 166150 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 167782 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24657180 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6871363 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3845087 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 401055 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 322271 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 280748481 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 429304 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278478009 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 108269 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 9486120 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 14384377 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 66849 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 154823972 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.798675 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.397594 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154116964 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.190577 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.939225 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10113688 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 93745988 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 23732554 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5061206 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 339409 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283817902 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 339409 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12262766 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76655623 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4610961 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 26368994 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12755160 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 282570010 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 203292 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5910187 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 59652 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4622392 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 337562699 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 617313701 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 378956511 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 176 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 325317107 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12245592 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 169706 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 171154 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 24674635 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6903065 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3842483 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 404867 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 342392 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 280633357 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 431682 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 278499537 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 103065 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 9014489 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 13791367 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 66778 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154116964 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.807066 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.400549 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 91620637 59.18% 59.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5352321 3.46% 62.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3836914 2.48% 65.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3858930 2.49% 67.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22596079 14.59% 82.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2789392 1.80% 84.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24067258 15.54% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 479282 0.31% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 223159 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 90926640 59.00% 59.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5330208 3.46% 62.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3853102 2.50% 64.96% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3864237 2.51% 67.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22585971 14.66% 82.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2780196 1.80% 83.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 24046184 15.60% 99.53% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 494962 0.32% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 235464 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 154823972 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154116964 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1768977 86.18% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 219653 10.70% 96.88% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 63974 3.12% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1774419 86.10% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.10% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 221659 10.76% 96.86% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 64684 3.14% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 83002 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 267565718 96.08% 96.11% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 58655 0.02% 96.13% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 54123 0.02% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 92 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.15% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 7168633 2.57% 98.73% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3547786 1.27% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 87958 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 267524922 96.06% 96.09% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 58980 0.02% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 56493 0.02% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 63 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 7208859 2.59% 98.72% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3562262 1.28% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278478009 # Type of FU issued -system.cpu2.iq.rate 1.786780 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2052604 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007371 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 713940607 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 290668150 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 276821518 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 256 # Number of floating instruction queue reads +system.cpu2.iq.FU_type_0::total 278499537 # Type of FU issued +system.cpu2.iq.rate 1.795462 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2060762 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007400 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 713279610 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 290083917 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 276907807 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 255 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 236 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 280447483 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 128 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 731517 # Number of loads that had data forwarded from stores +system.cpu2.iq.fp_inst_queue_wakeup_accesses 101 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 280472218 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 123 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 745560 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1286395 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6167 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5109 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 663777 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1225052 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5875 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5188 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 625672 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 750358 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 29268 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 750058 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 26954 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 359462 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70735218 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 3134704 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 281177785 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 44449 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6871363 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3845087 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 251829 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 166997 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2638299 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5109 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 196795 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 202269 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 399064 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 277848009 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 7014778 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 573017 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 339409 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 70544458 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 3078967 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 281065039 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 38553 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6903084 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3842483 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 256263 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 170697 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2578390 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5188 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 180466 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 193564 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 374030 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 277914745 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 7063605 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 530025 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10469775 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28224309 # Number of branches executed -system.cpu2.iew.exec_stores 3454997 # Number of stores executed -system.cpu2.iew.exec_rate 1.782738 # Inst execution rate -system.cpu2.iew.wb_sent 277647788 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 276821632 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 215782455 # num instructions producing a value -system.cpu2.iew.wb_consumers 353891684 # num instructions consuming a value +system.cpu2.iew.exec_refs 10537501 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28240197 # Number of branches executed +system.cpu2.iew.exec_stores 3473896 # Number of stores executed +system.cpu2.iew.exec_rate 1.791692 # Inst execution rate +system.cpu2.iew.wb_sent 277728046 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 276907908 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 215869899 # num instructions producing a value +system.cpu2.iew.wb_consumers 354183211 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.776152 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609742 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.785201 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609487 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9482298 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 362455 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 346445 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 153408349 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.771036 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.652208 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9010167 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 364904 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 325088 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 152771285 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.780770 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.657176 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 95336110 62.15% 62.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4415580 2.88% 65.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1307869 0.85% 65.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24753928 16.14% 82.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 995070 0.65% 82.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 727248 0.47% 83.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 439603 0.29% 83.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23319103 15.20% 98.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2113838 1.38% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 94646882 61.95% 61.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4418156 2.89% 64.85% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1318603 0.86% 65.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24750822 16.20% 81.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 992364 0.65% 82.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 731797 0.48% 83.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 443039 0.29% 83.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23300929 15.25% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2168693 1.42% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 153408349 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 137757751 # Number of instructions committed -system.cpu2.commit.committedOps 271691665 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 152771285 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137969360 # Number of instructions committed +system.cpu2.commit.committedOps 272050550 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8766278 # Number of memory references committed -system.cpu2.commit.loads 5584968 # Number of loads committed -system.cpu2.commit.membars 161958 # Number of memory barriers committed -system.cpu2.commit.branches 27804222 # Number of branches committed +system.cpu2.commit.refs 8894843 # Number of memory references committed +system.cpu2.commit.loads 5678032 # Number of loads committed +system.cpu2.commit.membars 160530 # Number of memory barriers committed +system.cpu2.commit.branches 27847068 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 248326046 # Number of committed integer instructions. -system.cpu2.commit.function_calls 453891 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 49969 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 262767573 96.72% 96.73% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 56460 0.02% 96.75% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 51419 0.02% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.77% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5584918 2.06% 98.83% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3181310 1.17% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 248702825 # Number of committed integer instructions. +system.cpu2.commit.function_calls 458806 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 52824 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 262991815 96.67% 96.69% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 56918 0.02% 96.71% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 54179 0.02% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.73% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5677987 2.09% 98.82% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3216811 1.18% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 271691665 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2113838 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 432438048 # The number of ROB reads -system.cpu2.rob.rob_writes 563770768 # The number of ROB writes -system.cpu2.timesIdled 121162 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1030703 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4911308393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 137757751 # Number of Instructions Simulated -system.cpu2.committedOps 271691665 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.131368 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.131368 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.883886 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.883886 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 370162227 # number of integer regfile reads -system.cpu2.int_regfile_writes 221868711 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73082 # number of floating regfile reads +system.cpu2.commit.op_class_0::total 272050550 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2168693 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 431630642 # The number of ROB reads +system.cpu2.rob.rob_writes 563473683 # The number of ROB writes +system.cpu2.timesIdled 116646 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 996081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4908046353 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137969360 # Number of Instructions Simulated +system.cpu2.committedOps 272050550 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.124257 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.124257 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.889476 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.889476 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 370420908 # number of integer regfile reads +system.cpu2.int_regfile_writes 221942656 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73069 # number of floating regfile reads system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 141178662 # number of cc regfile reads -system.cpu2.cc_regfile_writes 108439379 # number of cc regfile writes -system.cpu2.misc_regfile_reads 90543264 # number of misc regfile reads -system.cpu2.misc_regfile_writes 143975 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3552152 # Transaction distribution -system.iobus.trans_dist::ReadResp 3552152 # Transaction distribution -system.iobus.trans_dist::WriteReq 57748 # Transaction distribution -system.iobus.trans_dist::WriteResp 57748 # Transaction distribution -system.iobus.trans_dist::MessageReq 1661 # Transaction distribution -system.iobus.trans_dist::MessageResp 1661 # Transaction distribution +system.cpu2.cc_regfile_reads 141352578 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108476747 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90603281 # number of misc regfile reads +system.cpu2.misc_regfile_writes 149391 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3552124 # Transaction distribution +system.iobus.trans_dist::ReadResp 3552124 # Transaction distribution +system.iobus.trans_dist::WriteReq 57703 # Transaction distribution +system.iobus.trans_dist::WriteResp 57703 # Transaction distribution +system.iobus.trans_dist::MessageReq 1656 # Transaction distribution +system.iobus.trans_dist::MessageResp 1656 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) @@ -1163,15 +1166,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7124542 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3322 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3322 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7223122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7124404 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95250 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95250 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7222966 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) @@ -1187,25 +1190,25 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3568515 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6644 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6644 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6602975 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2788160 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3568437 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6602845 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2765072 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 5737000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5295000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -1213,62 +1216,62 @@ system.iobus.reqLayer8.occupancy 18000 # La system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 140109000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 441000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 421000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11321000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11369000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 105499646 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 144756051 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 300163000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 299839000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 23378000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 30990000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1173000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1161000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47574 # number of replacements -system.iocache.tags.tagsinuse 0.102984 # Cycle average of tags in use +system.iocache.tags.replacements 47570 # number of replacements +system.iocache.tags.tagsinuse 0.092294 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47586 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000591236509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.102984 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006437 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006437 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000591335509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092294 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005768 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005768 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428661 # Number of tag accesses -system.iocache.tags.data_accesses 428661 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses +system.iocache.tags.tag_accesses 428625 # Number of tag accesses +system.iocache.tags.data_accesses 428625 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 905 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses -system.iocache.demand_misses::total 909 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses -system.iocache.overall_misses::total 909 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126015772 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 126015772 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2387409874 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2387409874 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 126015772 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 126015772 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 126015772 # number of overall miss cycles -system.iocache.overall_miss_latency::total 126015772 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 905 # number of demand (read+write) misses +system.iocache.demand_misses::total 905 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 905 # number of overall misses +system.iocache.overall_misses::total 905 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128938756 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 128938756 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3283387295 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 3283387295 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 128938756 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 128938756 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 128938756 # number of overall miss cycles +system.iocache.overall_miss_latency::total 128938756 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 905 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 905 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 905 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 905 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1277,337 +1280,323 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138631.212321 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 138631.212321 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 51100.382577 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 51100.382577 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138631.212321 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 138631.212321 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138631.212321 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 138631.212321 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 218 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 142473.763536 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70277.981485 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 70277.981485 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 142473.763536 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 142473.763536 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 142473.763536 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 18 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.111111 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.913043 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 757 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 757 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 20232 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 20232 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 757 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 757 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 757 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 757 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88165772 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 88165772 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1375809874 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1375809874 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88165772 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 88165772 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88165772 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 88165772 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.832783 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.832783 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.433048 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.433048 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.832783 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.832783 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.832783 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.832783 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 116467.334214 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68001.674278 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68001.674278 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 116467.334214 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116467.334214 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 116467.334214 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 771 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 771 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 27816 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 27816 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 771 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 771 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 771 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 771 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 90388756 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1892587295 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1892587295 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 90388756 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 90388756 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 90388756 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.851934 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.595377 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.595377 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.851934 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.851934 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.851934 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117235.740597 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68039.520240 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68039.520240 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 117235.740597 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117235.740597 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 117235.740597 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 105183 # number of replacements -system.l2c.tags.tagsinuse 64828.721241 # Cycle average of tags in use -system.l2c.tags.total_refs 4684115 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169423 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 27.647456 # Average number of references to valid blocks. +system.l2c.tags.replacements 105297 # number of replacements +system.l2c.tags.tagsinuse 64829.932138 # Cycle average of tags in use +system.l2c.tags.total_refs 4653506 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169379 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.473925 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50898.132312 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.126487 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1607.202570 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5199.796885 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 251.414397 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1573.306131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.399418 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.004770 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1229.783276 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4062.554995 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.776644 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51173.407982 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134359 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1534.003878 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4961.516829 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 244.491161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1538.007484 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.330522 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1242.728330 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4127.311591 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.780844 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.024524 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.079343 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003836 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.024007 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000098 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.018765 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.061990 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989208 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6984 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54074 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.980225 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 41790330 # Number of tag accesses -system.l2c.tags.data_accesses 41790330 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 18694 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10376 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 14927 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 8452 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 63394 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13067 # number of ReadReq hits -system.l2c.ReadReq_hits::total 128910 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.023407 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003731 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000127 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.018963 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.062978 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989226 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64082 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3909 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7185 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52613 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.977814 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 41530530 # Number of tag accesses +system.l2c.tags.data_accesses 41530530 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 18603 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10268 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 13451 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7422 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 62068 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 13128 # number of ReadReq hits +system.l2c.ReadReq_hits::total 124940 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1547778 # number of Writeback hits -system.l2c.Writeback_hits::total 1547778 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 86 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 61 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 104 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 251 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57261 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 38255 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 63793 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 159309 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 284171 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 176684 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 403287 # 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mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.381032 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.231445 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019315 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014555 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010544 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019996 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.021822 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.013620 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019315 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.109644 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014555 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.072243 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.036020 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019315 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.109644 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014555 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.072243 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036020 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 82787.878788 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22609.872611 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20978.225806 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21526.766595 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65325.332136 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69441.634241 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67734.960027 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70241.302409 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75397.762747 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73498.192573 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72655.969332 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77973.823508 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76651.312922 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70241.302409 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66357.704766 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75397.762747 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71657.092559 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 70024.327007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70241.302409 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66357.704766 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 82787.878788 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75397.762747 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71657.092559 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70024.327007 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152098.675347 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149457.967672 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150716.387656 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167209.008514 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 191973.178001 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 179675.531915 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152388.307169 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 150211.166202 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 151249.478404 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5067102 # Transaction distribution -system.membus.trans_dist::ReadResp 5116344 # Transaction distribution -system.membus.trans_dist::WriteReq 13938 # Transaction distribution -system.membus.trans_dist::WriteResp 13938 # Transaction distribution -system.membus.trans_dist::Writeback 143722 # Transaction distribution -system.membus.trans_dist::CleanEvict 8694 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1684 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1684 # Transaction distribution -system.membus.trans_dist::ReadExReq 130671 # Transaction distribution -system.membus.trans_dist::ReadExResp 130671 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 49245 # Transaction distribution -system.membus.trans_dist::MessageReq 1661 # Transaction distribution -system.membus.trans_dist::MessageResp 1661 # Transaction distribution -system.membus.trans_dist::BadAddressError 3 # Transaction distribution +system.membus.trans_dist::ReadReq 5066901 # Transaction distribution +system.membus.trans_dist::ReadResp 5115808 # Transaction distribution +system.membus.trans_dist::WriteReq 13888 # Transaction distribution +system.membus.trans_dist::WriteResp 13888 # Transaction distribution +system.membus.trans_dist::Writeback 143652 # Transaction distribution +system.membus.trans_dist::CleanEvict 8856 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1645 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1645 # Transaction distribution +system.membus.trans_dist::ReadExReq 130459 # Transaction distribution +system.membus.trans_dist::ReadExResp 130459 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 48907 # Transaction distribution +system.membus.trans_dist::MessageReq 1656 # Transaction distribution +system.membus.trans_dist::MessageResp 1656 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124542 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 466123 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 6 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10628209 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142133 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142133 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10773664 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6644 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6644 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568515 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6075073 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17638016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27281604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3024768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3024768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30313016 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 794 # Total snoops (count) -system.membus.snoop_fanout::samples 5463823 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000304 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017433 # Request fanout histogram +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10626768 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10772166 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568437 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6074345 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17606208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27248990 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3023616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3023616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30279230 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 694 # Total snoops (count) +system.membus.snoop_fanout::samples 5463095 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000303 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017408 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5462162 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1661 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5461439 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1656 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5463823 # Request fanout histogram -system.membus.reqLayer0.occupancy 233077000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5463095 # Request fanout histogram +system.membus.reqLayer0.occupancy 232635000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 304111500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 304127000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2346000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2322000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 540335137 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 583726731 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 4500 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1173000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1161000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1355052899 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1349926167 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 39163714 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 52433855 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1847,54 +1814,53 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 5228129 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7456139 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13940 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13940 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1629241 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 974526 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1670 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1670 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 290245 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 290245 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 879202 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1349341 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 1173 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 3 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 20232 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2636646 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15081470 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73733 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 221081 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18012930 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56268288 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213600772 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 270696 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 799584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270939340 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 164260 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10415384 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.028580 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.166622 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5228525 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7442369 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13890 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13890 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1636010 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 961008 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1644 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1644 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 290225 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 290225 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 865835 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1348541 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 1161 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 27816 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2596558 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15078411 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72306 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 219403 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17966678 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55412672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213513438 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 261576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 779088 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 269966774 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 176011 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 10394757 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.029410 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.168953 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 10117715 97.14% 97.14% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 297669 2.86% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 10089048 97.06% 97.06% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 305709 2.94% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10415384 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2866108499 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 10394757 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2840392499 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 340500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 358500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 884325204 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 856033294 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1946611318 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1941516813 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 27584988 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 27469982 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 99698688 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 100352159 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal index 096700e63..898984ead 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal @@ -46,7 +46,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812519
+result 7812539
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
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